0.U\n when(io.inRow.fire) {\n upCounter := upCounter + 1.U\n }\n when(upCounter === (dim-1).U) {\n state := sMoveLeft\n leftCounter := 0.U\n }\n when(io.outCol.fire) {\n leftCounter := leftCounter - 1.U\n }\n }\n is(sMoveLeft) {\n io.inRow.ready := leftCounter <= dim.U // TODO: this is naive\n io.outCol.valid := upCounter > 0.U\n when(leftCounter === (dim-1).U) {\n state := sMoveUp\n }\n when(io.inRow.fire) {\n leftCounter := leftCounter + 1.U\n upCounter := 0.U\n }\n when(io.outCol.fire) {\n upCounter := upCounter - 1.U\n }\n }\n }\n\n // Propagate input from bottom row to top row systolically in the move up phase\n // TODO: need to iterate over columns to connect Chisel values of type T\n // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)\n for (colIdx <- 0 until dim) {\n regArray.foldRight(io.inRow.bits(colIdx)) {\n case (regRow, prevReg) =>\n when (state === sMoveUp) {\n regRow(colIdx) := prevReg\n }\n regRow(colIdx)\n }\n }\n\n // Propagate input from right side to left side systolically in the move left phase\n for (rowIdx <- 0 until dim) {\n regArrayT.foldRight(io.inRow.bits(rowIdx)) {\n case (regCol, prevReg) =>\n when (state === sMoveLeft) {\n regCol(rowIdx) := prevReg\n }\n regCol(rowIdx)\n }\n }\n\n // Pull from the left side or the top side based on the state\n for (idx <- 0 until dim) {\n when (state === sMoveUp) {\n io.outCol.bits(idx) := regArray(0)(idx)\n }.elsewhen(state === sMoveLeft) {\n io.outCol.bits(idx) := regArrayT(0)(idx)\n }.otherwise {\n io.outCol.bits(idx) := DontCare\n }\n }\n}\n\nclass AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {\n require(isPow2(dim))\n\n val LEFT_DIR = 0.U(1.W)\n val UP_DIR = 1.U(1.W)\n\n class PE extends Module {\n val io = IO(new Bundle {\n val inR = Input(dataType)\n val inD = Input(dataType)\n val outL = Output(dataType)\n val outU = Output(dataType)\n val dir = Input(UInt(1.W))\n val en = Input(Bool())\n })\n\n val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)\n\n io.outU := reg\n io.outL := reg\n }\n\n val pes = Seq.fill(dim,dim)(Module(new PE))\n val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter\n val dir = RegInit(LEFT_DIR)\n\n // Wire up horizontal signals\n for (row <- 0 until dim; col <- 0 until dim) {\n val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL\n pes(row)(col).io.inR := right_in\n }\n\n // Wire up vertical signals\n for (row <- 0 until dim; col <- 0 until dim) {\n val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU\n pes(row)(col).io.inD := down_in\n }\n\n // Wire up global signals\n pes.flatten.foreach(_.io.dir := dir)\n pes.flatten.foreach(_.io.en := io.inRow.fire)\n\n io.outCol.valid := true.B\n io.inRow.ready := true.B\n\n val left_out = VecInit(pes.transpose.head.map(_.io.outL))\n val up_out = VecInit(pes.head.map(_.io.outU))\n\n io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)\n\n when (io.inRow.fire) {\n counter := wrappingAdd(counter, 1.U, dim)\n }\n\n when (counter === (dim-1).U && io.inRow.fire) {\n dir := ~dir\n }\n}\n\nclass NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {\n val regArray = Seq.fill(dim, dim)(Reg(dataType))\n val regArrayT = regArray.transpose\n // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise\n val state = RegInit(0.U(1.W))\n val countInc = io.inRow.fire || io.outCol.fire\n val (countValue, countWrap) = Counter(countInc, dim)\n\n io.inRow.ready := state === 0.U\n io.outCol.valid := state === 1.U\n\n for (i <- 0 until dim) {\n for (j <- 0 until dim) {\n when(countValue === i.U && io.inRow.fire) {\n regArray(i)(j) := io.inRow.bits(j)\n }\n }\n }\n\n for (i <- 0 until dim) {\n io.outCol.bits(i) := 0.U\n for (j <- 0 until dim) {\n when(countValue === j.U) {\n io.outCol.bits(i) := regArrayT(j)(i)\n }\n }\n }\n\n when (io.inRow.fire && countWrap) {\n state := 1.U\n }\n when (io.outCol.fire && countWrap) {\n state := 0.U\n }\n\n assert(!(state === 0.U) || !io.outCol.fire)\n assert(!(state === 1.U) || !io.inRow.fire)\n}\n"},"response":{"kind":"string","value":"module PE_192(\t// @[Transposer.scala:100:9]\n input clock,\t// @[Transposer.scala:100:9]\n input reset,\t// @[Transposer.scala:100:9]\n input [7:0] io_inR,\t// @[Transposer.scala:101:16]\n input [7:0] io_inD,\t// @[Transposer.scala:101:16]\n output [7:0] io_outL,\t// @[Transposer.scala:101:16]\n output [7:0] io_outU,\t// @[Transposer.scala:101:16]\n input io_dir,\t// @[Transposer.scala:101:16]\n input io_en\t// @[Transposer.scala:101:16]\n);\n\n wire [7:0] io_inR_0 = io_inR;\t// @[Transposer.scala:100:9]\n wire [7:0] io_inD_0 = io_inD;\t// @[Transposer.scala:100:9]\n wire io_dir_0 = io_dir;\t// @[Transposer.scala:100:9]\n wire io_en_0 = io_en;\t// @[Transposer.scala:100:9]\n wire [7:0] io_outL_0;\t// @[Transposer.scala:100:9]\n wire [7:0] io_outU_0;\t// @[Transposer.scala:100:9]\n wire _reg_T = ~io_dir_0;\t// @[Transposer.scala:100:9, :110:36]\n wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0;\t// @[Transposer.scala:100:9, :110:{28,36}]\n reg [7:0] reg_0;\t// @[Transposer.scala:110:24]\n assign io_outL_0 = reg_0;\t// @[Transposer.scala:100:9, :110:24]\n assign io_outU_0 = reg_0;\t// @[Transposer.scala:100:9, :110:24]\n always @(posedge clock) begin\t// @[Transposer.scala:100:9]\n if (io_en_0)\t// @[Transposer.scala:100:9]\n reg_0 <= _reg_T_1;\t// @[Transposer.scala:110:{24,28}]\n always @(posedge)\n assign io_outL = io_outL_0;\t// @[Transposer.scala:100:9]\n assign io_outU = io_outU_0;\t// @[Transposer.scala:100:9]\nendmodule"}}},{"rowIdx":2089,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Tilelink.scala:\npackage constellation.protocol\n\nimport chisel3._\nimport chisel3.util._\n\nimport constellation.channel._\nimport constellation.noc._\nimport constellation.soc.{CanAttachToGlobalNoC}\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\nimport scala.collection.immutable.{ListMap}\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLMasterToNoC(\n edgeIn: TLEdge, edgesOut: Seq[TLEdge],\n sourceStart: Int, sourceSize: Int,\n wideBundle: TLBundleParameters,\n slaveToEgressOffset: Int => Int,\n flitWidth: Int\n)(implicit p: Parameters) extends Module {\n val io = IO(new Bundle {\n val tilelink = Flipped(new TLBundle(wideBundle))\n val flits = new Bundle {\n val a = Decoupled(new IngressFlit(flitWidth))\n val b = Flipped(Decoupled(new EgressFlit(flitWidth)))\n val c = Decoupled(new IngressFlit(flitWidth))\n val d = Flipped(Decoupled(new EgressFlit(flitWidth)))\n val e = Decoupled(new IngressFlit(flitWidth))\n }\n })\n val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))\n val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))\n val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))\n val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))\n val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2))\n a.io.protocol <> io.tilelink.a\n io.tilelink.b <> b.io.protocol\n c.io.protocol <> io.tilelink.c\n io.tilelink.d <> d.io.protocol\n e.io.protocol <> io.tilelink.e\n\n io.flits.a <> a.io.flit\n b.io.flit <> io.flits.b\n io.flits.c <> c.io.flit\n d.io.flit <> io.flits.d\n io.flits.e <> e.io.flit\n}\n\nclass TLMasterACDToNoC(\n edgeIn: TLEdge, edgesOut: Seq[TLEdge],\n sourceStart: Int, sourceSize: Int,\n wideBundle: TLBundleParameters,\n slaveToEgressOffset: Int => Int,\n flitWidth: Int\n)(implicit p: Parameters) extends Module {\n val io = IO(new Bundle {\n val tilelink = Flipped(new TLBundle(wideBundle))\n val flits = new Bundle {\n val a = Decoupled(new IngressFlit(flitWidth))\n val c = Decoupled(new IngressFlit(flitWidth))\n val d = Flipped(Decoupled(new EgressFlit(flitWidth)))\n }\n })\n io.tilelink := DontCare\n val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))\n val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))\n val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))\n a.io.protocol <> io.tilelink.a\n c.io.protocol <> io.tilelink.c\n io.tilelink.d <> d.io.protocol\n\n io.flits.a <> a.io.flit\n io.flits.c <> c.io.flit\n d.io.flit <> io.flits.d\n}\n\nclass TLMasterBEToNoC(\n edgeIn: TLEdge, edgesOut: Seq[TLEdge],\n sourceStart: Int, sourceSize: Int,\n wideBundle: TLBundleParameters,\n slaveToEgressOffset: Int => Int,\n flitWidth: Int\n)(implicit p: Parameters) extends Module {\n val io = IO(new Bundle {\n val tilelink = Flipped(new TLBundle(wideBundle))\n val flits = new Bundle {\n val b = Flipped(Decoupled(new EgressFlit(flitWidth)))\n val e = Decoupled(new IngressFlit(flitWidth))\n }\n })\n io.tilelink := DontCare\n val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))\n val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0))\n io.tilelink.b <> b.io.protocol\n e.io.protocol <> io.tilelink.e\n\n b.io.flit <> io.flits.b\n io.flits.e <> e.io.flit\n}\n\n\nclass TLSlaveToNoC(\n edgeOut: TLEdge, edgesIn: Seq[TLEdge],\n sourceStart: Int, sourceSize: Int,\n wideBundle: TLBundleParameters,\n masterToEgressOffset: Int => Int,\n flitWidth: Int\n)(implicit p: Parameters) extends Module {\n val io = IO(new Bundle {\n val tilelink = new TLBundle(wideBundle)\n val flits = new Bundle {\n val a = Flipped(Decoupled(new EgressFlit(flitWidth)))\n val b = Decoupled(new IngressFlit(flitWidth))\n val c = Flipped(Decoupled(new EgressFlit(flitWidth)))\n val d = Decoupled(new IngressFlit(flitWidth))\n val e = Flipped(Decoupled(new EgressFlit(flitWidth)))\n }\n })\n\n val a = Module(new TLAFromNoC(edgeOut, wideBundle))\n val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))\n val c = Module(new TLCFromNoC(edgeOut, wideBundle))\n val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart))\n val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))\n io.tilelink.a <> a.io.protocol\n b.io.protocol <> io.tilelink.b\n io.tilelink.c <> c.io.protocol\n d.io.protocol <> io.tilelink.d\n io.tilelink.e <> e.io.protocol\n\n a.io.flit <> io.flits.a\n io.flits.b <> b.io.flit\n c.io.flit <> io.flits.c\n io.flits.d <> d.io.flit\n e.io.flit <> io.flits.e\n}\n\nclass TLSlaveACDToNoC(\n edgeOut: TLEdge, edgesIn: Seq[TLEdge],\n sourceStart: Int, sourceSize: Int,\n wideBundle: TLBundleParameters,\n masterToEgressOffset: Int => Int,\n flitWidth: Int\n)(implicit p: Parameters) extends Module {\n val io = IO(new Bundle {\n val tilelink = new TLBundle(wideBundle)\n val flits = new Bundle {\n val a = Flipped(Decoupled(new EgressFlit(flitWidth)))\n val c = Flipped(Decoupled(new EgressFlit(flitWidth)))\n val d = Decoupled(new IngressFlit(flitWidth))\n }\n })\n io.tilelink := DontCare\n val a = Module(new TLAFromNoC(edgeOut, wideBundle))\n val c = Module(new TLCFromNoC(edgeOut, wideBundle))\n val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart))\n io.tilelink.a <> a.io.protocol\n io.tilelink.c <> c.io.protocol\n d.io.protocol <> io.tilelink.d\n\n a.io.flit <> io.flits.a\n c.io.flit <> io.flits.c\n io.flits.d <> d.io.flit\n}\n\nclass TLSlaveBEToNoC(\n edgeOut: TLEdge, edgesIn: Seq[TLEdge],\n sourceStart: Int, sourceSize: Int,\n wideBundle: TLBundleParameters,\n masterToEgressOffset: Int => Int,\n flitWidth: Int\n)(implicit p: Parameters) extends Module {\n val io = IO(new Bundle {\n val tilelink = new TLBundle(wideBundle)\n val flits = new Bundle {\n val b = Decoupled(new IngressFlit(flitWidth))\n val e = Flipped(Decoupled(new EgressFlit(flitWidth)))\n }\n })\n io.tilelink := DontCare\n val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))\n val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))\n b.io.protocol <> io.tilelink.b\n io.tilelink.e <> e.io.protocol\n\n io.flits.b <> b.io.flit\n e.io.flit <> io.flits.e\n}\n\nclass TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle {\n val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) })\n val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) })\n}\n\ntrait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper {\n def edgesIn: Seq[TLEdge]\n def edgesOut: Seq[TLEdge]\n def edgeInNodes: Seq[Int]\n def edgeOutNodes: Seq[Int]\n require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size)\n def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle))\n def genBundle = new TLBundle(wideBundle)\n def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))\n def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))\n\n val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee\n\n def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut)\n}\n\nobject TLConnect {\n def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = {\n l.valid := r.valid\n r.ready := l.ready\n l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll\n }\n}\n\n// BEGIN: TileLinkProtocolParams\ncase class TileLinkABCDEProtocolParams(\n edgesIn: Seq[TLEdge],\n edgesOut: Seq[TLEdge],\n edgeInNodes: Seq[Int],\n edgeOutNodes: Seq[Int]\n) extends TileLinkProtocolParams {\n // END: TileLinkProtocolParams\n val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle))\n val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten\n val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten\n val nVirtualNetworks = 5\n\n val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>\n val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>\n c.visibility.exists { ca => m.address.exists { ma =>\n ca.overlaps(ma)\n }}\n }}\n val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)\n val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB\n ( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A\n (if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B\n (if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C\n (if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D\n (if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E\n }}.flatten.flatten\n\n def interface(terminals: NoCTerminalIO,\n ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {\n val ingresses = terminals.ingress\n val egresses = terminals.egress\n protocol match { case protocol: TileLinkInterconnectInterface => {\n edgesIn.zipWithIndex.map { case (e,i) =>\n val nif_master = Module(new TLMasterToNoC(\n e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,\n wideBundle,\n (s) => s * 3 + edgesIn.size * 2 + egressOffset,\n minPayloadWidth\n ))\n nif_master.io.tilelink := DontCare\n nif_master.io.tilelink.a.valid := false.B\n nif_master.io.tilelink.c.valid := false.B\n nif_master.io.tilelink.e.valid := false.B\n\n TLConnect(nif_master.io.tilelink.a, protocol.in(i).a)\n TLConnect(protocol.in(i).d, nif_master.io.tilelink.d)\n\n if (protocol.in(i).params.hasBCE) {\n TLConnect(protocol.in(i).b, nif_master.io.tilelink.b)\n TLConnect(nif_master.io.tilelink.c, protocol.in(i).c)\n TLConnect(nif_master.io.tilelink.e, protocol.in(i).e)\n }\n\n ingresses(i * 3 + 0).flit <> nif_master.io.flits.a\n ingresses(i * 3 + 1).flit <> nif_master.io.flits.c\n ingresses(i * 3 + 2).flit <> nif_master.io.flits.e\n nif_master.io.flits.b <> egresses(i * 2 + 0).flit\n nif_master.io.flits.d <> egresses(i * 2 + 1).flit\n }\n edgesOut.zipWithIndex.map { case (e,i) =>\n val nif_slave = Module(new TLSlaveToNoC(\n e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,\n wideBundle,\n (s) => s * 2 + egressOffset,\n minPayloadWidth\n ))\n nif_slave.io.tilelink := DontCare\n nif_slave.io.tilelink.b.valid := false.B\n nif_slave.io.tilelink.d.valid := false.B\n\n TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a)\n TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d)\n\n if (protocol.out(i).params.hasBCE) {\n TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b)\n TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c)\n TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e)\n }\n\n ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b\n ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d\n nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit\n nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit\n nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit\n }\n } }\n }\n}\n\ncase class TileLinkACDProtocolParams(\n edgesIn: Seq[TLEdge],\n edgesOut: Seq[TLEdge],\n edgeInNodes: Seq[Int],\n edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {\n val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits))\n val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten\n val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten\n\n val nVirtualNetworks = 3\n val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>\n val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>\n c.visibility.exists { ca => m.address.exists { ma =>\n ca.overlaps(ma)\n }}\n }}\n val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB\n ( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A\n (if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C\n (if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D\n\n }}.flatten.flatten\n\n\n def interface(terminals: NoCTerminalIO,\n ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {\n val ingresses = terminals.ingress\n val egresses = terminals.egress\n protocol match { case protocol: TileLinkInterconnectInterface => {\n protocol := DontCare\n edgesIn.zipWithIndex.map { case (e,i) =>\n val nif_master_acd = Module(new TLMasterACDToNoC(\n e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,\n wideBundle,\n (s) => s * 2 + edgesIn.size * 1 + egressOffset,\n minPayloadWidth\n ))\n nif_master_acd.io.tilelink := DontCare\n nif_master_acd.io.tilelink.a.valid := false.B\n nif_master_acd.io.tilelink.c.valid := false.B\n nif_master_acd.io.tilelink.e.valid := false.B\n\n TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a)\n TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d)\n\n if (protocol.in(i).params.hasBCE) {\n TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c)\n }\n\n ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a\n ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c\n nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit\n }\n edgesOut.zipWithIndex.map { case (e,i) =>\n val nif_slave_acd = Module(new TLSlaveACDToNoC(\n e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,\n wideBundle,\n (s) => s * 1 + egressOffset,\n minPayloadWidth\n ))\n nif_slave_acd.io.tilelink := DontCare\n nif_slave_acd.io.tilelink.b.valid := false.B\n nif_slave_acd.io.tilelink.d.valid := false.B\n\n TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a)\n TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d)\n\n if (protocol.out(i).params.hasBCE) {\n TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c)\n }\n\n ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d\n nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit\n nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit\n }\n }}\n }\n}\n\ncase class TileLinkBEProtocolParams(\n edgesIn: Seq[TLEdge],\n edgesOut: Seq[TLEdge],\n edgeInNodes: Seq[Int],\n edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {\n val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits))\n val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten\n val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten\n\n val nVirtualNetworks = 2\n val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>\n val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)\n val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB\n ( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B\n (if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E\n }}.flatten.flatten\n\n def interface(terminals: NoCTerminalIO,\n ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {\n val ingresses = terminals.ingress\n val egresses = terminals.egress\n protocol match { case protocol: TileLinkInterconnectInterface => {\n protocol := DontCare\n edgesIn.zipWithIndex.map { case (e,i) =>\n val nif_master_be = Module(new TLMasterBEToNoC(\n e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,\n wideBundle,\n (s) => s * 1 + edgesIn.size * 1 + egressOffset,\n minPayloadWidth\n ))\n nif_master_be.io.tilelink := DontCare\n nif_master_be.io.tilelink.a.valid := false.B\n nif_master_be.io.tilelink.c.valid := false.B\n nif_master_be.io.tilelink.e.valid := false.B\n\n if (protocol.in(i).params.hasBCE) {\n TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b)\n TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e)\n }\n\n ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e\n nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit\n }\n edgesOut.zipWithIndex.map { case (e,i) =>\n val nif_slave_be = Module(new TLSlaveBEToNoC(\n e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,\n wideBundle,\n (s) => s * 1 + egressOffset,\n minPayloadWidth\n ))\n nif_slave_be.io.tilelink := DontCare\n nif_slave_be.io.tilelink.b.valid := false.B\n nif_slave_be.io.tilelink.d.valid := false.B\n\n if (protocol.out(i).params.hasBCE) {\n TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e)\n TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b)\n }\n\n ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b\n nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit\n }\n }}\n }\n}\n\nabstract class TLNoCLike(implicit p: Parameters) extends LazyModule {\n val node = new TLNexusNode(\n clientFn = { seq =>\n seq(0).v1copy(\n echoFields = BundleField.union(seq.flatMap(_.echoFields)),\n requestFields = BundleField.union(seq.flatMap(_.requestFields)),\n responseKeys = seq.flatMap(_.responseKeys).distinct,\n minLatency = seq.map(_.minLatency).min,\n clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>\n port.clients map { client => client.v1copy(\n sourceId = client.sourceId.shift(range.start)\n )}\n }\n )\n },\n managerFn = { seq =>\n val fifoIdFactory = TLXbar.relabeler()\n seq(0).v1copy(\n responseFields = BundleField.union(seq.flatMap(_.responseFields)),\n requestKeys = seq.flatMap(_.requestKeys).distinct,\n minLatency = seq.map(_.minLatency).min,\n endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,\n managers = seq.flatMap { port =>\n require (port.beatBytes == seq(0).beatBytes,\n s\"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B\")\n // TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers\n port.managers map { manager => manager.v1copy(fifoId = None) }\n }\n )\n }\n )\n}\n\nabstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) {\n val edgesIn: Seq[TLEdge]\n val edgesOut: Seq[TLEdge]\n val nodeMapping: DiplomaticNetworkNodeMapping\n val nocName: String\n lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name)))\n lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name)))\n lazy val edgeInNodes = nodeMapping.getNodesIn(inNames)\n lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames)\n def printNodeMappings() {\n println(s\"Constellation: TLNoC $nocName inwards mapping:\")\n for ((n, i) <- inNames zip edgeInNodes) {\n val node = i.map(_.toString).getOrElse(\"X\")\n println(s\" $node <- $n\")\n }\n\n println(s\"Constellation: TLNoC $nocName outwards mapping:\")\n for ((n, i) <- outNames zip edgeOutNodes) {\n val node = i.map(_.toString).getOrElse(\"X\")\n println(s\" $node <- $n\")\n }\n }\n}\n\ntrait TLNoCParams\n\n// Instantiates a private TLNoC. Replaces the TLXbar\n// BEGIN: TLNoCParams\ncase class SimpleTLNoCParams(\n nodeMappings: DiplomaticNetworkNodeMapping,\n nocParams: NoCParams = NoCParams(),\n) extends TLNoCParams\nclass TLNoC(params: SimpleTLNoCParams, name: String = \"test\", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {\n // END: TLNoCParams\n\n override def shouldBeInlined = inlineNoC\n lazy val module = new TLNoCModuleImp(this) {\n val (io_in, edgesIn) = node.in.unzip\n val (io_out, edgesOut) = node.out.unzip\n val nodeMapping = params.nodeMappings\n val nocName = name\n\n printNodeMappings()\n\n val protocolParams = TileLinkABCDEProtocolParams(\n edgesIn = edgesIn,\n edgesOut = edgesOut,\n edgeInNodes = edgeInNodes.flatten,\n edgeOutNodes = edgeOutNodes.flatten\n )\n\n val noc = Module(new ProtocolNoC(ProtocolNoCParams(\n params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC),\n Seq(protocolParams),\n inlineNoC = inlineNoC\n )))\n\n noc.io.protocol(0) match {\n case protocol: TileLinkInterconnectInterface => {\n (protocol.in zip io_in).foreach { case (l,r) => l <> r }\n (io_out zip protocol.out).foreach { case (l,r) => l <> r }\n }\n }\n }\n}\n\ncase class SplitACDxBETLNoCParams(\n nodeMappings: DiplomaticNetworkNodeMapping,\n acdNoCParams: NoCParams = NoCParams(),\n beNoCParams: NoCParams = NoCParams(),\n beDivision: Int = 2\n) extends TLNoCParams\nclass TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = \"test\", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {\n override def shouldBeInlined = inlineNoC\n lazy val module = new TLNoCModuleImp(this) {\n val (io_in, edgesIn) = node.in.unzip\n val (io_out, edgesOut) = node.out.unzip\n val nodeMapping = params.nodeMappings\n val nocName = name\n\n printNodeMappings()\n\n val acdProtocolParams = TileLinkACDProtocolParams(\n edgesIn = edgesIn,\n edgesOut = edgesOut,\n edgeInNodes = edgeInNodes.flatten,\n edgeOutNodes = edgeOutNodes.flatten\n )\n val beProtocolParams = TileLinkBEProtocolParams(\n edgesIn = edgesIn,\n edgesOut = edgesOut,\n edgeInNodes = edgeInNodes.flatten,\n edgeOutNodes = edgeOutNodes.flatten\n )\n\n val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams(\n params.acdNoCParams.copy(hasCtrl = false, nocName=s\"${name}_acd\", inlineNoC = inlineNoC),\n Seq(acdProtocolParams),\n inlineNoC = inlineNoC\n )))\n val be_noc = Module(new ProtocolNoC(ProtocolNoCParams(\n params.beNoCParams.copy(hasCtrl = false, nocName=s\"${name}_be\", inlineNoC = inlineNoC),\n Seq(beProtocolParams),\n widthDivision = params.beDivision,\n inlineNoC = inlineNoC\n )))\n\n acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {\n (protocol.in zip io_in).foreach { case (l,r) =>\n l := DontCare\n l.a <> r.a\n l.c <> r.c\n l.d <> r.d\n }\n (io_out zip protocol.out).foreach { case (l,r) =>\n r := DontCare\n l.a <> r.a\n l.c <> r.c\n l.d <> r.d\n }\n }}\n\n be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {\n (protocol.in zip io_in).foreach { case (l,r) =>\n l := DontCare\n l.b <> r.b\n l.e <> r.e\n }\n (io_out zip protocol.out).foreach { case (l,r) =>\n r := DontCare\n l.b <> r.b\n l.e <> r.e\n }\n }}\n }\n}\n\ncase class GlobalTLNoCParams(\n nodeMappings: DiplomaticNetworkNodeMapping\n) extends TLNoCParams\n// Maps this interconnect onto a global NoC\nclass TLGlobalNoC(params: GlobalTLNoCParams, name: String = \"test\")(implicit p: Parameters) extends TLNoCLike {\n lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC {\n val (io_in, edgesIn) = node.in.unzip\n val (io_out, edgesOut) = node.out.unzip\n val nodeMapping = params.nodeMappings\n val nocName = name\n\n val protocolParams = TileLinkABCDEProtocolParams(\n edgesIn = edgesIn,\n edgesOut = edgesOut,\n edgeInNodes = edgeInNodes.flatten,\n edgeOutNodes = edgeOutNodes.flatten\n )\n\n printNodeMappings()\n val io_global = IO(Flipped(protocolParams.genIO()))\n io_global match {\n case protocol: TileLinkInterconnectInterface => {\n (protocol.in zip io_in).foreach { case (l,r) => l <> r }\n (io_out zip protocol.out).foreach { case (l,r) => l <> r }\n }\n }\n\n }\n}\n"},"response":{"kind":"string","value":"module TLSlaveToNoC(\t// @[Tilelink.scala:125:7]\n input clock,\t// @[Tilelink.scala:125:7]\n input reset,\t// @[Tilelink.scala:125:7]\n input io_tilelink_a_ready,\t// @[Tilelink.scala:132:14]\n output io_tilelink_a_valid,\t// @[Tilelink.scala:132:14]\n output [2:0] io_tilelink_a_bits_opcode,\t// @[Tilelink.scala:132:14]\n output [2:0] io_tilelink_a_bits_param,\t// @[Tilelink.scala:132:14]\n output [3:0] io_tilelink_a_bits_size,\t// @[Tilelink.scala:132:14]\n output [5:0] io_tilelink_a_bits_source,\t// @[Tilelink.scala:132:14]\n output [31:0] io_tilelink_a_bits_address,\t// @[Tilelink.scala:132:14]\n output [7:0] io_tilelink_a_bits_mask,\t// @[Tilelink.scala:132:14]\n output [63:0] io_tilelink_a_bits_data,\t// @[Tilelink.scala:132:14]\n output io_tilelink_a_bits_corrupt,\t// @[Tilelink.scala:132:14]\n output io_tilelink_d_ready,\t// @[Tilelink.scala:132:14]\n input io_tilelink_d_valid,\t// @[Tilelink.scala:132:14]\n input [2:0] io_tilelink_d_bits_opcode,\t// @[Tilelink.scala:132:14]\n input [1:0] io_tilelink_d_bits_param,\t// @[Tilelink.scala:132:14]\n input [3:0] io_tilelink_d_bits_size,\t// @[Tilelink.scala:132:14]\n input [5:0] io_tilelink_d_bits_source,\t// @[Tilelink.scala:132:14]\n input [4:0] io_tilelink_d_bits_sink,\t// @[Tilelink.scala:132:14]\n input io_tilelink_d_bits_denied,\t// @[Tilelink.scala:132:14]\n input [63:0] io_tilelink_d_bits_data,\t// @[Tilelink.scala:132:14]\n input io_tilelink_d_bits_corrupt,\t// @[Tilelink.scala:132:14]\n output io_flits_a_ready,\t// @[Tilelink.scala:132:14]\n input io_flits_a_valid,\t// @[Tilelink.scala:132:14]\n input io_flits_a_bits_head,\t// @[Tilelink.scala:132:14]\n input io_flits_a_bits_tail,\t// @[Tilelink.scala:132:14]\n input [72:0] io_flits_a_bits_payload,\t// @[Tilelink.scala:132:14]\n output io_flits_b_valid,\t// @[Tilelink.scala:132:14]\n output io_flits_c_ready,\t// @[Tilelink.scala:132:14]\n input io_flits_c_valid,\t// @[Tilelink.scala:132:14]\n input io_flits_c_bits_head,\t// @[Tilelink.scala:132:14]\n input io_flits_c_bits_tail,\t// @[Tilelink.scala:132:14]\n input io_flits_d_ready,\t// @[Tilelink.scala:132:14]\n output io_flits_d_valid,\t// @[Tilelink.scala:132:14]\n output io_flits_d_bits_head,\t// @[Tilelink.scala:132:14]\n output io_flits_d_bits_tail,\t// @[Tilelink.scala:132:14]\n output [72:0] io_flits_d_bits_payload,\t// @[Tilelink.scala:132:14]\n output [3:0] io_flits_d_bits_egress_id,\t// @[Tilelink.scala:132:14]\n output io_flits_e_ready,\t// @[Tilelink.scala:132:14]\n input io_flits_e_valid,\t// @[Tilelink.scala:132:14]\n input io_flits_e_bits_head,\t// @[Tilelink.scala:132:14]\n input io_flits_e_bits_tail\t// @[Tilelink.scala:132:14]\n);\n\n wire [64:0] _d_io_flit_bits_payload;\t// @[Tilelink.scala:146:17]\n TLAFromNoC a (\t// @[Tilelink.scala:143:17]\n .clock (clock),\n .reset (reset),\n .io_protocol_ready (io_tilelink_a_ready),\n .io_protocol_valid (io_tilelink_a_valid),\n .io_protocol_bits_opcode (io_tilelink_a_bits_opcode),\n .io_protocol_bits_param (io_tilelink_a_bits_param),\n .io_protocol_bits_size (io_tilelink_a_bits_size),\n .io_protocol_bits_source (io_tilelink_a_bits_source),\n .io_protocol_bits_address (io_tilelink_a_bits_address),\n .io_protocol_bits_mask (io_tilelink_a_bits_mask),\n .io_protocol_bits_data (io_tilelink_a_bits_data),\n .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),\n .io_flit_ready (io_flits_a_ready),\n .io_flit_valid (io_flits_a_valid),\n .io_flit_bits_head (io_flits_a_bits_head),\n .io_flit_bits_tail (io_flits_a_bits_tail),\n .io_flit_bits_payload (io_flits_a_bits_payload)\n );\t// @[Tilelink.scala:143:17]\n TLBToNoC b (\t// @[Tilelink.scala:144:17]\n .clock (clock),\n .reset (reset),\n .io_flit_valid (io_flits_b_valid)\n );\t// @[Tilelink.scala:144:17]\n TLCFromNoC c (\t// @[Tilelink.scala:145:17]\n .clock (clock),\n .reset (reset),\n .io_flit_ready (io_flits_c_ready),\n .io_flit_valid (io_flits_c_valid),\n .io_flit_bits_head (io_flits_c_bits_head),\n .io_flit_bits_tail (io_flits_c_bits_tail)\n );\t// @[Tilelink.scala:145:17]\n TLDToNoC d (\t// @[Tilelink.scala:146:17]\n .clock (clock),\n .reset (reset),\n .io_protocol_ready (io_tilelink_d_ready),\n .io_protocol_valid (io_tilelink_d_valid),\n .io_protocol_bits_opcode (io_tilelink_d_bits_opcode),\n .io_protocol_bits_param (io_tilelink_d_bits_param),\n .io_protocol_bits_size (io_tilelink_d_bits_size),\n .io_protocol_bits_source (io_tilelink_d_bits_source),\n .io_protocol_bits_sink (io_tilelink_d_bits_sink),\n .io_protocol_bits_denied (io_tilelink_d_bits_denied),\n .io_protocol_bits_data (io_tilelink_d_bits_data),\n .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),\n .io_flit_ready (io_flits_d_ready),\n .io_flit_valid (io_flits_d_valid),\n .io_flit_bits_head (io_flits_d_bits_head),\n .io_flit_bits_tail (io_flits_d_bits_tail),\n .io_flit_bits_payload (_d_io_flit_bits_payload),\n .io_flit_bits_egress_id (io_flits_d_bits_egress_id)\n );\t// @[Tilelink.scala:146:17]\n TLEFromNoC e (\t// @[Tilelink.scala:147:17]\n .clock (clock),\n .reset (reset),\n .io_flit_ready (io_flits_e_ready),\n .io_flit_valid (io_flits_e_valid),\n .io_flit_bits_head (io_flits_e_bits_head),\n .io_flit_bits_tail (io_flits_e_bits_tail)\n );\t// @[Tilelink.scala:147:17]\n assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload};\t// @[Tilelink.scala:125:7, :146:17, :157:14]\nendmodule"}}},{"rowIdx":2090,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile ShiftReg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n// Similar to the Chisel ShiftRegister but allows the user to suggest a\n// name to the registers that get instantiated, and\n// to provide a reset value.\nobject ShiftRegInit {\n def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =\n\n (0 until n).foldRight(in) {\n case (i, next) => {\n val r = RegNext(next, init)\n name.foreach { na => r.suggestName(s\"${na}_${i}\") }\n r\n }\n }\n}\n\n/** These wrap behavioral\n * shift registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * The different types vary in their reset behavior:\n * AsyncResetShiftReg -- Asynchronously reset register array\n * A W(width) x D(depth) sized array is constructed from D instantiations of a\n * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,\n * but only used for timing applications\n */\n\nabstract class AbstractPipelineReg(w: Int = 1) extends Module {\n val io = IO(new Bundle {\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n }\n )\n}\n\nobject AbstractPipelineReg {\n def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {\n val chain = Module(gen)\n name.foreach{ chain.suggestName(_) }\n chain.io.d := in.asUInt\n chain.io.q.asTypeOf(in)\n }\n}\n\nclass AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = \"pipe\") extends AbstractPipelineReg(w) {\n require(depth > 0, \"Depth must be greater than 0.\")\n\n override def desiredName = s\"AsyncResetShiftReg_w${w}_d${depth}_i${init}\"\n\n val chain = List.tabulate(depth) { i =>\n Module (new AsyncResetRegVec(w, init)).suggestName(s\"${name}_${i}\")\n }\n\n chain.last.io.d := io.d\n chain.last.io.en := true.B\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink.io.d := source.io.q\n sink.io.en := true.B\n }\n io.q := chain.head.io.q\n}\n\nobject AsyncResetShiftReg {\n def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)\n\n def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =\n apply(in, depth, 0, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =\n apply(in, depth, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, depth: Int, init: T): T =\n apply (in, depth, init.litValue.toInt, None)\n}\nFile AsyncQueue.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}\n"},"response":{"kind":"string","value":"module AsyncValidSync_177(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_191 io_out_source_valid_1 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":2091,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_48(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [11:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [27:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [11:0] io_in_d_bits_source\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire a_first_done = io_in_a_ready & io_in_a_valid;\t// @[Decoupled.scala:51:35]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [1:0] size;\t// @[Monitor.scala:389:22]\n reg [11:0] source;\t// @[Monitor.scala:390:22]\n reg [27:0] address;\t// @[Monitor.scala:391:22]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg [11:0] source_1;\t// @[Monitor.scala:541:22]\n reg [2063:0] inflight;\t// @[Monitor.scala:614:27]\n reg [8255:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [8255:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [4095:0] _GEN = {4084'h0, io_in_a_bits_source};\t// @[OneHot.scala:58:35]\n wire _GEN_0 = a_first_done & ~a_first_counter_1;\t// @[Decoupled.scala:51:35]\n wire d_release_ack = io_in_d_bits_opcode == 3'h6;\t// @[Monitor.scala:673:46]\n wire _GEN_1 = io_in_d_bits_opcode != 3'h6;\t// @[Monitor.scala:673:46, :674:74]\n wire [4095:0] _GEN_2 = {4084'h0, io_in_d_bits_source};\t// @[OneHot.scala:58:35]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n reg [2063:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [8255:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":2092,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_65(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire [26:0] _GEN = {23'h0, io_in_a_bits_size};\t// @[package.scala:243:71]\n wire _a_first_T_1 = io_in_a_ready & io_in_a_valid;\t// @[Decoupled.scala:51:35]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [3:0] size;\t// @[Monitor.scala:389:22]\n reg source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [3:0] size_1;\t// @[Monitor.scala:540:22]\n reg source_1;\t// @[Monitor.scala:541:22]\n reg [2:0] sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [1:0] inflight;\t// @[Monitor.scala:614:27]\n reg [3:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [7:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n reg [8:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire a_first_1 = a_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [8:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire d_first_1 = d_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _GEN_0 = _a_first_T_1 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire d_release_ack = io_in_d_bits_opcode == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire _GEN_1 = io_in_d_bits_opcode != 3'h6;\t// @[Monitor.scala:36:7, :673:46, :674:74]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n reg [1:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [7:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n reg [8:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire d_first_2 = d_first_counter_2 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":2093,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_40(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [5:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [5:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire [12:0] _GEN = {10'h0, io_in_a_bits_size};\t// @[package.scala:243:71]\n wire _a_first_T_1 = io_in_a_ready & io_in_a_valid;\t// @[Decoupled.scala:51:35]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [5:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [5:0] source_1;\t// @[Monitor.scala:541:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [57:0] inflight;\t// @[Monitor.scala:614:27]\n reg [231:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [231:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source};\t// @[OneHot.scala:58:35]\n wire _GEN_1 = _a_first_T_1 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire d_release_ack = io_in_d_bits_opcode == 3'h6;\t// @[Monitor.scala:673:46]\n wire _GEN_2 = io_in_d_bits_opcode != 3'h6;\t// @[Monitor.scala:673:46, :674:74]\n wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source};\t// @[OneHot.scala:58:35]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n reg [57:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [231:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":2094,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile tage.scala:\npackage boom.v4.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v4.common._\nimport boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f2_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n us.suggestName(s\"tage_u_${histLength}\")\n table.suggestName(s\"tage_table_${histLength}\")\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry))\n val s2_req_rus = Wire(Vec(bankWidth*2, Bool()))\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f2_resp(w).valid := s2_req_rhits(w)\n io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2))\n io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n val wen = WireInit(doing_reset || io.update_mask.reduce(_||_))\n val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid)\n when (RegNext(wen) && singlePorted.B) {\n s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry))\n } .otherwise {\n s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry)))\n }\n when (wen) {\n val widx = Mux(doing_reset, reset_idx, update_idx)\n val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt)))\n val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt)\n table.write(widx, wdata, wmask.asBools)\n }\n\n val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)})\n val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_))\n val u_rdata = if (singlePorted) {\n us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid)\n } else {\n us.read(s1_hashed_idx, io.f1_req_valid)\n }\n s2_req_rus := u_rdata\n when (update_u_wen) {\n val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx))\n val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools))\n val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt))\n us.write(widx, wdata, wmask.asBools)\n }\n\n\n\n\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048,\n singlePorted: Boolean = false\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc))\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f2_resps = VecInit(tables.map(_.io.f2_resp))\n val f3_resps = RegNext(f2_resps)\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var s2_provided = false.B\n var s2_provider = 0.U\n var s2_alt_provided = false.B\n var s2_alt_provider = 0.U\n for (i <- 0 until tageNTables) {\n val hit = f2_resps(i)(w).valid\n s2_alt_provided = s2_alt_provided || (s2_provided && hit)\n s2_provided = s2_provided || hit\n\n s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider)\n s2_provider = Mux(hit, i.U, s2_provider)\n }\n val s3_provided = RegNext(s2_provided)\n val s3_provider = RegNext(s2_provider)\n val s3_alt_provided = RegNext(s2_alt_provided)\n val s3_alt_provider = RegNext(s2_alt_provider)\n\n val prov = RegNext(f2_resps(s2_provider)(w).bits)\n val alt = RegNext(f2_resps(s2_alt_provider)(w).bits)\n\n io.resp.f3(w).taken := Mux(s3_provided,\n Mux(prov.ctr === 3.U || prov.ctr === 4.U,\n Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken),\n prov.ctr(2)),\n io.resp_in(0).f3(w).taken\n )\n f3_meta.provider(w).valid := s3_provided\n f3_meta.provider(w).bits := s3_provider\n f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := prov.u\n f3_meta.provider_ctr(w) := prov.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}\n"},"response":{"kind":"string","value":"module tage_table_64_0(\t// @[tage.scala:90:27]\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [51:0] R0_data,\n input [6:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [51:0] W0_data,\n input [3:0] W0_mask\n);\n\n tage_table_32_ext tage_table_32_ext (\t// @[tage.scala:90:27]\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\t// @[tage.scala:90:27]\nendmodule"}}},{"rowIdx":2095,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Bundles.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport freechips.rocketchip.util._\nimport scala.collection.immutable.ListMap\nimport chisel3.util.Decoupled\nimport chisel3.util.DecoupledIO\nimport chisel3.reflect.DataMirror\n\nabstract class TLBundleBase(val params: TLBundleParameters) extends Bundle\n\n// common combos in lazy policy:\n// Put + Acquire\n// Release + AccessAck\n\nobject TLMessages\n{\n // A B C D E\n def PutFullData = 0.U // . . => AccessAck\n def PutPartialData = 1.U // . . => AccessAck\n def ArithmeticData = 2.U // . . => AccessAckData\n def LogicalData = 3.U // . . => AccessAckData\n def Get = 4.U // . . => AccessAckData\n def Hint = 5.U // . . => HintAck\n def AcquireBlock = 6.U // . => Grant[Data]\n def AcquirePerm = 7.U // . => Grant[Data]\n def Probe = 6.U // . => ProbeAck[Data]\n def AccessAck = 0.U // . .\n def AccessAckData = 1.U // . .\n def HintAck = 2.U // . .\n def ProbeAck = 4.U // .\n def ProbeAckData = 5.U // .\n def Release = 6.U // . => ReleaseAck\n def ReleaseData = 7.U // . => ReleaseAck\n def Grant = 4.U // . => GrantAck\n def GrantData = 5.U // . => GrantAck\n def ReleaseAck = 6.U // .\n def GrantAck = 0.U // .\n\n def isA(x: UInt) = x <= AcquirePerm\n def isB(x: UInt) = x <= Probe\n def isC(x: UInt) = x <= ReleaseData\n def isD(x: UInt) = x <= ReleaseAck\n\n def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)\n def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)\n\n def a = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"AcquireBlock\",TLPermissions.PermMsgGrow),\n (\"AcquirePerm\",TLPermissions.PermMsgGrow))\n\n def b = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"Probe\",TLPermissions.PermMsgCap))\n\n def c = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"ProbeAck\",TLPermissions.PermMsgReport),\n (\"ProbeAckData\",TLPermissions.PermMsgReport),\n (\"Release\",TLPermissions.PermMsgReport),\n (\"ReleaseData\",TLPermissions.PermMsgReport))\n\n def d = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"Grant\",TLPermissions.PermMsgCap),\n (\"GrantData\",TLPermissions.PermMsgCap),\n (\"ReleaseAck\",TLPermissions.PermMsgReserved))\n\n}\n\n/**\n * The three primary TileLink permissions are:\n * (T)runk: the agent is (or is on inwards path to) the global point of serialization.\n * (B)ranch: the agent is on an outwards path to\n * (N)one:\n * These permissions are permuted by transfer operations in various ways.\n * Operations can cap permissions, request for them to be grown or shrunk,\n * or for a report on their current status.\n */\nobject TLPermissions\n{\n val aWidth = 2\n val bdWidth = 2\n val cWidth = 3\n\n // Cap types (Grant = new permissions, Probe = permisions <= target)\n def toT = 0.U(bdWidth.W)\n def toB = 1.U(bdWidth.W)\n def toN = 2.U(bdWidth.W)\n def isCap(x: UInt) = x <= toN\n\n // Grow types (Acquire = permissions >= target)\n def NtoB = 0.U(aWidth.W)\n def NtoT = 1.U(aWidth.W)\n def BtoT = 2.U(aWidth.W)\n def isGrow(x: UInt) = x <= BtoT\n\n // Shrink types (ProbeAck, Release)\n def TtoB = 0.U(cWidth.W)\n def TtoN = 1.U(cWidth.W)\n def BtoN = 2.U(cWidth.W)\n def isShrink(x: UInt) = x <= BtoN\n\n // Report types (ProbeAck, Release)\n def TtoT = 3.U(cWidth.W)\n def BtoB = 4.U(cWidth.W)\n def NtoN = 5.U(cWidth.W)\n def isReport(x: UInt) = x <= NtoN\n\n def PermMsgGrow:Seq[String] = Seq(\"Grow NtoB\", \"Grow NtoT\", \"Grow BtoT\")\n def PermMsgCap:Seq[String] = Seq(\"Cap toT\", \"Cap toB\", \"Cap toN\")\n def PermMsgReport:Seq[String] = Seq(\"Shrink TtoB\", \"Shrink TtoN\", \"Shrink BtoN\", \"Report TotT\", \"Report BtoB\", \"Report NtoN\")\n def PermMsgReserved:Seq[String] = Seq(\"Reserved\")\n}\n\nobject TLAtomics\n{\n val width = 3\n\n // Arithmetic types\n def MIN = 0.U(width.W)\n def MAX = 1.U(width.W)\n def MINU = 2.U(width.W)\n def MAXU = 3.U(width.W)\n def ADD = 4.U(width.W)\n def isArithmetic(x: UInt) = x <= ADD\n\n // Logical types\n def XOR = 0.U(width.W)\n def OR = 1.U(width.W)\n def AND = 2.U(width.W)\n def SWAP = 3.U(width.W)\n def isLogical(x: UInt) = x <= SWAP\n\n def ArithMsg:Seq[String] = Seq(\"MIN\", \"MAX\", \"MINU\", \"MAXU\", \"ADD\")\n def LogicMsg:Seq[String] = Seq(\"XOR\", \"OR\", \"AND\", \"SWAP\")\n}\n\n\nobject TLHints\n{\n val width = 1\n\n def PREFETCH_READ = 0.U(width.W)\n def PREFETCH_WRITE = 1.U(width.W)\n def isHints(x: UInt) = x <= PREFETCH_WRITE\n\n def HintsMsg:Seq[String] = Seq(\"PrefetchRead\", \"PrefetchWrite\")\n}\n\nsealed trait TLChannel extends TLBundleBase {\n val channelName: String\n}\n\nsealed trait TLDataChannel extends TLChannel\nsealed trait TLAddrChannel extends TLDataChannel\n\nfinal class TLBundleA(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleA_${params.shortName}\"\n val channelName = \"'A' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\nfinal class TLBundleB(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleB_${params.shortName}\"\n val channelName = \"'B' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val address = UInt(params.addressBits.W) // from\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleC(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleC_${params.shortName}\"\n val channelName = \"'C' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.cWidth.W) // shrink or report perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleD(params: TLBundleParameters)\n extends TLBundleBase(params) with TLDataChannel\n{\n override def typeName = s\"TLBundleD_${params.shortName}\"\n val channelName = \"'D' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val sink = UInt(params.sinkBits.W) // from\n val denied = Bool() // implies corrupt iff *Data\n val user = BundleMap(params.responseFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleE(params: TLBundleParameters)\n extends TLBundleBase(params) with TLChannel\n{\n override def typeName = s\"TLBundleE_${params.shortName}\"\n val channelName = \"'E' channel\"\n val sink = UInt(params.sinkBits.W) // to\n}\n\nclass TLBundle(val params: TLBundleParameters) extends Record\n{\n // Emulate a Bundle with elements abcde or ad depending on params.hasBCE\n\n private val optA = Some (Decoupled(new TLBundleA(params)))\n private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))\n private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))\n private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))\n private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))\n\n def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))\n def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))\n def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))\n def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))\n def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))\n\n val elements =\n if (params.hasBCE) ListMap(\"e\" -> e, \"d\" -> d, \"c\" -> c, \"b\" -> b, \"a\" -> a)\n else ListMap(\"d\" -> d, \"a\" -> a)\n\n def tieoff(): Unit = {\n DataMirror.specifiedDirectionOf(a.ready) match {\n case SpecifiedDirection.Input =>\n a.ready := false.B\n c.ready := false.B\n e.ready := false.B\n b.valid := false.B\n d.valid := false.B\n case SpecifiedDirection.Output =>\n a.valid := false.B\n c.valid := false.B\n e.valid := false.B\n b.ready := false.B\n d.ready := false.B\n case _ =>\n }\n }\n}\n\nobject TLBundle\n{\n def apply(params: TLBundleParameters) = new TLBundle(params)\n}\n\nclass TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle\n\nclass TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)\n{\n val a = new AsyncBundle(new TLBundleA(params.base), params.async)\n val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))\n val c = new AsyncBundle(new TLBundleC(params.base), params.async)\n val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))\n val e = new AsyncBundle(new TLBundleE(params.base), params.async)\n}\n\nclass TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = RationalIO(new TLBundleA(params))\n val b = Flipped(RationalIO(new TLBundleB(params)))\n val c = RationalIO(new TLBundleC(params))\n val d = Flipped(RationalIO(new TLBundleD(params)))\n val e = RationalIO(new TLBundleE(params))\n}\n\nclass TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = CreditedIO(new TLBundleA(params))\n val b = Flipped(CreditedIO(new TLBundleB(params)))\n val c = CreditedIO(new TLBundleC(params))\n val d = Flipped(CreditedIO(new TLBundleD(params)))\n val e = CreditedIO(new TLBundleE(params))\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.nodes._\n\nimport freechips.rocketchip.diplomacy.{\n AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,\n IdRange, RegionType, TransferSizes\n}\nimport freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}\nimport freechips.rocketchip.util.{\n AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,\n CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct\n}\n\nimport scala.math.max\n\n//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel\ncase class TLMasterToSlaveTransferSizes(\n // Supports both Acquire+Release of the following two sizes:\n acquireT: TransferSizes = TransferSizes.none,\n acquireB: TransferSizes = TransferSizes.none,\n arithmetic: TransferSizes = TransferSizes.none,\n logical: TransferSizes = TransferSizes.none,\n get: TransferSizes = TransferSizes.none,\n putFull: TransferSizes = TransferSizes.none,\n putPartial: TransferSizes = TransferSizes.none,\n hint: TransferSizes = TransferSizes.none)\n extends TLCommonTransferSizes {\n def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(\n acquireT = acquireT .intersect(rhs.acquireT),\n acquireB = acquireB .intersect(rhs.acquireB),\n arithmetic = arithmetic.intersect(rhs.arithmetic),\n logical = logical .intersect(rhs.logical),\n get = get .intersect(rhs.get),\n putFull = putFull .intersect(rhs.putFull),\n putPartial = putPartial.intersect(rhs.putPartial),\n hint = hint .intersect(rhs.hint))\n def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(\n acquireT = acquireT .mincover(rhs.acquireT),\n acquireB = acquireB .mincover(rhs.acquireB),\n arithmetic = arithmetic.mincover(rhs.arithmetic),\n logical = logical .mincover(rhs.logical),\n get = get .mincover(rhs.get),\n putFull = putFull .mincover(rhs.putFull),\n putPartial = putPartial.mincover(rhs.putPartial),\n hint = hint .mincover(rhs.hint))\n // Reduce rendering to a simple yes/no per field\n override def toString = {\n def str(x: TransferSizes, flag: String) = if (x.none) \"\" else flag\n def flags = Vector(\n str(acquireT, \"T\"),\n str(acquireB, \"B\"),\n str(arithmetic, \"A\"),\n str(logical, \"L\"),\n str(get, \"G\"),\n str(putFull, \"F\"),\n str(putPartial, \"P\"),\n str(hint, \"H\"))\n flags.mkString\n }\n // Prints out the actual information in a user readable way\n def infoString = {\n s\"\"\"acquireT = ${acquireT}\n |acquireB = ${acquireB}\n |arithmetic = ${arithmetic}\n |logical = ${logical}\n |get = ${get}\n |putFull = ${putFull}\n |putPartial = ${putPartial}\n |hint = ${hint}\n |\n |\"\"\".stripMargin\n }\n}\n\nobject TLMasterToSlaveTransferSizes {\n def unknownEmits = TLMasterToSlaveTransferSizes(\n acquireT = TransferSizes(1, 4096),\n acquireB = TransferSizes(1, 4096),\n arithmetic = TransferSizes(1, 4096),\n logical = TransferSizes(1, 4096),\n get = TransferSizes(1, 4096),\n putFull = TransferSizes(1, 4096),\n putPartial = TransferSizes(1, 4096),\n hint = TransferSizes(1, 4096))\n def unknownSupports = TLMasterToSlaveTransferSizes()\n}\n\n//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel\ncase class TLSlaveToMasterTransferSizes(\n probe: TransferSizes = TransferSizes.none,\n arithmetic: TransferSizes = TransferSizes.none,\n logical: TransferSizes = TransferSizes.none,\n get: TransferSizes = TransferSizes.none,\n putFull: TransferSizes = TransferSizes.none,\n putPartial: TransferSizes = TransferSizes.none,\n hint: TransferSizes = TransferSizes.none\n) extends TLCommonTransferSizes {\n def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(\n probe = probe .intersect(rhs.probe),\n arithmetic = arithmetic.intersect(rhs.arithmetic),\n logical = logical .intersect(rhs.logical),\n get = get .intersect(rhs.get),\n putFull = putFull .intersect(rhs.putFull),\n putPartial = putPartial.intersect(rhs.putPartial),\n hint = hint .intersect(rhs.hint)\n )\n def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(\n probe = probe .mincover(rhs.probe),\n arithmetic = arithmetic.mincover(rhs.arithmetic),\n logical = logical .mincover(rhs.logical),\n get = get .mincover(rhs.get),\n putFull = putFull .mincover(rhs.putFull),\n putPartial = putPartial.mincover(rhs.putPartial),\n hint = hint .mincover(rhs.hint)\n )\n // Reduce rendering to a simple yes/no per field\n override def toString = {\n def str(x: TransferSizes, flag: String) = if (x.none) \"\" else flag\n def flags = Vector(\n str(probe, \"P\"),\n str(arithmetic, \"A\"),\n str(logical, \"L\"),\n str(get, \"G\"),\n str(putFull, \"F\"),\n str(putPartial, \"P\"),\n str(hint, \"H\"))\n flags.mkString\n }\n // Prints out the actual information in a user readable way\n def infoString = {\n s\"\"\"probe = ${probe}\n |arithmetic = ${arithmetic}\n |logical = ${logical}\n |get = ${get}\n |putFull = ${putFull}\n |putPartial = ${putPartial}\n |hint = ${hint}\n |\n |\"\"\".stripMargin\n }\n}\n\nobject TLSlaveToMasterTransferSizes {\n def unknownEmits = TLSlaveToMasterTransferSizes(\n arithmetic = TransferSizes(1, 4096),\n logical = TransferSizes(1, 4096),\n get = TransferSizes(1, 4096),\n putFull = TransferSizes(1, 4096),\n putPartial = TransferSizes(1, 4096),\n hint = TransferSizes(1, 4096),\n probe = TransferSizes(1, 4096))\n def unknownSupports = TLSlaveToMasterTransferSizes()\n}\n\ntrait TLCommonTransferSizes {\n def arithmetic: TransferSizes\n def logical: TransferSizes\n def get: TransferSizes\n def putFull: TransferSizes\n def putPartial: TransferSizes\n def hint: TransferSizes\n}\n\nclass TLSlaveParameters private(\n val nodePath: Seq[BaseNode],\n val resources: Seq[Resource],\n setName: Option[String],\n val address: Seq[AddressSet],\n val regionType: RegionType.T,\n val executable: Boolean,\n val fifoId: Option[Int],\n val supports: TLMasterToSlaveTransferSizes,\n val emits: TLSlaveToMasterTransferSizes,\n // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)\n val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData\n // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order\n // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo\n val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData\n val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck\n // ReleaseAck may NEVER be denied\n extends SimpleProduct\n{\n def sortedAddress = address.sorted\n override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]\n override def productPrefix = \"TLSlaveParameters\"\n // We intentionally omit nodePath for equality testing / formatting\n def productArity: Int = 11\n def productElement(n: Int): Any = n match {\n case 0 => name\n case 1 => address\n case 2 => resources\n case 3 => regionType\n case 4 => executable\n case 5 => fifoId\n case 6 => supports\n case 7 => emits\n case 8 => alwaysGrantsT\n case 9 => mayDenyGet\n case 10 => mayDenyPut\n case _ => throw new IndexOutOfBoundsException(n.toString)\n }\n\n def supportsAcquireT: TransferSizes = supports.acquireT\n def supportsAcquireB: TransferSizes = supports.acquireB\n def supportsArithmetic: TransferSizes = supports.arithmetic\n def supportsLogical: TransferSizes = supports.logical\n def supportsGet: TransferSizes = supports.get\n def supportsPutFull: TransferSizes = supports.putFull\n def supportsPutPartial: TransferSizes = supports.putPartial\n def supportsHint: TransferSizes = supports.hint\n\n require (!address.isEmpty, \"Address cannot be empty\")\n address.foreach { a => require (a.finite, \"Address must be finite\") }\n\n address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s\"$x and $y overlap.\") }\n require (supportsPutFull.contains(supportsPutPartial), s\"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)\")\n require (supportsPutFull.contains(supportsArithmetic), s\"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)\")\n require (supportsPutFull.contains(supportsLogical), s\"PutFull($supportsPutFull) < Logical($supportsLogical)\")\n require (supportsGet.contains(supportsArithmetic), s\"Get($supportsGet) < Arithmetic($supportsArithmetic)\")\n require (supportsGet.contains(supportsLogical), s\"Get($supportsGet) < Logical($supportsLogical)\")\n require (supportsAcquireB.contains(supportsAcquireT), s\"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)\")\n require (!alwaysGrantsT || supportsAcquireT, s\"Must supportAcquireT if promising to always grantT\")\n\n // Make sure that the regionType agrees with the capabilities\n require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached\n require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire\n require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet\n\n val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse(\"disconnected\")\n val maxTransfer = List( // Largest supported transfer of all types\n supportsAcquireT.max,\n supportsAcquireB.max,\n supportsArithmetic.max,\n supportsLogical.max,\n supportsGet.max,\n supportsPutFull.max,\n supportsPutPartial.max).max\n val maxAddress = address.map(_.max).max\n val minAlignment = address.map(_.alignment).min\n\n // The device had better not support a transfer larger than its alignment\n require (minAlignment >= maxTransfer, s\"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)\")\n\n def toResource: ResourceAddress = {\n ResourceAddress(address, ResourcePermissions(\n r = supportsAcquireB || supportsGet,\n w = supportsAcquireT || supportsPutFull,\n x = executable,\n c = supportsAcquireB,\n a = supportsArithmetic && supportsLogical))\n }\n\n def findTreeViolation() = nodePath.find {\n case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false\n case _: SinkNode[_, _, _, _, _] => false\n case node => node.inputs.size != 1\n }\n def isTree = findTreeViolation() == None\n\n def infoString = {\n s\"\"\"Slave Name = ${name}\n |Slave Address = ${address}\n |supports = ${supports.infoString}\n |\n |\"\"\".stripMargin\n }\n\n def v1copy(\n address: Seq[AddressSet] = address,\n resources: Seq[Resource] = resources,\n regionType: RegionType.T = regionType,\n executable: Boolean = executable,\n nodePath: Seq[BaseNode] = nodePath,\n supportsAcquireT: TransferSizes = supports.acquireT,\n supportsAcquireB: TransferSizes = supports.acquireB,\n supportsArithmetic: TransferSizes = supports.arithmetic,\n supportsLogical: TransferSizes = supports.logical,\n supportsGet: TransferSizes = supports.get,\n supportsPutFull: TransferSizes = supports.putFull,\n supportsPutPartial: TransferSizes = supports.putPartial,\n supportsHint: TransferSizes = supports.hint,\n mayDenyGet: Boolean = mayDenyGet,\n mayDenyPut: Boolean = mayDenyPut,\n alwaysGrantsT: Boolean = alwaysGrantsT,\n fifoId: Option[Int] = fifoId) =\n {\n new TLSlaveParameters(\n setName = setName,\n address = address,\n resources = resources,\n regionType = regionType,\n executable = executable,\n nodePath = nodePath,\n supports = TLMasterToSlaveTransferSizes(\n acquireT = supportsAcquireT,\n acquireB = supportsAcquireB,\n arithmetic = supportsArithmetic,\n logical = supportsLogical,\n get = supportsGet,\n putFull = supportsPutFull,\n putPartial = supportsPutPartial,\n hint = supportsHint),\n emits = emits,\n mayDenyGet = mayDenyGet,\n mayDenyPut = mayDenyPut,\n alwaysGrantsT = alwaysGrantsT,\n fifoId = fifoId)\n }\n\n def v2copy(\n nodePath: Seq[BaseNode] = nodePath,\n resources: Seq[Resource] = resources,\n name: Option[String] = setName,\n address: Seq[AddressSet] = address,\n regionType: RegionType.T = regionType,\n executable: Boolean = executable,\n fifoId: Option[Int] = fifoId,\n supports: TLMasterToSlaveTransferSizes = supports,\n emits: TLSlaveToMasterTransferSizes = emits,\n alwaysGrantsT: Boolean = alwaysGrantsT,\n mayDenyGet: Boolean = mayDenyGet,\n mayDenyPut: Boolean = mayDenyPut) =\n {\n new TLSlaveParameters(\n nodePath = nodePath,\n resources = resources,\n setName = name,\n address = address,\n regionType = regionType,\n executable = executable,\n fifoId = fifoId,\n supports = supports,\n emits = emits,\n alwaysGrantsT = alwaysGrantsT,\n mayDenyGet = mayDenyGet,\n mayDenyPut = mayDenyPut)\n }\n\n @deprecated(\"Use v1copy instead of copy\",\"\")\n def copy(\n address: Seq[AddressSet] = address,\n resources: Seq[Resource] = resources,\n regionType: RegionType.T = regionType,\n executable: Boolean = executable,\n nodePath: Seq[BaseNode] = nodePath,\n supportsAcquireT: TransferSizes = supports.acquireT,\n supportsAcquireB: TransferSizes = supports.acquireB,\n supportsArithmetic: TransferSizes = supports.arithmetic,\n supportsLogical: TransferSizes = supports.logical,\n supportsGet: TransferSizes = supports.get,\n supportsPutFull: TransferSizes = supports.putFull,\n supportsPutPartial: TransferSizes = supports.putPartial,\n supportsHint: TransferSizes = supports.hint,\n mayDenyGet: Boolean = mayDenyGet,\n mayDenyPut: Boolean = mayDenyPut,\n alwaysGrantsT: Boolean = alwaysGrantsT,\n fifoId: Option[Int] = fifoId) =\n {\n v1copy(\n address = address,\n resources = resources,\n regionType = regionType,\n executable = executable,\n nodePath = nodePath,\n supportsAcquireT = supportsAcquireT,\n supportsAcquireB = supportsAcquireB,\n supportsArithmetic = supportsArithmetic,\n supportsLogical = supportsLogical,\n supportsGet = supportsGet,\n supportsPutFull = supportsPutFull,\n supportsPutPartial = supportsPutPartial,\n supportsHint = supportsHint,\n mayDenyGet = mayDenyGet,\n mayDenyPut = mayDenyPut,\n alwaysGrantsT = alwaysGrantsT,\n fifoId = fifoId)\n }\n}\n\nobject TLSlaveParameters {\n def v1(\n address: Seq[AddressSet],\n resources: Seq[Resource] = Seq(),\n regionType: RegionType.T = RegionType.GET_EFFECTS,\n executable: Boolean = false,\n nodePath: Seq[BaseNode] = Seq(),\n supportsAcquireT: TransferSizes = TransferSizes.none,\n supportsAcquireB: TransferSizes = TransferSizes.none,\n supportsArithmetic: TransferSizes = TransferSizes.none,\n supportsLogical: TransferSizes = TransferSizes.none,\n supportsGet: TransferSizes = TransferSizes.none,\n supportsPutFull: TransferSizes = TransferSizes.none,\n supportsPutPartial: TransferSizes = TransferSizes.none,\n supportsHint: TransferSizes = TransferSizes.none,\n mayDenyGet: Boolean = false,\n mayDenyPut: Boolean = false,\n alwaysGrantsT: Boolean = false,\n fifoId: Option[Int] = None) =\n {\n new TLSlaveParameters(\n setName = None,\n address = address,\n resources = resources,\n regionType = regionType,\n executable = executable,\n nodePath = nodePath,\n supports = TLMasterToSlaveTransferSizes(\n acquireT = supportsAcquireT,\n acquireB = supportsAcquireB,\n arithmetic = supportsArithmetic,\n logical = supportsLogical,\n get = supportsGet,\n putFull = supportsPutFull,\n putPartial = supportsPutPartial,\n hint = supportsHint),\n emits = TLSlaveToMasterTransferSizes.unknownEmits,\n mayDenyGet = mayDenyGet,\n mayDenyPut = mayDenyPut,\n alwaysGrantsT = alwaysGrantsT,\n fifoId = fifoId)\n }\n\n def v2(\n address: Seq[AddressSet],\n nodePath: Seq[BaseNode] = Seq(),\n resources: Seq[Resource] = Seq(),\n name: Option[String] = None,\n regionType: RegionType.T = RegionType.GET_EFFECTS,\n executable: Boolean = false,\n fifoId: Option[Int] = None,\n supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,\n emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,\n alwaysGrantsT: Boolean = false,\n mayDenyGet: Boolean = false,\n mayDenyPut: Boolean = false) =\n {\n new TLSlaveParameters(\n nodePath = nodePath,\n resources = resources,\n setName = name,\n address = address,\n regionType = regionType,\n executable = executable,\n fifoId = fifoId,\n supports = supports,\n emits = emits,\n alwaysGrantsT = alwaysGrantsT,\n mayDenyGet = mayDenyGet,\n mayDenyPut = mayDenyPut)\n }\n}\n\nobject TLManagerParameters {\n @deprecated(\"Use TLSlaveParameters.v1 instead of TLManagerParameters\",\"\")\n def apply(\n address: Seq[AddressSet],\n resources: Seq[Resource] = Seq(),\n regionType: RegionType.T = RegionType.GET_EFFECTS,\n executable: Boolean = false,\n nodePath: Seq[BaseNode] = Seq(),\n supportsAcquireT: TransferSizes = TransferSizes.none,\n supportsAcquireB: TransferSizes = TransferSizes.none,\n supportsArithmetic: TransferSizes = TransferSizes.none,\n supportsLogical: TransferSizes = TransferSizes.none,\n supportsGet: TransferSizes = TransferSizes.none,\n supportsPutFull: TransferSizes = TransferSizes.none,\n supportsPutPartial: TransferSizes = TransferSizes.none,\n supportsHint: TransferSizes = TransferSizes.none,\n mayDenyGet: Boolean = false,\n mayDenyPut: Boolean = false,\n alwaysGrantsT: Boolean = false,\n fifoId: Option[Int] = None) =\n TLSlaveParameters.v1(\n address,\n resources,\n regionType,\n executable,\n nodePath,\n supportsAcquireT,\n supportsAcquireB,\n supportsArithmetic,\n supportsLogical,\n supportsGet,\n supportsPutFull,\n supportsPutPartial,\n supportsHint,\n mayDenyGet,\n mayDenyPut,\n alwaysGrantsT,\n fifoId,\n )\n}\n\ncase class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])\n{\n def members = Seq(a, b, c, d)\n members.collect { case Some(beatBytes) =>\n require (isPow2(beatBytes), \"Data channel width must be a power of 2\")\n }\n}\n\nobject TLChannelBeatBytes{\n def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(\n Some(beatBytes),\n Some(beatBytes),\n Some(beatBytes),\n Some(beatBytes))\n def apply(): TLChannelBeatBytes = TLChannelBeatBytes(\n None,\n None,\n None,\n None)\n}\n\nclass TLSlavePortParameters private(\n val slaves: Seq[TLSlaveParameters],\n val channelBytes: TLChannelBeatBytes,\n val endSinkId: Int,\n val minLatency: Int,\n val responseFields: Seq[BundleFieldBase],\n val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct\n{\n def sortedSlaves = slaves.sortBy(_.sortedAddress.head)\n override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]\n override def productPrefix = \"TLSlavePortParameters\"\n def productArity: Int = 6\n def productElement(n: Int): Any = n match {\n case 0 => slaves\n case 1 => channelBytes\n case 2 => endSinkId\n case 3 => minLatency\n case 4 => responseFields\n case 5 => requestKeys\n case _ => throw new IndexOutOfBoundsException(n.toString)\n }\n\n require (!slaves.isEmpty, \"Slave ports must have slaves\")\n require (endSinkId >= 0, \"Sink ids cannot be negative\")\n require (minLatency >= 0, \"Minimum required latency cannot be negative\")\n\n // Using this API implies you cannot handle mixed-width busses\n def beatBytes = {\n channelBytes.members.foreach { width =>\n require (width.isDefined && width == channelBytes.a)\n }\n channelBytes.a.get\n }\n\n // TODO this should be deprecated\n def managers = slaves\n\n def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {\n val relevant = slaves.filter(m => policy(m))\n relevant.foreach { m =>\n require(m.fifoId == relevant.head.fifoId, s\"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) \")\n }\n }\n\n // Bounds on required sizes\n def maxAddress = slaves.map(_.maxAddress).max\n def maxTransfer = slaves.map(_.maxTransfer).max\n def mayDenyGet = slaves.exists(_.mayDenyGet)\n def mayDenyPut = slaves.exists(_.mayDenyPut)\n\n // Diplomatically determined operation sizes emitted by all outward Slaves\n // as opposed to emits* which generate circuitry to check which specific addresses\n val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)\n\n // Operation Emitted by at least one outward Slaves\n // as opposed to emits* which generate circuitry to check which specific addresses\n val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)\n\n // Diplomatically determined operation sizes supported by all outward Slaves\n // as opposed to supports* which generate circuitry to check which specific addresses\n val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)\n val allSupportAcquireT = allSupportClaims.acquireT\n val allSupportAcquireB = allSupportClaims.acquireB\n val allSupportArithmetic = allSupportClaims.arithmetic\n val allSupportLogical = allSupportClaims.logical\n val allSupportGet = allSupportClaims.get\n val allSupportPutFull = allSupportClaims.putFull\n val allSupportPutPartial = allSupportClaims.putPartial\n val allSupportHint = allSupportClaims.hint\n\n // Operation supported by at least one outward Slaves\n // as opposed to supports* which generate circuitry to check which specific addresses\n val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)\n val anySupportAcquireT = !anySupportClaims.acquireT.none\n val anySupportAcquireB = !anySupportClaims.acquireB.none\n val anySupportArithmetic = !anySupportClaims.arithmetic.none\n val anySupportLogical = !anySupportClaims.logical.none\n val anySupportGet = !anySupportClaims.get.none\n val anySupportPutFull = !anySupportClaims.putFull.none\n val anySupportPutPartial = !anySupportClaims.putPartial.none\n val anySupportHint = !anySupportClaims.hint.none\n\n // Supporting Acquire means being routable for GrantAck\n require ((endSinkId == 0) == !anySupportAcquireB)\n\n // These return Option[TLSlaveParameters] for your convenience\n def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))\n\n // The safe version will check the entire address\n def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))\n // The fast version assumes the address is valid (you probably want fastProperty instead of this function)\n def findFast(address: UInt) = {\n val routingMask = AddressDecoder(slaves.map(_.address))\n VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))\n }\n\n // Compute the simplest AddressSets that decide a key\n def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {\n val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>\n k -> vs.flatMap(_._2)\n }\n val reductionMask = AddressDecoder(groups.map(_._2))\n groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }\n }\n // Select a property\n def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =\n Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })\n\n // Note: returns the actual fifoId + 1 or 0 if None\n def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)\n def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)\n\n // Does this Port manage this ID/address?\n def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)\n\n private def addressHelper(\n // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity\n safe: Boolean,\n // member filters out the sizes being checked based on the opcode being emitted or supported\n member: TLSlaveParameters => TransferSizes,\n address: UInt,\n lgSize: UInt,\n // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity\n range: Option[TransferSizes]): Bool = {\n // trim reduces circuit complexity by intersecting checked sizes with the range argument\n def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)\n // groupBy returns an unordered map, convert back to Seq and sort the result for determinism\n // groupByIntoSeq is turning slaves into trimmed membership sizes\n // We are grouping all the slaves by their transfer size where\n // if they support the trimmed size then\n // member is the type of transfer that you are looking for (What you are trying to filter on)\n // When you consider membership, you are trimming the sizes to only the ones that you care about\n // you are filtering the slaves based on both whether they support a particular opcode and the size\n // Grouping the slaves based on the actual transfer size range they support\n // intersecting the range and checking their membership\n // FOR SUPPORTCASES instead of returning the list of slaves,\n // you are returning a map from transfer size to the set of\n // address sets that are supported for that transfer size\n\n // find all the slaves that support a certain type of operation and then group their addresses by the supported size\n // for every size there could be multiple address ranges\n // safety is a trade off between checking between all possible addresses vs only the addresses\n // that are known to have supported sizes\n // the trade off is 'checking all addresses is a more expensive circuit but will always give you\n // the right answer even if you give it an illegal address'\n // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer\n // fast presumes address legality\n\n // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.\n // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.\n val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>\n k -> vs.flatMap(_.address)\n }\n // safe produces a circuit that compares against all possible addresses,\n // whereas fast presumes that the address is legal but uses an efficient address decoder\n val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))\n // Simplified creates the most concise possible representation of each cases' address sets based on the mask.\n val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }\n simplified.map { case (s, a) =>\n // s is a size, you are checking for this size either the size of the operation is in s\n // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.\n ((Some(s) == range).B || s.containsLg(lgSize)) &&\n a.map(_.contains(address)).reduce(_||_)\n }.foldLeft(false.B)(_||_)\n }\n\n def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)\n def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)\n def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)\n def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)\n def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)\n def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)\n def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)\n def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)\n\n def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)\n def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)\n def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)\n def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)\n def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)\n def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)\n def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)\n def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)\n\n def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)\n def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)\n def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)\n def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)\n def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)\n def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)\n def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)\n\n def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption\n def isTree = !slaves.exists(!_.isTree)\n\n def infoString = \"Slave Port Beatbytes = \" + beatBytes + \"\\n\" + \"Slave Port MinLatency = \" + minLatency + \"\\n\\n\" + slaves.map(_.infoString).mkString\n\n def v1copy(\n managers: Seq[TLSlaveParameters] = slaves,\n beatBytes: Int = -1,\n endSinkId: Int = endSinkId,\n minLatency: Int = minLatency,\n responseFields: Seq[BundleFieldBase] = responseFields,\n requestKeys: Seq[BundleKeyBase] = requestKeys) =\n {\n new TLSlavePortParameters(\n slaves = managers,\n channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,\n endSinkId = endSinkId,\n minLatency = minLatency,\n responseFields = responseFields,\n requestKeys = requestKeys)\n }\n\n def v2copy(\n slaves: Seq[TLSlaveParameters] = slaves,\n channelBytes: TLChannelBeatBytes = channelBytes,\n endSinkId: Int = endSinkId,\n minLatency: Int = minLatency,\n responseFields: Seq[BundleFieldBase] = responseFields,\n requestKeys: Seq[BundleKeyBase] = requestKeys) =\n {\n new TLSlavePortParameters(\n slaves = slaves,\n channelBytes = channelBytes,\n endSinkId = endSinkId,\n minLatency = minLatency,\n responseFields = responseFields,\n requestKeys = requestKeys)\n }\n\n @deprecated(\"Use v1copy instead of copy\",\"\")\n def copy(\n managers: Seq[TLSlaveParameters] = slaves,\n beatBytes: Int = -1,\n endSinkId: Int = endSinkId,\n minLatency: Int = minLatency,\n responseFields: Seq[BundleFieldBase] = responseFields,\n requestKeys: Seq[BundleKeyBase] = requestKeys) =\n {\n v1copy(\n managers,\n beatBytes,\n endSinkId,\n minLatency,\n responseFields,\n requestKeys)\n }\n}\n\nobject TLSlavePortParameters {\n def v1(\n managers: Seq[TLSlaveParameters],\n beatBytes: Int,\n endSinkId: Int = 0,\n minLatency: Int = 0,\n responseFields: Seq[BundleFieldBase] = Nil,\n requestKeys: Seq[BundleKeyBase] = Nil) =\n {\n new TLSlavePortParameters(\n slaves = managers,\n channelBytes = TLChannelBeatBytes(beatBytes),\n endSinkId = endSinkId,\n minLatency = minLatency,\n responseFields = responseFields,\n requestKeys = requestKeys)\n }\n\n}\n\nobject TLManagerPortParameters {\n @deprecated(\"Use TLSlavePortParameters.v1 instead of TLManagerPortParameters\",\"\")\n def apply(\n managers: Seq[TLSlaveParameters],\n beatBytes: Int,\n endSinkId: Int = 0,\n minLatency: Int = 0,\n responseFields: Seq[BundleFieldBase] = Nil,\n requestKeys: Seq[BundleKeyBase] = Nil) =\n {\n TLSlavePortParameters.v1(\n managers,\n beatBytes,\n endSinkId,\n minLatency,\n responseFields,\n requestKeys)\n }\n}\n\nclass TLMasterParameters private(\n val nodePath: Seq[BaseNode],\n val resources: Seq[Resource],\n val name: String,\n val visibility: Seq[AddressSet],\n val unusedRegionTypes: Set[RegionType.T],\n val executesOnly: Boolean,\n val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.\n val supports: TLSlaveToMasterTransferSizes,\n val emits: TLMasterToSlaveTransferSizes,\n val neverReleasesData: Boolean,\n val sourceId: IdRange) extends SimpleProduct\n{\n override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]\n override def productPrefix = \"TLMasterParameters\"\n // We intentionally omit nodePath for equality testing / formatting\n def productArity: Int = 10\n def productElement(n: Int): Any = n match {\n case 0 => name\n case 1 => sourceId\n case 2 => resources\n case 3 => visibility\n case 4 => unusedRegionTypes\n case 5 => executesOnly\n case 6 => requestFifo\n case 7 => supports\n case 8 => emits\n case 9 => neverReleasesData\n case _ => throw new IndexOutOfBoundsException(n.toString)\n }\n\n require (!sourceId.isEmpty)\n require (!visibility.isEmpty)\n require (supports.putFull.contains(supports.putPartial))\n // We only support these operations if we support Probe (ie: we're a cache)\n require (supports.probe.contains(supports.arithmetic))\n require (supports.probe.contains(supports.logical))\n require (supports.probe.contains(supports.get))\n require (supports.probe.contains(supports.putFull))\n require (supports.probe.contains(supports.putPartial))\n require (supports.probe.contains(supports.hint))\n\n visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s\"$x and $y overlap.\") }\n\n val maxTransfer = List(\n supports.probe.max,\n supports.arithmetic.max,\n supports.logical.max,\n supports.get.max,\n supports.putFull.max,\n supports.putPartial.max).max\n\n def infoString = {\n s\"\"\"Master Name = ${name}\n |visibility = ${visibility}\n |emits = ${emits.infoString}\n |sourceId = ${sourceId}\n |\n |\"\"\".stripMargin\n }\n\n def v1copy(\n name: String = name,\n sourceId: IdRange = sourceId,\n nodePath: Seq[BaseNode] = nodePath,\n requestFifo: Boolean = requestFifo,\n visibility: Seq[AddressSet] = visibility,\n supportsProbe: TransferSizes = supports.probe,\n supportsArithmetic: TransferSizes = supports.arithmetic,\n supportsLogical: TransferSizes = supports.logical,\n supportsGet: TransferSizes = supports.get,\n supportsPutFull: TransferSizes = supports.putFull,\n supportsPutPartial: TransferSizes = supports.putPartial,\n supportsHint: TransferSizes = supports.hint) =\n {\n new TLMasterParameters(\n nodePath = nodePath,\n resources = this.resources,\n name = name,\n visibility = visibility,\n unusedRegionTypes = this.unusedRegionTypes,\n executesOnly = this.executesOnly,\n requestFifo = requestFifo,\n supports = TLSlaveToMasterTransferSizes(\n probe = supportsProbe,\n arithmetic = supportsArithmetic,\n logical = supportsLogical,\n get = supportsGet,\n putFull = supportsPutFull,\n putPartial = supportsPutPartial,\n hint = supportsHint),\n emits = this.emits,\n neverReleasesData = this.neverReleasesData,\n sourceId = sourceId)\n }\n\n def v2copy(\n nodePath: Seq[BaseNode] = nodePath,\n resources: Seq[Resource] = resources,\n name: String = name,\n visibility: Seq[AddressSet] = visibility,\n unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,\n executesOnly: Boolean = executesOnly,\n requestFifo: Boolean = requestFifo,\n supports: TLSlaveToMasterTransferSizes = supports,\n emits: TLMasterToSlaveTransferSizes = emits,\n neverReleasesData: Boolean = neverReleasesData,\n sourceId: IdRange = sourceId) =\n {\n new TLMasterParameters(\n nodePath = nodePath,\n resources = resources,\n name = name,\n visibility = visibility,\n unusedRegionTypes = unusedRegionTypes,\n executesOnly = executesOnly,\n requestFifo = requestFifo,\n supports = supports,\n emits = emits,\n neverReleasesData = neverReleasesData,\n sourceId = sourceId)\n }\n\n @deprecated(\"Use v1copy instead of copy\",\"\")\n def copy(\n name: String = name,\n sourceId: IdRange = sourceId,\n nodePath: Seq[BaseNode] = nodePath,\n requestFifo: Boolean = requestFifo,\n visibility: Seq[AddressSet] = visibility,\n supportsProbe: TransferSizes = supports.probe,\n supportsArithmetic: TransferSizes = supports.arithmetic,\n supportsLogical: TransferSizes = supports.logical,\n supportsGet: TransferSizes = supports.get,\n supportsPutFull: TransferSizes = supports.putFull,\n supportsPutPartial: TransferSizes = supports.putPartial,\n supportsHint: TransferSizes = supports.hint) =\n {\n v1copy(\n name = name,\n sourceId = sourceId,\n nodePath = nodePath,\n requestFifo = requestFifo,\n visibility = visibility,\n supportsProbe = supportsProbe,\n supportsArithmetic = supportsArithmetic,\n supportsLogical = supportsLogical,\n supportsGet = supportsGet,\n supportsPutFull = supportsPutFull,\n supportsPutPartial = supportsPutPartial,\n supportsHint = supportsHint)\n }\n}\n\nobject TLMasterParameters {\n def v1(\n name: String,\n sourceId: IdRange = IdRange(0,1),\n nodePath: Seq[BaseNode] = Seq(),\n requestFifo: Boolean = false,\n visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),\n supportsProbe: TransferSizes = TransferSizes.none,\n supportsArithmetic: TransferSizes = TransferSizes.none,\n supportsLogical: TransferSizes = TransferSizes.none,\n supportsGet: TransferSizes = TransferSizes.none,\n supportsPutFull: TransferSizes = TransferSizes.none,\n supportsPutPartial: TransferSizes = TransferSizes.none,\n supportsHint: TransferSizes = TransferSizes.none) =\n {\n new TLMasterParameters(\n nodePath = nodePath,\n resources = Nil,\n name = name,\n visibility = visibility,\n unusedRegionTypes = Set(),\n executesOnly = false,\n requestFifo = requestFifo,\n supports = TLSlaveToMasterTransferSizes(\n probe = supportsProbe,\n arithmetic = supportsArithmetic,\n logical = supportsLogical,\n get = supportsGet,\n putFull = supportsPutFull,\n putPartial = supportsPutPartial,\n hint = supportsHint),\n emits = TLMasterToSlaveTransferSizes.unknownEmits,\n neverReleasesData = false,\n sourceId = sourceId)\n }\n\n def v2(\n nodePath: Seq[BaseNode] = Seq(),\n resources: Seq[Resource] = Nil,\n name: String,\n visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),\n unusedRegionTypes: Set[RegionType.T] = Set(),\n executesOnly: Boolean = false,\n requestFifo: Boolean = false,\n supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,\n emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,\n neverReleasesData: Boolean = false,\n sourceId: IdRange = IdRange(0,1)) =\n {\n new TLMasterParameters(\n nodePath = nodePath,\n resources = resources,\n name = name,\n visibility = visibility,\n unusedRegionTypes = unusedRegionTypes,\n executesOnly = executesOnly,\n requestFifo = requestFifo,\n supports = supports,\n emits = emits,\n neverReleasesData = neverReleasesData,\n sourceId = sourceId)\n }\n}\n \nobject TLClientParameters {\n @deprecated(\"Use TLMasterParameters.v1 instead of TLClientParameters\",\"\")\n def apply(\n name: String,\n sourceId: IdRange = IdRange(0,1),\n nodePath: Seq[BaseNode] = Seq(),\n requestFifo: Boolean = false,\n visibility: Seq[AddressSet] = Seq(AddressSet.everything),\n supportsProbe: TransferSizes = TransferSizes.none,\n supportsArithmetic: TransferSizes = TransferSizes.none,\n supportsLogical: TransferSizes = TransferSizes.none,\n supportsGet: TransferSizes = TransferSizes.none,\n supportsPutFull: TransferSizes = TransferSizes.none,\n supportsPutPartial: TransferSizes = TransferSizes.none,\n supportsHint: TransferSizes = TransferSizes.none) =\n {\n TLMasterParameters.v1(\n name = name,\n sourceId = sourceId,\n nodePath = nodePath,\n requestFifo = requestFifo,\n visibility = visibility,\n supportsProbe = supportsProbe,\n supportsArithmetic = supportsArithmetic,\n supportsLogical = supportsLogical,\n supportsGet = supportsGet,\n supportsPutFull = supportsPutFull,\n supportsPutPartial = supportsPutPartial,\n supportsHint = supportsHint)\n }\n}\n\nclass TLMasterPortParameters private(\n val masters: Seq[TLMasterParameters],\n val channelBytes: TLChannelBeatBytes,\n val minLatency: Int,\n val echoFields: Seq[BundleFieldBase],\n val requestFields: Seq[BundleFieldBase],\n val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct\n{\n override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]\n override def productPrefix = \"TLMasterPortParameters\"\n def productArity: Int = 6\n def productElement(n: Int): Any = n match {\n case 0 => masters\n case 1 => channelBytes\n case 2 => minLatency\n case 3 => echoFields\n case 4 => requestFields\n case 5 => responseKeys\n case _ => throw new IndexOutOfBoundsException(n.toString)\n }\n\n require (!masters.isEmpty)\n require (minLatency >= 0)\n\n def clients = masters\n\n // Require disjoint ranges for Ids\n IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>\n require (!x.overlaps(y), s\"TLClientParameters.sourceId ${x} overlaps ${y}\")\n }\n\n // Bounds on required sizes\n def endSourceId = masters.map(_.sourceId.end).max\n def maxTransfer = masters.map(_.maxTransfer).max\n\n // The unused sources < endSourceId\n def unusedSources: Seq[Int] = {\n val usedSources = masters.map(_.sourceId).sortBy(_.start)\n ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>\n end until start\n }\n }\n\n // Diplomatically determined operation sizes emitted by all inward Masters\n // as opposed to emits* which generate circuitry to check which specific addresses\n val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)\n\n // Diplomatically determined operation sizes Emitted by at least one inward Masters\n // as opposed to emits* which generate circuitry to check which specific addresses\n val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)\n\n // Diplomatically determined operation sizes supported by all inward Masters\n // as opposed to supports* which generate circuitry to check which specific addresses\n val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)\n val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)\n val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)\n val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)\n val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)\n val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)\n val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)\n\n // Diplomatically determined operation sizes supported by at least one master\n // as opposed to supports* which generate circuitry to check which specific addresses\n val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)\n val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)\n val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)\n val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)\n val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)\n val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)\n val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)\n\n // These return Option[TLMasterParameters] for your convenience\n def find(id: Int) = masters.find(_.sourceId.contains(id))\n\n // Synthesizable lookup methods\n def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))\n def contains(id: UInt) = find(id).reduce(_ || _)\n\n def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))\n\n // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters\n private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {\n val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)\n // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;\n // the case where there is only one group.\n if (allSame) member(masters(0)).containsLg(lgSize) else {\n // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize\n Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))\n }\n }\n\n // Check for support of a given operation at a specific id\n val supportsProbe = sourceIdHelper(_.supports.probe) _\n val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _\n val supportsLogical = sourceIdHelper(_.supports.logical) _\n val supportsGet = sourceIdHelper(_.supports.get) _\n val supportsPutFull = sourceIdHelper(_.supports.putFull) _\n val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _\n val supportsHint = sourceIdHelper(_.supports.hint) _\n\n // TODO: Merge sourceIdHelper2 with sourceIdHelper\n private def sourceIdHelper2(\n member: TLMasterParameters => TransferSizes,\n sourceId: UInt,\n lgSize: UInt): Bool = {\n // Because sourceIds are uniquely owned by each master, we use them to group the\n // cases that have to be checked.\n val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>\n k -> vs.map(_.sourceId)\n }\n emitCases.map { case (s, a) =>\n (s.containsLg(lgSize)) &&\n a.map(_.contains(sourceId)).reduce(_||_)\n }.foldLeft(false.B)(_||_)\n }\n\n // Check for emit of a given operation at a specific id\n def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)\n def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)\n def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)\n def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)\n def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)\n def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)\n def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)\n def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)\n\n def infoString = masters.map(_.infoString).mkString\n\n def v1copy(\n clients: Seq[TLMasterParameters] = masters,\n minLatency: Int = minLatency,\n echoFields: Seq[BundleFieldBase] = echoFields,\n requestFields: Seq[BundleFieldBase] = requestFields,\n responseKeys: Seq[BundleKeyBase] = responseKeys) =\n {\n new TLMasterPortParameters(\n masters = clients,\n channelBytes = channelBytes,\n minLatency = minLatency,\n echoFields = echoFields,\n requestFields = requestFields,\n responseKeys = responseKeys)\n }\n\n def v2copy(\n masters: Seq[TLMasterParameters] = masters,\n channelBytes: TLChannelBeatBytes = channelBytes,\n minLatency: Int = minLatency,\n echoFields: Seq[BundleFieldBase] = echoFields,\n requestFields: Seq[BundleFieldBase] = requestFields,\n responseKeys: Seq[BundleKeyBase] = responseKeys) =\n {\n new TLMasterPortParameters(\n masters = masters,\n channelBytes = channelBytes,\n minLatency = minLatency,\n echoFields = echoFields,\n requestFields = requestFields,\n responseKeys = responseKeys)\n }\n\n @deprecated(\"Use v1copy instead of copy\",\"\")\n def copy(\n clients: Seq[TLMasterParameters] = masters,\n minLatency: Int = minLatency,\n echoFields: Seq[BundleFieldBase] = echoFields,\n requestFields: Seq[BundleFieldBase] = requestFields,\n responseKeys: Seq[BundleKeyBase] = responseKeys) =\n {\n v1copy(\n clients,\n minLatency,\n echoFields,\n requestFields,\n responseKeys)\n }\n}\n\nobject TLClientPortParameters {\n @deprecated(\"Use TLMasterPortParameters.v1 instead of TLClientPortParameters\",\"\")\n def apply(\n clients: Seq[TLMasterParameters],\n minLatency: Int = 0,\n echoFields: Seq[BundleFieldBase] = Nil,\n requestFields: Seq[BundleFieldBase] = Nil,\n responseKeys: Seq[BundleKeyBase] = Nil) =\n {\n TLMasterPortParameters.v1(\n clients,\n minLatency,\n echoFields,\n requestFields,\n responseKeys)\n }\n}\n\nobject TLMasterPortParameters {\n def v1(\n clients: Seq[TLMasterParameters],\n minLatency: Int = 0,\n echoFields: Seq[BundleFieldBase] = Nil,\n requestFields: Seq[BundleFieldBase] = Nil,\n responseKeys: Seq[BundleKeyBase] = Nil) =\n {\n new TLMasterPortParameters(\n masters = clients,\n channelBytes = TLChannelBeatBytes(),\n minLatency = minLatency,\n echoFields = echoFields,\n requestFields = requestFields,\n responseKeys = responseKeys)\n }\n def v2(\n masters: Seq[TLMasterParameters],\n channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),\n minLatency: Int = 0,\n echoFields: Seq[BundleFieldBase] = Nil,\n requestFields: Seq[BundleFieldBase] = Nil,\n responseKeys: Seq[BundleKeyBase] = Nil) =\n {\n new TLMasterPortParameters(\n masters = masters,\n channelBytes = channelBytes,\n minLatency = minLatency,\n echoFields = echoFields,\n requestFields = requestFields,\n responseKeys = responseKeys)\n }\n}\n\ncase class TLBundleParameters(\n addressBits: Int,\n dataBits: Int,\n sourceBits: Int,\n sinkBits: Int,\n sizeBits: Int,\n echoFields: Seq[BundleFieldBase],\n requestFields: Seq[BundleFieldBase],\n responseFields: Seq[BundleFieldBase],\n hasBCE: Boolean)\n{\n // Chisel has issues with 0-width wires\n require (addressBits >= 1)\n require (dataBits >= 8)\n require (sourceBits >= 1)\n require (sinkBits >= 1)\n require (sizeBits >= 1)\n require (isPow2(dataBits))\n echoFields.foreach { f => require (f.key.isControl, s\"${f} is not a legal echo field\") }\n\n val addrLoBits = log2Up(dataBits/8)\n\n // Used to uniquify bus IP names\n def shortName = s\"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}\" + (if (hasBCE) \"c\" else \"u\")\n\n def union(x: TLBundleParameters) =\n TLBundleParameters(\n max(addressBits, x.addressBits),\n max(dataBits, x.dataBits),\n max(sourceBits, x.sourceBits),\n max(sinkBits, x.sinkBits),\n max(sizeBits, x.sizeBits),\n echoFields = BundleField.union(echoFields ++ x.echoFields),\n requestFields = BundleField.union(requestFields ++ x.requestFields),\n responseFields = BundleField.union(responseFields ++ x.responseFields),\n hasBCE || x.hasBCE)\n}\n\nobject TLBundleParameters\n{\n val emptyBundleParams = TLBundleParameters(\n addressBits = 1,\n dataBits = 8,\n sourceBits = 1,\n sinkBits = 1,\n sizeBits = 1,\n echoFields = Nil,\n requestFields = Nil,\n responseFields = Nil,\n hasBCE = false)\n\n def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))\n\n def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =\n new TLBundleParameters(\n addressBits = log2Up(slave.maxAddress + 1),\n dataBits = slave.beatBytes * 8,\n sourceBits = log2Up(master.endSourceId),\n sinkBits = log2Up(slave.endSinkId),\n sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),\n echoFields = master.echoFields,\n requestFields = BundleField.accept(master.requestFields, slave.requestKeys),\n responseFields = BundleField.accept(slave.responseFields, master.responseKeys),\n hasBCE = master.anySupportProbe && slave.anySupportAcquireB)\n}\n\ncase class TLEdgeParameters(\n master: TLMasterPortParameters,\n slave: TLSlavePortParameters,\n params: Parameters,\n sourceInfo: SourceInfo) extends FormatEdge\n{\n // legacy names:\n def manager = slave\n def client = master\n\n val maxTransfer = max(master.maxTransfer, slave.maxTransfer)\n val maxLgSize = log2Ceil(maxTransfer)\n\n // Sanity check the link...\n require (maxTransfer >= slave.beatBytes, s\"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})\")\n\n def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)\n\n val bundle = TLBundleParameters(master, slave)\n def formatEdge = master.infoString + \"\\n\" + slave.infoString\n}\n\ncase class TLCreditedDelay(\n a: CreditedDelay,\n b: CreditedDelay,\n c: CreditedDelay,\n d: CreditedDelay,\n e: CreditedDelay)\n{\n def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(\n a = a + that.a,\n b = b + that.b,\n c = c + that.c,\n d = d + that.d,\n e = e + that.e)\n\n override def toString = s\"(${a}, ${b}, ${c}, ${d}, ${e})\"\n}\n\nobject TLCreditedDelay {\n def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)\n}\n\ncase class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}\ncase class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}\ncase class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge\n{\n val delay = client.delay + manager.delay\n val bundle = TLBundleParameters(client.base, manager.base)\n def formatEdge = client.infoString + \"\\n\" + manager.infoString\n}\n\ncase class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}\ncase class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}\ncase class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)\ncase class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge\n{\n val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))\n def formatEdge = client.infoString + \"\\n\" + manager.infoString\n}\n\ncase class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}\ncase class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}\n\ncase class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge\n{\n val bundle = TLBundleParameters(client.base, manager.base)\n def formatEdge = client.infoString + \"\\n\" + manager.infoString\n}\n\n// To be unified, devices must agree on all of these terms\ncase class ManagerUnificationKey(\n resources: Seq[Resource],\n regionType: RegionType.T,\n executable: Boolean,\n supportsAcquireT: TransferSizes,\n supportsAcquireB: TransferSizes,\n supportsArithmetic: TransferSizes,\n supportsLogical: TransferSizes,\n supportsGet: TransferSizes,\n supportsPutFull: TransferSizes,\n supportsPutPartial: TransferSizes,\n supportsHint: TransferSizes)\n\nobject ManagerUnificationKey\n{\n def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(\n resources = x.resources,\n regionType = x.regionType,\n executable = x.executable,\n supportsAcquireT = x.supportsAcquireT,\n supportsAcquireB = x.supportsAcquireB,\n supportsArithmetic = x.supportsArithmetic,\n supportsLogical = x.supportsLogical,\n supportsGet = x.supportsGet,\n supportsPutFull = x.supportsPutFull,\n supportsPutPartial = x.supportsPutPartial,\n supportsHint = x.supportsHint)\n}\n\nobject ManagerUnification\n{\n def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {\n slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>\n val agree = seq.forall(_.fifoId == seq.head.fifoId)\n seq(0).v1copy(\n address = AddressSet.unify(seq.flatMap(_.address)),\n fifoId = if (agree) seq(0).fifoId else None)\n }.toList\n }\n}\n\ncase class TLBufferParams(\n a: BufferParams = BufferParams.none,\n b: BufferParams = BufferParams.none,\n c: BufferParams = BufferParams.none,\n d: BufferParams = BufferParams.none,\n e: BufferParams = BufferParams.none\n) extends DirectedBuffers[TLBufferParams] {\n def copyIn(x: BufferParams) = this.copy(b = x, d = x)\n def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)\n def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)\n}\n\n/** Pretty printing of TL source id maps */\nclass TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {\n private val tlDigits = String.valueOf(tl.endSourceId-1).length()\n protected val fmt = s\"\\t[%${tlDigits}d, %${tlDigits}d) %s%s%s\"\n private val sorted = tl.masters.sortBy(_.sourceId)\n\n val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>\n TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)\n }\n}\n\ncase class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)\n extends IdMapEntry\n{\n val from = tlId\n val to = tlId\n val maxTransactionsInFlight = Some(tlId.size)\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_38(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [127:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_source = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_source = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire mask_sizeOH_shiftAmount = 1'h0;\t// @[OneHot.scala:64:49]\n wire mask_sub_size = 1'h0;\t// @[Misc.scala:209:26]\n wire _mask_sub_acc_T = 1'h0;\t// @[Misc.scala:215:38]\n wire _mask_sub_acc_T_1 = 1'h0;\t// @[Misc.scala:215:38]\n wire a_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire a_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire c_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_first_count_T = 1'h0;\t// @[Edges.scala:234:27]\n wire c_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_counter_T = 1'h0;\t// @[Edges.scala:236:21]\n wire d_first_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire c_set = 1'h0;\t// @[Monitor.scala:738:34]\n wire c_set_wo_ready = 1'h0;\t// @[Monitor.scala:739:34]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire _source_ok_T = 1'h1;\t// @[Parameters.scala:46:9]\n wire _source_ok_WIRE_0 = 1'h1;\t// @[Parameters.scala:1138:31]\n wire mask_sub_sub_0_1 = 1'h1;\t// @[Misc.scala:206:21]\n wire mask_sub_0_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_sub_1_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_size = 1'h1;\t// @[Misc.scala:209:26]\n wire mask_acc = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_2 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_3 = 1'h1;\t// @[Misc.scala:215:29]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:46:9]\n wire _source_ok_WIRE_1_0 = 1'h1;\t// @[Parameters.scala:1138:31]\n wire sink_ok = 1'h1;\t// @[Monitor.scala:309:31]\n wire _a_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _a_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _same_cycle_resp_T_2 = 1'h1;\t// @[Monitor.scala:684:113]\n wire c_first_counter1 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_2 = 1'h1;\t// @[Edges.scala:232:33]\n wire _same_cycle_resp_T_8 = 1'h1;\t// @[Monitor.scala:795:113]\n wire [1:0] is_aligned_mask = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] mask_lo = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] _a_first_beats1_decode_T_2 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _a_first_beats1_decode_T_5 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _c_first_beats1_decode_T_1 = 2'h3;\t// @[package.scala:243:76]\n wire [1:0] _c_first_counter1_T = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_a_bits_size = 2'h2;\t// @[Monitor.scala:36:7]\n wire [1:0] _mask_sizeOH_T = 2'h2;\t// @[Misc.scala:202:34]\n wire [2:0] io_in_a_bits_param = 3'h0;\t// @[Monitor.scala:36:7]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_sizes_set_interm = 3'h0;\t// @[Monitor.scala:755:40]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_T = 3'h0;\t// @[Monitor.scala:766:51]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] io_in_a_bits_mask = 4'hF;\t// @[Monitor.scala:36:7]\n wire [3:0] mask = 4'hF;\t// @[Misc.scala:222:10]\n wire [31:0] io_in_d_bits_data = 32'h0;\t// @[Monitor.scala:36:7]\n wire [31:0] _c_first_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_first_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_first_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_first_WIRE_2_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_first_WIRE_3_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_set_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_set_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _is_aligned_mask_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_4 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _c_first_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_beats1_decode_T_2 = 2'h0;\t// @[package.scala:243:46]\n wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [30:0] _d_opcodes_clr_T_5 = 31'hF;\t// @[Monitor.scala:680:76]\n wire [30:0] _d_sizes_clr_T_5 = 31'hF;\t// @[Monitor.scala:681:74]\n wire [30:0] _d_opcodes_clr_T_11 = 31'hF;\t// @[Monitor.scala:790:76]\n wire [30:0] _d_sizes_clr_T_11 = 31'hF;\t// @[Monitor.scala:791:74]\n wire [3:0] _a_opcode_lookup_T = 4'h0;\t// @[Monitor.scala:637:69]\n wire [3:0] _a_size_lookup_T = 4'h0;\t// @[Monitor.scala:641:65]\n wire [3:0] _a_opcodes_set_T = 4'h0;\t// @[Monitor.scala:659:79]\n wire [3:0] _a_sizes_set_T = 4'h0;\t// @[Monitor.scala:660:77]\n wire [3:0] _d_opcodes_clr_T_4 = 4'h0;\t// @[Monitor.scala:680:101]\n wire [3:0] _d_sizes_clr_T_4 = 4'h0;\t// @[Monitor.scala:681:99]\n wire [3:0] c_opcodes_set = 4'h0;\t// @[Monitor.scala:740:34]\n wire [3:0] c_sizes_set = 4'h0;\t// @[Monitor.scala:741:34]\n wire [3:0] _c_opcode_lookup_T = 4'h0;\t// @[Monitor.scala:749:69]\n wire [3:0] _c_size_lookup_T = 4'h0;\t// @[Monitor.scala:750:67]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_opcodes_set_T = 4'h0;\t// @[Monitor.scala:767:79]\n wire [3:0] _c_sizes_set_T = 4'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _d_opcodes_clr_T_10 = 4'h0;\t// @[Monitor.scala:790:101]\n wire [3:0] _d_sizes_clr_T_10 = 4'h0;\t// @[Monitor.scala:791:99]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [1:0] _mask_sizeOH_T_1 = 2'h1;\t// @[OneHot.scala:65:12]\n wire [1:0] _mask_sizeOH_T_2 = 2'h1;\t// @[OneHot.scala:65:27]\n wire [1:0] mask_sizeOH = 2'h1;\t// @[Misc.scala:202:81]\n wire [1:0] _a_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _a_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T_1 = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T_1 = 2'h1;\t// @[OneHot.scala:58:35]\n wire [17:0] _c_sizes_set_T_1 = 18'h0;\t// @[Monitor.scala:768:52]\n wire [18:0] _c_opcodes_set_T_1 = 19'h0;\t// @[Monitor.scala:767:54]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_sizes_set_interm_T_1 = 3'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [4:0] _c_first_beats1_decode_T = 5'h3;\t// @[package.scala:243:71]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T_1 = 3'h5;\t// @[Monitor.scala:658:59]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T = 3'h4;\t// @[Monitor.scala:658:51]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [4:0] _is_aligned_mask_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T_3 = 5'hC;\t// @[package.scala:243:71]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]};\t// @[Monitor.scala:36:7]\n wire is_aligned = _is_aligned_T == 128'h0;\t// @[Edges.scala:21:{16,24}]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_1_2 = mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_eq;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_eq_1;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_eq_2;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_eq_3;\t// @[Misc.scala:214:27, :215:38]\n wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_607;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_607;\t// @[Decoupled.scala:51:35]\n wire a_first_done = _a_first_T;\t// @[Decoupled.scala:51:35]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n wire _a_first_last_T = a_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1 = _a_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~a_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T = ~a_first & a_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [127:0] address;\t// @[Monitor.scala:391:22]\n wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_675;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_675;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_675;\t// @[Decoupled.scala:51:35]\n wire d_first_done = _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN;\t// @[package.scala:243:71]\n wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n wire _d_first_last_T = d_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1 = _d_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire d_first = ~d_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T = ~d_first & d_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [1:0] inflight;\t// @[Monitor.scala:614:27]\n reg [3:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes;\t// @[Monitor.scala:616:35, :637:44]\n reg [3:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [3:0] _a_size_lookup_T_1 = inflight_sizes;\t// @[Monitor.scala:618:33, :641:40]\n wire a_first_done_1 = _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n wire _a_first_last_T_2 = a_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1_1 = _a_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire a_first_1 = ~a_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_first_done_1 = _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_2 = d_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_1 = _d_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire d_first_1 = ~d_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire a_set;\t// @[Monitor.scala:626:34]\n wire a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [3:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [3:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1};\t// @[Monitor.scala:637:{44,97}]\n wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1};\t// @[Monitor.scala:637:97, :641:{40,91}]\n wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [2:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _T_537 = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26]\n assign a_set_wo_ready = _T_537;\t// @[Monitor.scala:627:34, :651:26]\n wire _same_cycle_resp_T;\t// @[Monitor.scala:684:44]\n assign _same_cycle_resp_T = _T_537;\t// @[Monitor.scala:651:26, :684:44]\n assign a_set = _T_607 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]\n assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0;\t// @[Monitor.scala:626:34, :648:38, :655:70, :658:28]\n wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm};\t// @[Monitor.scala:646:40, :659:54]\n assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]\n wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm};\t// @[Monitor.scala:648:38, :659:54, :660:52]\n assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]\n wire d_clr;\t// @[Monitor.scala:664:34]\n wire d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [3:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [3:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_0;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_0;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_586 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n assign d_clr_wo_ready = _T_586 & ~d_release_ack;\t// @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]\n assign d_clr = _T_675 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n wire [3:0] _GEN_1 = {4{d_clr}};\t// @[Monitor.scala:664:34, :668:33, :678:89, :680:21]\n assign d_opcodes_clr = _GEN_1;\t// @[Monitor.scala:668:33, :678:89, :680:21]\n assign d_sizes_clr = _GEN_1;\t// @[Monitor.scala:668:33, :670:31, :678:89, :680:21]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire same_cycle_resp = _same_cycle_resp_T_1;\t// @[Monitor.scala:684:{55,88}]\n wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set};\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1};\t// @[Monitor.scala:705:{27,36,38}]\n wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [1:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [1:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [3:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :749:44]\n wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [3:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :750:42]\n wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire d_first_done_2 = _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_4 = d_first_counter_2;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_2 = _d_first_counter1_T_2[0];\t// @[Edges.scala:230:28]\n wire d_first_2 = ~d_first_counter_2;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1};\t// @[Monitor.scala:637:97, :749:{44,97}]\n wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1};\t// @[Monitor.scala:637:97, :750:{42,93}]\n wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire d_clr_1;\t// @[Monitor.scala:774:34]\n wire d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [3:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [3:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_651 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1;\t// @[Monitor.scala:775:34, :783:46, :784:{26,71}]\n assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n wire [3:0] _GEN_2 = {4{d_clr_1}};\t// @[Monitor.scala:774:34, :776:34, :788:88, :790:21]\n assign d_opcodes_clr_1 = _GEN_2;\t// @[Monitor.scala:776:34, :788:88, :790:21]\n assign d_sizes_clr_1 = _GEN_2;\t// @[Monitor.scala:776:34, :777:34, :788:88, :790:21]\n wire _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4};\t// @[Monitor.scala:814:{35,44,46}]\n wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":2096,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Bundles.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport freechips.rocketchip.util._\nimport scala.collection.immutable.ListMap\nimport chisel3.util.Decoupled\nimport chisel3.util.DecoupledIO\nimport chisel3.reflect.DataMirror\n\nabstract class TLBundleBase(val params: TLBundleParameters) extends Bundle\n\n// common combos in lazy policy:\n// Put + Acquire\n// Release + AccessAck\n\nobject TLMessages\n{\n // A B C D E\n def PutFullData = 0.U // . . => AccessAck\n def PutPartialData = 1.U // . . => AccessAck\n def ArithmeticData = 2.U // . . => AccessAckData\n def LogicalData = 3.U // . . => AccessAckData\n def Get = 4.U // . . => AccessAckData\n def Hint = 5.U // . . => HintAck\n def AcquireBlock = 6.U // . => Grant[Data]\n def AcquirePerm = 7.U // . => Grant[Data]\n def Probe = 6.U // . => ProbeAck[Data]\n def AccessAck = 0.U // . .\n def AccessAckData = 1.U // . .\n def HintAck = 2.U // . .\n def ProbeAck = 4.U // .\n def ProbeAckData = 5.U // .\n def Release = 6.U // . => ReleaseAck\n def ReleaseData = 7.U // . => ReleaseAck\n def Grant = 4.U // . => GrantAck\n def GrantData = 5.U // . => GrantAck\n def ReleaseAck = 6.U // .\n def GrantAck = 0.U // .\n\n def isA(x: UInt) = x <= AcquirePerm\n def isB(x: UInt) = x <= Probe\n def isC(x: UInt) = x <= ReleaseData\n def isD(x: UInt) = x <= ReleaseAck\n\n def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)\n def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)\n\n def a = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"AcquireBlock\",TLPermissions.PermMsgGrow),\n (\"AcquirePerm\",TLPermissions.PermMsgGrow))\n\n def b = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"Probe\",TLPermissions.PermMsgCap))\n\n def c = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"ProbeAck\",TLPermissions.PermMsgReport),\n (\"ProbeAckData\",TLPermissions.PermMsgReport),\n (\"Release\",TLPermissions.PermMsgReport),\n (\"ReleaseData\",TLPermissions.PermMsgReport))\n\n def d = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"Grant\",TLPermissions.PermMsgCap),\n (\"GrantData\",TLPermissions.PermMsgCap),\n (\"ReleaseAck\",TLPermissions.PermMsgReserved))\n\n}\n\n/**\n * The three primary TileLink permissions are:\n * (T)runk: the agent is (or is on inwards path to) the global point of serialization.\n * (B)ranch: the agent is on an outwards path to\n * (N)one:\n * These permissions are permuted by transfer operations in various ways.\n * Operations can cap permissions, request for them to be grown or shrunk,\n * or for a report on their current status.\n */\nobject TLPermissions\n{\n val aWidth = 2\n val bdWidth = 2\n val cWidth = 3\n\n // Cap types (Grant = new permissions, Probe = permisions <= target)\n def toT = 0.U(bdWidth.W)\n def toB = 1.U(bdWidth.W)\n def toN = 2.U(bdWidth.W)\n def isCap(x: UInt) = x <= toN\n\n // Grow types (Acquire = permissions >= target)\n def NtoB = 0.U(aWidth.W)\n def NtoT = 1.U(aWidth.W)\n def BtoT = 2.U(aWidth.W)\n def isGrow(x: UInt) = x <= BtoT\n\n // Shrink types (ProbeAck, Release)\n def TtoB = 0.U(cWidth.W)\n def TtoN = 1.U(cWidth.W)\n def BtoN = 2.U(cWidth.W)\n def isShrink(x: UInt) = x <= BtoN\n\n // Report types (ProbeAck, Release)\n def TtoT = 3.U(cWidth.W)\n def BtoB = 4.U(cWidth.W)\n def NtoN = 5.U(cWidth.W)\n def isReport(x: UInt) = x <= NtoN\n\n def PermMsgGrow:Seq[String] = Seq(\"Grow NtoB\", \"Grow NtoT\", \"Grow BtoT\")\n def PermMsgCap:Seq[String] = Seq(\"Cap toT\", \"Cap toB\", \"Cap toN\")\n def PermMsgReport:Seq[String] = Seq(\"Shrink TtoB\", \"Shrink TtoN\", \"Shrink BtoN\", \"Report TotT\", \"Report BtoB\", \"Report NtoN\")\n def PermMsgReserved:Seq[String] = Seq(\"Reserved\")\n}\n\nobject TLAtomics\n{\n val width = 3\n\n // Arithmetic types\n def MIN = 0.U(width.W)\n def MAX = 1.U(width.W)\n def MINU = 2.U(width.W)\n def MAXU = 3.U(width.W)\n def ADD = 4.U(width.W)\n def isArithmetic(x: UInt) = x <= ADD\n\n // Logical types\n def XOR = 0.U(width.W)\n def OR = 1.U(width.W)\n def AND = 2.U(width.W)\n def SWAP = 3.U(width.W)\n def isLogical(x: UInt) = x <= SWAP\n\n def ArithMsg:Seq[String] = Seq(\"MIN\", \"MAX\", \"MINU\", \"MAXU\", \"ADD\")\n def LogicMsg:Seq[String] = Seq(\"XOR\", \"OR\", \"AND\", \"SWAP\")\n}\n\n\nobject TLHints\n{\n val width = 1\n\n def PREFETCH_READ = 0.U(width.W)\n def PREFETCH_WRITE = 1.U(width.W)\n def isHints(x: UInt) = x <= PREFETCH_WRITE\n\n def HintsMsg:Seq[String] = Seq(\"PrefetchRead\", \"PrefetchWrite\")\n}\n\nsealed trait TLChannel extends TLBundleBase {\n val channelName: String\n}\n\nsealed trait TLDataChannel extends TLChannel\nsealed trait TLAddrChannel extends TLDataChannel\n\nfinal class TLBundleA(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleA_${params.shortName}\"\n val channelName = \"'A' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\nfinal class TLBundleB(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleB_${params.shortName}\"\n val channelName = \"'B' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val address = UInt(params.addressBits.W) // from\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleC(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleC_${params.shortName}\"\n val channelName = \"'C' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.cWidth.W) // shrink or report perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleD(params: TLBundleParameters)\n extends TLBundleBase(params) with TLDataChannel\n{\n override def typeName = s\"TLBundleD_${params.shortName}\"\n val channelName = \"'D' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val sink = UInt(params.sinkBits.W) // from\n val denied = Bool() // implies corrupt iff *Data\n val user = BundleMap(params.responseFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleE(params: TLBundleParameters)\n extends TLBundleBase(params) with TLChannel\n{\n override def typeName = s\"TLBundleE_${params.shortName}\"\n val channelName = \"'E' channel\"\n val sink = UInt(params.sinkBits.W) // to\n}\n\nclass TLBundle(val params: TLBundleParameters) extends Record\n{\n // Emulate a Bundle with elements abcde or ad depending on params.hasBCE\n\n private val optA = Some (Decoupled(new TLBundleA(params)))\n private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))\n private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))\n private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))\n private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))\n\n def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))\n def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))\n def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))\n def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))\n def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))\n\n val elements =\n if (params.hasBCE) ListMap(\"e\" -> e, \"d\" -> d, \"c\" -> c, \"b\" -> b, \"a\" -> a)\n else ListMap(\"d\" -> d, \"a\" -> a)\n\n def tieoff(): Unit = {\n DataMirror.specifiedDirectionOf(a.ready) match {\n case SpecifiedDirection.Input =>\n a.ready := false.B\n c.ready := false.B\n e.ready := false.B\n b.valid := false.B\n d.valid := false.B\n case SpecifiedDirection.Output =>\n a.valid := false.B\n c.valid := false.B\n e.valid := false.B\n b.ready := false.B\n d.ready := false.B\n case _ =>\n }\n }\n}\n\nobject TLBundle\n{\n def apply(params: TLBundleParameters) = new TLBundle(params)\n}\n\nclass TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle\n\nclass TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)\n{\n val a = new AsyncBundle(new TLBundleA(params.base), params.async)\n val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))\n val c = new AsyncBundle(new TLBundleC(params.base), params.async)\n val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))\n val e = new AsyncBundle(new TLBundleE(params.base), params.async)\n}\n\nclass TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = RationalIO(new TLBundleA(params))\n val b = Flipped(RationalIO(new TLBundleB(params)))\n val c = RationalIO(new TLBundleC(params))\n val d = Flipped(RationalIO(new TLBundleD(params)))\n val e = RationalIO(new TLBundleE(params))\n}\n\nclass TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = CreditedIO(new TLBundleA(params))\n val b = Flipped(CreditedIO(new TLBundleB(params)))\n val c = CreditedIO(new TLBundleC(params))\n val d = Flipped(CreditedIO(new TLBundleD(params)))\n val e = CreditedIO(new TLBundleE(params))\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_57(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [4:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [27:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [4:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _source_ok_T_6 = 1'h0;\t// @[Parameters.scala:54:10]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _source_ok_T_7 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:54:67]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_d_bits_param = 2'h0;\t// @[Monitor.scala:36:7]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_first_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_first_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_first_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_first_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_first_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_first_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_first_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_first_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [258:0] _c_opcodes_set_T_1 = 259'h0;\t// @[Monitor.scala:767:54]\n wire [258:0] _c_sizes_set_T_1 = 259'h0;\t// @[Monitor.scala:768:52]\n wire [7:0] _c_opcodes_set_T = 8'h0;\t// @[Monitor.scala:767:79]\n wire [7:0] _c_sizes_set_T = 8'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [31:0] _c_set_wo_ready_T = 32'h1;\t// @[OneHot.scala:58:35]\n wire [31:0] _c_set_T = 32'h1;\t// @[OneHot.scala:58:35]\n wire [79:0] c_opcodes_set = 80'h0;\t// @[Monitor.scala:740:34]\n wire [79:0] c_sizes_set = 80'h0;\t// @[Monitor.scala:741:34]\n wire [19:0] c_set = 20'h0;\t// @[Monitor.scala:738:34]\n wire [19:0] c_set_wo_ready = 20'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_4;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 28'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [4:0] uncommonBits = _uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_1 = _uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_2 = _uncommonBits_T_2;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_3 = _uncommonBits_T_3;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_4 = _uncommonBits_T_4;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_5 = _uncommonBits_T_5;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_6 = _uncommonBits_T_6;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_7 = _uncommonBits_T_7;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_8 = _uncommonBits_T_8;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_10;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_672;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_672;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [4:0] source;\t// @[Monitor.scala:390:22]\n reg [27:0] address;\t// @[Monitor.scala:391:22]\n wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_745;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_745;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_745;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [4:0] source_1;\t// @[Monitor.scala:541:22]\n reg [19:0] inflight;\t// @[Monitor.scala:614:27]\n reg [79:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [79:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [19:0] a_set;\t// @[Monitor.scala:626:34]\n wire [19:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [79:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [79:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [7:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [7:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [7:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [7:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [7:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [7:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [7:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [7:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [31:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [31:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_598 = _T_672 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [7:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [7:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [19:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [19:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [79:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [79:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_644 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_613 = _T_745 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [19:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [19:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [19:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [19:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [79:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [79:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [19:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [19:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [79:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [79:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_716 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_698 = _T_745 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [19:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":2097,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\n"},"response":{"kind":"string","value":"module OptimizationBarrier_TLBEntryData_3(\t// @[package.scala:267:30]\n input clock,\t// @[package.scala:267:30]\n input reset,\t// @[package.scala:267:30]\n input [19:0] io_x_ppn,\t// @[package.scala:268:18]\n input io_x_u,\t// @[package.scala:268:18]\n input io_x_g,\t// @[package.scala:268:18]\n input io_x_ae_ptw,\t// @[package.scala:268:18]\n input io_x_ae_final,\t// @[package.scala:268:18]\n input io_x_ae_stage2,\t// @[package.scala:268:18]\n input io_x_pf,\t// @[package.scala:268:18]\n input io_x_gf,\t// @[package.scala:268:18]\n input io_x_sw,\t// @[package.scala:268:18]\n input io_x_sx,\t// @[package.scala:268:18]\n input io_x_sr,\t// @[package.scala:268:18]\n input io_x_hw,\t// @[package.scala:268:18]\n input io_x_hx,\t// @[package.scala:268:18]\n input io_x_hr,\t// @[package.scala:268:18]\n input io_x_pw,\t// @[package.scala:268:18]\n input io_x_px,\t// @[package.scala:268:18]\n input io_x_pr,\t// @[package.scala:268:18]\n input io_x_ppp,\t// @[package.scala:268:18]\n input io_x_pal,\t// @[package.scala:268:18]\n input io_x_paa,\t// @[package.scala:268:18]\n input io_x_eff,\t// @[package.scala:268:18]\n input io_x_c,\t// @[package.scala:268:18]\n input io_x_fragmented_superpage,\t// @[package.scala:268:18]\n output io_y_u,\t// @[package.scala:268:18]\n output io_y_ae_ptw,\t// @[package.scala:268:18]\n output io_y_ae_final,\t// @[package.scala:268:18]\n output io_y_ae_stage2,\t// @[package.scala:268:18]\n output io_y_pf,\t// @[package.scala:268:18]\n output io_y_gf,\t// @[package.scala:268:18]\n output io_y_sw,\t// @[package.scala:268:18]\n output io_y_sx,\t// @[package.scala:268:18]\n output io_y_sr,\t// @[package.scala:268:18]\n output io_y_hw,\t// @[package.scala:268:18]\n output io_y_hx,\t// @[package.scala:268:18]\n output io_y_hr,\t// @[package.scala:268:18]\n output io_y_pw,\t// @[package.scala:268:18]\n output io_y_px,\t// @[package.scala:268:18]\n output io_y_pr,\t// @[package.scala:268:18]\n output io_y_ppp,\t// @[package.scala:268:18]\n output io_y_pal,\t// @[package.scala:268:18]\n output io_y_paa,\t// @[package.scala:268:18]\n output io_y_eff,\t// @[package.scala:268:18]\n output io_y_c\t// @[package.scala:268:18]\n);\n\n wire [19:0] io_x_ppn_0 = io_x_ppn;\t// @[package.scala:267:30]\n wire io_x_u_0 = io_x_u;\t// @[package.scala:267:30]\n wire io_x_g_0 = io_x_g;\t// @[package.scala:267:30]\n wire io_x_ae_ptw_0 = io_x_ae_ptw;\t// @[package.scala:267:30]\n wire io_x_ae_final_0 = io_x_ae_final;\t// @[package.scala:267:30]\n wire io_x_ae_stage2_0 = io_x_ae_stage2;\t// @[package.scala:267:30]\n wire io_x_pf_0 = io_x_pf;\t// @[package.scala:267:30]\n wire io_x_gf_0 = io_x_gf;\t// @[package.scala:267:30]\n wire io_x_sw_0 = io_x_sw;\t// @[package.scala:267:30]\n wire io_x_sx_0 = io_x_sx;\t// @[package.scala:267:30]\n wire io_x_sr_0 = io_x_sr;\t// @[package.scala:267:30]\n wire io_x_hw_0 = io_x_hw;\t// @[package.scala:267:30]\n wire io_x_hx_0 = io_x_hx;\t// @[package.scala:267:30]\n wire io_x_hr_0 = io_x_hr;\t// @[package.scala:267:30]\n wire io_x_pw_0 = io_x_pw;\t// @[package.scala:267:30]\n wire io_x_px_0 = io_x_px;\t// @[package.scala:267:30]\n wire io_x_pr_0 = io_x_pr;\t// @[package.scala:267:30]\n wire io_x_ppp_0 = io_x_ppp;\t// @[package.scala:267:30]\n wire io_x_pal_0 = io_x_pal;\t// @[package.scala:267:30]\n wire io_x_paa_0 = io_x_paa;\t// @[package.scala:267:30]\n wire io_x_eff_0 = io_x_eff;\t// @[package.scala:267:30]\n wire io_x_c_0 = io_x_c;\t// @[package.scala:267:30]\n wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage;\t// @[package.scala:267:30]\n wire [19:0] io_y_ppn = io_x_ppn_0;\t// @[package.scala:267:30]\n wire io_y_u_0 = io_x_u_0;\t// @[package.scala:267:30]\n wire io_y_g = io_x_g_0;\t// @[package.scala:267:30]\n wire io_y_ae_ptw_0 = io_x_ae_ptw_0;\t// @[package.scala:267:30]\n wire io_y_ae_final_0 = io_x_ae_final_0;\t// @[package.scala:267:30]\n wire io_y_ae_stage2_0 = io_x_ae_stage2_0;\t// @[package.scala:267:30]\n wire io_y_pf_0 = io_x_pf_0;\t// @[package.scala:267:30]\n wire io_y_gf_0 = io_x_gf_0;\t// @[package.scala:267:30]\n wire io_y_sw_0 = io_x_sw_0;\t// @[package.scala:267:30]\n wire io_y_sx_0 = io_x_sx_0;\t// @[package.scala:267:30]\n wire io_y_sr_0 = io_x_sr_0;\t// @[package.scala:267:30]\n wire io_y_hw_0 = io_x_hw_0;\t// @[package.scala:267:30]\n wire io_y_hx_0 = io_x_hx_0;\t// @[package.scala:267:30]\n wire io_y_hr_0 = io_x_hr_0;\t// @[package.scala:267:30]\n wire io_y_pw_0 = io_x_pw_0;\t// @[package.scala:267:30]\n wire io_y_px_0 = io_x_px_0;\t// @[package.scala:267:30]\n wire io_y_pr_0 = io_x_pr_0;\t// @[package.scala:267:30]\n wire io_y_ppp_0 = io_x_ppp_0;\t// @[package.scala:267:30]\n wire io_y_pal_0 = io_x_pal_0;\t// @[package.scala:267:30]\n wire io_y_paa_0 = io_x_paa_0;\t// @[package.scala:267:30]\n wire io_y_eff_0 = io_x_eff_0;\t// @[package.scala:267:30]\n wire io_y_c_0 = io_x_c_0;\t// @[package.scala:267:30]\n wire io_y_fragmented_superpage = io_x_fragmented_superpage_0;\t// @[package.scala:267:30]\n assign io_y_u = io_y_u_0;\t// @[package.scala:267:30]\n assign io_y_ae_ptw = io_y_ae_ptw_0;\t// @[package.scala:267:30]\n assign io_y_ae_final = io_y_ae_final_0;\t// @[package.scala:267:30]\n assign io_y_ae_stage2 = io_y_ae_stage2_0;\t// @[package.scala:267:30]\n assign io_y_pf = io_y_pf_0;\t// @[package.scala:267:30]\n assign io_y_gf = io_y_gf_0;\t// @[package.scala:267:30]\n assign io_y_sw = io_y_sw_0;\t// @[package.scala:267:30]\n assign io_y_sx = io_y_sx_0;\t// @[package.scala:267:30]\n assign io_y_sr = io_y_sr_0;\t// @[package.scala:267:30]\n assign io_y_hw = io_y_hw_0;\t// @[package.scala:267:30]\n assign io_y_hx = io_y_hx_0;\t// @[package.scala:267:30]\n assign io_y_hr = io_y_hr_0;\t// @[package.scala:267:30]\n assign io_y_pw = io_y_pw_0;\t// @[package.scala:267:30]\n assign io_y_px = io_y_px_0;\t// @[package.scala:267:30]\n assign io_y_pr = io_y_pr_0;\t// @[package.scala:267:30]\n assign io_y_ppp = io_y_ppp_0;\t// @[package.scala:267:30]\n assign io_y_pal = io_y_pal_0;\t// @[package.scala:267:30]\n assign io_y_paa = io_y_paa_0;\t// @[package.scala:267:30]\n assign io_y_eff = io_y_eff_0;\t// @[package.scala:267:30]\n assign io_y_c = io_y_c_0;\t// @[package.scala:267:30]\nendmodule"}}},{"rowIdx":2098,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile IngressUnit.scala:\npackage constellation.router\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.util._\n\nimport constellation.channel._\n\nclass IngressUnit(\n ingressNodeId: Int,\n cParam: IngressChannelParams,\n outParams: Seq[ChannelParams],\n egressParams: Seq[EgressChannelParams],\n combineRCVA: Boolean,\n combineSAST: Boolean,\n)\n (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {\n\n class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {\n val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))\n }\n val io = IO(new IngressUnitIO)\n\n val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))\n val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,\n flow=combineRCVA))\n\n assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n\n route_buffer.io.enq.bits.head := io.in.bits.head\n route_buffer.io.enq.bits.tail := io.in.bits.tail\n val flows = cParam.possibleFlows.toSeq\n if (flows.size == 0) {\n route_buffer.io.enq.bits.flow := DontCare\n } else {\n route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U\n route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U\n route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U\n route_buffer.io.enq.bits.flow.egress_node := Mux1H(\n flows.map(_.egressId.U === io.in.bits.egress_id),\n flows.map(_.egressNode.U)\n )\n route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(\n flows.map(_.egressId.U === io.in.bits.egress_id),\n flows.map(_.egressNodeId.U)\n )\n }\n route_buffer.io.enq.bits.payload := io.in.bits.payload\n route_buffer.io.enq.bits.virt_channel_id := DontCare\n io.router_req.bits.src_virt_id := 0.U\n io.router_req.bits.flow := route_buffer.io.enq.bits.flow\n\n val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U\n route_buffer.io.enq.valid := io.in.valid && (\n io.router_req.ready || !io.in.bits.head || at_dest)\n io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest\n io.in.ready := route_buffer.io.enq.ready && (\n io.router_req.ready || !io.in.bits.head || at_dest)\n\n route_q.io.enq.valid := io.router_req.fire\n route_q.io.enq.bits := io.router_resp\n when (io.in.fire && io.in.bits.head && at_dest) {\n route_q.io.enq.valid := true.B\n route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))\n for (o <- 0 until nEgress) {\n when (egressParams(o).egressId.U === io.in.bits.egress_id) {\n route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B\n }\n }\n }\n assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n\n val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))\n val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),\n 1, pipe=true))\n\n vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits\n\n io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel\n io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow\n io.vcalloc_req.bits.in_vc := 0.U\n\n val head = route_buffer.io.deq.bits.head\n val tail = route_buffer.io.deq.bits.tail\n vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&\n (route_q.io.deq.valid || !head) &&\n (io.vcalloc_req.ready || !head)\n )\n io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&\n head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)\n route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&\n (route_q.io.deq.valid || !head) &&\n (io.vcalloc_req.ready || !head) &&\n (vcalloc_q.io.enq.ready || !head))\n route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)\n\n\n vcalloc_q.io.enq.valid := io.vcalloc_req.fire\n vcalloc_q.io.enq.bits := io.vcalloc_resp\n assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n\n io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel\n io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail\n\n val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U\n val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail\n io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block\n vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block\n vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire\n\n val out_bundle = if (combineSAST) {\n Wire(Valid(new SwitchBundle(outParams, egressParams)))\n } else {\n Reg(Valid(new SwitchBundle(outParams, egressParams)))\n }\n io.out(0) := out_bundle\n\n out_bundle.valid := vcalloc_buffer.io.deq.fire\n out_bundle.bits.flit := vcalloc_buffer.io.deq.bits\n out_bundle.bits.flit.virt_channel_id := 0.U\n val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq\n out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,\n vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)\n\n io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready\n io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready\n\n // TODO: We should not generate input/ingress/output/egress units for untraversable channels\n if (!cParam.traversable) {\n io.in.ready := false.B\n io.router_req.valid := false.B\n io.router_req.bits := DontCare\n io.vcalloc_req.valid := false.B\n io.vcalloc_req.bits := DontCare\n io.salloc_req.foreach(_.valid := false.B)\n io.salloc_req.foreach(_.bits := DontCare)\n io.out.foreach(_.valid := false.B)\n io.out.foreach(_.bits := DontCare)\n }\n\n}\n"},"response":{"kind":"string","value":"module IngressUnit_33(\t// @[IngressUnit.scala:11:7]\n input clock,\t// @[IngressUnit.scala:11:7]\n input reset,\t// @[IngressUnit.scala:11:7]\n output [3:0] io_router_req_bits_flow_egress_node,\t// @[IngressUnit.scala:24:14]\n input io_router_resp_vc_sel_0_0,\t// @[IngressUnit.scala:24:14]\n input io_router_resp_vc_sel_0_1,\t// @[IngressUnit.scala:24:14]\n input io_router_resp_vc_sel_0_2,\t// @[IngressUnit.scala:24:14]\n input io_router_resp_vc_sel_0_3,\t// @[IngressUnit.scala:24:14]\n input io_vcalloc_req_ready,\t// @[IngressUnit.scala:24:14]\n output io_vcalloc_req_valid,\t// @[IngressUnit.scala:24:14]\n output io_vcalloc_req_bits_vc_sel_1_0,\t// @[IngressUnit.scala:24:14]\n output io_vcalloc_req_bits_vc_sel_0_0,\t// @[IngressUnit.scala:24:14]\n output io_vcalloc_req_bits_vc_sel_0_1,\t// @[IngressUnit.scala:24:14]\n output io_vcalloc_req_bits_vc_sel_0_2,\t// @[IngressUnit.scala:24:14]\n output io_vcalloc_req_bits_vc_sel_0_3,\t// @[IngressUnit.scala:24:14]\n input io_vcalloc_resp_vc_sel_1_0,\t// @[IngressUnit.scala:24:14]\n input io_vcalloc_resp_vc_sel_0_0,\t// @[IngressUnit.scala:24:14]\n input io_vcalloc_resp_vc_sel_0_1,\t// @[IngressUnit.scala:24:14]\n input io_vcalloc_resp_vc_sel_0_2,\t// @[IngressUnit.scala:24:14]\n input io_vcalloc_resp_vc_sel_0_3,\t// @[IngressUnit.scala:24:14]\n input io_out_credit_available_1_0,\t// @[IngressUnit.scala:24:14]\n input io_out_credit_available_0_0,\t// @[IngressUnit.scala:24:14]\n input io_out_credit_available_0_1,\t// @[IngressUnit.scala:24:14]\n input io_out_credit_available_0_3,\t// @[IngressUnit.scala:24:14]\n input io_salloc_req_0_ready,\t// @[IngressUnit.scala:24:14]\n output io_salloc_req_0_valid,\t// @[IngressUnit.scala:24:14]\n output io_salloc_req_0_bits_vc_sel_1_0,\t// @[IngressUnit.scala:24:14]\n output io_salloc_req_0_bits_vc_sel_0_0,\t// @[IngressUnit.scala:24:14]\n output io_salloc_req_0_bits_vc_sel_0_1,\t// @[IngressUnit.scala:24:14]\n output io_salloc_req_0_bits_vc_sel_0_2,\t// @[IngressUnit.scala:24:14]\n output io_salloc_req_0_bits_vc_sel_0_3,\t// @[IngressUnit.scala:24:14]\n output io_salloc_req_0_bits_tail,\t// @[IngressUnit.scala:24:14]\n output io_out_0_valid,\t// @[IngressUnit.scala:24:14]\n output io_out_0_bits_flit_head,\t// @[IngressUnit.scala:24:14]\n output io_out_0_bits_flit_tail,\t// @[IngressUnit.scala:24:14]\n output [36:0] io_out_0_bits_flit_payload,\t// @[IngressUnit.scala:24:14]\n output io_out_0_bits_flit_flow_vnet_id,\t// @[IngressUnit.scala:24:14]\n output [3:0] io_out_0_bits_flit_flow_ingress_node,\t// @[IngressUnit.scala:24:14]\n output io_out_0_bits_flit_flow_ingress_node_id,\t// @[IngressUnit.scala:24:14]\n output [3:0] io_out_0_bits_flit_flow_egress_node,\t// @[IngressUnit.scala:24:14]\n output io_out_0_bits_flit_flow_egress_node_id,\t// @[IngressUnit.scala:24:14]\n output [1:0] io_out_0_bits_out_virt_channel,\t// @[IngressUnit.scala:24:14]\n output io_in_ready,\t// @[IngressUnit.scala:24:14]\n input io_in_valid,\t// @[IngressUnit.scala:24:14]\n input io_in_bits_head,\t// @[IngressUnit.scala:24:14]\n input io_in_bits_tail,\t// @[IngressUnit.scala:24:14]\n input [36:0] io_in_bits_payload,\t// @[IngressUnit.scala:24:14]\n input [3:0] io_in_bits_egress_id\t// @[IngressUnit.scala:24:14]\n);\n\n wire _vcalloc_q_io_enq_ready;\t// @[IngressUnit.scala:76:25]\n wire _vcalloc_q_io_deq_valid;\t// @[IngressUnit.scala:76:25]\n wire _vcalloc_q_io_deq_bits_vc_sel_1_0;\t// @[IngressUnit.scala:76:25]\n wire _vcalloc_q_io_deq_bits_vc_sel_0_0;\t// @[IngressUnit.scala:76:25]\n wire _vcalloc_q_io_deq_bits_vc_sel_0_1;\t// @[IngressUnit.scala:76:25]\n wire _vcalloc_q_io_deq_bits_vc_sel_0_2;\t// @[IngressUnit.scala:76:25]\n wire _vcalloc_q_io_deq_bits_vc_sel_0_3;\t// @[IngressUnit.scala:76:25]\n wire _vcalloc_buffer_io_enq_ready;\t// @[IngressUnit.scala:75:30]\n wire _vcalloc_buffer_io_deq_valid;\t// @[IngressUnit.scala:75:30]\n wire _vcalloc_buffer_io_deq_bits_head;\t// @[IngressUnit.scala:75:30]\n wire _vcalloc_buffer_io_deq_bits_tail;\t// @[IngressUnit.scala:75:30]\n wire [36:0] _vcalloc_buffer_io_deq_bits_payload;\t// @[IngressUnit.scala:75:30]\n wire _vcalloc_buffer_io_deq_bits_flow_vnet_id;\t// @[IngressUnit.scala:75:30]\n wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node;\t// @[IngressUnit.scala:75:30]\n wire _vcalloc_buffer_io_deq_bits_flow_ingress_node_id;\t// @[IngressUnit.scala:75:30]\n wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node;\t// @[IngressUnit.scala:75:30]\n wire _vcalloc_buffer_io_deq_bits_flow_egress_node_id;\t// @[IngressUnit.scala:75:30]\n wire _route_q_io_enq_ready;\t// @[IngressUnit.scala:27:23]\n wire _route_q_io_deq_valid;\t// @[IngressUnit.scala:27:23]\n wire _route_buffer_io_enq_ready;\t// @[IngressUnit.scala:26:28]\n wire _route_buffer_io_deq_valid;\t// @[IngressUnit.scala:26:28]\n wire _route_buffer_io_deq_bits_head;\t// @[IngressUnit.scala:26:28]\n wire _route_buffer_io_deq_bits_tail;\t// @[IngressUnit.scala:26:28]\n wire [36:0] _route_buffer_io_deq_bits_payload;\t// @[IngressUnit.scala:26:28]\n wire _route_buffer_io_deq_bits_flow_vnet_id;\t// @[IngressUnit.scala:26:28]\n wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node;\t// @[IngressUnit.scala:26:28]\n wire _route_buffer_io_deq_bits_flow_ingress_node_id;\t// @[IngressUnit.scala:26:28]\n wire [3:0] _route_buffer_io_deq_bits_flow_egress_node;\t// @[IngressUnit.scala:26:28]\n wire _route_buffer_io_deq_bits_flow_egress_node_id;\t// @[IngressUnit.scala:26:28]\n wire [1:0] _route_buffer_io_deq_bits_virt_channel_id;\t// @[IngressUnit.scala:26:28]\n wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'h5;\t// @[IngressUnit.scala:30:72]\n wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h2;\t// @[IngressUnit.scala:30:72]\n wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h4;\t// @[IngressUnit.scala:30:72]\n wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h7;\t// @[IngressUnit.scala:30:72]\n wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 4'h6;\t// @[IngressUnit.scala:30:72]\n wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 4'h8;\t// @[IngressUnit.scala:30:72]\n wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 4'h3;\t// @[IngressUnit.scala:30:72]\n wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_T_20 = {_route_buffer_io_enq_bits_flow_egress_node_id_T, {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_1} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_2}}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_5}};\t// @[Mux.scala:30:73]\n wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_T_20[2], _route_buffer_io_enq_bits_flow_egress_node_T_20[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_6, 1'h0}};\t// @[Mux.scala:30:73]\n wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head;\t// @[IngressUnit.scala:26:28, :58:{38,67}]\n wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready;\t// @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]\n wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head);\t// @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]\n wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0;\t// @[Decoupled.scala:51:35]"}}},{"rowIdx":2099,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to the following Chisel files.\nFile Monitor.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceLine\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy._\n\nimport freechips.rocketchip.diplomacy.EnableMonitors\nimport freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}\nimport freechips.rocketchip.util.PlusArg\n\ncase class TLMonitorArgs(edge: TLEdge)\n\nabstract class TLMonitorBase(args: TLMonitorArgs) extends Module\n{\n val io = IO(new Bundle {\n val in = Input(new TLBundle(args.edge.bundle))\n })\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit\n legalize(io.in, args.edge, reset)\n}\n\nobject TLMonitor {\n def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {\n if (enable) {\n EnableMonitors { implicit p => node := TLEphemeralNode()(ValName(\"monitor\")) }\n } else { node }\n }\n}\n\nclass TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)\n{\n require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))\n\n val cover_prop_class = PropertyClass.Default\n\n //Like assert but can flip to being an assumption for formal verification\n def monAssert(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir, cond, message, PropertyClass.Default)\n }\n\n def assume(cond: Bool, message: String): Unit =\n if (monitorDir == MonitorDirection.Monitor) {\n assert(cond, message)\n } else {\n Property(monitorDir.flip, cond, message, PropertyClass.Default)\n }\n\n def extra = {\n args.edge.sourceInfo match {\n case SourceLine(filename, line, col) => s\" (connected at $filename:$line:$col)\"\n case _ => \"\"\n }\n }\n\n def visible(address: UInt, source: UInt, edge: TLEdge) =\n edge.client.clients.map { c =>\n !c.sourceId.contains(source) ||\n c.visibility.map(_.contains(address)).reduce(_ || _)\n }.reduce(_ && _)\n\n def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {\n //switch this flag to turn on diplomacy in error messages\n def diplomacyInfo = if (true) \"\" else \"\\nThe diplomacy information for the edge is as follows:\\n\" + edge.formatEdge + \"\\n\"\n monAssert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n\n // Reuse these subexpressions to save some firrtl lines\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n\n //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B\n //TODO: check for acquireT?\n when (bundle.opcode === TLMessages.AcquireBlock) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquireBlock smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquireBlock contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AcquirePerm) {\n monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'A' channel AcquirePerm smaller than a beat\" + extra)\n monAssert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n monAssert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n monAssert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n monAssert (~bundle.mask === 0.U, \"'A' channel AcquirePerm contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.emitsGet(bundle.source, bundle.size), \"'A' channel carries Get type which master claims it can't emit\" + diplomacyInfo + extra)\n monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), \"'A' channel carries Get type which slave claims it can't support\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel Get carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type which is unexpected using diplomatic parameters\" + diplomacyInfo + extra)\n monAssert (source_ok, \"'A' channel PutFull carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'A' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'A' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Logical carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type which is unexpected using diplomatic parameters\" + extra)\n monAssert (source_ok, \"'A' channel Hint carries invalid source ID\" + diplomacyInfo + extra)\n monAssert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n monAssert (TLHints.isHints(bundle.param), \"'A' channel Hint carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {\n monAssert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n\n // Reuse these subexpressions to save some firrtl lines\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val mask = edge.full_mask(bundle)\n val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source\n\n when (bundle.opcode === TLMessages.Probe) {\n assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'B' channel carries Probe type which is unexpected using diplomatic parameters\" + extra)\n assume (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n assume (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n assume (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n assume (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n assume (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Get) {\n monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), \"'B' channel carries Get type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel Get carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutFullData) {\n monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutFull type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutFull carries invalid param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.PutPartialData) {\n monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), \"'B' channel carries PutPartial type which is unexpected using diplomatic parameters\" + extra)\n monAssert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'B' channel PutPartial carries invalid param\" + extra)\n monAssert ((bundle.mask & ~mask) === 0.U, \"'B' channel PutPartial contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ArithmeticData) {\n monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), \"'B' channel carries Arithmetic type unsupported by master\" + extra)\n monAssert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n monAssert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.LogicalData) {\n monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n monAssert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Hint) {\n monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n monAssert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n monAssert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n monAssert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n monAssert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n monAssert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n }\n }\n\n def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {\n monAssert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val is_aligned = edge.isAligned(bundle.address, bundle.size)\n val address_ok = edge.manager.containsSafe(edge.address(bundle))\n\n monAssert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n\n when (bundle.opcode === TLMessages.ProbeAck) {\n monAssert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAck smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ProbeAckData) {\n monAssert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ProbeAckData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Release) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel Release smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel Release carries invalid report param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.ReleaseData) {\n monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n monAssert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'C' channel ReleaseData smaller than a beat\" + extra)\n monAssert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n monAssert (TLPermissions.isReport(bundle.param), \"'C' channel ReleaseData carries invalid report param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n monAssert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n monAssert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel AccessAckData carries invalid param\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n monAssert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n monAssert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n monAssert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n monAssert (bundle.param === 0.U, \"'C' channel HintAck carries invalid param\" + extra)\n monAssert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n }\n }\n\n def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {\n assume (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n\n val source_ok = edge.client.contains(bundle.source)\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n val deny_put_ok = edge.manager.mayDenyPut.B\n val deny_get_ok = edge.manager.mayDenyGet.B\n\n when (bundle.opcode === TLMessages.ReleaseAck) {\n assume (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel ReleaseAck smaller than a beat\" + extra)\n assume (bundle.param === 0.U, \"'D' channel ReleaseeAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n assume (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.Grant) {\n assume (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel Grant smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n assume (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.GrantData) {\n assume (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n assume (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, \"'D' channel GrantData smaller than a beat\" + extra)\n assume (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n assume (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAck) {\n assume (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.AccessAckData) {\n assume (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel AccessAckData carries invalid param\" + extra)\n assume (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n assume (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n }\n\n when (bundle.opcode === TLMessages.HintAck) {\n assume (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n // size is ignored\n assume (bundle.param === 0.U, \"'D' channel HintAck carries invalid param\" + extra)\n assume (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n assume (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n }\n }\n\n def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {\n val sink_ok = bundle.sink < edge.manager.endSinkId.U\n monAssert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n }\n\n def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {\n when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }\n when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }\n when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }\n when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }\n } else {\n monAssert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n monAssert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n monAssert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n }\n }\n\n def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {\n val a_first = edge.first(a.bits, a.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (a.valid && !a_first) {\n monAssert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n monAssert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n monAssert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n monAssert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n monAssert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n }\n when (a.fire && a_first) {\n opcode := a.bits.opcode\n param := a.bits.param\n size := a.bits.size\n source := a.bits.source\n address := a.bits.address\n }\n }\n\n def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {\n val b_first = edge.first(b.bits, b.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (b.valid && !b_first) {\n monAssert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n monAssert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n monAssert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n monAssert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n monAssert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n }\n when (b.fire && b_first) {\n opcode := b.bits.opcode\n param := b.bits.param\n size := b.bits.size\n source := b.bits.source\n address := b.bits.address\n }\n }\n\n def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {\n // Symbolic variable\n val sym_source = Wire(UInt(edge.client.endSourceId.W))\n // TODO: Connect sym_source to a fixed value for simulation and to a\n // free wire in formal\n sym_source := 0.U\n\n // Type casting Int to UInt\n val maxSourceId = Wire(UInt(edge.client.endSourceId.W))\n maxSourceId := edge.client.endSourceId.U\n\n // Delayed verison of sym_source\n val sym_source_d = Reg(UInt(edge.client.endSourceId.W))\n sym_source_d := sym_source\n\n // These will be constraints for FV setup\n Property(\n MonitorDirection.Monitor,\n (sym_source === sym_source_d),\n \"sym_source should remain stable\",\n PropertyClass.Default)\n Property(\n MonitorDirection.Monitor,\n (sym_source <= maxSourceId),\n \"sym_source should take legal value\",\n PropertyClass.Default)\n\n val my_resp_pend = RegInit(false.B)\n val my_opcode = Reg(UInt())\n val my_size = Reg(UInt())\n\n val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)\n\n val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)\n val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)\n\n val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)\n val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)\n when (my_set_resp_pend) {\n my_resp_pend := true.B\n } .elsewhen (my_clr_resp_pend) {\n my_resp_pend := false.B\n }\n\n when (my_a_first_beat) {\n my_opcode := bundle.a.bits.opcode\n my_size := bundle.a.bits.size\n }\n\n val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)\n val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)\n\n val my_resp_opcode_legal = Wire(Bool())\n when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||\n (my_resp_opcode === TLMessages.LogicalData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)\n } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)\n } .otherwise {\n my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)\n }\n\n monAssert (IfThen(my_resp_pend, !my_a_first_beat),\n \"Request message should not be sent with a source ID, for which a response message\" +\n \"is already pending (not received until current cycle) for a prior request message\" +\n \"with the same source ID\" + extra)\n\n assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),\n \"Response message should be accepted with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being accepted in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),\n \"Response message should be sent with a source ID only if a request message with the\" +\n \"same source ID has been accepted or is being sent in the current cycle\" + extra)\n assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),\n \"If d_valid is 1, then d_size should be same as a_size of the corresponding request\" +\n \"message\" + extra)\n assume (IfThen(my_d_first_beat, my_resp_opcode_legal),\n \"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding\" +\n \"request message\" + extra)\n }\n\n def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {\n val c_first = edge.first(c.bits, c.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val address = Reg(UInt())\n when (c.valid && !c_first) {\n monAssert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n monAssert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n monAssert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n monAssert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n monAssert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n }\n when (c.fire && c_first) {\n opcode := c.bits.opcode\n param := c.bits.param\n size := c.bits.size\n source := c.bits.source\n address := c.bits.address\n }\n }\n\n def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {\n val d_first = edge.first(d.bits, d.fire)\n val opcode = Reg(UInt())\n val param = Reg(UInt())\n val size = Reg(UInt())\n val source = Reg(UInt())\n val sink = Reg(UInt())\n val denied = Reg(Bool())\n when (d.valid && !d_first) {\n assume (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n assume (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n assume (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n assume (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n assume (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n assume (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n }\n when (d.fire && d_first) {\n opcode := d.bits.opcode\n param := d.bits.param\n size := d.bits.size\n source := d.bits.source\n sink := d.bits.sink\n denied := d.bits.denied\n }\n }\n\n def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {\n legalizeMultibeatA(bundle.a, edge)\n legalizeMultibeatD(bundle.d, edge)\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n legalizeMultibeatB(bundle.b, edge)\n legalizeMultibeatC(bundle.c, edge)\n }\n }\n\n //This is left in for almond which doesn't adhere to the tilelink protocol\n @deprecated(\"Use legalizeADSource instead if possible\",\"\")\n def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.client.endSourceId.W))\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n assume((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n assert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)\n val log_a_size_bus_size = log2Ceil(a_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error\n inflight.suggestName(\"inflight\")\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val a_first = edge.first(bundle.a.bits, bundle.a.fire)\n a_first.suggestName(\"a_first\")\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n d_first.suggestName(\"d_first\")\n\n val a_set = WireInit(0.U(edge.client.endSourceId.W))\n val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n a_set.suggestName(\"a_set\")\n a_set_wo_ready.suggestName(\"a_set_wo_ready\")\n val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n a_opcodes_set.suggestName(\"a_opcodes_set\")\n val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n a_sizes_set.suggestName(\"a_sizes_set\")\n\n val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))\n a_opcode_lookup.suggestName(\"a_opcode_lookup\")\n a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U\n\n val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))\n a_size_lookup.suggestName(\"a_size_lookup\")\n a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U\n\n val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))\n val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))\n\n val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))\n a_opcodes_set_interm.suggestName(\"a_opcodes_set_interm\")\n val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))\n a_sizes_set_interm.suggestName(\"a_sizes_set_interm\")\n\n when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {\n a_set_wo_ready := UIntToOH(bundle.a.bits.source)\n }\n\n when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {\n a_set := UIntToOH(bundle.a.bits.source)\n a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U\n a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U\n a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)\n a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)\n monAssert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n }\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)\n }\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {\n val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n\n when (same_cycle_resp) {\n assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.a.bits.size === bundle.d.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||\n (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), \"'D' channel contains improper opcode response\" + extra)\n assume((bundle.d.bits.size === a_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {\n assume((!bundle.d.ready) || bundle.a.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s\"'A' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n\n inflight := (inflight | a_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {\n val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)\n val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything\n\n val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)\n val log_c_size_bus_size = log2Ceil(c_size_bus_size)\n def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits\n\n val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))\n val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n inflight.suggestName(\"inflight\")\n inflight_opcodes.suggestName(\"inflight_opcodes\")\n inflight_sizes.suggestName(\"inflight_sizes\")\n\n val c_first = edge.first(bundle.c.bits, bundle.c.fire)\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n c_first.suggestName(\"c_first\")\n d_first.suggestName(\"d_first\")\n\n val c_set = WireInit(0.U(edge.client.endSourceId.W))\n val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n c_set.suggestName(\"c_set\")\n c_set_wo_ready.suggestName(\"c_set_wo_ready\")\n c_opcodes_set.suggestName(\"c_opcodes_set\")\n c_sizes_set.suggestName(\"c_sizes_set\")\n\n val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))\n val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))\n c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U\n c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U\n c_opcode_lookup.suggestName(\"c_opcode_lookup\")\n c_size_lookup.suggestName(\"c_size_lookup\")\n\n val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))\n val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))\n c_opcodes_set_interm.suggestName(\"c_opcodes_set_interm\")\n c_sizes_set_interm.suggestName(\"c_sizes_set_interm\")\n\n when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {\n c_set_wo_ready := UIntToOH(bundle.c.bits.source)\n }\n\n when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {\n c_set := UIntToOH(bundle.c.bits.source)\n c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U\n c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U\n c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)\n c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)\n monAssert(!inflight(bundle.c.bits.source), \"'C' channel re-used a source ID\" + extra)\n }\n\n val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData\n\n val d_clr = WireInit(0.U(edge.client.endSourceId.W))\n val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))\n val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))\n val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))\n d_clr.suggestName(\"d_clr\")\n d_clr_wo_ready.suggestName(\"d_clr_wo_ready\")\n d_opcodes_clr.suggestName(\"d_opcodes_clr\")\n d_sizes_clr.suggestName(\"d_sizes_clr\")\n\n val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr_wo_ready := UIntToOH(bundle.d.bits.source)\n }\n\n when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n d_clr := UIntToOH(bundle.d.bits.source)\n d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)\n d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)\n }\n\n when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {\n val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)\n assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, \"'D' channel acknowledged for nothing inflight\" + extra)\n when (same_cycle_resp) {\n assume((bundle.d.bits.size === bundle.c.bits.size), \"'D' channel contains improper response size\" + extra)\n } .otherwise {\n assume((bundle.d.bits.size === c_size_lookup), \"'D' channel contains improper response size\" + extra)\n }\n }\n\n when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {\n assume((!bundle.d.ready) || bundle.c.ready, \"ready check\")\n }\n\n if (edge.manager.minLatency > 0) {\n when (c_set_wo_ready.orR) {\n assume(c_set_wo_ready =/= d_clr_wo_ready, s\"'C' and 'D' concurrent, despite minlatency > 0\" + extra)\n }\n }\n\n inflight := (inflight | c_set) & ~d_clr\n inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr\n inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr\n\n val watchdog = RegInit(0.U(32.W))\n val limit = PlusArg(\"tilelink_timeout\",\n docstring=\"Kill emulation after INT waiting TileLink cycles. Off if 0.\")\n monAssert (!inflight.orR || limit === 0.U || watchdog < limit, \"TileLink timeout expired\" + extra)\n\n watchdog := watchdog + 1.U\n when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }\n }\n\n def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {\n val inflight = RegInit(0.U(edge.manager.endSinkId.W))\n\n val d_first = edge.first(bundle.d.bits, bundle.d.fire)\n val e_first = true.B\n\n val d_set = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {\n d_set := UIntToOH(bundle.d.bits.sink)\n assume(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n }\n\n val e_clr = WireInit(0.U(edge.manager.endSinkId.W))\n when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {\n e_clr := UIntToOH(bundle.e.bits.sink)\n monAssert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n }\n\n // edge.client.minLatency applies to BC, not DE\n\n inflight := (inflight | d_set) & ~e_clr\n }\n\n def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {\n val sourceBits = log2Ceil(edge.client.endSourceId)\n val tooBig = 14 // >16kB worth of flight information gets to be too much\n if (sourceBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked\")\n } else {\n if (args.edge.params(TestplanTestType).simulation) {\n if (args.edge.params(TLMonitorStrictMode)) {\n legalizeADSource(bundle, edge)\n legalizeCDSource(bundle, edge)\n } else {\n legalizeADSourceOld(bundle, edge)\n }\n }\n if (args.edge.params(TestplanTestType).formal) {\n legalizeADSourceFormal(bundle, edge)\n }\n }\n if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {\n // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...\n val sinkBits = log2Ceil(edge.manager.endSinkId)\n if (sinkBits > tooBig) {\n println(s\"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked\")\n } else {\n legalizeDESink(bundle, edge)\n }\n }\n }\n\n def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {\n legalizeFormat (bundle, edge)\n legalizeMultibeat (bundle, edge)\n legalizeUnique (bundle, edge)\n }\n}\nFile Misc.scala:\n// See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random.LFSR\nimport org.chipsalliance.cde.config.Parameters\nimport scala.math._\n\nclass ParameterizedBundle(implicit p: Parameters) extends Bundle\n\ntrait Clocked extends Bundle {\n val clock = Clock()\n val reset = Bool() \n}\n\nobject DecoupledHelper {\n def apply(rvs: Bool*) = new DecoupledHelper(rvs)\n}\n\nclass DecoupledHelper(val rvs: Seq[Bool]) {\n def fire(exclude: Bool, includes: Bool*) = {\n require(rvs.contains(exclude), \"Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!\")\n (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)\n }\n def fire() = {\n rvs.reduce(_ && _)\n }\n}\n\nobject MuxT {\n def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))\n\n def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))\n\n def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =\n (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))\n}\n\n/** Creates a cascade of n MuxTs to search for a key value. */\nobject MuxTLookup {\n def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n\n def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {\n var res = default\n for ((k, v) <- mapping.reverse)\n res = MuxT(k === key, v, res)\n res\n }\n}\n\nobject ValidMux {\n def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {\n apply(v1 +: v2.toSeq)\n }\n def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {\n val out = Wire(Valid(valids.head.bits.cloneType))\n out.valid := valids.map(_.valid).reduce(_ || _)\n out.bits := MuxCase(valids.head.bits,\n valids.map(v => (v.valid -> v.bits)))\n out\n }\n}\n\nobject Str\n{\n def apply(s: String): UInt = {\n var i = BigInt(0)\n require(s.forall(validChar _))\n for (c <- s)\n i = (i << 8) | c\n i.U((s.length*8).W)\n }\n def apply(x: Char): UInt = {\n require(validChar(x))\n x.U(8.W)\n }\n def apply(x: UInt): UInt = apply(x, 10)\n def apply(x: UInt, radix: Int): UInt = {\n val rad = radix.U\n val w = x.getWidth\n require(w > 0)\n\n var q = x\n var s = digit(q % rad)\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)\n }\n s\n }\n def apply(x: SInt): UInt = apply(x, 10)\n def apply(x: SInt, radix: Int): UInt = {\n val neg = x < 0.S\n val abs = x.abs.asUInt\n if (radix != 10) {\n Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))\n } else {\n val rad = radix.U\n val w = abs.getWidth\n require(w > 0)\n\n var q = abs\n var s = digit(q % rad)\n var needSign = neg\n for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {\n q = q / rad\n val placeSpace = q === 0.U\n val space = Mux(needSign, Str('-'), Str(' '))\n needSign = needSign && !placeSpace\n s = Cat(Mux(placeSpace, space, digit(q % rad)), s)\n }\n Cat(Mux(needSign, Str('-'), Str(' ')), s)\n }\n }\n\n private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)\n private def validChar(x: Char) = x == (x & 0xFF)\n}\n\nobject Split\n{\n def apply(x: UInt, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {\n val w = x.getWidth\n (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))\n }\n}\n\nobject Random\n{\n def apply(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)\n else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))\n }\n def apply(mod: Int): UInt = apply(mod, randomizer)\n def oneHot(mod: Int, random: UInt): UInt = {\n if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))\n else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt\n }\n def oneHot(mod: Int): UInt = oneHot(mod, randomizer)\n\n private def randomizer = LFSR(16)\n private def partition(value: UInt, slices: Int) =\n Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)\n}\n\nobject Majority {\n def apply(in: Set[Bool]): Bool = {\n val n = (in.size >> 1) + 1\n val clauses = in.subsets(n).map(_.reduce(_ && _))\n clauses.reduce(_ || _)\n }\n\n def apply(in: Seq[Bool]): Bool = apply(in.toSet)\n\n def apply(in: UInt): Bool = apply(in.asBools.toSet)\n}\n\nobject PopCountAtLeast {\n private def two(x: UInt): (Bool, Bool) = x.getWidth match {\n case 1 => (x.asBool, false.B)\n case n =>\n val half = x.getWidth / 2\n val (leftOne, leftTwo) = two(x(half - 1, 0))\n val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))\n (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))\n }\n def apply(x: UInt, n: Int): Bool = n match {\n case 0 => true.B\n case 1 => x.orR\n case 2 => two(x)._2\n case 3 => PopCount(x) >= n.U\n }\n}\n\n// This gets used everywhere, so make the smallest circuit possible ...\n// Given an address and size, create a mask of beatBytes size\n// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111\n// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01\nobject MaskGen {\n def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {\n require (groupBy >= 1 && beatBytes >= groupBy)\n require (isPow2(beatBytes) && isPow2(groupBy))\n val lgBytes = log2Ceil(beatBytes)\n val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U\n\n def helper(i: Int): Seq[(Bool, Bool)] = {\n if (i == 0) {\n Seq((lgSize >= lgBytes.asUInt, true.B))\n } else {\n val sub = helper(i-1)\n val size = sizeOH(lgBytes - i)\n val bit = addr_lo(lgBytes - i)\n val nbit = !bit\n Seq.tabulate (1 << i) { j =>\n val (sub_acc, sub_eq) = sub(j/2)\n val eq = sub_eq && (if (j % 2 == 1) bit else nbit)\n val acc = sub_acc || (size && eq)\n (acc, eq)\n }\n }\n }\n\n if (groupBy == beatBytes) 1.U else\n Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)\n }\n}\nFile PlusArg.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}\nFile package.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}\nFile Bundles.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport freechips.rocketchip.util._\nimport scala.collection.immutable.ListMap\nimport chisel3.util.Decoupled\nimport chisel3.util.DecoupledIO\nimport chisel3.reflect.DataMirror\n\nabstract class TLBundleBase(val params: TLBundleParameters) extends Bundle\n\n// common combos in lazy policy:\n// Put + Acquire\n// Release + AccessAck\n\nobject TLMessages\n{\n // A B C D E\n def PutFullData = 0.U // . . => AccessAck\n def PutPartialData = 1.U // . . => AccessAck\n def ArithmeticData = 2.U // . . => AccessAckData\n def LogicalData = 3.U // . . => AccessAckData\n def Get = 4.U // . . => AccessAckData\n def Hint = 5.U // . . => HintAck\n def AcquireBlock = 6.U // . => Grant[Data]\n def AcquirePerm = 7.U // . => Grant[Data]\n def Probe = 6.U // . => ProbeAck[Data]\n def AccessAck = 0.U // . .\n def AccessAckData = 1.U // . .\n def HintAck = 2.U // . .\n def ProbeAck = 4.U // .\n def ProbeAckData = 5.U // .\n def Release = 6.U // . => ReleaseAck\n def ReleaseData = 7.U // . => ReleaseAck\n def Grant = 4.U // . => GrantAck\n def GrantData = 5.U // . => GrantAck\n def ReleaseAck = 6.U // .\n def GrantAck = 0.U // .\n\n def isA(x: UInt) = x <= AcquirePerm\n def isB(x: UInt) = x <= Probe\n def isC(x: UInt) = x <= ReleaseData\n def isD(x: UInt) = x <= ReleaseAck\n\n def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)\n def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)\n\n def a = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"AcquireBlock\",TLPermissions.PermMsgGrow),\n (\"AcquirePerm\",TLPermissions.PermMsgGrow))\n\n def b = Seq( (\"PutFullData\",TLPermissions.PermMsgReserved),\n (\"PutPartialData\",TLPermissions.PermMsgReserved),\n (\"ArithmeticData\",TLAtomics.ArithMsg),\n (\"LogicalData\",TLAtomics.LogicMsg),\n (\"Get\",TLPermissions.PermMsgReserved),\n (\"Hint\",TLHints.HintsMsg),\n (\"Probe\",TLPermissions.PermMsgCap))\n\n def c = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"ProbeAck\",TLPermissions.PermMsgReport),\n (\"ProbeAckData\",TLPermissions.PermMsgReport),\n (\"Release\",TLPermissions.PermMsgReport),\n (\"ReleaseData\",TLPermissions.PermMsgReport))\n\n def d = Seq( (\"AccessAck\",TLPermissions.PermMsgReserved),\n (\"AccessAckData\",TLPermissions.PermMsgReserved),\n (\"HintAck\",TLPermissions.PermMsgReserved),\n (\"Invalid Opcode\",TLPermissions.PermMsgReserved),\n (\"Grant\",TLPermissions.PermMsgCap),\n (\"GrantData\",TLPermissions.PermMsgCap),\n (\"ReleaseAck\",TLPermissions.PermMsgReserved))\n\n}\n\n/**\n * The three primary TileLink permissions are:\n * (T)runk: the agent is (or is on inwards path to) the global point of serialization.\n * (B)ranch: the agent is on an outwards path to\n * (N)one:\n * These permissions are permuted by transfer operations in various ways.\n * Operations can cap permissions, request for them to be grown or shrunk,\n * or for a report on their current status.\n */\nobject TLPermissions\n{\n val aWidth = 2\n val bdWidth = 2\n val cWidth = 3\n\n // Cap types (Grant = new permissions, Probe = permisions <= target)\n def toT = 0.U(bdWidth.W)\n def toB = 1.U(bdWidth.W)\n def toN = 2.U(bdWidth.W)\n def isCap(x: UInt) = x <= toN\n\n // Grow types (Acquire = permissions >= target)\n def NtoB = 0.U(aWidth.W)\n def NtoT = 1.U(aWidth.W)\n def BtoT = 2.U(aWidth.W)\n def isGrow(x: UInt) = x <= BtoT\n\n // Shrink types (ProbeAck, Release)\n def TtoB = 0.U(cWidth.W)\n def TtoN = 1.U(cWidth.W)\n def BtoN = 2.U(cWidth.W)\n def isShrink(x: UInt) = x <= BtoN\n\n // Report types (ProbeAck, Release)\n def TtoT = 3.U(cWidth.W)\n def BtoB = 4.U(cWidth.W)\n def NtoN = 5.U(cWidth.W)\n def isReport(x: UInt) = x <= NtoN\n\n def PermMsgGrow:Seq[String] = Seq(\"Grow NtoB\", \"Grow NtoT\", \"Grow BtoT\")\n def PermMsgCap:Seq[String] = Seq(\"Cap toT\", \"Cap toB\", \"Cap toN\")\n def PermMsgReport:Seq[String] = Seq(\"Shrink TtoB\", \"Shrink TtoN\", \"Shrink BtoN\", \"Report TotT\", \"Report BtoB\", \"Report NtoN\")\n def PermMsgReserved:Seq[String] = Seq(\"Reserved\")\n}\n\nobject TLAtomics\n{\n val width = 3\n\n // Arithmetic types\n def MIN = 0.U(width.W)\n def MAX = 1.U(width.W)\n def MINU = 2.U(width.W)\n def MAXU = 3.U(width.W)\n def ADD = 4.U(width.W)\n def isArithmetic(x: UInt) = x <= ADD\n\n // Logical types\n def XOR = 0.U(width.W)\n def OR = 1.U(width.W)\n def AND = 2.U(width.W)\n def SWAP = 3.U(width.W)\n def isLogical(x: UInt) = x <= SWAP\n\n def ArithMsg:Seq[String] = Seq(\"MIN\", \"MAX\", \"MINU\", \"MAXU\", \"ADD\")\n def LogicMsg:Seq[String] = Seq(\"XOR\", \"OR\", \"AND\", \"SWAP\")\n}\n\n\nobject TLHints\n{\n val width = 1\n\n def PREFETCH_READ = 0.U(width.W)\n def PREFETCH_WRITE = 1.U(width.W)\n def isHints(x: UInt) = x <= PREFETCH_WRITE\n\n def HintsMsg:Seq[String] = Seq(\"PrefetchRead\", \"PrefetchWrite\")\n}\n\nsealed trait TLChannel extends TLBundleBase {\n val channelName: String\n}\n\nsealed trait TLDataChannel extends TLChannel\nsealed trait TLAddrChannel extends TLDataChannel\n\nfinal class TLBundleA(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleA_${params.shortName}\"\n val channelName = \"'A' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\nfinal class TLBundleB(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleB_${params.shortName}\"\n val channelName = \"'B' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val address = UInt(params.addressBits.W) // from\n // variable fields during multibeat:\n val mask = UInt((params.dataBits/8).W)\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleC(params: TLBundleParameters)\n extends TLBundleBase(params) with TLAddrChannel\n{\n override def typeName = s\"TLBundleC_${params.shortName}\"\n val channelName = \"'C' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.cWidth.W) // shrink or report perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // from\n val address = UInt(params.addressBits.W) // to\n val user = BundleMap(params.requestFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleD(params: TLBundleParameters)\n extends TLBundleBase(params) with TLDataChannel\n{\n override def typeName = s\"TLBundleD_${params.shortName}\"\n val channelName = \"'D' channel\"\n // fixed fields during multibeat:\n val opcode = UInt(3.W)\n val param = UInt(TLPermissions.bdWidth.W) // cap perms\n val size = UInt(params.sizeBits.W)\n val source = UInt(params.sourceBits.W) // to\n val sink = UInt(params.sinkBits.W) // from\n val denied = Bool() // implies corrupt iff *Data\n val user = BundleMap(params.responseFields)\n val echo = BundleMap(params.echoFields)\n // variable fields during multibeat:\n val data = UInt(params.dataBits.W)\n val corrupt = Bool() // only applies to *Data messages\n}\n\nfinal class TLBundleE(params: TLBundleParameters)\n extends TLBundleBase(params) with TLChannel\n{\n override def typeName = s\"TLBundleE_${params.shortName}\"\n val channelName = \"'E' channel\"\n val sink = UInt(params.sinkBits.W) // to\n}\n\nclass TLBundle(val params: TLBundleParameters) extends Record\n{\n // Emulate a Bundle with elements abcde or ad depending on params.hasBCE\n\n private val optA = Some (Decoupled(new TLBundleA(params)))\n private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))\n private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))\n private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))\n private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))\n\n def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))\n def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))\n def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))\n def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))\n def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))\n\n val elements =\n if (params.hasBCE) ListMap(\"e\" -> e, \"d\" -> d, \"c\" -> c, \"b\" -> b, \"a\" -> a)\n else ListMap(\"d\" -> d, \"a\" -> a)\n\n def tieoff(): Unit = {\n DataMirror.specifiedDirectionOf(a.ready) match {\n case SpecifiedDirection.Input =>\n a.ready := false.B\n c.ready := false.B\n e.ready := false.B\n b.valid := false.B\n d.valid := false.B\n case SpecifiedDirection.Output =>\n a.valid := false.B\n c.valid := false.B\n e.valid := false.B\n b.ready := false.B\n d.ready := false.B\n case _ =>\n }\n }\n}\n\nobject TLBundle\n{\n def apply(params: TLBundleParameters) = new TLBundle(params)\n}\n\nclass TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle\n\nclass TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)\n{\n val a = new AsyncBundle(new TLBundleA(params.base), params.async)\n val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))\n val c = new AsyncBundle(new TLBundleC(params.base), params.async)\n val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))\n val e = new AsyncBundle(new TLBundleE(params.base), params.async)\n}\n\nclass TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = RationalIO(new TLBundleA(params))\n val b = Flipped(RationalIO(new TLBundleB(params)))\n val c = RationalIO(new TLBundleC(params))\n val d = Flipped(RationalIO(new TLBundleD(params)))\n val e = RationalIO(new TLBundleE(params))\n}\n\nclass TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)\n{\n val a = CreditedIO(new TLBundleA(params))\n val b = Flipped(CreditedIO(new TLBundleB(params)))\n val c = CreditedIO(new TLBundleC(params))\n val d = Flipped(CreditedIO(new TLBundleD(params)))\n val e = CreditedIO(new TLBundleE(params))\n}\nFile Parameters.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.diplomacy\n\nimport chisel3._\nimport chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}\nimport freechips.rocketchip.util.ShiftQueue\n\n/** Options for describing the attributes of memory regions */\nobject RegionType {\n // Define the 'more relaxed than' ordering\n val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)\n sealed trait T extends Ordered[T] {\n def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)\n }\n\n case object CACHED extends T // an intermediate agent may have cached a copy of the region for you\n case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided\n case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible\n case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached\n case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects\n case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed\n case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively\n}\n\n// A non-empty half-open range; [start, end)\ncase class IdRange(start: Int, end: Int) extends Ordered[IdRange]\n{\n require (start >= 0, s\"Ids cannot be negative, but got: $start.\")\n require (start <= end, \"Id ranges cannot be negative.\")\n\n def compare(x: IdRange) = {\n val primary = (this.start - x.start).signum\n val secondary = (x.end - this.end).signum\n if (primary != 0) primary else secondary\n }\n\n def overlaps(x: IdRange) = start < x.end && x.start < end\n def contains(x: IdRange) = start <= x.start && x.end <= end\n\n def contains(x: Int) = start <= x && x < end\n def contains(x: UInt) =\n if (size == 0) {\n false.B\n } else if (size == 1) { // simple comparison\n x === start.U\n } else {\n // find index of largest different bit\n val largestDeltaBit = log2Floor(start ^ (end-1))\n val smallestCommonBit = largestDeltaBit + 1 // may not exist in x\n val uncommonMask = (1 << smallestCommonBit) - 1\n val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)\n // the prefix must match exactly (note: may shift ALL bits away)\n (x >> smallestCommonBit) === (start >> smallestCommonBit).U &&\n // firrtl constant prop range analysis can eliminate these two:\n (start & uncommonMask).U <= uncommonBits &&\n uncommonBits <= ((end-1) & uncommonMask).U\n }\n\n def shift(x: Int) = IdRange(start+x, end+x)\n def size = end - start\n def isEmpty = end == start\n\n def range = start until end\n}\n\nobject IdRange\n{\n def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {\n val ranges = s.sorted\n (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }\n }\n}\n\n// An potentially empty inclusive range of 2-powers [min, max] (in bytes)\ncase class TransferSizes(min: Int, max: Int)\n{\n def this(x: Int) = this(x, x)\n\n require (min <= max, s\"Min transfer $min > max transfer $max\")\n require (min >= 0 && max >= 0, s\"TransferSizes must be positive, got: ($min, $max)\")\n require (max == 0 || isPow2(max), s\"TransferSizes must be a power of 2, got: $max\")\n require (min == 0 || isPow2(min), s\"TransferSizes must be a power of 2, got: $min\")\n require (max == 0 || min != 0, s\"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)\")\n\n def none = min == 0\n def contains(x: Int) = isPow2(x) && min <= x && x <= max\n def containsLg(x: Int) = contains(1 << x)\n def containsLg(x: UInt) =\n if (none) false.B\n else if (min == max) { log2Ceil(min).U === x }\n else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }\n\n def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)\n\n def intersect(x: TransferSizes) =\n if (x.max < min || max < x.min) TransferSizes.none\n else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))\n\n // Not a union, because the result may contain sizes contained by neither term\n // NOT TO BE CONFUSED WITH COVERPOINTS\n def mincover(x: TransferSizes) = {\n if (none) {\n x\n } else if (x.none) {\n this\n } else {\n TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))\n }\n }\n\n override def toString() = \"TransferSizes[%d, %d]\".format(min, max)\n}\n\nobject TransferSizes {\n def apply(x: Int) = new TransferSizes(x)\n val none = new TransferSizes(0)\n\n def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)\n def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)\n\n implicit def asBool(x: TransferSizes) = !x.none\n}\n\n// AddressSets specify the address space managed by the manager\n// Base is the base address, and mask are the bits consumed by the manager\n// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff\n// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...\ncase class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]\n{\n // Forbid misaligned base address (and empty sets)\n require ((base & mask) == 0, s\"Mis-aligned AddressSets are forbidden, got: ${this.toString}\")\n require (base >= 0, s\"AddressSet negative base is ambiguous: $base\") // TL2 address widths are not fixed => negative is ambiguous\n // We do allow negative mask (=> ignore all high bits)\n\n def contains(x: BigInt) = ((x ^ base) & ~mask) == 0\n def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S\n\n // turn x into an address contained in this set\n def legalize(x: UInt): UInt = base.U | (mask.U & x)\n\n // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)\n def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0\n // contains iff bitwise: x.mask => mask && contains(x.base)\n def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0\n\n // The number of bytes to which the manager must be aligned\n def alignment = ((mask + 1) & ~mask)\n // Is this a contiguous memory range\n def contiguous = alignment == mask+1\n\n def finite = mask >= 0\n def max = { require (finite, \"Max cannot be calculated on infinite mask\"); base | mask }\n\n // Widen the match function to ignore all bits in imask\n def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)\n\n // Return an AddressSet that only contains the addresses both sets contain\n def intersect(x: AddressSet): Option[AddressSet] = {\n if (!overlaps(x)) {\n None\n } else {\n val r_mask = mask & x.mask\n val r_base = base | x.base\n Some(AddressSet(r_base, r_mask))\n }\n }\n\n def subtract(x: AddressSet): Seq[AddressSet] = {\n intersect(x) match {\n case None => Seq(this)\n case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>\n val nmask = (mask & (bit-1)) | remove.mask\n val nbase = (remove.base ^ bit) & ~nmask\n AddressSet(nbase, nmask)\n }\n }\n }\n\n // AddressSets have one natural Ordering (the containment order, if contiguous)\n def compare(x: AddressSet) = {\n val primary = (this.base - x.base).signum // smallest address first\n val secondary = (x.mask - this.mask).signum // largest mask first\n if (primary != 0) primary else secondary\n }\n\n // We always want to see things in hex\n override def toString() = {\n if (mask >= 0) {\n \"AddressSet(0x%x, 0x%x)\".format(base, mask)\n } else {\n \"AddressSet(0x%x, ~0x%x)\".format(base, ~mask)\n }\n }\n\n def toRanges = {\n require (finite, \"Ranges cannot be calculated on infinite mask\")\n val size = alignment\n val fragments = mask & ~(size-1)\n val bits = bitIndexes(fragments)\n (BigInt(0) until (BigInt(1) << bits.size)).map { i =>\n val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }\n AddressRange(off, size)\n }\n }\n}\n\nobject AddressSet\n{\n val everything = AddressSet(0, -1)\n def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {\n if (size == 0) tail.reverse else {\n val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)\n val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size\n val step =\n if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)\n maxSizeAlignment else maxBaseAlignment\n misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)\n }\n }\n\n def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {\n // Pair terms up by ignoring 'bit'\n seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>\n if (seq.size == 1) {\n seq.head // singleton -> unaffected\n } else {\n key.copy(mask = key.mask | bit) // pair - widen mask by bit\n }\n }.toList\n }\n\n def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {\n val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)\n AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted\n }\n\n def enumerateMask(mask: BigInt): Seq[BigInt] = {\n def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =\n if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)\n helper(0, Nil)\n }\n\n def enumerateBits(mask: BigInt): Seq[BigInt] = {\n def helper(x: BigInt): Seq[BigInt] = {\n if (x == 0) {\n Nil\n } else {\n val bit = x & (-x)\n bit +: helper(x & ~bit)\n }\n }\n helper(mask)\n }\n}\n\ncase class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)\n{\n require (depth >= 0, \"Buffer depth must be >= 0\")\n def isDefined = depth > 0\n def latency = if (isDefined && !flow) 1 else 0\n\n def apply[T <: Data](x: DecoupledIO[T]) =\n if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)\n else x\n\n def irrevocable[T <: Data](x: ReadyValidIO[T]) =\n if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)\n else x\n\n def sq[T <: Data](x: DecoupledIO[T]) =\n if (!isDefined) x else {\n val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))\n sq.io.enq <> x\n sq.io.deq\n }\n\n override def toString() = \"BufferParams:%d%s%s\".format(depth, if (flow) \"F\" else \"\", if (pipe) \"P\" else \"\")\n\n}\n\nobject BufferParams\n{\n implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)\n\n val default = BufferParams(2)\n val none = BufferParams(0)\n val flow = BufferParams(1, true, false)\n val pipe = BufferParams(1, false, true)\n}\n\ncase class TriStateValue(value: Boolean, set: Boolean)\n{\n def update(orig: Boolean) = if (set) value else orig\n}\n\nobject TriStateValue\n{\n implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)\n def unset = TriStateValue(false, false)\n}\n\ntrait DirectedBuffers[T] {\n def copyIn(x: BufferParams): T\n def copyOut(x: BufferParams): T\n def copyInOut(x: BufferParams): T\n}\n\ntrait IdMapEntry {\n def name: String\n def from: IdRange\n def to: IdRange\n def isCache: Boolean\n def requestFifo: Boolean\n def maxTransactionsInFlight: Option[Int]\n def pretty(fmt: String) =\n if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5\n fmt.format(to.start, to.end, from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n } else {\n fmt.format(from.start, from.end, s\"\"\"\"$name\"\"\"\", if (isCache) \" [CACHE]\" else \"\", if (requestFifo) \" [FIFO]\" else \"\")\n }\n}\n\nabstract class IdMap[T <: IdMapEntry] {\n protected val fmt: String\n val mapping: Seq[T]\n def pretty: String = mapping.map(_.pretty(fmt)).mkString(\",\\n\")\n}\nFile Edges.scala:\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nclass TLEdge(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdgeParameters(client, manager, params, sourceInfo)\n{\n def isAligned(address: UInt, lgSize: UInt): Bool = {\n if (maxLgSize == 0) true.B else {\n val mask = UIntToOH1(lgSize, maxLgSize)\n (address & mask) === 0.U\n }\n }\n\n def mask(address: UInt, lgSize: UInt): UInt =\n MaskGen(address, lgSize, manager.beatBytes)\n\n def staticHasData(bundle: TLChannel): Option[Boolean] = {\n bundle match {\n case _:TLBundleA => {\n // Do there exist A messages with Data?\n val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial\n // Do there exist A messages without Data?\n val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None\n }\n case _:TLBundleB => {\n // Do there exist B messages with Data?\n val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial\n // Do there exist B messages without Data?\n val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint\n // Statically optimize the case where hasData is a constant\n if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None\n }\n case _:TLBundleC => {\n // Do there eixst C messages with Data?\n val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe\n // Do there exist C messages without Data?\n val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe\n if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None\n }\n case _:TLBundleD => {\n // Do there eixst D messages with Data?\n val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB\n // Do there exist D messages without Data?\n val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT\n if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None\n }\n case _:TLBundleE => Some(false)\n }\n }\n\n def isRequest(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => true.B\n case b: TLBundleB => true.B\n case c: TLBundleC => c.opcode(2) && c.opcode(1)\n // opcode === TLMessages.Release ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(2) && !d.opcode(1)\n // opcode === TLMessages.Grant ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n }\n\n def isResponse(x: TLChannel): Bool = {\n x match {\n case a: TLBundleA => false.B\n case b: TLBundleB => false.B\n case c: TLBundleC => !c.opcode(2) || !c.opcode(1)\n // opcode =/= TLMessages.Release &&\n // opcode =/= TLMessages.ReleaseData\n case d: TLBundleD => true.B // Grant isResponse + isRequest\n case e: TLBundleE => true.B\n }\n }\n\n def hasData(x: TLChannel): Bool = {\n val opdata = x match {\n case a: TLBundleA => !a.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case b: TLBundleB => !b.opcode(2)\n // opcode === TLMessages.PutFullData ||\n // opcode === TLMessages.PutPartialData ||\n // opcode === TLMessages.ArithmeticData ||\n // opcode === TLMessages.LogicalData\n case c: TLBundleC => c.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.ProbeAckData ||\n // opcode === TLMessages.ReleaseData\n case d: TLBundleD => d.opcode(0)\n // opcode === TLMessages.AccessAckData ||\n // opcode === TLMessages.GrantData\n case e: TLBundleE => false.B\n }\n staticHasData(x).map(_.B).getOrElse(opdata)\n }\n\n def opcode(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.opcode\n case b: TLBundleB => b.opcode\n case c: TLBundleC => c.opcode\n case d: TLBundleD => d.opcode\n }\n }\n\n def param(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.param\n case b: TLBundleB => b.param\n case c: TLBundleC => c.param\n case d: TLBundleD => d.param\n }\n }\n\n def size(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.size\n case b: TLBundleB => b.size\n case c: TLBundleC => c.size\n case d: TLBundleD => d.size\n }\n }\n\n def data(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.data\n case b: TLBundleB => b.data\n case c: TLBundleC => c.data\n case d: TLBundleD => d.data\n }\n }\n\n def corrupt(x: TLDataChannel): Bool = {\n x match {\n case a: TLBundleA => a.corrupt\n case b: TLBundleB => b.corrupt\n case c: TLBundleC => c.corrupt\n case d: TLBundleD => d.corrupt\n }\n }\n\n def mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.mask\n case b: TLBundleB => b.mask\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def full_mask(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => mask(a.address, a.size)\n case b: TLBundleB => mask(b.address, b.size)\n case c: TLBundleC => mask(c.address, c.size)\n }\n }\n\n def address(x: TLAddrChannel): UInt = {\n x match {\n case a: TLBundleA => a.address\n case b: TLBundleB => b.address\n case c: TLBundleC => c.address\n }\n }\n\n def source(x: TLDataChannel): UInt = {\n x match {\n case a: TLBundleA => a.source\n case b: TLBundleB => b.source\n case c: TLBundleC => c.source\n case d: TLBundleD => d.source\n }\n }\n\n def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)\n def addr_lo(x: UInt): UInt =\n if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)\n\n def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))\n def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))\n\n def numBeats(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 1.U\n case bundle: TLDataChannel => {\n val hasData = this.hasData(bundle)\n val size = this.size(bundle)\n val cutoff = log2Ceil(manager.beatBytes)\n val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U\n val decode = UIntToOH(size, maxLgSize+1) >> cutoff\n Mux(hasData, decode | small.asUInt, 1.U)\n }\n }\n }\n\n def numBeats1(x: TLChannel): UInt = {\n x match {\n case _: TLBundleE => 0.U\n case bundle: TLDataChannel => {\n if (maxLgSize == 0) {\n 0.U\n } else {\n val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)\n Mux(hasData(bundle), decode, 0.U)\n }\n }\n }\n }\n\n def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val beats1 = numBeats1(bits)\n val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))\n val counter1 = counter - 1.U\n val first = counter === 0.U\n val last = counter === 1.U || beats1 === 0.U\n val done = last && fire\n val count = (beats1 & ~counter1)\n when (fire) {\n counter := Mux(first, beats1, counter1)\n }\n (first, last, done, count)\n }\n\n def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1\n def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)\n def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)\n\n def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2\n def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)\n def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)\n\n def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3\n def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)\n def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)\n\n def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3)\n }\n def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)\n def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)\n\n def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4)\n }\n def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)\n def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)\n\n def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {\n val r = firstlastHelper(bits, fire)\n (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))\n }\n def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)\n def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)\n\n // Does the request need T permissions to be executed?\n def needT(a: TLBundleA): Bool = {\n val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLPermissions.NtoB -> false.B,\n TLPermissions.NtoT -> true.B,\n TLPermissions.BtoT -> true.B))\n MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(\n TLMessages.PutFullData -> true.B,\n TLMessages.PutPartialData -> true.B,\n TLMessages.ArithmeticData -> true.B,\n TLMessages.LogicalData -> true.B,\n TLMessages.Get -> false.B,\n TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(\n TLHints.PREFETCH_READ -> false.B,\n TLHints.PREFETCH_WRITE -> true.B)),\n TLMessages.AcquireBlock -> acq_needT,\n TLMessages.AcquirePerm -> acq_needT))\n }\n\n // This is a very expensive circuit; use only if you really mean it!\n def inFlight(x: TLBundle): (UInt, UInt) = {\n val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))\n val bce = manager.anySupportAcquireB && client.anySupportProbe\n\n val (a_first, a_last, _) = firstlast(x.a)\n val (b_first, b_last, _) = firstlast(x.b)\n val (c_first, c_last, _) = firstlast(x.c)\n val (d_first, d_last, _) = firstlast(x.d)\n val (e_first, e_last, _) = firstlast(x.e)\n\n val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))\n val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))\n val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))\n val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))\n val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))\n\n val a_inc = x.a.fire && a_first && a_request\n val b_inc = x.b.fire && b_first && b_request\n val c_inc = x.c.fire && c_first && c_request\n val d_inc = x.d.fire && d_first && d_request\n val e_inc = x.e.fire && e_first && e_request\n val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))\n\n val a_dec = x.a.fire && a_last && a_response\n val b_dec = x.b.fire && b_last && b_response\n val c_dec = x.c.fire && c_last && c_response\n val d_dec = x.d.fire && d_last && d_response\n val e_dec = x.e.fire && e_last && e_response\n val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))\n\n val next_flight = flight + PopCount(inc) - PopCount(dec)\n flight := next_flight\n\n (flight, next_flight)\n }\n\n def prettySourceMapping(context: String): String = {\n s\"TL-Source mapping for $context:\\n${(new TLSourceIdMap(client)).pretty}\\n\"\n }\n}\n\nclass TLEdgeOut(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n // Transfers\n def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquireBlock\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.AcquirePerm\n a.param := growPermissions\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.Release\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {\n require (manager.anySupportAcquireB, s\"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsAcquireBFast(toAddress, lgSize)\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ReleaseData\n c.param := shrinkPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n (legal, c)\n }\n\n def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =\n Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAck\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(b.source, b.address, b.size, reportPermissions, data)\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.ProbeAckData\n c.param := reportPermissions\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =\n ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)\n\n def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)\n def GrantAck(toSink: UInt): TLBundleE = {\n val e = Wire(new TLBundleE(bundle))\n e.sink := toSink\n e\n }\n\n // Accesses\n def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n require (manager.anySupportGet, s\"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsGetFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Get\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutFull, s\"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutFullFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutFullData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =\n Put(fromSource, toAddress, lgSize, data, mask, false.B)\n\n def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {\n require (manager.anySupportPutPartial, s\"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsPutPartialFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.PutPartialData\n a.param := 0.U\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {\n require (manager.anySupportArithmetic, s\"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsArithmeticFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.ArithmeticData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (manager.anySupportLogical, s\"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsLogicalFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.LogicalData\n a.param := atomic\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := data\n a.corrupt := corrupt\n (legal, a)\n }\n\n def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {\n require (manager.anySupportHint, s\"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}\")\n val legal = manager.supportsHintFast(toAddress, lgSize)\n val a = Wire(new TLBundleA(bundle))\n a.opcode := TLMessages.Hint\n a.param := param\n a.size := lgSize\n a.source := fromSource\n a.address := toAddress\n a.user := DontCare\n a.echo := DontCare\n a.mask := mask(toAddress, lgSize)\n a.data := DontCare\n a.corrupt := false.B\n (legal, a)\n }\n\n def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n\n def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)\n def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)\n def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.AccessAckData\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := data\n c.corrupt := corrupt\n c\n }\n\n def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)\n def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {\n val c = Wire(new TLBundleC(bundle))\n c.opcode := TLMessages.HintAck\n c.param := 0.U\n c.size := lgSize\n c.source := fromSource\n c.address := toAddress\n c.user := DontCare\n c.echo := DontCare\n c.data := DontCare\n c.corrupt := false.B\n c\n }\n}\n\nclass TLEdgeIn(\n client: TLClientPortParameters,\n manager: TLManagerPortParameters,\n params: Parameters,\n sourceInfo: SourceInfo)\n extends TLEdge(client, manager, params, sourceInfo)\n{\n private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {\n val todo = x.filter(!_.isEmpty)\n val heads = todo.map(_.head)\n val tails = todo.map(_.tail)\n if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }\n }\n\n // Transfers\n def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {\n require (client.anySupportProbe, s\"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}\")\n val legal = client.supportsProbe(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Probe\n b.param := capPermissions\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.Grant\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)\n def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.GrantData\n d.param := capPermissions\n d.size := lgSize\n d.source := toSource\n d.sink := fromSink\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)\n def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.ReleaseAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n // Accesses\n def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {\n require (client.anySupportGet, s\"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsGet(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Get\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutFull, s\"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}\")\n val legal = client.supportsPutFull(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutFullData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =\n Put(fromAddress, toSource, lgSize, data, mask, false.B)\n\n def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {\n require (client.anySupportPutPartial, s\"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsPutPartial(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.PutPartialData\n b.param := 0.U\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportArithmetic, s\"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsArithmetic(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.ArithmeticData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {\n require (client.anySupportLogical, s\"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsLogical(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.LogicalData\n b.param := atomic\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := data\n b.corrupt := corrupt\n (legal, b)\n }\n\n def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {\n require (client.anySupportHint, s\"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}\")\n val legal = client.supportsHint(toSource, lgSize)\n val b = Wire(new TLBundleB(bundle))\n b.opcode := TLMessages.Hint\n b.param := param\n b.size := lgSize\n b.source := toSource\n b.address := fromAddress\n b.mask := mask(fromAddress, lgSize)\n b.data := DontCare\n b.corrupt := false.B\n (legal, b)\n }\n\n def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)\n def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)\n def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n\n def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)\n def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)\n def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.AccessAckData\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := data\n d.corrupt := corrupt\n d\n }\n\n def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)\n def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)\n def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)\n def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {\n val d = Wire(new TLBundleD(bundle))\n d.opcode := TLMessages.HintAck\n d.param := 0.U\n d.size := lgSize\n d.source := toSource\n d.sink := 0.U\n d.denied := denied\n d.user := DontCare\n d.echo := DontCare\n d.data := DontCare\n d.corrupt := false.B\n d\n }\n}\n"},"response":{"kind":"string","value":"module TLMonitor_42(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_14 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_20 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_26 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_32 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_38 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_44 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_56 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_62 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_68 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_74 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_80 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_86 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_92 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_98 = 1'h1;\t// @[Parameters.scala:56:32]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_d_bits_param = 2'h0;\t// @[Monitor.scala:36:7]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_first_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_first_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0;\t// @[Bundles.scala:265:74]\n wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [2050:0] _c_opcodes_set_T_1 = 2051'h0;\t// @[Monitor.scala:767:54]\n wire [2050:0] _c_sizes_set_T_1 = 2051'h0;\t// @[Monitor.scala:768:52]\n wire [10:0] _c_opcodes_set_T = 11'h0;\t// @[Monitor.scala:767:79]\n wire [10:0] _c_sizes_set_T = 11'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [255:0] _c_set_wo_ready_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [255:0] _c_set_T = 256'h1;\t// @[OneHot.scala:58:35]\n wire [975:0] c_opcodes_set = 976'h0;\t// @[Monitor.scala:740:34]\n wire [975:0] c_sizes_set = 976'h0;\t// @[Monitor.scala:741:34]\n wire [243:0] c_set = 244'h0;\t// @[Monitor.scala:738:34]\n wire [243:0] c_set_wo_ready = 244'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_14 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [7:0] _source_ok_uncommonBits_T_15 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] _source_ok_T = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_6 = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_12 = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_18 = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_24 = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_30 = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_36 = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_42 = io_in_a_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_1 = &_source_ok_T;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_3 = _source_ok_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_7 = _source_ok_T_6 == 3'h6;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_9 = _source_ok_T_7;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_9 & _source_ok_T_10;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_13 = _source_ok_T_12 == 3'h5;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_15 = _source_ok_T_13;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_16 = source_ok_uncommonBits_2 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_17 = _source_ok_T_15 & _source_ok_T_16;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_2 = _source_ok_T_17;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_19 = _source_ok_T_18 == 3'h4;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_21 = _source_ok_T_19;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_22 = source_ok_uncommonBits_3 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_3 = _source_ok_T_23;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_25 = _source_ok_T_24 == 3'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_27 = _source_ok_T_25;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_28 = source_ok_uncommonBits_4 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_29 = _source_ok_T_27 & _source_ok_T_28;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_4 = _source_ok_T_29;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_31 = _source_ok_T_30 == 3'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_33 = _source_ok_T_31;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_34 = source_ok_uncommonBits_5 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_35 = _source_ok_T_33 & _source_ok_T_34;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_5 = _source_ok_T_35;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_37 = _source_ok_T_36 == 3'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_39 = _source_ok_T_37;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_40 = source_ok_uncommonBits_6 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_41 = _source_ok_T_39 & _source_ok_T_40;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_6 = _source_ok_T_41;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_43 = _source_ok_T_42 == 3'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_45 = _source_ok_T_43;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_46 = source_ok_uncommonBits_7 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_47 = _source_ok_T_45 & _source_ok_T_46;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_7 = _source_ok_T_47;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_53 | _source_ok_WIRE_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [4:0] uncommonBits = _uncommonBits_T[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_1 = _uncommonBits_T_1[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_2 = _uncommonBits_T_2[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_3 = _uncommonBits_T_3[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_12 = _uncommonBits_T_12[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_13 = _uncommonBits_T_13[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_24 = _uncommonBits_T_24[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_25 = _uncommonBits_T_25[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_26 = _uncommonBits_T_26[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_27 = _uncommonBits_T_27[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_44 = _uncommonBits_T_44[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_45 = _uncommonBits_T_45[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_48 = _uncommonBits_T_48[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_49 = _uncommonBits_T_49[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_56 = _uncommonBits_T_56[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_57 = _uncommonBits_T_57[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_66 = _uncommonBits_T_66[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_67 = _uncommonBits_T_67[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_68 = _uncommonBits_T_68[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_69 = _uncommonBits_T_69[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_70 = _uncommonBits_T_70[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_71 = _uncommonBits_T_71[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire [2:0] _source_ok_T_54 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_60 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_66 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_72 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_78 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_84 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_90 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire [2:0] _source_ok_T_96 = io_in_d_bits_source_0[7:5];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_55 = &_source_ok_T_54;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_57 = _source_ok_T_55;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_58 = source_ok_uncommonBits_8 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_59 = _source_ok_T_57 & _source_ok_T_58;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_59;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_61 = _source_ok_T_60 == 3'h6;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_63 = _source_ok_T_61;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_64 = source_ok_uncommonBits_9 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_65 = _source_ok_T_63 & _source_ok_T_64;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_1 = _source_ok_T_65;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_67 = _source_ok_T_66 == 3'h5;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_69 = _source_ok_T_67;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_70 = source_ok_uncommonBits_10 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_2 = _source_ok_T_71;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_73 = _source_ok_T_72 == 3'h4;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_75 = _source_ok_T_73;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_76 = source_ok_uncommonBits_11 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_77 = _source_ok_T_75 & _source_ok_T_76;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_3 = _source_ok_T_77;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_79 = _source_ok_T_78 == 3'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_81 = _source_ok_T_79;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_82 = source_ok_uncommonBits_12 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_83 = _source_ok_T_81 & _source_ok_T_82;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_4 = _source_ok_T_83;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_85 = _source_ok_T_84 == 3'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_87 = _source_ok_T_85;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_88 = source_ok_uncommonBits_13 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_89 = _source_ok_T_87 & _source_ok_T_88;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_5 = _source_ok_T_89;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_91 = _source_ok_T_90 == 3'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_93 = _source_ok_T_91;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_94 = source_ok_uncommonBits_14 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_6 = _source_ok_T_95;\t// @[Parameters.scala:1138:31]\n wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_97 = _source_ok_T_96 == 3'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_99 = _source_ok_T_97;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_100 = source_ok_uncommonBits_15 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_101 = _source_ok_T_99 & _source_ok_T_100;\t// @[Parameters.scala:54:67, :56:48, :57:20]\n wire _source_ok_WIRE_1_7 = _source_ok_T_101;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_102 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_4;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_5;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_6;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_107 | _source_ok_WIRE_1_7;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1162 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1162;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1162;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [7:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _T_1235 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_1235;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_1235;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_1235;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [7:0] source_1;\t// @[Monitor.scala:541:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [243:0] inflight;\t// @[Monitor.scala:614:27]\n reg [975:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [975:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [243:0] a_set;\t// @[Monitor.scala:626:34]\n wire [243:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [975:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [975:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [10:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [10:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [10:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [10:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [10:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [10:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [10:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [10:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [975:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [975:0] _a_opcode_lookup_T_6 = {972'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [975:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[975:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [975:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [975:0] _a_size_lookup_T_6 = {972'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [975:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[975:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [255:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[243:0] : 244'h0;\t// @[OneHot.scala:58:35]\n wire _T_1088 = _T_1162 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1088 ? _a_set_T[243:0] : 244'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1088 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1088 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [10:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [10:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1088 ? _a_opcodes_set_T_1[975:0] : 976'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_1088 ? _a_sizes_set_T_1[975:0] : 976'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [243:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [243:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [975:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [975:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1134 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [255:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1134 & ~d_release_ack ? _d_clr_wo_ready_T[243:0] : 244'h0;\t// @[OneHot.scala:58:35]\n wire _T_1103 = _T_1235 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1103 ? _d_clr_T[243:0] : 244'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1103 ? _d_opcodes_clr_T_5[975:0] : 976'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1103 ? _d_sizes_clr_T_5[975:0] : 976'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [243:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [243:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [243:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [975:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [975:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [975:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [975:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [975:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [975:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [243:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [243:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [975:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [975:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [975:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [975:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [975:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [975:0] _c_opcode_lookup_T_6 = {972'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [975:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[975:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [975:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [975:0] _c_size_lookup_T_6 = {972'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [975:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[975:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [243:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [243:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [975:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [975:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1206 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1206 & d_release_ack_1 ? _d_clr_wo_ready_T_1[243:0] : 244'h0;\t// @[OneHot.scala:58:35]\n wire _T_1188 = _T_1235 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1188 ? _d_clr_T_1[243:0] : 244'h0;\t// @[OneHot.scala:58:35]\n wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1188 ? _d_opcodes_clr_T_11[975:0] : 976'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1188 ? _d_sizes_clr_T_11[975:0] : 976'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [243:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [243:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [975:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [975:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [975:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [975:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":20,"numItemsPerPage":100,"numTotalItems":35529,"offset":2000,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc1MjQyNzgzNiwic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vY2hpc2VsLXZlcmlsb2ctcGFpcnMiLCJleHAiOjE3NTI0MzE0MzYsImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.9VIv5OWtebs1jTE1TcrSRMXCdu1vI1mkkwggSh0gFm_G-XppmzBV6SGxBLNbG5mjRtKIRxnvGWTxmIaZPSxYDQ","displayUrls":true},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
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Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_47( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_303 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_146( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_402 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_335( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_79 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File ToAXI4.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField}
import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp}
import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1}
import freechips.rocketchip.util.DataToAugmentedData
class AXI4TLStateBundle(val sourceBits: Int) extends Bundle {
val size = UInt(4.W)
val source = UInt((sourceBits max 1).W)
}
case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state")
case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLtoAXI4IdMap serves as a record for the translation performed between id spaces.
*
* Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy.
* Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module.
*/
class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry]
{
val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType)
private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size }
private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init
val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) =>
AXI4MasterParameters(
name = tl.name,
id = IdRange(start, start+size),
aligned = true,
maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1),
nodePath = tl.nodePath)
}
private val axi4IdEnd = axi4Masters.map(_.id.end).max
private val axiDigits = String.valueOf(axi4IdEnd-1).length()
private val tlDigits = String.valueOf(tlPort.endSourceId-1).length()
protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s"
val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) =>
TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo)
}
}
case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = axi4Id
val maxTransactionsInFlight = Some(tlId.size)
}
case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)(
dFn = { p =>
AXI4MasterPortParameters(
masters = (new TLtoAXI4IdMap(p)).axi4Masters,
requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]),
echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields,
responseKeys = p.responseKeys)
},
uFn = { p => TLSlavePortParameters.v1(
managers = p.slaves.map { case s =>
TLSlaveParameters.v1(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,
supportsGet = s.supportsRead,
supportsPutFull = s.supportsWrite,
supportsPutPartial = s.supportsWrite,
fifoId = Some(0),
mayDenyPut = true,
mayDenyGet = true)},
beatBytes = p.beatBytes,
minLatency = p.minLatency,
responseFields = p.responseFields,
requestKeys = AMBAProt +: p.requestKeys)
})
// wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys
class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4")
val node = TLToAXI4Node(wcorrupt)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val slaves = edgeOut.slave.slaves
// All pairs of slaves must promise that they will never interleave data
require (slaves(0).interleavedId.isDefined)
slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) }
// Construct the source=>ID mapping table
val map = new TLtoAXI4IdMap(edgeIn.client)
val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B))
val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id)))
val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B))
var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] }
map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) =>
for (i <- 0 until tlId.size) {
val id = axi4Id.start + (if (fifo) 0 else i)
sourceStall(tlId.start + i) := idStall(id)
sourceTable(tlId.start + i) := id.U
}
if (fifo) { idCount(axi4Id.start) = Some(tlId.size) }
}
adapterName.foreach { n =>
println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n")
ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""")
}
// We need to keep the following state from A => D: (size, source)
// All of those fields could potentially require 0 bits (argh. Chisel.)
// We will pack all of that extra information into the echo bits.
require (log2Ceil(edgeIn.maxLgSize+1) <= 4)
val a_address = edgeIn.address(in.a.bits)
val a_source = in.a.bits.source
val a_size = edgeIn.size(in.a.bits)
val a_isPut = edgeIn.hasData(in.a.bits)
val (a_first, a_last, _) = edgeIn.firstlast(in.a)
val r_state = out.r.bits.echo(AXI4TLState)
val r_source = r_state.source
val r_size = r_state.size
val b_state = out.b.bits.echo(AXI4TLState)
val b_source = b_state.source
val b_size = b_state.size
// We need these Queues because AXI4 queues are irrevocable
val depth = if (combinational) 1 else 2
val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params)))
val out_w = Wire(chiselTypeOf(out.w))
out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational)
val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational)
// Fan out the ARW channel to AR and AW
out.ar.bits := queue_arw.bits
out.aw.bits := queue_arw.bits
out.ar.valid := queue_arw.valid && !queue_arw.bits.wen
out.aw.valid := queue_arw.valid && queue_arw.bits.wen
queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready)
val beatBytes = edgeIn.manager.beatBytes
val maxSize = log2Ceil(beatBytes).U
val doneAW = RegInit(false.B)
when (in.a.fire) { doneAW := !a_last }
val arw = out_arw.bits
arw.wen := a_isPut
arw.id := sourceTable(a_source)
arw.addr := a_address
arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes)
arw.size := Mux(a_size >= maxSize, maxSize, a_size)
arw.burst := AXI4Parameters.BURST_INCR
arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee)
arw.cache := 0.U // do not allow AXI to modify our transactions
arw.prot := AXI4Parameters.PROT_PRIVILEGED
arw.qos := 0.U // no QoS
Connectable.waiveUnmatched(arw.user, in.a.bits.user) match {
case (lhs, rhs) => lhs :<= rhs
}
Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = arw.echo(AXI4TLState)
a_extra.source := a_source
a_extra.size := a_size
in.a.bits.user.lift(AMBAProt).foreach { x =>
val prot = Wire(Vec(3, Bool()))
val cache = Wire(Vec(4, Bool()))
prot(0) := x.privileged
prot(1) := !x.secure
prot(2) := x.fetch
cache(0) := x.bufferable
cache(1) := x.modifiable
cache(2) := x.readalloc
cache(3) := x.writealloc
arw.prot := Cat(prot.reverse)
arw.cache := Cat(cache.reverse)
}
val stall = sourceStall(in.a.bits.source) && a_first
in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready)
out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B)
out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready)
out_w.bits.data := in.a.bits.data
out_w.bits.strb := in.a.bits.mask
out_w.bits.last := a_last
out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt }
// R and B => D arbitration
val r_holds_d = RegInit(false.B)
when (out.r.fire) { r_holds_d := !out.r.bits.last }
// Give R higher priority than B, unless B has been delayed for 8 cycles
val b_delay = Reg(UInt(3.W))
when (out.b.valid && !out.b.ready) {
b_delay := b_delay + 1.U
} .otherwise {
b_delay := 0.U
}
val r_wins = (out.r.valid && b_delay =/= 7.U) || r_holds_d
out.r.ready := in.d.ready && r_wins
out.b.ready := in.d.ready && !r_wins
in.d.valid := Mux(r_wins, out.r.valid, out.b.valid)
// If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied
// request. We must pulse extend this value as AXI is allowed to change the
// value of RRESP on every beat, and ChipLink may not.
val r_first = RegInit(true.B)
when (out.r.fire) { r_first := out.r.bits.last }
val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first
val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt || r_denied)
val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied)
Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
in.d.bits := Mux(r_wins, r_d, b_d)
in.d.bits.data := out.r.bits.data // avoid a costly Mux
// We need to track if any reads or writes are inflight for a given ID.
// If the opposite type arrives, we must stall until it completes.
val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools
val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools
val d_last = Mux(r_wins, out.r.bits.last, true.B)
// If FIFO was requested, ensure that R+W ordering is preserved
(a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) =>
// AXI does not guarantee read vs. write ordering. In particular, if we
// are in the middle of receiving a read burst and then issue a write,
// the write might affect the read burst. This violates FIFO behaviour.
// To solve this, we must wait until the last beat of a burst, but this
// means that a TileLink master which performs early source reuse can
// have one more transaction inflight than we promised AXI; stall it too.
val maxCount = n.getOrElse(1)
val count = RegInit(0.U(log2Ceil(maxCount + 1).W))
val write = Reg(Bool())
val idle = count === 0.U
val inc = as && out_arw.fire
val dec = ds && d_last && in.d.fire
count := count + inc.asUInt - dec.asUInt
assert (!dec || count =/= 0.U) // underflow
assert (!inc || count =/= maxCount.U) // overflow
when (inc) { write := arw.wen }
// If only one transaction can be inflight, it can't mismatch
val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B }
s := (!idle && mismatch) || (count === maxCount.U)
}
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
}
object TLToAXI4
{
def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) =
{
val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt))
tl2axi4.node
}
def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = {
if ( a.supports.probe && !b.supports.probe) return false
if (!a.supports.probe && b.supports.probe) return true
if ( a.requestFifo && !b.requestFifo ) return false
if (!a.requestFifo && b.requestFifo ) return true
return false
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLToAXI4_3( // @[ToAXI4.scala:103:9]
input clock, // @[ToAXI4.scala:103:9]
input reset, // @[ToAXI4.scala:103:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
wire [7:0] out_arw_bits_id; // @[ToAXI4.scala:153:25]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[ToAXI4.scala:103:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[ToAXI4.scala:103:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[ToAXI4.scala:103:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[ToAXI4.scala:103:9]
wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[ToAXI4.scala:103:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[ToAXI4.scala:103:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[ToAXI4.scala:103:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[ToAXI4.scala:103:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[ToAXI4.scala:103:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[ToAXI4.scala:103:9]
wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[ToAXI4.scala:103:9]
wire auto_out_w_ready_0 = auto_out_w_ready; // @[ToAXI4.scala:103:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[ToAXI4.scala:103:9]
wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_b_bits_echo_tl_state_size_0 = auto_out_b_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_b_bits_echo_tl_state_source_0 = auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9]
wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[ToAXI4.scala:103:9]
wire auto_out_r_valid_0 = auto_out_r_valid; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[ToAXI4.scala:103:9]
wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[ToAXI4.scala:103:9]
wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_r_bits_echo_tl_state_size_0 = auto_out_r_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_r_bits_echo_tl_state_source_0 = auto_out_r_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9]
wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[ToAXI4.scala:103:9]
wire [255:0][7:0] _GEN = '{8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'h0, 8'hF3, 8'hF2, 8'hF1, 8'hF0, 8'hEF, 8'hEE, 8'hED, 8'hEC, 8'hEB, 8'hEA, 8'hE9, 8'hE8, 8'hE7, 8'hE6, 8'hE5, 8'hE4, 8'hE3, 8'hE2, 8'hE1, 8'hE0, 8'hDF, 8'hDE, 8'hDD, 8'hDC, 8'hDB, 8'hDA, 8'hD9, 8'hD8, 8'hD7, 8'hD6, 8'hD5, 8'hD4, 8'hD3, 8'hD2, 8'hD1, 8'hD0, 8'hCF, 8'hCE, 8'hCD, 8'hCC, 8'hCB, 8'hCA, 8'hC9, 8'hC8, 8'hC7, 8'hC6, 8'hC5, 8'hC4, 8'hC3, 8'hC2, 8'hC1, 8'hC0, 8'hBF, 8'hBE, 8'hBD, 8'hBC, 8'hBB, 8'hBA, 8'hB9, 8'hB8, 8'hB7, 8'hB6, 8'hB5, 8'hB4, 8'hB3, 8'hB2, 8'hB1, 8'hB0, 8'hAF, 8'hAE, 8'hAD, 8'hAC, 8'hAB, 8'hAA, 8'hA9, 8'hA8, 8'hA7, 8'hA6, 8'hA5, 8'hA4, 8'hA3, 8'hA2, 8'hA1, 8'hA0, 8'h9F, 8'h9E, 8'h9D, 8'h9C, 8'h9B, 8'h9A, 8'h99, 8'h98, 8'h97, 8'h96, 8'h95, 8'h94, 8'h93, 8'h92, 8'h91, 8'h90, 8'h8F, 8'h8E, 8'h8D, 8'h8C, 8'h8B, 8'h8A, 8'h89, 8'h88, 8'h87, 8'h86, 8'h85, 8'h84, 8'h83, 8'h82, 8'h81, 8'h80, 8'h7F, 8'h7E, 8'h7D, 8'h7C, 8'h7B, 8'h7A, 8'h79, 8'h78, 8'h77, 8'h76, 8'h75, 8'h74, 8'h73, 8'h72, 8'h71, 8'h70, 8'h6F, 8'h6E, 8'h6D, 8'h6C, 8'h6B, 8'h6A, 8'h69, 8'h68, 8'h67, 8'h66, 8'h65, 8'h64, 8'h63, 8'h62, 8'h61, 8'h60, 8'h5F, 8'h5E, 8'h5D, 8'h5C, 8'h5B, 8'h5A, 8'h59, 8'h58, 8'h57, 8'h56, 8'h55, 8'h54, 8'h53, 8'h52, 8'h51, 8'h50, 8'h4F, 8'h4E, 8'h4D, 8'h4C, 8'h4B, 8'h4A, 8'h49, 8'h48, 8'h47, 8'h46, 8'h45, 8'h44, 8'h43, 8'h42, 8'h41, 8'h40, 8'h3F, 8'h3E, 8'h3D, 8'h3C, 8'h3B, 8'h3A, 8'h39, 8'h38, 8'h37, 8'h36, 8'h35, 8'h34, 8'h33, 8'h32, 8'h31, 8'h30, 8'h2F, 8'h2E, 8'h2D, 8'h2C, 8'h2B, 8'h2A, 8'h29, 8'h28, 8'h27, 8'h26, 8'h25, 8'h24, 8'h23, 8'h22, 8'h21, 8'h20, 8'h1F, 8'h1E, 8'h1D, 8'h1C, 8'h1B, 8'h1A, 8'h19, 8'h18, 8'h17, 8'h16, 8'h15, 8'h14, 8'h13, 8'h12, 8'h11, 8'h10, 8'hF, 8'hE, 8'hD, 8'hC, 8'hB, 8'hA, 8'h9, 8'h8, 8'h7, 8'h6, 8'h5, 8'h4, 8'h3, 8'h2, 8'h1, 8'h0};
wire [1:0] auto_in_d_bits_param = 2'h0; // @[ToAXI4.scala:103:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] r_d_param = 2'h0; // @[Edges.scala:810:17]
wire [1:0] b_d_param = 2'h0; // @[Edges.scala:792:17]
wire [1:0] _nodeIn_d_bits_T_param = 2'h0; // @[ToAXI4.scala:255:23]
wire auto_in_d_bits_sink = 1'h0; // @[ToAXI4.scala:103:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire _sourceStall_WIRE_0 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_1 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_2 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_3 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_4 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_5 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_6 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_7 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_8 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_9 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_10 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_11 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_12 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_13 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_14 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_15 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_16 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_17 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_18 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_19 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_20 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_21 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_22 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_23 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_24 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_25 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_26 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_27 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_28 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_29 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_30 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_31 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_32 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_33 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_34 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_35 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_36 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_37 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_38 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_39 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_40 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_41 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_42 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_43 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_44 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_45 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_46 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_47 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_48 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_49 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_50 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_51 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_52 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_53 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_54 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_55 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_56 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_57 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_58 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_59 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_60 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_61 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_62 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_63 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_64 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_65 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_66 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_67 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_68 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_69 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_70 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_71 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_72 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_73 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_74 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_75 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_76 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_77 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_78 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_79 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_80 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_81 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_82 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_83 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_84 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_85 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_86 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_87 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_88 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_89 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_90 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_91 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_92 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_93 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_94 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_95 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_96 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_97 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_98 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_99 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_100 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_101 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_102 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_103 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_104 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_105 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_106 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_107 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_108 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_109 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_110 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_111 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_112 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_113 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_114 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_115 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_116 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_117 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_118 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_119 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_120 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_121 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_122 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_123 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_124 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_125 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_126 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_127 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_128 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_129 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_130 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_131 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_132 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_133 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_134 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_135 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_136 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_137 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_138 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_139 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_140 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_141 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_142 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_143 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_144 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_145 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_146 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_147 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_148 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_149 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_150 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_151 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_152 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_153 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_154 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_155 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_156 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_157 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_158 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_159 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_160 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_161 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_162 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_163 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_164 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_165 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_166 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_167 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_168 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_169 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_170 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_171 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_172 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_173 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_174 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_175 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_176 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_177 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_178 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_179 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_180 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_181 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_182 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_183 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_184 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_185 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_186 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_187 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_188 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_189 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_190 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_191 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_192 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_193 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_194 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_195 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_196 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_197 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_198 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_199 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_200 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_201 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_202 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_203 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_204 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_205 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_206 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_207 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_208 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_209 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_210 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_211 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_212 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_213 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_214 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_215 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_216 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_217 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_218 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_219 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_220 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_221 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_222 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_223 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_224 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_225 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_226 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_227 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_228 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_229 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_230 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_231 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_232 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_233 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_234 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_235 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_236 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_237 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_238 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_239 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_240 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_241 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_242 = 1'h0; // @[ToAXI4.scala:113:76]
wire _sourceStall_WIRE_243 = 1'h0; // @[ToAXI4.scala:113:76]
wire _idStall_WIRE_0 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_1 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_2 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_3 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_4 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_5 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_6 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_7 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_8 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_9 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_10 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_11 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_12 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_13 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_14 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_15 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_16 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_17 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_18 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_19 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_20 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_21 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_22 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_23 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_24 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_25 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_26 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_27 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_28 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_29 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_30 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_31 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_32 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_33 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_34 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_35 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_36 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_37 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_38 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_39 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_40 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_41 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_42 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_43 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_44 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_45 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_46 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_47 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_48 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_49 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_50 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_51 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_52 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_53 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_54 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_55 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_56 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_57 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_58 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_59 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_60 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_61 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_62 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_63 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_64 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_65 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_66 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_67 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_68 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_69 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_70 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_71 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_72 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_73 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_74 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_75 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_76 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_77 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_78 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_79 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_80 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_81 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_82 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_83 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_84 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_85 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_86 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_87 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_88 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_89 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_90 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_91 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_92 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_93 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_94 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_95 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_96 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_97 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_98 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_99 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_100 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_101 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_102 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_103 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_104 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_105 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_106 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_107 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_108 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_109 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_110 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_111 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_112 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_113 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_114 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_115 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_116 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_117 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_118 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_119 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_120 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_121 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_122 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_123 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_124 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_125 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_126 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_127 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_128 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_129 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_130 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_131 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_132 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_133 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_134 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_135 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_136 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_137 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_138 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_139 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_140 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_141 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_142 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_143 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_144 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_145 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_146 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_147 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_148 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_149 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_150 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_151 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_152 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_153 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_154 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_155 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_156 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_157 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_158 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_159 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_160 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_161 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_162 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_163 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_164 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_165 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_166 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_167 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_168 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_169 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_170 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_171 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_172 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_173 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_174 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_175 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_176 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_177 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_178 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_179 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_180 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_181 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_182 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_183 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_184 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_185 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_186 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_187 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_188 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_189 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_190 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_191 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_192 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_193 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_194 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_195 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_196 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_197 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_198 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_199 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_200 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_201 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_202 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_203 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_204 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_205 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_206 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_207 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_208 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_209 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_210 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_211 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_212 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_213 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_214 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_215 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_216 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_217 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_218 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_219 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_220 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_221 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_222 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_223 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_224 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_225 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_226 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_227 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_228 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_229 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_230 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_231 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_232 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_233 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_234 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_235 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_236 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_237 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_238 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_239 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_240 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_241 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_242 = 1'h0; // @[ToAXI4.scala:115:67]
wire _idStall_WIRE_243 = 1'h0; // @[ToAXI4.scala:115:67]
wire out_arw_bits_lock = 1'h0; // @[ToAXI4.scala:153:25]
wire r_d_sink = 1'h0; // @[Edges.scala:810:17]
wire b_d_sink = 1'h0; // @[Edges.scala:792:17]
wire b_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire _nodeIn_d_bits_T_sink = 1'h0; // @[ToAXI4.scala:255:23]
wire _idStall_0_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_1_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_2_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_3_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_4_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_5_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_6_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_7_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_8_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_9_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_10_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_11_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_12_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_13_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_14_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_15_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_16_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_17_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_18_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_19_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_20_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_21_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_22_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_23_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_24_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_25_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_26_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_27_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_28_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_29_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_30_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_31_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_32_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_33_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_34_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_35_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_36_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_37_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_38_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_39_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_40_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_41_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_42_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_43_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_44_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_45_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_46_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_47_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_48_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_49_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_50_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_51_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_52_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_53_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_54_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_55_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_56_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_57_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_58_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_59_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_60_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_61_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_62_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_63_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_64_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_65_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_66_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_67_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_68_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_69_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_70_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_71_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_72_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_73_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_74_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_75_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_76_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_77_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_78_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_79_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_80_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_81_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_82_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_83_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_84_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_85_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_86_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_87_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_88_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_89_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_90_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_91_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_92_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_93_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_94_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_95_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_96_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_97_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_98_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_99_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_100_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_101_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_102_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_103_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_104_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_105_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_106_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_107_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_108_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_109_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_110_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_111_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_112_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_113_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_114_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_115_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_116_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_117_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_118_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_119_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_120_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_121_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_122_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_123_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_124_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_125_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_126_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_127_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_128_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_129_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_130_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_131_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_132_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_133_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_134_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_135_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_136_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_137_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_138_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_139_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_140_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_141_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_142_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_143_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_144_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_145_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_146_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_147_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_148_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_149_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_150_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_151_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_152_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_153_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_154_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_155_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_156_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_157_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_158_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_159_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_160_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_161_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_162_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_163_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_164_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_165_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_166_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_167_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_168_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_169_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_170_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_171_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_172_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_173_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_174_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_175_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_176_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_177_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_178_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_179_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_180_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_181_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_182_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_183_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_184_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_185_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_186_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_187_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_188_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_189_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_190_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_191_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_192_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_193_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_194_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_195_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_196_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_197_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_198_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_199_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_200_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_201_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_202_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_203_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_204_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_205_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_206_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_207_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_208_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_209_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_210_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_211_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_212_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_213_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_214_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_215_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_216_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_217_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_218_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_219_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_220_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_221_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_222_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_223_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_224_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_225_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_226_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_227_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_228_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_229_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_230_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_231_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_232_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_233_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_234_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_235_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_236_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_237_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_238_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_239_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_240_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_241_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_242_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire _idStall_243_T_1 = 1'h0; // @[ToAXI4.scala:286:21]
wire [63:0] r_d_data = 64'h0; // @[Edges.scala:810:17]
wire [63:0] b_d_data = 64'h0; // @[Edges.scala:792:17]
wire [63:0] _nodeIn_d_bits_T_data = 64'h0; // @[ToAXI4.scala:255:23]
wire [2:0] b_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [2:0] out_arw_bits_prot = 3'h1; // @[ToAXI4.scala:153:25]
wire [2:0] r_d_opcode = 3'h1; // @[Edges.scala:810:17]
wire [3:0] out_arw_bits_cache = 4'h0; // @[ToAXI4.scala:153:25]
wire [3:0] out_arw_bits_qos = 4'h0; // @[ToAXI4.scala:153:25]
wire [1:0] out_arw_bits_burst = 2'h1; // @[ToAXI4.scala:153:25]
wire [7:0] sourceTable_243 = 8'hF3; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_242 = 8'hF2; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_241 = 8'hF1; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_240 = 8'hF0; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_239 = 8'hEF; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_238 = 8'hEE; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_237 = 8'hED; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_236 = 8'hEC; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_235 = 8'hEB; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_234 = 8'hEA; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_233 = 8'hE9; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_232 = 8'hE8; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_231 = 8'hE7; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_230 = 8'hE6; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_229 = 8'hE5; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_228 = 8'hE4; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_227 = 8'hE3; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_226 = 8'hE2; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_225 = 8'hE1; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_224 = 8'hE0; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_223 = 8'hDF; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_222 = 8'hDE; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_221 = 8'hDD; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_220 = 8'hDC; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_219 = 8'hDB; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_218 = 8'hDA; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_217 = 8'hD9; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_216 = 8'hD8; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_215 = 8'hD7; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_214 = 8'hD6; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_213 = 8'hD5; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_212 = 8'hD4; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_211 = 8'hD3; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_210 = 8'hD2; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_209 = 8'hD1; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_208 = 8'hD0; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_207 = 8'hCF; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_206 = 8'hCE; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_205 = 8'hCD; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_204 = 8'hCC; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_203 = 8'hCB; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_202 = 8'hCA; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_201 = 8'hC9; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_200 = 8'hC8; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_199 = 8'hC7; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_198 = 8'hC6; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_197 = 8'hC5; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_196 = 8'hC4; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_195 = 8'hC3; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_194 = 8'hC2; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_193 = 8'hC1; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_192 = 8'hC0; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_191 = 8'hBF; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_190 = 8'hBE; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_189 = 8'hBD; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_188 = 8'hBC; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_187 = 8'hBB; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_186 = 8'hBA; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_185 = 8'hB9; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_184 = 8'hB8; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_183 = 8'hB7; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_182 = 8'hB6; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_181 = 8'hB5; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_180 = 8'hB4; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_179 = 8'hB3; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_178 = 8'hB2; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_177 = 8'hB1; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_176 = 8'hB0; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_175 = 8'hAF; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_174 = 8'hAE; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_173 = 8'hAD; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_172 = 8'hAC; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_171 = 8'hAB; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_170 = 8'hAA; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_169 = 8'hA9; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_168 = 8'hA8; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_167 = 8'hA7; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_166 = 8'hA6; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_165 = 8'hA5; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_164 = 8'hA4; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_163 = 8'hA3; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_162 = 8'hA2; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_161 = 8'hA1; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_160 = 8'hA0; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_159 = 8'h9F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_158 = 8'h9E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_157 = 8'h9D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_156 = 8'h9C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_155 = 8'h9B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_154 = 8'h9A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_153 = 8'h99; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_152 = 8'h98; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_151 = 8'h97; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_150 = 8'h96; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_149 = 8'h95; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_148 = 8'h94; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_147 = 8'h93; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_146 = 8'h92; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_145 = 8'h91; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_144 = 8'h90; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_143 = 8'h8F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_142 = 8'h8E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_141 = 8'h8D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_140 = 8'h8C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_139 = 8'h8B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_138 = 8'h8A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_137 = 8'h89; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_136 = 8'h88; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_135 = 8'h87; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_134 = 8'h86; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_133 = 8'h85; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_132 = 8'h84; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_131 = 8'h83; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_130 = 8'h82; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_129 = 8'h81; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_128 = 8'h80; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_127 = 8'h7F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_126 = 8'h7E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_125 = 8'h7D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_124 = 8'h7C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_123 = 8'h7B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_122 = 8'h7A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_121 = 8'h79; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_120 = 8'h78; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_119 = 8'h77; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_118 = 8'h76; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_117 = 8'h75; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_116 = 8'h74; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_115 = 8'h73; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_114 = 8'h72; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_113 = 8'h71; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_112 = 8'h70; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_111 = 8'h6F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_110 = 8'h6E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_109 = 8'h6D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_108 = 8'h6C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_107 = 8'h6B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_106 = 8'h6A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_105 = 8'h69; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_104 = 8'h68; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_103 = 8'h67; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_102 = 8'h66; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_101 = 8'h65; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_100 = 8'h64; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_99 = 8'h63; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_98 = 8'h62; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_97 = 8'h61; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_96 = 8'h60; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_95 = 8'h5F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_94 = 8'h5E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_93 = 8'h5D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_92 = 8'h5C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_91 = 8'h5B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_90 = 8'h5A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_89 = 8'h59; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_88 = 8'h58; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_87 = 8'h57; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_86 = 8'h56; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_85 = 8'h55; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_84 = 8'h54; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_83 = 8'h53; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_82 = 8'h52; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_81 = 8'h51; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_80 = 8'h50; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_79 = 8'h4F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_78 = 8'h4E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_77 = 8'h4D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_76 = 8'h4C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_75 = 8'h4B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_74 = 8'h4A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_73 = 8'h49; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_72 = 8'h48; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_71 = 8'h47; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_70 = 8'h46; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_69 = 8'h45; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_68 = 8'h44; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_67 = 8'h43; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_66 = 8'h42; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_65 = 8'h41; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_64 = 8'h40; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_63 = 8'h3F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_62 = 8'h3E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_61 = 8'h3D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_60 = 8'h3C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_59 = 8'h3B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_58 = 8'h3A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_57 = 8'h39; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_56 = 8'h38; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_55 = 8'h37; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_54 = 8'h36; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_53 = 8'h35; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_52 = 8'h34; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_51 = 8'h33; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_50 = 8'h32; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_49 = 8'h31; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_48 = 8'h30; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_47 = 8'h2F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_46 = 8'h2E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_45 = 8'h2D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_44 = 8'h2C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_43 = 8'h2B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_42 = 8'h2A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_41 = 8'h29; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_40 = 8'h28; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_39 = 8'h27; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_38 = 8'h26; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_37 = 8'h25; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_36 = 8'h24; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_35 = 8'h23; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_34 = 8'h22; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_33 = 8'h21; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_32 = 8'h20; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_31 = 8'h1F; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_30 = 8'h1E; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_29 = 8'h1D; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_28 = 8'h1C; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_27 = 8'h1B; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_26 = 8'h1A; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_25 = 8'h19; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_24 = 8'h18; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_23 = 8'h17; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_22 = 8'h16; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_21 = 8'h15; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_20 = 8'h14; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_19 = 8'h13; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_18 = 8'h12; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_17 = 8'h11; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_16 = 8'h10; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_15 = 8'hF; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_14 = 8'hE; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_13 = 8'hD; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_12 = 8'hC; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_11 = 8'hB; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_10 = 8'hA; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_9 = 8'h9; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_8 = 8'h8; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_7 = 8'h7; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_6 = 8'h6; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_5 = 8'h5; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_4 = 8'h4; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_3 = 8'h3; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_2 = 8'h2; // @[ToAXI4.scala:114:36]
wire [7:0] sourceTable_1 = 8'h1; // @[ToAXI4.scala:114:36]
wire [7:0] _sourceTable_WIRE = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_1 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_2 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_3 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_4 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_5 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_6 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_7 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_8 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_9 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_10 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_11 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_12 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_13 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_14 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_15 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_16 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_17 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_18 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_19 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_20 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_21 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_22 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_23 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_24 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_25 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_26 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_27 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_28 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_29 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_30 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_31 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_32 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_33 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_34 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_35 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_36 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_37 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_38 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_39 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_40 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_41 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_42 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_43 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_44 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_45 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_46 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_47 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_48 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_49 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_50 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_51 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_52 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_53 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_54 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_55 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_56 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_57 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_58 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_59 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_60 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_61 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_62 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_63 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_64 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_65 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_66 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_67 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_68 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_69 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_70 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_71 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_72 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_73 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_74 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_75 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_76 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_77 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_78 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_79 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_80 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_81 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_82 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_83 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_84 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_85 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_86 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_87 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_88 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_89 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_90 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_91 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_92 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_93 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_94 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_95 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_96 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_97 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_98 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_99 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_100 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_101 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_102 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_103 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_104 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_105 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_106 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_107 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_108 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_109 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_110 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_111 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_112 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_113 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_114 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_115 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_116 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_117 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_118 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_119 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_120 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_121 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_122 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_123 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_124 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_125 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_126 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_127 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_128 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_129 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_130 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_131 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_132 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_133 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_134 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_135 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_136 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_137 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_138 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_139 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_140 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_141 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_142 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_143 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_144 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_145 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_146 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_147 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_148 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_149 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_150 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_151 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_152 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_153 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_154 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_155 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_156 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_157 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_158 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_159 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_160 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_161 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_162 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_163 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_164 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_165 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_166 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_167 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_168 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_169 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_170 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_171 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_172 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_173 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_174 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_175 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_176 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_177 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_178 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_179 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_180 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_181 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_182 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_183 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_184 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_185 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_186 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_187 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_188 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_189 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_190 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_191 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_192 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_193 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_194 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_195 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_196 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_197 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_198 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_199 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_200 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_201 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_202 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_203 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_204 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_205 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_206 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_207 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_208 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_209 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_210 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_211 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_212 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_213 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_214 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_215 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_216 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_217 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_218 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_219 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_220 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_221 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_222 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_223 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_224 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_225 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_226 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_227 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_228 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_229 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_230 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_231 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_232 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_233 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_234 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_235 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_236 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_237 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_238 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_239 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_240 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_241 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_242 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_243 = 8'h0; // @[ToAXI4.scala:114:89]
wire [7:0] _sourceTable_WIRE_244_0 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_1 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_2 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_3 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_4 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_5 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_6 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_7 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_8 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_9 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_10 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_11 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_12 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_13 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_14 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_15 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_16 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_17 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_18 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_19 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_20 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_21 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_22 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_23 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_24 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_25 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_26 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_27 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_28 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_29 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_30 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_31 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_32 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_33 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_34 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_35 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_36 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_37 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_38 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_39 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_40 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_41 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_42 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_43 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_44 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_45 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_46 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_47 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_48 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_49 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_50 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_51 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_52 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_53 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_54 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_55 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_56 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_57 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_58 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_59 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_60 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_61 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_62 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_63 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_64 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_65 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_66 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_67 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_68 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_69 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_70 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_71 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_72 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_73 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_74 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_75 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_76 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_77 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_78 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_79 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_80 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_81 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_82 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_83 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_84 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_85 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_86 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_87 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_88 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_89 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_90 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_91 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_92 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_93 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_94 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_95 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_96 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_97 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_98 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_99 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_100 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_101 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_102 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_103 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_104 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_105 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_106 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_107 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_108 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_109 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_110 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_111 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_112 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_113 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_114 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_115 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_116 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_117 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_118 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_119 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_120 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_121 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_122 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_123 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_124 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_125 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_126 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_127 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_128 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_129 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_130 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_131 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_132 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_133 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_134 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_135 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_136 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_137 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_138 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_139 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_140 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_141 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_142 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_143 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_144 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_145 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_146 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_147 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_148 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_149 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_150 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_151 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_152 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_153 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_154 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_155 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_156 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_157 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_158 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_159 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_160 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_161 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_162 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_163 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_164 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_165 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_166 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_167 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_168 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_169 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_170 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_171 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_172 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_173 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_174 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_175 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_176 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_177 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_178 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_179 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_180 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_181 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_182 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_183 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_184 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_185 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_186 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_187 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_188 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_189 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_190 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_191 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_192 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_193 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_194 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_195 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_196 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_197 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_198 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_199 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_200 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_201 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_202 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_203 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_204 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_205 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_206 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_207 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_208 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_209 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_210 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_211 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_212 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_213 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_214 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_215 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_216 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_217 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_218 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_219 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_220 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_221 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_222 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_223 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_224 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_225 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_226 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_227 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_228 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_229 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_230 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_231 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_232 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_233 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_234 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_235 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_236 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_237 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_238 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_239 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_240 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_241 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_242 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] _sourceTable_WIRE_244_243 = 8'h0; // @[ToAXI4.scala:114:76]
wire [7:0] sourceTable_0 = 8'h0; // @[ToAXI4.scala:114:36]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[ToAXI4.scala:103:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[ToAXI4.scala:103:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[ToAXI4.scala:103:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[ToAXI4.scala:103:9]
wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[ToAXI4.scala:103:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[ToAXI4.scala:103:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[ToAXI4.scala:103:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[ToAXI4.scala:103:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[ToAXI4.scala:103:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[ToAXI4.scala:103:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[ToAXI4.scala:103:9]
wire nodeOut_aw_valid; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_echo_tl_state_size; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_aw_bits_echo_tl_state_source; // @[MixedNode.scala:542:17]
wire nodeOut_w_ready = auto_out_w_ready_0; // @[ToAXI4.scala:103:9]
wire nodeOut_w_valid; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17]
wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[ToAXI4.scala:103:9]
wire [7:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[ToAXI4.scala:103:9]
wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[ToAXI4.scala:103:9]
wire [3:0] nodeOut_b_bits_echo_tl_state_size = auto_out_b_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9]
wire [7:0] nodeOut_b_bits_echo_tl_state_source = auto_out_b_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9]
wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[ToAXI4.scala:103:9]
wire nodeOut_ar_valid; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_echo_tl_state_size; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_ar_bits_echo_tl_state_source; // @[MixedNode.scala:542:17]
wire nodeOut_r_ready; // @[MixedNode.scala:542:17]
wire nodeOut_r_valid = auto_out_r_valid_0; // @[ToAXI4.scala:103:9]
wire [7:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[ToAXI4.scala:103:9]
wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[ToAXI4.scala:103:9]
wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[ToAXI4.scala:103:9]
wire [3:0] nodeOut_r_bits_echo_tl_state_size = auto_out_r_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9]
wire [7:0] nodeOut_r_bits_echo_tl_state_source = auto_out_r_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9]
wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[ToAXI4.scala:103:9]
wire auto_in_a_ready_0; // @[ToAXI4.scala:103:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[ToAXI4.scala:103:9]
wire [2:0] auto_in_d_bits_size_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_in_d_bits_source_0; // @[ToAXI4.scala:103:9]
wire auto_in_d_bits_denied_0; // @[ToAXI4.scala:103:9]
wire [63:0] auto_in_d_bits_data_0; // @[ToAXI4.scala:103:9]
wire auto_in_d_bits_corrupt_0; // @[ToAXI4.scala:103:9]
wire auto_in_d_valid_0; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_aw_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_aw_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_aw_bits_id_0; // @[ToAXI4.scala:103:9]
wire [31:0] auto_out_aw_bits_addr_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_aw_bits_len_0; // @[ToAXI4.scala:103:9]
wire [2:0] auto_out_aw_bits_size_0; // @[ToAXI4.scala:103:9]
wire [1:0] auto_out_aw_bits_burst_0; // @[ToAXI4.scala:103:9]
wire auto_out_aw_bits_lock_0; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_aw_bits_cache_0; // @[ToAXI4.scala:103:9]
wire [2:0] auto_out_aw_bits_prot_0; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_aw_bits_qos_0; // @[ToAXI4.scala:103:9]
wire auto_out_aw_valid_0; // @[ToAXI4.scala:103:9]
wire [63:0] auto_out_w_bits_data_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_w_bits_strb_0; // @[ToAXI4.scala:103:9]
wire auto_out_w_bits_last_0; // @[ToAXI4.scala:103:9]
wire auto_out_w_valid_0; // @[ToAXI4.scala:103:9]
wire auto_out_b_ready_0; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_ar_bits_echo_tl_state_size_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_ar_bits_echo_tl_state_source_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_ar_bits_id_0; // @[ToAXI4.scala:103:9]
wire [31:0] auto_out_ar_bits_addr_0; // @[ToAXI4.scala:103:9]
wire [7:0] auto_out_ar_bits_len_0; // @[ToAXI4.scala:103:9]
wire [2:0] auto_out_ar_bits_size_0; // @[ToAXI4.scala:103:9]
wire [1:0] auto_out_ar_bits_burst_0; // @[ToAXI4.scala:103:9]
wire auto_out_ar_bits_lock_0; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_ar_bits_cache_0; // @[ToAXI4.scala:103:9]
wire [2:0] auto_out_ar_bits_prot_0; // @[ToAXI4.scala:103:9]
wire [3:0] auto_out_ar_bits_qos_0; // @[ToAXI4.scala:103:9]
wire auto_out_ar_valid_0; // @[ToAXI4.scala:103:9]
wire auto_out_r_ready_0; // @[ToAXI4.scala:103:9]
wire _nodeIn_a_ready_T_4; // @[ToAXI4.scala:206:28]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[ToAXI4.scala:103:9]
wire [7:0] out_arw_bits_echo_tl_state_source = nodeIn_a_bits_source; // @[ToAXI4.scala:153:25]
wire [31:0] out_arw_bits_addr = nodeIn_a_bits_address; // @[ToAXI4.scala:153:25]
wire [7:0] out_w_bits_strb = nodeIn_a_bits_mask; // @[ToAXI4.scala:154:23]
wire [63:0] out_w_bits_data = nodeIn_a_bits_data; // @[ToAXI4.scala:154:23]
wire _nodeIn_d_valid_T; // @[ToAXI4.scala:229:24]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[ToAXI4.scala:103:9]
wire [2:0] _nodeIn_d_bits_T_opcode; // @[ToAXI4.scala:255:23]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ToAXI4.scala:103:9]
wire [2:0] _nodeIn_d_bits_T_size; // @[ToAXI4.scala:255:23]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[ToAXI4.scala:103:9]
wire [7:0] _nodeIn_d_bits_T_source; // @[ToAXI4.scala:255:23]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[ToAXI4.scala:103:9]
wire _nodeIn_d_bits_T_denied; // @[ToAXI4.scala:255:23]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ToAXI4.scala:103:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[ToAXI4.scala:103:9]
wire _nodeIn_d_bits_T_corrupt; // @[ToAXI4.scala:255:23]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ToAXI4.scala:103:9]
wire _nodeOut_aw_valid_T; // @[ToAXI4.scala:162:39]
assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[ToAXI4.scala:103:9]
wire [7:0] queue_arw_bits_id; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[ToAXI4.scala:103:9]
wire [31:0] queue_arw_bits_addr; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[ToAXI4.scala:103:9]
wire [7:0] queue_arw_bits_len; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[ToAXI4.scala:103:9]
wire [2:0] queue_arw_bits_size; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[ToAXI4.scala:103:9]
wire [1:0] queue_arw_bits_burst; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[ToAXI4.scala:103:9]
wire queue_arw_bits_lock; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[ToAXI4.scala:103:9]
wire [3:0] queue_arw_bits_cache; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[ToAXI4.scala:103:9]
wire [2:0] queue_arw_bits_prot; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[ToAXI4.scala:103:9]
wire [3:0] queue_arw_bits_qos; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[ToAXI4.scala:103:9]
wire [3:0] queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_echo_tl_state_size_0 = nodeOut_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9]
wire [7:0] queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_echo_tl_state_source_0 = nodeOut_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9]
wire nodeOut_w_irr_ready = nodeOut_w_ready; // @[Decoupled.scala:401:19]
wire nodeOut_w_irr_valid; // @[Decoupled.scala:401:19]
assign auto_out_w_valid_0 = nodeOut_w_valid; // @[ToAXI4.scala:103:9]
wire [63:0] nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[ToAXI4.scala:103:9]
wire [7:0] nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[ToAXI4.scala:103:9]
wire nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[ToAXI4.scala:103:9]
wire _nodeOut_b_ready_T_1; // @[ToAXI4.scala:228:33]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[ToAXI4.scala:103:9]
wire [7:0] b_d_source = nodeOut_b_bits_echo_tl_state_source; // @[Edges.scala:792:17]
wire _nodeOut_ar_valid_T_1; // @[ToAXI4.scala:161:39]
assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_echo_tl_state_size_0 = nodeOut_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:103:9]
assign auto_out_ar_bits_echo_tl_state_source_0 = nodeOut_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:103:9]
wire _nodeOut_r_ready_T; // @[ToAXI4.scala:227:33]
assign auto_out_r_ready_0 = nodeOut_r_ready; // @[ToAXI4.scala:103:9]
assign nodeIn_d_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] r_d_source = nodeOut_r_bits_echo_tl_state_source; // @[Edges.scala:810:17]
wire idStall_0; // @[ToAXI4.scala:115:32]
wire idStall_1; // @[ToAXI4.scala:115:32]
wire idStall_2; // @[ToAXI4.scala:115:32]
wire idStall_3; // @[ToAXI4.scala:115:32]
wire idStall_4; // @[ToAXI4.scala:115:32]
wire idStall_5; // @[ToAXI4.scala:115:32]
wire idStall_6; // @[ToAXI4.scala:115:32]
wire idStall_7; // @[ToAXI4.scala:115:32]
wire idStall_8; // @[ToAXI4.scala:115:32]
wire idStall_9; // @[ToAXI4.scala:115:32]
wire idStall_10; // @[ToAXI4.scala:115:32]
wire idStall_11; // @[ToAXI4.scala:115:32]
wire idStall_12; // @[ToAXI4.scala:115:32]
wire idStall_13; // @[ToAXI4.scala:115:32]
wire idStall_14; // @[ToAXI4.scala:115:32]
wire idStall_15; // @[ToAXI4.scala:115:32]
wire idStall_16; // @[ToAXI4.scala:115:32]
wire idStall_17; // @[ToAXI4.scala:115:32]
wire idStall_18; // @[ToAXI4.scala:115:32]
wire idStall_19; // @[ToAXI4.scala:115:32]
wire idStall_20; // @[ToAXI4.scala:115:32]
wire idStall_21; // @[ToAXI4.scala:115:32]
wire idStall_22; // @[ToAXI4.scala:115:32]
wire idStall_23; // @[ToAXI4.scala:115:32]
wire idStall_24; // @[ToAXI4.scala:115:32]
wire idStall_25; // @[ToAXI4.scala:115:32]
wire idStall_26; // @[ToAXI4.scala:115:32]
wire idStall_27; // @[ToAXI4.scala:115:32]
wire idStall_28; // @[ToAXI4.scala:115:32]
wire idStall_29; // @[ToAXI4.scala:115:32]
wire idStall_30; // @[ToAXI4.scala:115:32]
wire idStall_31; // @[ToAXI4.scala:115:32]
wire idStall_32; // @[ToAXI4.scala:115:32]
wire idStall_33; // @[ToAXI4.scala:115:32]
wire idStall_34; // @[ToAXI4.scala:115:32]
wire idStall_35; // @[ToAXI4.scala:115:32]
wire idStall_36; // @[ToAXI4.scala:115:32]
wire idStall_37; // @[ToAXI4.scala:115:32]
wire idStall_38; // @[ToAXI4.scala:115:32]
wire idStall_39; // @[ToAXI4.scala:115:32]
wire idStall_40; // @[ToAXI4.scala:115:32]
wire idStall_41; // @[ToAXI4.scala:115:32]
wire idStall_42; // @[ToAXI4.scala:115:32]
wire idStall_43; // @[ToAXI4.scala:115:32]
wire idStall_44; // @[ToAXI4.scala:115:32]
wire idStall_45; // @[ToAXI4.scala:115:32]
wire idStall_46; // @[ToAXI4.scala:115:32]
wire idStall_47; // @[ToAXI4.scala:115:32]
wire idStall_48; // @[ToAXI4.scala:115:32]
wire idStall_49; // @[ToAXI4.scala:115:32]
wire idStall_50; // @[ToAXI4.scala:115:32]
wire idStall_51; // @[ToAXI4.scala:115:32]
wire idStall_52; // @[ToAXI4.scala:115:32]
wire idStall_53; // @[ToAXI4.scala:115:32]
wire idStall_54; // @[ToAXI4.scala:115:32]
wire idStall_55; // @[ToAXI4.scala:115:32]
wire idStall_56; // @[ToAXI4.scala:115:32]
wire idStall_57; // @[ToAXI4.scala:115:32]
wire idStall_58; // @[ToAXI4.scala:115:32]
wire idStall_59; // @[ToAXI4.scala:115:32]
wire idStall_60; // @[ToAXI4.scala:115:32]
wire idStall_61; // @[ToAXI4.scala:115:32]
wire idStall_62; // @[ToAXI4.scala:115:32]
wire idStall_63; // @[ToAXI4.scala:115:32]
wire idStall_64; // @[ToAXI4.scala:115:32]
wire idStall_65; // @[ToAXI4.scala:115:32]
wire idStall_66; // @[ToAXI4.scala:115:32]
wire idStall_67; // @[ToAXI4.scala:115:32]
wire idStall_68; // @[ToAXI4.scala:115:32]
wire idStall_69; // @[ToAXI4.scala:115:32]
wire idStall_70; // @[ToAXI4.scala:115:32]
wire idStall_71; // @[ToAXI4.scala:115:32]
wire idStall_72; // @[ToAXI4.scala:115:32]
wire idStall_73; // @[ToAXI4.scala:115:32]
wire idStall_74; // @[ToAXI4.scala:115:32]
wire idStall_75; // @[ToAXI4.scala:115:32]
wire idStall_76; // @[ToAXI4.scala:115:32]
wire idStall_77; // @[ToAXI4.scala:115:32]
wire idStall_78; // @[ToAXI4.scala:115:32]
wire idStall_79; // @[ToAXI4.scala:115:32]
wire idStall_80; // @[ToAXI4.scala:115:32]
wire idStall_81; // @[ToAXI4.scala:115:32]
wire idStall_82; // @[ToAXI4.scala:115:32]
wire idStall_83; // @[ToAXI4.scala:115:32]
wire idStall_84; // @[ToAXI4.scala:115:32]
wire idStall_85; // @[ToAXI4.scala:115:32]
wire idStall_86; // @[ToAXI4.scala:115:32]
wire idStall_87; // @[ToAXI4.scala:115:32]
wire idStall_88; // @[ToAXI4.scala:115:32]
wire idStall_89; // @[ToAXI4.scala:115:32]
wire idStall_90; // @[ToAXI4.scala:115:32]
wire idStall_91; // @[ToAXI4.scala:115:32]
wire idStall_92; // @[ToAXI4.scala:115:32]
wire idStall_93; // @[ToAXI4.scala:115:32]
wire idStall_94; // @[ToAXI4.scala:115:32]
wire idStall_95; // @[ToAXI4.scala:115:32]
wire idStall_96; // @[ToAXI4.scala:115:32]
wire idStall_97; // @[ToAXI4.scala:115:32]
wire idStall_98; // @[ToAXI4.scala:115:32]
wire idStall_99; // @[ToAXI4.scala:115:32]
wire idStall_100; // @[ToAXI4.scala:115:32]
wire idStall_101; // @[ToAXI4.scala:115:32]
wire idStall_102; // @[ToAXI4.scala:115:32]
wire idStall_103; // @[ToAXI4.scala:115:32]
wire idStall_104; // @[ToAXI4.scala:115:32]
wire idStall_105; // @[ToAXI4.scala:115:32]
wire idStall_106; // @[ToAXI4.scala:115:32]
wire idStall_107; // @[ToAXI4.scala:115:32]
wire idStall_108; // @[ToAXI4.scala:115:32]
wire idStall_109; // @[ToAXI4.scala:115:32]
wire idStall_110; // @[ToAXI4.scala:115:32]
wire idStall_111; // @[ToAXI4.scala:115:32]
wire idStall_112; // @[ToAXI4.scala:115:32]
wire idStall_113; // @[ToAXI4.scala:115:32]
wire idStall_114; // @[ToAXI4.scala:115:32]
wire idStall_115; // @[ToAXI4.scala:115:32]
wire idStall_116; // @[ToAXI4.scala:115:32]
wire idStall_117; // @[ToAXI4.scala:115:32]
wire idStall_118; // @[ToAXI4.scala:115:32]
wire idStall_119; // @[ToAXI4.scala:115:32]
wire idStall_120; // @[ToAXI4.scala:115:32]
wire idStall_121; // @[ToAXI4.scala:115:32]
wire idStall_122; // @[ToAXI4.scala:115:32]
wire idStall_123; // @[ToAXI4.scala:115:32]
wire idStall_124; // @[ToAXI4.scala:115:32]
wire idStall_125; // @[ToAXI4.scala:115:32]
wire idStall_126; // @[ToAXI4.scala:115:32]
wire idStall_127; // @[ToAXI4.scala:115:32]
wire idStall_128; // @[ToAXI4.scala:115:32]
wire idStall_129; // @[ToAXI4.scala:115:32]
wire idStall_130; // @[ToAXI4.scala:115:32]
wire idStall_131; // @[ToAXI4.scala:115:32]
wire idStall_132; // @[ToAXI4.scala:115:32]
wire idStall_133; // @[ToAXI4.scala:115:32]
wire idStall_134; // @[ToAXI4.scala:115:32]
wire idStall_135; // @[ToAXI4.scala:115:32]
wire idStall_136; // @[ToAXI4.scala:115:32]
wire idStall_137; // @[ToAXI4.scala:115:32]
wire idStall_138; // @[ToAXI4.scala:115:32]
wire idStall_139; // @[ToAXI4.scala:115:32]
wire idStall_140; // @[ToAXI4.scala:115:32]
wire idStall_141; // @[ToAXI4.scala:115:32]
wire idStall_142; // @[ToAXI4.scala:115:32]
wire idStall_143; // @[ToAXI4.scala:115:32]
wire idStall_144; // @[ToAXI4.scala:115:32]
wire idStall_145; // @[ToAXI4.scala:115:32]
wire idStall_146; // @[ToAXI4.scala:115:32]
wire idStall_147; // @[ToAXI4.scala:115:32]
wire idStall_148; // @[ToAXI4.scala:115:32]
wire idStall_149; // @[ToAXI4.scala:115:32]
wire idStall_150; // @[ToAXI4.scala:115:32]
wire idStall_151; // @[ToAXI4.scala:115:32]
wire idStall_152; // @[ToAXI4.scala:115:32]
wire idStall_153; // @[ToAXI4.scala:115:32]
wire idStall_154; // @[ToAXI4.scala:115:32]
wire idStall_155; // @[ToAXI4.scala:115:32]
wire idStall_156; // @[ToAXI4.scala:115:32]
wire idStall_157; // @[ToAXI4.scala:115:32]
wire idStall_158; // @[ToAXI4.scala:115:32]
wire idStall_159; // @[ToAXI4.scala:115:32]
wire idStall_160; // @[ToAXI4.scala:115:32]
wire idStall_161; // @[ToAXI4.scala:115:32]
wire idStall_162; // @[ToAXI4.scala:115:32]
wire idStall_163; // @[ToAXI4.scala:115:32]
wire idStall_164; // @[ToAXI4.scala:115:32]
wire idStall_165; // @[ToAXI4.scala:115:32]
wire idStall_166; // @[ToAXI4.scala:115:32]
wire idStall_167; // @[ToAXI4.scala:115:32]
wire idStall_168; // @[ToAXI4.scala:115:32]
wire idStall_169; // @[ToAXI4.scala:115:32]
wire idStall_170; // @[ToAXI4.scala:115:32]
wire idStall_171; // @[ToAXI4.scala:115:32]
wire idStall_172; // @[ToAXI4.scala:115:32]
wire idStall_173; // @[ToAXI4.scala:115:32]
wire idStall_174; // @[ToAXI4.scala:115:32]
wire idStall_175; // @[ToAXI4.scala:115:32]
wire idStall_176; // @[ToAXI4.scala:115:32]
wire idStall_177; // @[ToAXI4.scala:115:32]
wire idStall_178; // @[ToAXI4.scala:115:32]
wire idStall_179; // @[ToAXI4.scala:115:32]
wire idStall_180; // @[ToAXI4.scala:115:32]
wire idStall_181; // @[ToAXI4.scala:115:32]
wire idStall_182; // @[ToAXI4.scala:115:32]
wire idStall_183; // @[ToAXI4.scala:115:32]
wire idStall_184; // @[ToAXI4.scala:115:32]
wire idStall_185; // @[ToAXI4.scala:115:32]
wire idStall_186; // @[ToAXI4.scala:115:32]
wire idStall_187; // @[ToAXI4.scala:115:32]
wire idStall_188; // @[ToAXI4.scala:115:32]
wire idStall_189; // @[ToAXI4.scala:115:32]
wire idStall_190; // @[ToAXI4.scala:115:32]
wire idStall_191; // @[ToAXI4.scala:115:32]
wire idStall_192; // @[ToAXI4.scala:115:32]
wire idStall_193; // @[ToAXI4.scala:115:32]
wire idStall_194; // @[ToAXI4.scala:115:32]
wire idStall_195; // @[ToAXI4.scala:115:32]
wire idStall_196; // @[ToAXI4.scala:115:32]
wire idStall_197; // @[ToAXI4.scala:115:32]
wire idStall_198; // @[ToAXI4.scala:115:32]
wire idStall_199; // @[ToAXI4.scala:115:32]
wire idStall_200; // @[ToAXI4.scala:115:32]
wire idStall_201; // @[ToAXI4.scala:115:32]
wire idStall_202; // @[ToAXI4.scala:115:32]
wire idStall_203; // @[ToAXI4.scala:115:32]
wire idStall_204; // @[ToAXI4.scala:115:32]
wire idStall_205; // @[ToAXI4.scala:115:32]
wire idStall_206; // @[ToAXI4.scala:115:32]
wire idStall_207; // @[ToAXI4.scala:115:32]
wire idStall_208; // @[ToAXI4.scala:115:32]
wire idStall_209; // @[ToAXI4.scala:115:32]
wire idStall_210; // @[ToAXI4.scala:115:32]
wire idStall_211; // @[ToAXI4.scala:115:32]
wire idStall_212; // @[ToAXI4.scala:115:32]
wire idStall_213; // @[ToAXI4.scala:115:32]
wire idStall_214; // @[ToAXI4.scala:115:32]
wire idStall_215; // @[ToAXI4.scala:115:32]
wire idStall_216; // @[ToAXI4.scala:115:32]
wire idStall_217; // @[ToAXI4.scala:115:32]
wire idStall_218; // @[ToAXI4.scala:115:32]
wire idStall_219; // @[ToAXI4.scala:115:32]
wire idStall_220; // @[ToAXI4.scala:115:32]
wire idStall_221; // @[ToAXI4.scala:115:32]
wire idStall_222; // @[ToAXI4.scala:115:32]
wire idStall_223; // @[ToAXI4.scala:115:32]
wire idStall_224; // @[ToAXI4.scala:115:32]
wire idStall_225; // @[ToAXI4.scala:115:32]
wire idStall_226; // @[ToAXI4.scala:115:32]
wire idStall_227; // @[ToAXI4.scala:115:32]
wire idStall_228; // @[ToAXI4.scala:115:32]
wire idStall_229; // @[ToAXI4.scala:115:32]
wire idStall_230; // @[ToAXI4.scala:115:32]
wire idStall_231; // @[ToAXI4.scala:115:32]
wire idStall_232; // @[ToAXI4.scala:115:32]
wire idStall_233; // @[ToAXI4.scala:115:32]
wire idStall_234; // @[ToAXI4.scala:115:32]
wire idStall_235; // @[ToAXI4.scala:115:32]
wire idStall_236; // @[ToAXI4.scala:115:32]
wire idStall_237; // @[ToAXI4.scala:115:32]
wire idStall_238; // @[ToAXI4.scala:115:32]
wire idStall_239; // @[ToAXI4.scala:115:32]
wire idStall_240; // @[ToAXI4.scala:115:32]
wire idStall_241; // @[ToAXI4.scala:115:32]
wire idStall_242; // @[ToAXI4.scala:115:32]
wire idStall_243; // @[ToAXI4.scala:115:32]
wire sourceStall_0; // @[ToAXI4.scala:113:36]
wire sourceStall_1; // @[ToAXI4.scala:113:36]
wire sourceStall_2; // @[ToAXI4.scala:113:36]
wire sourceStall_3; // @[ToAXI4.scala:113:36]
wire sourceStall_4; // @[ToAXI4.scala:113:36]
wire sourceStall_5; // @[ToAXI4.scala:113:36]
wire sourceStall_6; // @[ToAXI4.scala:113:36]
wire sourceStall_7; // @[ToAXI4.scala:113:36]
wire sourceStall_8; // @[ToAXI4.scala:113:36]
wire sourceStall_9; // @[ToAXI4.scala:113:36]
wire sourceStall_10; // @[ToAXI4.scala:113:36]
wire sourceStall_11; // @[ToAXI4.scala:113:36]
wire sourceStall_12; // @[ToAXI4.scala:113:36]
wire sourceStall_13; // @[ToAXI4.scala:113:36]
wire sourceStall_14; // @[ToAXI4.scala:113:36]
wire sourceStall_15; // @[ToAXI4.scala:113:36]
wire sourceStall_16; // @[ToAXI4.scala:113:36]
wire sourceStall_17; // @[ToAXI4.scala:113:36]
wire sourceStall_18; // @[ToAXI4.scala:113:36]
wire sourceStall_19; // @[ToAXI4.scala:113:36]
wire sourceStall_20; // @[ToAXI4.scala:113:36]
wire sourceStall_21; // @[ToAXI4.scala:113:36]
wire sourceStall_22; // @[ToAXI4.scala:113:36]
wire sourceStall_23; // @[ToAXI4.scala:113:36]
wire sourceStall_24; // @[ToAXI4.scala:113:36]
wire sourceStall_25; // @[ToAXI4.scala:113:36]
wire sourceStall_26; // @[ToAXI4.scala:113:36]
wire sourceStall_27; // @[ToAXI4.scala:113:36]
wire sourceStall_28; // @[ToAXI4.scala:113:36]
wire sourceStall_29; // @[ToAXI4.scala:113:36]
wire sourceStall_30; // @[ToAXI4.scala:113:36]
wire sourceStall_31; // @[ToAXI4.scala:113:36]
wire sourceStall_32; // @[ToAXI4.scala:113:36]
wire sourceStall_33; // @[ToAXI4.scala:113:36]
wire sourceStall_34; // @[ToAXI4.scala:113:36]
wire sourceStall_35; // @[ToAXI4.scala:113:36]
wire sourceStall_36; // @[ToAXI4.scala:113:36]
wire sourceStall_37; // @[ToAXI4.scala:113:36]
wire sourceStall_38; // @[ToAXI4.scala:113:36]
wire sourceStall_39; // @[ToAXI4.scala:113:36]
wire sourceStall_40; // @[ToAXI4.scala:113:36]
wire sourceStall_41; // @[ToAXI4.scala:113:36]
wire sourceStall_42; // @[ToAXI4.scala:113:36]
wire sourceStall_43; // @[ToAXI4.scala:113:36]
wire sourceStall_44; // @[ToAXI4.scala:113:36]
wire sourceStall_45; // @[ToAXI4.scala:113:36]
wire sourceStall_46; // @[ToAXI4.scala:113:36]
wire sourceStall_47; // @[ToAXI4.scala:113:36]
wire sourceStall_48; // @[ToAXI4.scala:113:36]
wire sourceStall_49; // @[ToAXI4.scala:113:36]
wire sourceStall_50; // @[ToAXI4.scala:113:36]
wire sourceStall_51; // @[ToAXI4.scala:113:36]
wire sourceStall_52; // @[ToAXI4.scala:113:36]
wire sourceStall_53; // @[ToAXI4.scala:113:36]
wire sourceStall_54; // @[ToAXI4.scala:113:36]
wire sourceStall_55; // @[ToAXI4.scala:113:36]
wire sourceStall_56; // @[ToAXI4.scala:113:36]
wire sourceStall_57; // @[ToAXI4.scala:113:36]
wire sourceStall_58; // @[ToAXI4.scala:113:36]
wire sourceStall_59; // @[ToAXI4.scala:113:36]
wire sourceStall_60; // @[ToAXI4.scala:113:36]
wire sourceStall_61; // @[ToAXI4.scala:113:36]
wire sourceStall_62; // @[ToAXI4.scala:113:36]
wire sourceStall_63; // @[ToAXI4.scala:113:36]
wire sourceStall_64; // @[ToAXI4.scala:113:36]
wire sourceStall_65; // @[ToAXI4.scala:113:36]
wire sourceStall_66; // @[ToAXI4.scala:113:36]
wire sourceStall_67; // @[ToAXI4.scala:113:36]
wire sourceStall_68; // @[ToAXI4.scala:113:36]
wire sourceStall_69; // @[ToAXI4.scala:113:36]
wire sourceStall_70; // @[ToAXI4.scala:113:36]
wire sourceStall_71; // @[ToAXI4.scala:113:36]
wire sourceStall_72; // @[ToAXI4.scala:113:36]
wire sourceStall_73; // @[ToAXI4.scala:113:36]
wire sourceStall_74; // @[ToAXI4.scala:113:36]
wire sourceStall_75; // @[ToAXI4.scala:113:36]
wire sourceStall_76; // @[ToAXI4.scala:113:36]
wire sourceStall_77; // @[ToAXI4.scala:113:36]
wire sourceStall_78; // @[ToAXI4.scala:113:36]
wire sourceStall_79; // @[ToAXI4.scala:113:36]
wire sourceStall_80; // @[ToAXI4.scala:113:36]
wire sourceStall_81; // @[ToAXI4.scala:113:36]
wire sourceStall_82; // @[ToAXI4.scala:113:36]
wire sourceStall_83; // @[ToAXI4.scala:113:36]
wire sourceStall_84; // @[ToAXI4.scala:113:36]
wire sourceStall_85; // @[ToAXI4.scala:113:36]
wire sourceStall_86; // @[ToAXI4.scala:113:36]
wire sourceStall_87; // @[ToAXI4.scala:113:36]
wire sourceStall_88; // @[ToAXI4.scala:113:36]
wire sourceStall_89; // @[ToAXI4.scala:113:36]
wire sourceStall_90; // @[ToAXI4.scala:113:36]
wire sourceStall_91; // @[ToAXI4.scala:113:36]
wire sourceStall_92; // @[ToAXI4.scala:113:36]
wire sourceStall_93; // @[ToAXI4.scala:113:36]
wire sourceStall_94; // @[ToAXI4.scala:113:36]
wire sourceStall_95; // @[ToAXI4.scala:113:36]
wire sourceStall_96; // @[ToAXI4.scala:113:36]
wire sourceStall_97; // @[ToAXI4.scala:113:36]
wire sourceStall_98; // @[ToAXI4.scala:113:36]
wire sourceStall_99; // @[ToAXI4.scala:113:36]
wire sourceStall_100; // @[ToAXI4.scala:113:36]
wire sourceStall_101; // @[ToAXI4.scala:113:36]
wire sourceStall_102; // @[ToAXI4.scala:113:36]
wire sourceStall_103; // @[ToAXI4.scala:113:36]
wire sourceStall_104; // @[ToAXI4.scala:113:36]
wire sourceStall_105; // @[ToAXI4.scala:113:36]
wire sourceStall_106; // @[ToAXI4.scala:113:36]
wire sourceStall_107; // @[ToAXI4.scala:113:36]
wire sourceStall_108; // @[ToAXI4.scala:113:36]
wire sourceStall_109; // @[ToAXI4.scala:113:36]
wire sourceStall_110; // @[ToAXI4.scala:113:36]
wire sourceStall_111; // @[ToAXI4.scala:113:36]
wire sourceStall_112; // @[ToAXI4.scala:113:36]
wire sourceStall_113; // @[ToAXI4.scala:113:36]
wire sourceStall_114; // @[ToAXI4.scala:113:36]
wire sourceStall_115; // @[ToAXI4.scala:113:36]
wire sourceStall_116; // @[ToAXI4.scala:113:36]
wire sourceStall_117; // @[ToAXI4.scala:113:36]
wire sourceStall_118; // @[ToAXI4.scala:113:36]
wire sourceStall_119; // @[ToAXI4.scala:113:36]
wire sourceStall_120; // @[ToAXI4.scala:113:36]
wire sourceStall_121; // @[ToAXI4.scala:113:36]
wire sourceStall_122; // @[ToAXI4.scala:113:36]
wire sourceStall_123; // @[ToAXI4.scala:113:36]
wire sourceStall_124; // @[ToAXI4.scala:113:36]
wire sourceStall_125; // @[ToAXI4.scala:113:36]
wire sourceStall_126; // @[ToAXI4.scala:113:36]
wire sourceStall_127; // @[ToAXI4.scala:113:36]
wire sourceStall_128; // @[ToAXI4.scala:113:36]
wire sourceStall_129; // @[ToAXI4.scala:113:36]
wire sourceStall_130; // @[ToAXI4.scala:113:36]
wire sourceStall_131; // @[ToAXI4.scala:113:36]
wire sourceStall_132; // @[ToAXI4.scala:113:36]
wire sourceStall_133; // @[ToAXI4.scala:113:36]
wire sourceStall_134; // @[ToAXI4.scala:113:36]
wire sourceStall_135; // @[ToAXI4.scala:113:36]
wire sourceStall_136; // @[ToAXI4.scala:113:36]
wire sourceStall_137; // @[ToAXI4.scala:113:36]
wire sourceStall_138; // @[ToAXI4.scala:113:36]
wire sourceStall_139; // @[ToAXI4.scala:113:36]
wire sourceStall_140; // @[ToAXI4.scala:113:36]
wire sourceStall_141; // @[ToAXI4.scala:113:36]
wire sourceStall_142; // @[ToAXI4.scala:113:36]
wire sourceStall_143; // @[ToAXI4.scala:113:36]
wire sourceStall_144; // @[ToAXI4.scala:113:36]
wire sourceStall_145; // @[ToAXI4.scala:113:36]
wire sourceStall_146; // @[ToAXI4.scala:113:36]
wire sourceStall_147; // @[ToAXI4.scala:113:36]
wire sourceStall_148; // @[ToAXI4.scala:113:36]
wire sourceStall_149; // @[ToAXI4.scala:113:36]
wire sourceStall_150; // @[ToAXI4.scala:113:36]
wire sourceStall_151; // @[ToAXI4.scala:113:36]
wire sourceStall_152; // @[ToAXI4.scala:113:36]
wire sourceStall_153; // @[ToAXI4.scala:113:36]
wire sourceStall_154; // @[ToAXI4.scala:113:36]
wire sourceStall_155; // @[ToAXI4.scala:113:36]
wire sourceStall_156; // @[ToAXI4.scala:113:36]
wire sourceStall_157; // @[ToAXI4.scala:113:36]
wire sourceStall_158; // @[ToAXI4.scala:113:36]
wire sourceStall_159; // @[ToAXI4.scala:113:36]
wire sourceStall_160; // @[ToAXI4.scala:113:36]
wire sourceStall_161; // @[ToAXI4.scala:113:36]
wire sourceStall_162; // @[ToAXI4.scala:113:36]
wire sourceStall_163; // @[ToAXI4.scala:113:36]
wire sourceStall_164; // @[ToAXI4.scala:113:36]
wire sourceStall_165; // @[ToAXI4.scala:113:36]
wire sourceStall_166; // @[ToAXI4.scala:113:36]
wire sourceStall_167; // @[ToAXI4.scala:113:36]
wire sourceStall_168; // @[ToAXI4.scala:113:36]
wire sourceStall_169; // @[ToAXI4.scala:113:36]
wire sourceStall_170; // @[ToAXI4.scala:113:36]
wire sourceStall_171; // @[ToAXI4.scala:113:36]
wire sourceStall_172; // @[ToAXI4.scala:113:36]
wire sourceStall_173; // @[ToAXI4.scala:113:36]
wire sourceStall_174; // @[ToAXI4.scala:113:36]
wire sourceStall_175; // @[ToAXI4.scala:113:36]
wire sourceStall_176; // @[ToAXI4.scala:113:36]
wire sourceStall_177; // @[ToAXI4.scala:113:36]
wire sourceStall_178; // @[ToAXI4.scala:113:36]
wire sourceStall_179; // @[ToAXI4.scala:113:36]
wire sourceStall_180; // @[ToAXI4.scala:113:36]
wire sourceStall_181; // @[ToAXI4.scala:113:36]
wire sourceStall_182; // @[ToAXI4.scala:113:36]
wire sourceStall_183; // @[ToAXI4.scala:113:36]
wire sourceStall_184; // @[ToAXI4.scala:113:36]
wire sourceStall_185; // @[ToAXI4.scala:113:36]
wire sourceStall_186; // @[ToAXI4.scala:113:36]
wire sourceStall_187; // @[ToAXI4.scala:113:36]
wire sourceStall_188; // @[ToAXI4.scala:113:36]
wire sourceStall_189; // @[ToAXI4.scala:113:36]
wire sourceStall_190; // @[ToAXI4.scala:113:36]
wire sourceStall_191; // @[ToAXI4.scala:113:36]
wire sourceStall_192; // @[ToAXI4.scala:113:36]
wire sourceStall_193; // @[ToAXI4.scala:113:36]
wire sourceStall_194; // @[ToAXI4.scala:113:36]
wire sourceStall_195; // @[ToAXI4.scala:113:36]
wire sourceStall_196; // @[ToAXI4.scala:113:36]
wire sourceStall_197; // @[ToAXI4.scala:113:36]
wire sourceStall_198; // @[ToAXI4.scala:113:36]
wire sourceStall_199; // @[ToAXI4.scala:113:36]
wire sourceStall_200; // @[ToAXI4.scala:113:36]
wire sourceStall_201; // @[ToAXI4.scala:113:36]
wire sourceStall_202; // @[ToAXI4.scala:113:36]
wire sourceStall_203; // @[ToAXI4.scala:113:36]
wire sourceStall_204; // @[ToAXI4.scala:113:36]
wire sourceStall_205; // @[ToAXI4.scala:113:36]
wire sourceStall_206; // @[ToAXI4.scala:113:36]
wire sourceStall_207; // @[ToAXI4.scala:113:36]
wire sourceStall_208; // @[ToAXI4.scala:113:36]
wire sourceStall_209; // @[ToAXI4.scala:113:36]
wire sourceStall_210; // @[ToAXI4.scala:113:36]
wire sourceStall_211; // @[ToAXI4.scala:113:36]
wire sourceStall_212; // @[ToAXI4.scala:113:36]
wire sourceStall_213; // @[ToAXI4.scala:113:36]
wire sourceStall_214; // @[ToAXI4.scala:113:36]
wire sourceStall_215; // @[ToAXI4.scala:113:36]
wire sourceStall_216; // @[ToAXI4.scala:113:36]
wire sourceStall_217; // @[ToAXI4.scala:113:36]
wire sourceStall_218; // @[ToAXI4.scala:113:36]
wire sourceStall_219; // @[ToAXI4.scala:113:36]
wire sourceStall_220; // @[ToAXI4.scala:113:36]
wire sourceStall_221; // @[ToAXI4.scala:113:36]
wire sourceStall_222; // @[ToAXI4.scala:113:36]
wire sourceStall_223; // @[ToAXI4.scala:113:36]
wire sourceStall_224; // @[ToAXI4.scala:113:36]
wire sourceStall_225; // @[ToAXI4.scala:113:36]
wire sourceStall_226; // @[ToAXI4.scala:113:36]
wire sourceStall_227; // @[ToAXI4.scala:113:36]
wire sourceStall_228; // @[ToAXI4.scala:113:36]
wire sourceStall_229; // @[ToAXI4.scala:113:36]
wire sourceStall_230; // @[ToAXI4.scala:113:36]
wire sourceStall_231; // @[ToAXI4.scala:113:36]
wire sourceStall_232; // @[ToAXI4.scala:113:36]
wire sourceStall_233; // @[ToAXI4.scala:113:36]
wire sourceStall_234; // @[ToAXI4.scala:113:36]
wire sourceStall_235; // @[ToAXI4.scala:113:36]
wire sourceStall_236; // @[ToAXI4.scala:113:36]
wire sourceStall_237; // @[ToAXI4.scala:113:36]
wire sourceStall_238; // @[ToAXI4.scala:113:36]
wire sourceStall_239; // @[ToAXI4.scala:113:36]
wire sourceStall_240; // @[ToAXI4.scala:113:36]
wire sourceStall_241; // @[ToAXI4.scala:113:36]
wire sourceStall_242; // @[ToAXI4.scala:113:36]
wire sourceStall_243; // @[ToAXI4.scala:113:36]
wire _idStall_0_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_0 = idStall_0; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_1_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_1 = idStall_1; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_2_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_2 = idStall_2; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_3_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_3 = idStall_3; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_4_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_4 = idStall_4; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_5_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_5 = idStall_5; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_6_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_6 = idStall_6; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_7_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_7 = idStall_7; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_8_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_8 = idStall_8; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_9_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_9 = idStall_9; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_10_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_10 = idStall_10; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_11_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_11 = idStall_11; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_12_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_12 = idStall_12; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_13_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_13 = idStall_13; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_14_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_14 = idStall_14; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_15_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_15 = idStall_15; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_16_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_16 = idStall_16; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_17_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_17 = idStall_17; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_18_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_18 = idStall_18; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_19_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_19 = idStall_19; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_20_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_20 = idStall_20; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_21_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_21 = idStall_21; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_22_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_22 = idStall_22; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_23_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_23 = idStall_23; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_24_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_24 = idStall_24; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_25_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_25 = idStall_25; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_26_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_26 = idStall_26; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_27_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_27 = idStall_27; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_28_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_28 = idStall_28; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_29_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_29 = idStall_29; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_30_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_30 = idStall_30; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_31_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_31 = idStall_31; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_32_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_32 = idStall_32; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_33_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_33 = idStall_33; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_34_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_34 = idStall_34; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_35_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_35 = idStall_35; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_36_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_36 = idStall_36; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_37_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_37 = idStall_37; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_38_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_38 = idStall_38; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_39_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_39 = idStall_39; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_40_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_40 = idStall_40; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_41_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_41 = idStall_41; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_42_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_42 = idStall_42; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_43_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_43 = idStall_43; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_44_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_44 = idStall_44; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_45_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_45 = idStall_45; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_46_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_46 = idStall_46; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_47_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_47 = idStall_47; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_48_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_48 = idStall_48; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_49_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_49 = idStall_49; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_50_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_50 = idStall_50; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_51_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_51 = idStall_51; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_52_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_52 = idStall_52; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_53_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_53 = idStall_53; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_54_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_54 = idStall_54; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_55_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_55 = idStall_55; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_56_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_56 = idStall_56; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_57_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_57 = idStall_57; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_58_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_58 = idStall_58; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_59_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_59 = idStall_59; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_60_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_60 = idStall_60; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_61_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_61 = idStall_61; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_62_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_62 = idStall_62; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_63_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_63 = idStall_63; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_64_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_64 = idStall_64; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_65_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_65 = idStall_65; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_66_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_66 = idStall_66; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_67_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_67 = idStall_67; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_68_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_68 = idStall_68; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_69_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_69 = idStall_69; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_70_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_70 = idStall_70; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_71_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_71 = idStall_71; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_72_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_72 = idStall_72; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_73_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_73 = idStall_73; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_74_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_74 = idStall_74; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_75_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_75 = idStall_75; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_76_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_76 = idStall_76; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_77_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_77 = idStall_77; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_78_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_78 = idStall_78; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_79_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_79 = idStall_79; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_80_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_80 = idStall_80; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_81_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_81 = idStall_81; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_82_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_82 = idStall_82; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_83_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_83 = idStall_83; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_84_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_84 = idStall_84; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_85_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_85 = idStall_85; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_86_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_86 = idStall_86; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_87_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_87 = idStall_87; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_88_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_88 = idStall_88; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_89_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_89 = idStall_89; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_90_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_90 = idStall_90; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_91_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_91 = idStall_91; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_92_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_92 = idStall_92; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_93_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_93 = idStall_93; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_94_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_94 = idStall_94; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_95_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_95 = idStall_95; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_96_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_96 = idStall_96; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_97_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_97 = idStall_97; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_98_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_98 = idStall_98; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_99_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_99 = idStall_99; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_100_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_100 = idStall_100; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_101_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_101 = idStall_101; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_102_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_102 = idStall_102; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_103_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_103 = idStall_103; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_104_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_104 = idStall_104; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_105_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_105 = idStall_105; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_106_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_106 = idStall_106; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_107_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_107 = idStall_107; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_108_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_108 = idStall_108; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_109_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_109 = idStall_109; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_110_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_110 = idStall_110; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_111_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_111 = idStall_111; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_112_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_112 = idStall_112; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_113_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_113 = idStall_113; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_114_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_114 = idStall_114; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_115_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_115 = idStall_115; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_116_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_116 = idStall_116; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_117_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_117 = idStall_117; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_118_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_118 = idStall_118; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_119_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_119 = idStall_119; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_120_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_120 = idStall_120; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_121_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_121 = idStall_121; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_122_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_122 = idStall_122; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_123_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_123 = idStall_123; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_124_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_124 = idStall_124; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_125_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_125 = idStall_125; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_126_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_126 = idStall_126; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_127_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_127 = idStall_127; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_128_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_128 = idStall_128; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_129_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_129 = idStall_129; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_130_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_130 = idStall_130; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_131_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_131 = idStall_131; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_132_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_132 = idStall_132; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_133_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_133 = idStall_133; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_134_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_134 = idStall_134; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_135_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_135 = idStall_135; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_136_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_136 = idStall_136; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_137_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_137 = idStall_137; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_138_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_138 = idStall_138; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_139_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_139 = idStall_139; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_140_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_140 = idStall_140; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_141_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_141 = idStall_141; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_142_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_142 = idStall_142; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_143_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_143 = idStall_143; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_144_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_144 = idStall_144; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_145_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_145 = idStall_145; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_146_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_146 = idStall_146; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_147_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_147 = idStall_147; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_148_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_148 = idStall_148; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_149_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_149 = idStall_149; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_150_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_150 = idStall_150; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_151_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_151 = idStall_151; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_152_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_152 = idStall_152; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_153_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_153 = idStall_153; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_154_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_154 = idStall_154; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_155_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_155 = idStall_155; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_156_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_156 = idStall_156; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_157_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_157 = idStall_157; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_158_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_158 = idStall_158; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_159_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_159 = idStall_159; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_160_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_160 = idStall_160; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_161_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_161 = idStall_161; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_162_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_162 = idStall_162; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_163_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_163 = idStall_163; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_164_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_164 = idStall_164; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_165_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_165 = idStall_165; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_166_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_166 = idStall_166; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_167_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_167 = idStall_167; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_168_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_168 = idStall_168; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_169_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_169 = idStall_169; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_170_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_170 = idStall_170; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_171_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_171 = idStall_171; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_172_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_172 = idStall_172; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_173_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_173 = idStall_173; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_174_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_174 = idStall_174; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_175_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_175 = idStall_175; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_176_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_176 = idStall_176; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_177_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_177 = idStall_177; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_178_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_178 = idStall_178; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_179_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_179 = idStall_179; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_180_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_180 = idStall_180; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_181_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_181 = idStall_181; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_182_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_182 = idStall_182; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_183_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_183 = idStall_183; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_184_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_184 = idStall_184; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_185_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_185 = idStall_185; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_186_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_186 = idStall_186; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_187_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_187 = idStall_187; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_188_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_188 = idStall_188; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_189_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_189 = idStall_189; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_190_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_190 = idStall_190; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_191_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_191 = idStall_191; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_192_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_192 = idStall_192; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_193_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_193 = idStall_193; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_194_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_194 = idStall_194; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_195_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_195 = idStall_195; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_196_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_196 = idStall_196; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_197_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_197 = idStall_197; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_198_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_198 = idStall_198; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_199_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_199 = idStall_199; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_200_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_200 = idStall_200; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_201_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_201 = idStall_201; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_202_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_202 = idStall_202; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_203_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_203 = idStall_203; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_204_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_204 = idStall_204; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_205_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_205 = idStall_205; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_206_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_206 = idStall_206; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_207_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_207 = idStall_207; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_208_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_208 = idStall_208; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_209_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_209 = idStall_209; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_210_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_210 = idStall_210; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_211_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_211 = idStall_211; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_212_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_212 = idStall_212; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_213_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_213 = idStall_213; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_214_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_214 = idStall_214; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_215_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_215 = idStall_215; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_216_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_216 = idStall_216; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_217_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_217 = idStall_217; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_218_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_218 = idStall_218; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_219_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_219 = idStall_219; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_220_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_220 = idStall_220; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_221_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_221 = idStall_221; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_222_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_222 = idStall_222; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_223_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_223 = idStall_223; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_224_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_224 = idStall_224; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_225_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_225 = idStall_225; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_226_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_226 = idStall_226; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_227_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_227 = idStall_227; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_228_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_228 = idStall_228; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_229_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_229 = idStall_229; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_230_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_230 = idStall_230; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_231_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_231 = idStall_231; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_232_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_232 = idStall_232; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_233_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_233 = idStall_233; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_234_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_234 = idStall_234; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_235_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_235 = idStall_235; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_236_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_236 = idStall_236; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_237_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_237 = idStall_237; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_238_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_238 = idStall_238; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_239_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_239 = idStall_239; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_240_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_240 = idStall_240; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_241_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_241 = idStall_241; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_242_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_242 = idStall_242; // @[ToAXI4.scala:113:36, :115:32]
wire _idStall_243_T_3; // @[ToAXI4.scala:286:34]
assign sourceStall_243 = idStall_243; // @[ToAXI4.scala:113:36, :115:32]
wire _a_isPut_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire a_isPut = ~_a_isPut_opdata_T; // @[Edges.scala:92:{28,37}]
wire out_arw_bits_wen = a_isPut; // @[ToAXI4.scala:153:25]
wire _T_1 = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35]
wire [12:0] _r_beats1_decode_T = 13'h3F << nodeIn_a_bits_size; // @[package.scala:243:71]
wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] r_counter; // @[Edges.scala:229:27]
wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire out_w_bits_last = a_last; // @[ToAXI4.scala:154:23]
wire r_3 = a_last & _T_1; // @[Decoupled.scala:51:35]
wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _r_counter_T = a_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _out_arw_valid_T_5; // @[ToAXI4.scala:207:45]
wire [7:0] a_sel_shiftAmount = out_arw_bits_id; // @[OneHot.scala:64:49]
wire [7:0] _out_arw_bits_len_T_3; // @[ToAXI4.scala:174:84]
wire [2:0] _out_arw_bits_size_T_1; // @[ToAXI4.scala:175:23]
wire [3:0] out_arw_bits_echo_tl_state_size; // @[ToAXI4.scala:153:25]
wire [7:0] out_arw_bits_len; // @[ToAXI4.scala:153:25]
wire [2:0] out_arw_bits_size; // @[ToAXI4.scala:153:25]
wire out_arw_ready; // @[ToAXI4.scala:153:25]
wire out_arw_valid; // @[ToAXI4.scala:153:25]
wire _out_w_valid_T_4; // @[ToAXI4.scala:209:54]
wire out_w_ready; // @[ToAXI4.scala:154:23]
wire out_w_valid; // @[ToAXI4.scala:154:23]
assign nodeOut_w_valid = nodeOut_w_irr_valid; // @[Decoupled.scala:401:19]
assign nodeOut_w_bits_data = nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19]
assign nodeOut_w_bits_strb = nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19]
assign nodeOut_w_bits_last = nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19]
wire _queue_arw_ready_T; // @[ToAXI4.scala:163:29]
assign nodeOut_aw_bits_id = queue_arw_bits_id; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_id = queue_arw_bits_id; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_addr = queue_arw_bits_addr; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_addr = queue_arw_bits_addr; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_len = queue_arw_bits_len; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_len = queue_arw_bits_len; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_size = queue_arw_bits_size; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_size = queue_arw_bits_size; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_burst = queue_arw_bits_burst; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_burst = queue_arw_bits_burst; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_lock = queue_arw_bits_lock; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_lock = queue_arw_bits_lock; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_cache = queue_arw_bits_cache; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_cache = queue_arw_bits_cache; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_prot = queue_arw_bits_prot; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_prot = queue_arw_bits_prot; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_qos = queue_arw_bits_qos; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_qos = queue_arw_bits_qos; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_echo_tl_state_size = queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_echo_tl_state_size = queue_arw_bits_echo_tl_state_size; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_echo_tl_state_source = queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_echo_tl_state_source = queue_arw_bits_echo_tl_state_source; // @[Decoupled.scala:401:19]
wire queue_arw_bits_wen; // @[Decoupled.scala:401:19]
wire queue_arw_ready; // @[Decoupled.scala:401:19]
wire queue_arw_valid; // @[Decoupled.scala:401:19]
wire _nodeOut_ar_valid_T = ~queue_arw_bits_wen; // @[Decoupled.scala:401:19]
assign _nodeOut_ar_valid_T_1 = queue_arw_valid & _nodeOut_ar_valid_T; // @[Decoupled.scala:401:19]
assign nodeOut_ar_valid = _nodeOut_ar_valid_T_1; // @[ToAXI4.scala:161:39]
assign _nodeOut_aw_valid_T = queue_arw_valid & queue_arw_bits_wen; // @[Decoupled.scala:401:19]
assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[ToAXI4.scala:162:39]
assign _queue_arw_ready_T = queue_arw_bits_wen ? nodeOut_aw_ready : nodeOut_ar_ready; // @[Decoupled.scala:401:19]
assign queue_arw_ready = _queue_arw_ready_T; // @[Decoupled.scala:401:19]
reg doneAW; // @[ToAXI4.scala:167:30]
wire _doneAW_T = ~a_last; // @[ToAXI4.scala:168:36]
assign out_arw_bits_id = _GEN[nodeIn_a_bits_source]; // @[ToAXI4.scala:153:25, :172:17]
wire [17:0] _out_arw_bits_len_T = 18'h7FF << nodeIn_a_bits_size; // @[package.scala:243:71]
wire [10:0] _out_arw_bits_len_T_1 = _out_arw_bits_len_T[10:0]; // @[package.scala:243:{71,76}]
wire [10:0] _out_arw_bits_len_T_2 = ~_out_arw_bits_len_T_1; // @[package.scala:243:{46,76}]
assign _out_arw_bits_len_T_3 = _out_arw_bits_len_T_2[10:3]; // @[package.scala:243:46]
assign out_arw_bits_len = _out_arw_bits_len_T_3; // @[ToAXI4.scala:153:25, :174:84]
wire _out_arw_bits_size_T = nodeIn_a_bits_size > 3'h2; // @[ToAXI4.scala:175:31]
assign _out_arw_bits_size_T_1 = _out_arw_bits_size_T ? 3'h3 : nodeIn_a_bits_size; // @[ToAXI4.scala:175:{23,31}]
assign out_arw_bits_size = _out_arw_bits_size_T_1; // @[ToAXI4.scala:153:25, :175:23]
assign out_arw_bits_echo_tl_state_size = {1'h0, nodeIn_a_bits_size}; // @[ToAXI4.scala:153:25, :189:22]
wire [255:0] _GEN_0 =
{{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_0},
{sourceStall_243},
{sourceStall_242},
{sourceStall_241},
{sourceStall_240},
{sourceStall_239},
{sourceStall_238},
{sourceStall_237},
{sourceStall_236},
{sourceStall_235},
{sourceStall_234},
{sourceStall_233},
{sourceStall_232},
{sourceStall_231},
{sourceStall_230},
{sourceStall_229},
{sourceStall_228},
{sourceStall_227},
{sourceStall_226},
{sourceStall_225},
{sourceStall_224},
{sourceStall_223},
{sourceStall_222},
{sourceStall_221},
{sourceStall_220},
{sourceStall_219},
{sourceStall_218},
{sourceStall_217},
{sourceStall_216},
{sourceStall_215},
{sourceStall_214},
{sourceStall_213},
{sourceStall_212},
{sourceStall_211},
{sourceStall_210},
{sourceStall_209},
{sourceStall_208},
{sourceStall_207},
{sourceStall_206},
{sourceStall_205},
{sourceStall_204},
{sourceStall_203},
{sourceStall_202},
{sourceStall_201},
{sourceStall_200},
{sourceStall_199},
{sourceStall_198},
{sourceStall_197},
{sourceStall_196},
{sourceStall_195},
{sourceStall_194},
{sourceStall_193},
{sourceStall_192},
{sourceStall_191},
{sourceStall_190},
{sourceStall_189},
{sourceStall_188},
{sourceStall_187},
{sourceStall_186},
{sourceStall_185},
{sourceStall_184},
{sourceStall_183},
{sourceStall_182},
{sourceStall_181},
{sourceStall_180},
{sourceStall_179},
{sourceStall_178},
{sourceStall_177},
{sourceStall_176},
{sourceStall_175},
{sourceStall_174},
{sourceStall_173},
{sourceStall_172},
{sourceStall_171},
{sourceStall_170},
{sourceStall_169},
{sourceStall_168},
{sourceStall_167},
{sourceStall_166},
{sourceStall_165},
{sourceStall_164},
{sourceStall_163},
{sourceStall_162},
{sourceStall_161},
{sourceStall_160},
{sourceStall_159},
{sourceStall_158},
{sourceStall_157},
{sourceStall_156},
{sourceStall_155},
{sourceStall_154},
{sourceStall_153},
{sourceStall_152},
{sourceStall_151},
{sourceStall_150},
{sourceStall_149},
{sourceStall_148},
{sourceStall_147},
{sourceStall_146},
{sourceStall_145},
{sourceStall_144},
{sourceStall_143},
{sourceStall_142},
{sourceStall_141},
{sourceStall_140},
{sourceStall_139},
{sourceStall_138},
{sourceStall_137},
{sourceStall_136},
{sourceStall_135},
{sourceStall_134},
{sourceStall_133},
{sourceStall_132},
{sourceStall_131},
{sourceStall_130},
{sourceStall_129},
{sourceStall_128},
{sourceStall_127},
{sourceStall_126},
{sourceStall_125},
{sourceStall_124},
{sourceStall_123},
{sourceStall_122},
{sourceStall_121},
{sourceStall_120},
{sourceStall_119},
{sourceStall_118},
{sourceStall_117},
{sourceStall_116},
{sourceStall_115},
{sourceStall_114},
{sourceStall_113},
{sourceStall_112},
{sourceStall_111},
{sourceStall_110},
{sourceStall_109},
{sourceStall_108},
{sourceStall_107},
{sourceStall_106},
{sourceStall_105},
{sourceStall_104},
{sourceStall_103},
{sourceStall_102},
{sourceStall_101},
{sourceStall_100},
{sourceStall_99},
{sourceStall_98},
{sourceStall_97},
{sourceStall_96},
{sourceStall_95},
{sourceStall_94},
{sourceStall_93},
{sourceStall_92},
{sourceStall_91},
{sourceStall_90},
{sourceStall_89},
{sourceStall_88},
{sourceStall_87},
{sourceStall_86},
{sourceStall_85},
{sourceStall_84},
{sourceStall_83},
{sourceStall_82},
{sourceStall_81},
{sourceStall_80},
{sourceStall_79},
{sourceStall_78},
{sourceStall_77},
{sourceStall_76},
{sourceStall_75},
{sourceStall_74},
{sourceStall_73},
{sourceStall_72},
{sourceStall_71},
{sourceStall_70},
{sourceStall_69},
{sourceStall_68},
{sourceStall_67},
{sourceStall_66},
{sourceStall_65},
{sourceStall_64},
{sourceStall_63},
{sourceStall_62},
{sourceStall_61},
{sourceStall_60},
{sourceStall_59},
{sourceStall_58},
{sourceStall_57},
{sourceStall_56},
{sourceStall_55},
{sourceStall_54},
{sourceStall_53},
{sourceStall_52},
{sourceStall_51},
{sourceStall_50},
{sourceStall_49},
{sourceStall_48},
{sourceStall_47},
{sourceStall_46},
{sourceStall_45},
{sourceStall_44},
{sourceStall_43},
{sourceStall_42},
{sourceStall_41},
{sourceStall_40},
{sourceStall_39},
{sourceStall_38},
{sourceStall_37},
{sourceStall_36},
{sourceStall_35},
{sourceStall_34},
{sourceStall_33},
{sourceStall_32},
{sourceStall_31},
{sourceStall_30},
{sourceStall_29},
{sourceStall_28},
{sourceStall_27},
{sourceStall_26},
{sourceStall_25},
{sourceStall_24},
{sourceStall_23},
{sourceStall_22},
{sourceStall_21},
{sourceStall_20},
{sourceStall_19},
{sourceStall_18},
{sourceStall_17},
{sourceStall_16},
{sourceStall_15},
{sourceStall_14},
{sourceStall_13},
{sourceStall_12},
{sourceStall_11},
{sourceStall_10},
{sourceStall_9},
{sourceStall_8},
{sourceStall_7},
{sourceStall_6},
{sourceStall_5},
{sourceStall_4},
{sourceStall_3},
{sourceStall_2},
{sourceStall_1},
{sourceStall_0}}; // @[ToAXI4.scala:113:36, :205:49]
wire stall = _GEN_0[nodeIn_a_bits_source] & a_first; // @[ToAXI4.scala:205:49]
wire _nodeIn_a_ready_T = ~stall; // @[ToAXI4.scala:205:49, :206:21]
wire _GEN_1 = doneAW | out_arw_ready; // @[ToAXI4.scala:153:25, :167:30, :206:52]
wire _nodeIn_a_ready_T_1; // @[ToAXI4.scala:206:52]
assign _nodeIn_a_ready_T_1 = _GEN_1; // @[ToAXI4.scala:206:52]
wire _out_w_valid_T_3; // @[ToAXI4.scala:209:65]
assign _out_w_valid_T_3 = _GEN_1; // @[ToAXI4.scala:206:52, :209:65]
wire _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T_1 & out_w_ready; // @[ToAXI4.scala:154:23, :206:{52,70}]
wire _nodeIn_a_ready_T_3 = a_isPut ? _nodeIn_a_ready_T_2 : out_arw_ready; // @[ToAXI4.scala:153:25, :206:{34,70}]
assign _nodeIn_a_ready_T_4 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_3; // @[ToAXI4.scala:206:{21,28,34}]
assign nodeIn_a_ready = _nodeIn_a_ready_T_4; // @[ToAXI4.scala:206:28]
wire _out_arw_valid_T = ~stall; // @[ToAXI4.scala:205:49, :206:21, :207:24]
wire _out_arw_valid_T_1 = _out_arw_valid_T & nodeIn_a_valid; // @[ToAXI4.scala:207:{24,31}]
wire _out_arw_valid_T_2 = ~doneAW; // @[ToAXI4.scala:167:30, :207:61]
wire _out_arw_valid_T_3 = _out_arw_valid_T_2 & out_w_ready; // @[ToAXI4.scala:154:23, :207:{61,69}]
wire _out_arw_valid_T_4 = ~a_isPut | _out_arw_valid_T_3; // @[ToAXI4.scala:207:{51,69}]
assign _out_arw_valid_T_5 = _out_arw_valid_T_1 & _out_arw_valid_T_4; // @[ToAXI4.scala:207:{31,45,51}]
assign out_arw_valid = _out_arw_valid_T_5; // @[ToAXI4.scala:153:25, :207:45]
wire _out_w_valid_T = ~stall; // @[ToAXI4.scala:205:49, :206:21, :209:22]
wire _out_w_valid_T_1 = _out_w_valid_T & nodeIn_a_valid; // @[ToAXI4.scala:209:{22,29}]
wire _out_w_valid_T_2 = _out_w_valid_T_1 & a_isPut; // @[ToAXI4.scala:209:{29,43}]
assign _out_w_valid_T_4 = _out_w_valid_T_2 & _out_w_valid_T_3; // @[ToAXI4.scala:209:{43,54,65}]
assign out_w_valid = _out_w_valid_T_4; // @[ToAXI4.scala:154:23, :209:54]
reg r_holds_d; // @[ToAXI4.scala:216:30]
wire _r_holds_d_T = ~nodeOut_r_bits_last; // @[ToAXI4.scala:217:40]
reg [2:0] b_delay; // @[ToAXI4.scala:219:24]
wire [3:0] _b_delay_T = {1'h0, b_delay} + 4'h1; // @[ToAXI4.scala:219:24, :221:28]
wire [2:0] _b_delay_T_1 = _b_delay_T[2:0]; // @[ToAXI4.scala:221:28]
wire _r_wins_T = b_delay != 3'h7; // @[ToAXI4.scala:219:24, :225:44]
wire _r_wins_T_1 = nodeOut_r_valid & _r_wins_T; // @[ToAXI4.scala:225:{33,44}]
wire r_wins = _r_wins_T_1 | r_holds_d; // @[ToAXI4.scala:216:30, :225:{33,53}]
assign _nodeOut_r_ready_T = nodeIn_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33]
assign nodeOut_r_ready = _nodeOut_r_ready_T; // @[ToAXI4.scala:227:33]
wire _nodeOut_b_ready_T = ~r_wins; // @[ToAXI4.scala:225:53, :228:36]
assign _nodeOut_b_ready_T_1 = nodeIn_d_ready & _nodeOut_b_ready_T; // @[ToAXI4.scala:228:{33,36}]
assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[ToAXI4.scala:228:33]
assign _nodeIn_d_valid_T = r_wins ? nodeOut_r_valid : nodeOut_b_valid; // @[ToAXI4.scala:225:53, :229:24]
assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[ToAXI4.scala:229:24]
reg r_first; // @[ToAXI4.scala:234:28]
wire _r_denied_T = &nodeOut_r_bits_resp; // @[ToAXI4.scala:236:39]
reg r_denied_r; // @[package.scala:88:63]
wire r_denied = r_first ? _r_denied_T : r_denied_r; // @[package.scala:88:{42,63}]
wire r_d_denied = r_denied; // @[package.scala:88:42]
wire r_corrupt = |nodeOut_r_bits_resp; // @[ToAXI4.scala:237:39]
wire b_denied = |nodeOut_b_bits_resp; // @[ToAXI4.scala:238:39]
wire b_d_denied = b_denied; // @[ToAXI4.scala:238:39]
wire _r_d_T = r_corrupt | r_denied; // @[package.scala:88:42]
wire r_d_corrupt = _r_d_T; // @[ToAXI4.scala:240:96]
wire [2:0] r_d_size; // @[Edges.scala:810:17]
assign r_d_size = nodeOut_r_bits_echo_tl_state_size[2:0]; // @[Edges.scala:810:17, :813:15]
wire [2:0] b_d_size; // @[Edges.scala:792:17]
assign b_d_size = nodeOut_b_bits_echo_tl_state_size[2:0]; // @[Edges.scala:792:17, :795:15]
assign _nodeIn_d_bits_T_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:225:53, :255:23]
assign _nodeIn_d_bits_T_size = r_wins ? r_d_size : b_d_size; // @[ToAXI4.scala:225:53, :255:23]
assign _nodeIn_d_bits_T_source = r_wins ? r_d_source : b_d_source; // @[ToAXI4.scala:225:53, :255:23]
assign _nodeIn_d_bits_T_denied = r_wins ? r_d_denied : b_d_denied; // @[ToAXI4.scala:225:53, :255:23]
assign _nodeIn_d_bits_T_corrupt = r_wins & r_d_corrupt; // @[ToAXI4.scala:225:53, :255:23]
assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[ToAXI4.scala:255:23]
assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[ToAXI4.scala:255:23]
assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[ToAXI4.scala:255:23]
assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[ToAXI4.scala:255:23]
assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[ToAXI4.scala:255:23]
wire [255:0] _a_sel_T = 256'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [243:0] _a_sel_T_1 = _a_sel_T[243:0]; // @[OneHot.scala:65:{12,27}]
wire a_sel_0 = _a_sel_T_1[0]; // @[OneHot.scala:65:27]
wire a_sel_1 = _a_sel_T_1[1]; // @[OneHot.scala:65:27]
wire a_sel_2 = _a_sel_T_1[2]; // @[OneHot.scala:65:27]
wire a_sel_3 = _a_sel_T_1[3]; // @[OneHot.scala:65:27]
wire a_sel_4 = _a_sel_T_1[4]; // @[OneHot.scala:65:27]
wire a_sel_5 = _a_sel_T_1[5]; // @[OneHot.scala:65:27]
wire a_sel_6 = _a_sel_T_1[6]; // @[OneHot.scala:65:27]
wire a_sel_7 = _a_sel_T_1[7]; // @[OneHot.scala:65:27]
wire a_sel_8 = _a_sel_T_1[8]; // @[OneHot.scala:65:27]
wire a_sel_9 = _a_sel_T_1[9]; // @[OneHot.scala:65:27]
wire a_sel_10 = _a_sel_T_1[10]; // @[OneHot.scala:65:27]
wire a_sel_11 = _a_sel_T_1[11]; // @[OneHot.scala:65:27]
wire a_sel_12 = _a_sel_T_1[12]; // @[OneHot.scala:65:27]
wire a_sel_13 = _a_sel_T_1[13]; // @[OneHot.scala:65:27]
wire a_sel_14 = _a_sel_T_1[14]; // @[OneHot.scala:65:27]
wire a_sel_15 = _a_sel_T_1[15]; // @[OneHot.scala:65:27]
wire a_sel_16 = _a_sel_T_1[16]; // @[OneHot.scala:65:27]
wire a_sel_17 = _a_sel_T_1[17]; // @[OneHot.scala:65:27]
wire a_sel_18 = _a_sel_T_1[18]; // @[OneHot.scala:65:27]
wire a_sel_19 = _a_sel_T_1[19]; // @[OneHot.scala:65:27]
wire a_sel_20 = _a_sel_T_1[20]; // @[OneHot.scala:65:27]
wire a_sel_21 = _a_sel_T_1[21]; // @[OneHot.scala:65:27]
wire a_sel_22 = _a_sel_T_1[22]; // @[OneHot.scala:65:27]
wire a_sel_23 = _a_sel_T_1[23]; // @[OneHot.scala:65:27]
wire a_sel_24 = _a_sel_T_1[24]; // @[OneHot.scala:65:27]
wire a_sel_25 = _a_sel_T_1[25]; // @[OneHot.scala:65:27]
wire a_sel_26 = _a_sel_T_1[26]; // @[OneHot.scala:65:27]
wire a_sel_27 = _a_sel_T_1[27]; // @[OneHot.scala:65:27]
wire a_sel_28 = _a_sel_T_1[28]; // @[OneHot.scala:65:27]
wire a_sel_29 = _a_sel_T_1[29]; // @[OneHot.scala:65:27]
wire a_sel_30 = _a_sel_T_1[30]; // @[OneHot.scala:65:27]
wire a_sel_31 = _a_sel_T_1[31]; // @[OneHot.scala:65:27]
wire a_sel_32 = _a_sel_T_1[32]; // @[OneHot.scala:65:27]
wire a_sel_33 = _a_sel_T_1[33]; // @[OneHot.scala:65:27]
wire a_sel_34 = _a_sel_T_1[34]; // @[OneHot.scala:65:27]
wire a_sel_35 = _a_sel_T_1[35]; // @[OneHot.scala:65:27]
wire a_sel_36 = _a_sel_T_1[36]; // @[OneHot.scala:65:27]
wire a_sel_37 = _a_sel_T_1[37]; // @[OneHot.scala:65:27]
wire a_sel_38 = _a_sel_T_1[38]; // @[OneHot.scala:65:27]
wire a_sel_39 = _a_sel_T_1[39]; // @[OneHot.scala:65:27]
wire a_sel_40 = _a_sel_T_1[40]; // @[OneHot.scala:65:27]
wire a_sel_41 = _a_sel_T_1[41]; // @[OneHot.scala:65:27]
wire a_sel_42 = _a_sel_T_1[42]; // @[OneHot.scala:65:27]
wire a_sel_43 = _a_sel_T_1[43]; // @[OneHot.scala:65:27]
wire a_sel_44 = _a_sel_T_1[44]; // @[OneHot.scala:65:27]
wire a_sel_45 = _a_sel_T_1[45]; // @[OneHot.scala:65:27]
wire a_sel_46 = _a_sel_T_1[46]; // @[OneHot.scala:65:27]
wire a_sel_47 = _a_sel_T_1[47]; // @[OneHot.scala:65:27]
wire a_sel_48 = _a_sel_T_1[48]; // @[OneHot.scala:65:27]
wire a_sel_49 = _a_sel_T_1[49]; // @[OneHot.scala:65:27]
wire a_sel_50 = _a_sel_T_1[50]; // @[OneHot.scala:65:27]
wire a_sel_51 = _a_sel_T_1[51]; // @[OneHot.scala:65:27]
wire a_sel_52 = _a_sel_T_1[52]; // @[OneHot.scala:65:27]
wire a_sel_53 = _a_sel_T_1[53]; // @[OneHot.scala:65:27]
wire a_sel_54 = _a_sel_T_1[54]; // @[OneHot.scala:65:27]
wire a_sel_55 = _a_sel_T_1[55]; // @[OneHot.scala:65:27]
wire a_sel_56 = _a_sel_T_1[56]; // @[OneHot.scala:65:27]
wire a_sel_57 = _a_sel_T_1[57]; // @[OneHot.scala:65:27]
wire a_sel_58 = _a_sel_T_1[58]; // @[OneHot.scala:65:27]
wire a_sel_59 = _a_sel_T_1[59]; // @[OneHot.scala:65:27]
wire a_sel_60 = _a_sel_T_1[60]; // @[OneHot.scala:65:27]
wire a_sel_61 = _a_sel_T_1[61]; // @[OneHot.scala:65:27]
wire a_sel_62 = _a_sel_T_1[62]; // @[OneHot.scala:65:27]
wire a_sel_63 = _a_sel_T_1[63]; // @[OneHot.scala:65:27]
wire a_sel_64 = _a_sel_T_1[64]; // @[OneHot.scala:65:27]
wire a_sel_65 = _a_sel_T_1[65]; // @[OneHot.scala:65:27]
wire a_sel_66 = _a_sel_T_1[66]; // @[OneHot.scala:65:27]
wire a_sel_67 = _a_sel_T_1[67]; // @[OneHot.scala:65:27]
wire a_sel_68 = _a_sel_T_1[68]; // @[OneHot.scala:65:27]
wire a_sel_69 = _a_sel_T_1[69]; // @[OneHot.scala:65:27]
wire a_sel_70 = _a_sel_T_1[70]; // @[OneHot.scala:65:27]
wire a_sel_71 = _a_sel_T_1[71]; // @[OneHot.scala:65:27]
wire a_sel_72 = _a_sel_T_1[72]; // @[OneHot.scala:65:27]
wire a_sel_73 = _a_sel_T_1[73]; // @[OneHot.scala:65:27]
wire a_sel_74 = _a_sel_T_1[74]; // @[OneHot.scala:65:27]
wire a_sel_75 = _a_sel_T_1[75]; // @[OneHot.scala:65:27]
wire a_sel_76 = _a_sel_T_1[76]; // @[OneHot.scala:65:27]
wire a_sel_77 = _a_sel_T_1[77]; // @[OneHot.scala:65:27]
wire a_sel_78 = _a_sel_T_1[78]; // @[OneHot.scala:65:27]
wire a_sel_79 = _a_sel_T_1[79]; // @[OneHot.scala:65:27]
wire a_sel_80 = _a_sel_T_1[80]; // @[OneHot.scala:65:27]
wire a_sel_81 = _a_sel_T_1[81]; // @[OneHot.scala:65:27]
wire a_sel_82 = _a_sel_T_1[82]; // @[OneHot.scala:65:27]
wire a_sel_83 = _a_sel_T_1[83]; // @[OneHot.scala:65:27]
wire a_sel_84 = _a_sel_T_1[84]; // @[OneHot.scala:65:27]
wire a_sel_85 = _a_sel_T_1[85]; // @[OneHot.scala:65:27]
wire a_sel_86 = _a_sel_T_1[86]; // @[OneHot.scala:65:27]
wire a_sel_87 = _a_sel_T_1[87]; // @[OneHot.scala:65:27]
wire a_sel_88 = _a_sel_T_1[88]; // @[OneHot.scala:65:27]
wire a_sel_89 = _a_sel_T_1[89]; // @[OneHot.scala:65:27]
wire a_sel_90 = _a_sel_T_1[90]; // @[OneHot.scala:65:27]
wire a_sel_91 = _a_sel_T_1[91]; // @[OneHot.scala:65:27]
wire a_sel_92 = _a_sel_T_1[92]; // @[OneHot.scala:65:27]
wire a_sel_93 = _a_sel_T_1[93]; // @[OneHot.scala:65:27]
wire a_sel_94 = _a_sel_T_1[94]; // @[OneHot.scala:65:27]
wire a_sel_95 = _a_sel_T_1[95]; // @[OneHot.scala:65:27]
wire a_sel_96 = _a_sel_T_1[96]; // @[OneHot.scala:65:27]
wire a_sel_97 = _a_sel_T_1[97]; // @[OneHot.scala:65:27]
wire a_sel_98 = _a_sel_T_1[98]; // @[OneHot.scala:65:27]
wire a_sel_99 = _a_sel_T_1[99]; // @[OneHot.scala:65:27]
wire a_sel_100 = _a_sel_T_1[100]; // @[OneHot.scala:65:27]
wire a_sel_101 = _a_sel_T_1[101]; // @[OneHot.scala:65:27]
wire a_sel_102 = _a_sel_T_1[102]; // @[OneHot.scala:65:27]
wire a_sel_103 = _a_sel_T_1[103]; // @[OneHot.scala:65:27]
wire a_sel_104 = _a_sel_T_1[104]; // @[OneHot.scala:65:27]
wire a_sel_105 = _a_sel_T_1[105]; // @[OneHot.scala:65:27]
wire a_sel_106 = _a_sel_T_1[106]; // @[OneHot.scala:65:27]
wire a_sel_107 = _a_sel_T_1[107]; // @[OneHot.scala:65:27]
wire a_sel_108 = _a_sel_T_1[108]; // @[OneHot.scala:65:27]
wire a_sel_109 = _a_sel_T_1[109]; // @[OneHot.scala:65:27]
wire a_sel_110 = _a_sel_T_1[110]; // @[OneHot.scala:65:27]
wire a_sel_111 = _a_sel_T_1[111]; // @[OneHot.scala:65:27]
wire a_sel_112 = _a_sel_T_1[112]; // @[OneHot.scala:65:27]
wire a_sel_113 = _a_sel_T_1[113]; // @[OneHot.scala:65:27]
wire a_sel_114 = _a_sel_T_1[114]; // @[OneHot.scala:65:27]
wire a_sel_115 = _a_sel_T_1[115]; // @[OneHot.scala:65:27]
wire a_sel_116 = _a_sel_T_1[116]; // @[OneHot.scala:65:27]
wire a_sel_117 = _a_sel_T_1[117]; // @[OneHot.scala:65:27]
wire a_sel_118 = _a_sel_T_1[118]; // @[OneHot.scala:65:27]
wire a_sel_119 = _a_sel_T_1[119]; // @[OneHot.scala:65:27]
wire a_sel_120 = _a_sel_T_1[120]; // @[OneHot.scala:65:27]
wire a_sel_121 = _a_sel_T_1[121]; // @[OneHot.scala:65:27]
wire a_sel_122 = _a_sel_T_1[122]; // @[OneHot.scala:65:27]
wire a_sel_123 = _a_sel_T_1[123]; // @[OneHot.scala:65:27]
wire a_sel_124 = _a_sel_T_1[124]; // @[OneHot.scala:65:27]
wire a_sel_125 = _a_sel_T_1[125]; // @[OneHot.scala:65:27]
wire a_sel_126 = _a_sel_T_1[126]; // @[OneHot.scala:65:27]
wire a_sel_127 = _a_sel_T_1[127]; // @[OneHot.scala:65:27]
wire a_sel_128 = _a_sel_T_1[128]; // @[OneHot.scala:65:27]
wire a_sel_129 = _a_sel_T_1[129]; // @[OneHot.scala:65:27]
wire a_sel_130 = _a_sel_T_1[130]; // @[OneHot.scala:65:27]
wire a_sel_131 = _a_sel_T_1[131]; // @[OneHot.scala:65:27]
wire a_sel_132 = _a_sel_T_1[132]; // @[OneHot.scala:65:27]
wire a_sel_133 = _a_sel_T_1[133]; // @[OneHot.scala:65:27]
wire a_sel_134 = _a_sel_T_1[134]; // @[OneHot.scala:65:27]
wire a_sel_135 = _a_sel_T_1[135]; // @[OneHot.scala:65:27]
wire a_sel_136 = _a_sel_T_1[136]; // @[OneHot.scala:65:27]
wire a_sel_137 = _a_sel_T_1[137]; // @[OneHot.scala:65:27]
wire a_sel_138 = _a_sel_T_1[138]; // @[OneHot.scala:65:27]
wire a_sel_139 = _a_sel_T_1[139]; // @[OneHot.scala:65:27]
wire a_sel_140 = _a_sel_T_1[140]; // @[OneHot.scala:65:27]
wire a_sel_141 = _a_sel_T_1[141]; // @[OneHot.scala:65:27]
wire a_sel_142 = _a_sel_T_1[142]; // @[OneHot.scala:65:27]
wire a_sel_143 = _a_sel_T_1[143]; // @[OneHot.scala:65:27]
wire a_sel_144 = _a_sel_T_1[144]; // @[OneHot.scala:65:27]
wire a_sel_145 = _a_sel_T_1[145]; // @[OneHot.scala:65:27]
wire a_sel_146 = _a_sel_T_1[146]; // @[OneHot.scala:65:27]
wire a_sel_147 = _a_sel_T_1[147]; // @[OneHot.scala:65:27]
wire a_sel_148 = _a_sel_T_1[148]; // @[OneHot.scala:65:27]
wire a_sel_149 = _a_sel_T_1[149]; // @[OneHot.scala:65:27]
wire a_sel_150 = _a_sel_T_1[150]; // @[OneHot.scala:65:27]
wire a_sel_151 = _a_sel_T_1[151]; // @[OneHot.scala:65:27]
wire a_sel_152 = _a_sel_T_1[152]; // @[OneHot.scala:65:27]
wire a_sel_153 = _a_sel_T_1[153]; // @[OneHot.scala:65:27]
wire a_sel_154 = _a_sel_T_1[154]; // @[OneHot.scala:65:27]
wire a_sel_155 = _a_sel_T_1[155]; // @[OneHot.scala:65:27]
wire a_sel_156 = _a_sel_T_1[156]; // @[OneHot.scala:65:27]
wire a_sel_157 = _a_sel_T_1[157]; // @[OneHot.scala:65:27]
wire a_sel_158 = _a_sel_T_1[158]; // @[OneHot.scala:65:27]
wire a_sel_159 = _a_sel_T_1[159]; // @[OneHot.scala:65:27]
wire a_sel_160 = _a_sel_T_1[160]; // @[OneHot.scala:65:27]
wire a_sel_161 = _a_sel_T_1[161]; // @[OneHot.scala:65:27]
wire a_sel_162 = _a_sel_T_1[162]; // @[OneHot.scala:65:27]
wire a_sel_163 = _a_sel_T_1[163]; // @[OneHot.scala:65:27]
wire a_sel_164 = _a_sel_T_1[164]; // @[OneHot.scala:65:27]
wire a_sel_165 = _a_sel_T_1[165]; // @[OneHot.scala:65:27]
wire a_sel_166 = _a_sel_T_1[166]; // @[OneHot.scala:65:27]
wire a_sel_167 = _a_sel_T_1[167]; // @[OneHot.scala:65:27]
wire a_sel_168 = _a_sel_T_1[168]; // @[OneHot.scala:65:27]
wire a_sel_169 = _a_sel_T_1[169]; // @[OneHot.scala:65:27]
wire a_sel_170 = _a_sel_T_1[170]; // @[OneHot.scala:65:27]
wire a_sel_171 = _a_sel_T_1[171]; // @[OneHot.scala:65:27]
wire a_sel_172 = _a_sel_T_1[172]; // @[OneHot.scala:65:27]
wire a_sel_173 = _a_sel_T_1[173]; // @[OneHot.scala:65:27]
wire a_sel_174 = _a_sel_T_1[174]; // @[OneHot.scala:65:27]
wire a_sel_175 = _a_sel_T_1[175]; // @[OneHot.scala:65:27]
wire a_sel_176 = _a_sel_T_1[176]; // @[OneHot.scala:65:27]
wire a_sel_177 = _a_sel_T_1[177]; // @[OneHot.scala:65:27]
wire a_sel_178 = _a_sel_T_1[178]; // @[OneHot.scala:65:27]
wire a_sel_179 = _a_sel_T_1[179]; // @[OneHot.scala:65:27]
wire a_sel_180 = _a_sel_T_1[180]; // @[OneHot.scala:65:27]
wire a_sel_181 = _a_sel_T_1[181]; // @[OneHot.scala:65:27]
wire a_sel_182 = _a_sel_T_1[182]; // @[OneHot.scala:65:27]
wire a_sel_183 = _a_sel_T_1[183]; // @[OneHot.scala:65:27]
wire a_sel_184 = _a_sel_T_1[184]; // @[OneHot.scala:65:27]
wire a_sel_185 = _a_sel_T_1[185]; // @[OneHot.scala:65:27]
wire a_sel_186 = _a_sel_T_1[186]; // @[OneHot.scala:65:27]
wire a_sel_187 = _a_sel_T_1[187]; // @[OneHot.scala:65:27]
wire a_sel_188 = _a_sel_T_1[188]; // @[OneHot.scala:65:27]
wire a_sel_189 = _a_sel_T_1[189]; // @[OneHot.scala:65:27]
wire a_sel_190 = _a_sel_T_1[190]; // @[OneHot.scala:65:27]
wire a_sel_191 = _a_sel_T_1[191]; // @[OneHot.scala:65:27]
wire a_sel_192 = _a_sel_T_1[192]; // @[OneHot.scala:65:27]
wire a_sel_193 = _a_sel_T_1[193]; // @[OneHot.scala:65:27]
wire a_sel_194 = _a_sel_T_1[194]; // @[OneHot.scala:65:27]
wire a_sel_195 = _a_sel_T_1[195]; // @[OneHot.scala:65:27]
wire a_sel_196 = _a_sel_T_1[196]; // @[OneHot.scala:65:27]
wire a_sel_197 = _a_sel_T_1[197]; // @[OneHot.scala:65:27]
wire a_sel_198 = _a_sel_T_1[198]; // @[OneHot.scala:65:27]
wire a_sel_199 = _a_sel_T_1[199]; // @[OneHot.scala:65:27]
wire a_sel_200 = _a_sel_T_1[200]; // @[OneHot.scala:65:27]
wire a_sel_201 = _a_sel_T_1[201]; // @[OneHot.scala:65:27]
wire a_sel_202 = _a_sel_T_1[202]; // @[OneHot.scala:65:27]
wire a_sel_203 = _a_sel_T_1[203]; // @[OneHot.scala:65:27]
wire a_sel_204 = _a_sel_T_1[204]; // @[OneHot.scala:65:27]
wire a_sel_205 = _a_sel_T_1[205]; // @[OneHot.scala:65:27]
wire a_sel_206 = _a_sel_T_1[206]; // @[OneHot.scala:65:27]
wire a_sel_207 = _a_sel_T_1[207]; // @[OneHot.scala:65:27]
wire a_sel_208 = _a_sel_T_1[208]; // @[OneHot.scala:65:27]
wire a_sel_209 = _a_sel_T_1[209]; // @[OneHot.scala:65:27]
wire a_sel_210 = _a_sel_T_1[210]; // @[OneHot.scala:65:27]
wire a_sel_211 = _a_sel_T_1[211]; // @[OneHot.scala:65:27]
wire a_sel_212 = _a_sel_T_1[212]; // @[OneHot.scala:65:27]
wire a_sel_213 = _a_sel_T_1[213]; // @[OneHot.scala:65:27]
wire a_sel_214 = _a_sel_T_1[214]; // @[OneHot.scala:65:27]
wire a_sel_215 = _a_sel_T_1[215]; // @[OneHot.scala:65:27]
wire a_sel_216 = _a_sel_T_1[216]; // @[OneHot.scala:65:27]
wire a_sel_217 = _a_sel_T_1[217]; // @[OneHot.scala:65:27]
wire a_sel_218 = _a_sel_T_1[218]; // @[OneHot.scala:65:27]
wire a_sel_219 = _a_sel_T_1[219]; // @[OneHot.scala:65:27]
wire a_sel_220 = _a_sel_T_1[220]; // @[OneHot.scala:65:27]
wire a_sel_221 = _a_sel_T_1[221]; // @[OneHot.scala:65:27]
wire a_sel_222 = _a_sel_T_1[222]; // @[OneHot.scala:65:27]
wire a_sel_223 = _a_sel_T_1[223]; // @[OneHot.scala:65:27]
wire a_sel_224 = _a_sel_T_1[224]; // @[OneHot.scala:65:27]
wire a_sel_225 = _a_sel_T_1[225]; // @[OneHot.scala:65:27]
wire a_sel_226 = _a_sel_T_1[226]; // @[OneHot.scala:65:27]
wire a_sel_227 = _a_sel_T_1[227]; // @[OneHot.scala:65:27]
wire a_sel_228 = _a_sel_T_1[228]; // @[OneHot.scala:65:27]
wire a_sel_229 = _a_sel_T_1[229]; // @[OneHot.scala:65:27]
wire a_sel_230 = _a_sel_T_1[230]; // @[OneHot.scala:65:27]
wire a_sel_231 = _a_sel_T_1[231]; // @[OneHot.scala:65:27]
wire a_sel_232 = _a_sel_T_1[232]; // @[OneHot.scala:65:27]
wire a_sel_233 = _a_sel_T_1[233]; // @[OneHot.scala:65:27]
wire a_sel_234 = _a_sel_T_1[234]; // @[OneHot.scala:65:27]
wire a_sel_235 = _a_sel_T_1[235]; // @[OneHot.scala:65:27]
wire a_sel_236 = _a_sel_T_1[236]; // @[OneHot.scala:65:27]
wire a_sel_237 = _a_sel_T_1[237]; // @[OneHot.scala:65:27]
wire a_sel_238 = _a_sel_T_1[238]; // @[OneHot.scala:65:27]
wire a_sel_239 = _a_sel_T_1[239]; // @[OneHot.scala:65:27]
wire a_sel_240 = _a_sel_T_1[240]; // @[OneHot.scala:65:27]
wire a_sel_241 = _a_sel_T_1[241]; // @[OneHot.scala:65:27]
wire a_sel_242 = _a_sel_T_1[242]; // @[OneHot.scala:65:27]
wire a_sel_243 = _a_sel_T_1[243]; // @[OneHot.scala:65:27]
wire [7:0] _d_sel_T = r_wins ? nodeOut_r_bits_id : nodeOut_b_bits_id; // @[ToAXI4.scala:225:53, :261:31]
wire [7:0] d_sel_shiftAmount = _d_sel_T; // @[OneHot.scala:64:49]
wire [255:0] _d_sel_T_1 = 256'h1 << d_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [243:0] _d_sel_T_2 = _d_sel_T_1[243:0]; // @[OneHot.scala:65:{12,27}]
wire d_sel_0 = _d_sel_T_2[0]; // @[OneHot.scala:65:27]
wire d_sel_1 = _d_sel_T_2[1]; // @[OneHot.scala:65:27]
wire d_sel_2 = _d_sel_T_2[2]; // @[OneHot.scala:65:27]
wire d_sel_3 = _d_sel_T_2[3]; // @[OneHot.scala:65:27]
wire d_sel_4 = _d_sel_T_2[4]; // @[OneHot.scala:65:27]
wire d_sel_5 = _d_sel_T_2[5]; // @[OneHot.scala:65:27]
wire d_sel_6 = _d_sel_T_2[6]; // @[OneHot.scala:65:27]
wire d_sel_7 = _d_sel_T_2[7]; // @[OneHot.scala:65:27]
wire d_sel_8 = _d_sel_T_2[8]; // @[OneHot.scala:65:27]
wire d_sel_9 = _d_sel_T_2[9]; // @[OneHot.scala:65:27]
wire d_sel_10 = _d_sel_T_2[10]; // @[OneHot.scala:65:27]
wire d_sel_11 = _d_sel_T_2[11]; // @[OneHot.scala:65:27]
wire d_sel_12 = _d_sel_T_2[12]; // @[OneHot.scala:65:27]
wire d_sel_13 = _d_sel_T_2[13]; // @[OneHot.scala:65:27]
wire d_sel_14 = _d_sel_T_2[14]; // @[OneHot.scala:65:27]
wire d_sel_15 = _d_sel_T_2[15]; // @[OneHot.scala:65:27]
wire d_sel_16 = _d_sel_T_2[16]; // @[OneHot.scala:65:27]
wire d_sel_17 = _d_sel_T_2[17]; // @[OneHot.scala:65:27]
wire d_sel_18 = _d_sel_T_2[18]; // @[OneHot.scala:65:27]
wire d_sel_19 = _d_sel_T_2[19]; // @[OneHot.scala:65:27]
wire d_sel_20 = _d_sel_T_2[20]; // @[OneHot.scala:65:27]
wire d_sel_21 = _d_sel_T_2[21]; // @[OneHot.scala:65:27]
wire d_sel_22 = _d_sel_T_2[22]; // @[OneHot.scala:65:27]
wire d_sel_23 = _d_sel_T_2[23]; // @[OneHot.scala:65:27]
wire d_sel_24 = _d_sel_T_2[24]; // @[OneHot.scala:65:27]
wire d_sel_25 = _d_sel_T_2[25]; // @[OneHot.scala:65:27]
wire d_sel_26 = _d_sel_T_2[26]; // @[OneHot.scala:65:27]
wire d_sel_27 = _d_sel_T_2[27]; // @[OneHot.scala:65:27]
wire d_sel_28 = _d_sel_T_2[28]; // @[OneHot.scala:65:27]
wire d_sel_29 = _d_sel_T_2[29]; // @[OneHot.scala:65:27]
wire d_sel_30 = _d_sel_T_2[30]; // @[OneHot.scala:65:27]
wire d_sel_31 = _d_sel_T_2[31]; // @[OneHot.scala:65:27]
wire d_sel_32 = _d_sel_T_2[32]; // @[OneHot.scala:65:27]
wire d_sel_33 = _d_sel_T_2[33]; // @[OneHot.scala:65:27]
wire d_sel_34 = _d_sel_T_2[34]; // @[OneHot.scala:65:27]
wire d_sel_35 = _d_sel_T_2[35]; // @[OneHot.scala:65:27]
wire d_sel_36 = _d_sel_T_2[36]; // @[OneHot.scala:65:27]
wire d_sel_37 = _d_sel_T_2[37]; // @[OneHot.scala:65:27]
wire d_sel_38 = _d_sel_T_2[38]; // @[OneHot.scala:65:27]
wire d_sel_39 = _d_sel_T_2[39]; // @[OneHot.scala:65:27]
wire d_sel_40 = _d_sel_T_2[40]; // @[OneHot.scala:65:27]
wire d_sel_41 = _d_sel_T_2[41]; // @[OneHot.scala:65:27]
wire d_sel_42 = _d_sel_T_2[42]; // @[OneHot.scala:65:27]
wire d_sel_43 = _d_sel_T_2[43]; // @[OneHot.scala:65:27]
wire d_sel_44 = _d_sel_T_2[44]; // @[OneHot.scala:65:27]
wire d_sel_45 = _d_sel_T_2[45]; // @[OneHot.scala:65:27]
wire d_sel_46 = _d_sel_T_2[46]; // @[OneHot.scala:65:27]
wire d_sel_47 = _d_sel_T_2[47]; // @[OneHot.scala:65:27]
wire d_sel_48 = _d_sel_T_2[48]; // @[OneHot.scala:65:27]
wire d_sel_49 = _d_sel_T_2[49]; // @[OneHot.scala:65:27]
wire d_sel_50 = _d_sel_T_2[50]; // @[OneHot.scala:65:27]
wire d_sel_51 = _d_sel_T_2[51]; // @[OneHot.scala:65:27]
wire d_sel_52 = _d_sel_T_2[52]; // @[OneHot.scala:65:27]
wire d_sel_53 = _d_sel_T_2[53]; // @[OneHot.scala:65:27]
wire d_sel_54 = _d_sel_T_2[54]; // @[OneHot.scala:65:27]
wire d_sel_55 = _d_sel_T_2[55]; // @[OneHot.scala:65:27]
wire d_sel_56 = _d_sel_T_2[56]; // @[OneHot.scala:65:27]
wire d_sel_57 = _d_sel_T_2[57]; // @[OneHot.scala:65:27]
wire d_sel_58 = _d_sel_T_2[58]; // @[OneHot.scala:65:27]
wire d_sel_59 = _d_sel_T_2[59]; // @[OneHot.scala:65:27]
wire d_sel_60 = _d_sel_T_2[60]; // @[OneHot.scala:65:27]
wire d_sel_61 = _d_sel_T_2[61]; // @[OneHot.scala:65:27]
wire d_sel_62 = _d_sel_T_2[62]; // @[OneHot.scala:65:27]
wire d_sel_63 = _d_sel_T_2[63]; // @[OneHot.scala:65:27]
wire d_sel_64 = _d_sel_T_2[64]; // @[OneHot.scala:65:27]
wire d_sel_65 = _d_sel_T_2[65]; // @[OneHot.scala:65:27]
wire d_sel_66 = _d_sel_T_2[66]; // @[OneHot.scala:65:27]
wire d_sel_67 = _d_sel_T_2[67]; // @[OneHot.scala:65:27]
wire d_sel_68 = _d_sel_T_2[68]; // @[OneHot.scala:65:27]
wire d_sel_69 = _d_sel_T_2[69]; // @[OneHot.scala:65:27]
wire d_sel_70 = _d_sel_T_2[70]; // @[OneHot.scala:65:27]
wire d_sel_71 = _d_sel_T_2[71]; // @[OneHot.scala:65:27]
wire d_sel_72 = _d_sel_T_2[72]; // @[OneHot.scala:65:27]
wire d_sel_73 = _d_sel_T_2[73]; // @[OneHot.scala:65:27]
wire d_sel_74 = _d_sel_T_2[74]; // @[OneHot.scala:65:27]
wire d_sel_75 = _d_sel_T_2[75]; // @[OneHot.scala:65:27]
wire d_sel_76 = _d_sel_T_2[76]; // @[OneHot.scala:65:27]
wire d_sel_77 = _d_sel_T_2[77]; // @[OneHot.scala:65:27]
wire d_sel_78 = _d_sel_T_2[78]; // @[OneHot.scala:65:27]
wire d_sel_79 = _d_sel_T_2[79]; // @[OneHot.scala:65:27]
wire d_sel_80 = _d_sel_T_2[80]; // @[OneHot.scala:65:27]
wire d_sel_81 = _d_sel_T_2[81]; // @[OneHot.scala:65:27]
wire d_sel_82 = _d_sel_T_2[82]; // @[OneHot.scala:65:27]
wire d_sel_83 = _d_sel_T_2[83]; // @[OneHot.scala:65:27]
wire d_sel_84 = _d_sel_T_2[84]; // @[OneHot.scala:65:27]
wire d_sel_85 = _d_sel_T_2[85]; // @[OneHot.scala:65:27]
wire d_sel_86 = _d_sel_T_2[86]; // @[OneHot.scala:65:27]
wire d_sel_87 = _d_sel_T_2[87]; // @[OneHot.scala:65:27]
wire d_sel_88 = _d_sel_T_2[88]; // @[OneHot.scala:65:27]
wire d_sel_89 = _d_sel_T_2[89]; // @[OneHot.scala:65:27]
wire d_sel_90 = _d_sel_T_2[90]; // @[OneHot.scala:65:27]
wire d_sel_91 = _d_sel_T_2[91]; // @[OneHot.scala:65:27]
wire d_sel_92 = _d_sel_T_2[92]; // @[OneHot.scala:65:27]
wire d_sel_93 = _d_sel_T_2[93]; // @[OneHot.scala:65:27]
wire d_sel_94 = _d_sel_T_2[94]; // @[OneHot.scala:65:27]
wire d_sel_95 = _d_sel_T_2[95]; // @[OneHot.scala:65:27]
wire d_sel_96 = _d_sel_T_2[96]; // @[OneHot.scala:65:27]
wire d_sel_97 = _d_sel_T_2[97]; // @[OneHot.scala:65:27]
wire d_sel_98 = _d_sel_T_2[98]; // @[OneHot.scala:65:27]
wire d_sel_99 = _d_sel_T_2[99]; // @[OneHot.scala:65:27]
wire d_sel_100 = _d_sel_T_2[100]; // @[OneHot.scala:65:27]
wire d_sel_101 = _d_sel_T_2[101]; // @[OneHot.scala:65:27]
wire d_sel_102 = _d_sel_T_2[102]; // @[OneHot.scala:65:27]
wire d_sel_103 = _d_sel_T_2[103]; // @[OneHot.scala:65:27]
wire d_sel_104 = _d_sel_T_2[104]; // @[OneHot.scala:65:27]
wire d_sel_105 = _d_sel_T_2[105]; // @[OneHot.scala:65:27]
wire d_sel_106 = _d_sel_T_2[106]; // @[OneHot.scala:65:27]
wire d_sel_107 = _d_sel_T_2[107]; // @[OneHot.scala:65:27]
wire d_sel_108 = _d_sel_T_2[108]; // @[OneHot.scala:65:27]
wire d_sel_109 = _d_sel_T_2[109]; // @[OneHot.scala:65:27]
wire d_sel_110 = _d_sel_T_2[110]; // @[OneHot.scala:65:27]
wire d_sel_111 = _d_sel_T_2[111]; // @[OneHot.scala:65:27]
wire d_sel_112 = _d_sel_T_2[112]; // @[OneHot.scala:65:27]
wire d_sel_113 = _d_sel_T_2[113]; // @[OneHot.scala:65:27]
wire d_sel_114 = _d_sel_T_2[114]; // @[OneHot.scala:65:27]
wire d_sel_115 = _d_sel_T_2[115]; // @[OneHot.scala:65:27]
wire d_sel_116 = _d_sel_T_2[116]; // @[OneHot.scala:65:27]
wire d_sel_117 = _d_sel_T_2[117]; // @[OneHot.scala:65:27]
wire d_sel_118 = _d_sel_T_2[118]; // @[OneHot.scala:65:27]
wire d_sel_119 = _d_sel_T_2[119]; // @[OneHot.scala:65:27]
wire d_sel_120 = _d_sel_T_2[120]; // @[OneHot.scala:65:27]
wire d_sel_121 = _d_sel_T_2[121]; // @[OneHot.scala:65:27]
wire d_sel_122 = _d_sel_T_2[122]; // @[OneHot.scala:65:27]
wire d_sel_123 = _d_sel_T_2[123]; // @[OneHot.scala:65:27]
wire d_sel_124 = _d_sel_T_2[124]; // @[OneHot.scala:65:27]
wire d_sel_125 = _d_sel_T_2[125]; // @[OneHot.scala:65:27]
wire d_sel_126 = _d_sel_T_2[126]; // @[OneHot.scala:65:27]
wire d_sel_127 = _d_sel_T_2[127]; // @[OneHot.scala:65:27]
wire d_sel_128 = _d_sel_T_2[128]; // @[OneHot.scala:65:27]
wire d_sel_129 = _d_sel_T_2[129]; // @[OneHot.scala:65:27]
wire d_sel_130 = _d_sel_T_2[130]; // @[OneHot.scala:65:27]
wire d_sel_131 = _d_sel_T_2[131]; // @[OneHot.scala:65:27]
wire d_sel_132 = _d_sel_T_2[132]; // @[OneHot.scala:65:27]
wire d_sel_133 = _d_sel_T_2[133]; // @[OneHot.scala:65:27]
wire d_sel_134 = _d_sel_T_2[134]; // @[OneHot.scala:65:27]
wire d_sel_135 = _d_sel_T_2[135]; // @[OneHot.scala:65:27]
wire d_sel_136 = _d_sel_T_2[136]; // @[OneHot.scala:65:27]
wire d_sel_137 = _d_sel_T_2[137]; // @[OneHot.scala:65:27]
wire d_sel_138 = _d_sel_T_2[138]; // @[OneHot.scala:65:27]
wire d_sel_139 = _d_sel_T_2[139]; // @[OneHot.scala:65:27]
wire d_sel_140 = _d_sel_T_2[140]; // @[OneHot.scala:65:27]
wire d_sel_141 = _d_sel_T_2[141]; // @[OneHot.scala:65:27]
wire d_sel_142 = _d_sel_T_2[142]; // @[OneHot.scala:65:27]
wire d_sel_143 = _d_sel_T_2[143]; // @[OneHot.scala:65:27]
wire d_sel_144 = _d_sel_T_2[144]; // @[OneHot.scala:65:27]
wire d_sel_145 = _d_sel_T_2[145]; // @[OneHot.scala:65:27]
wire d_sel_146 = _d_sel_T_2[146]; // @[OneHot.scala:65:27]
wire d_sel_147 = _d_sel_T_2[147]; // @[OneHot.scala:65:27]
wire d_sel_148 = _d_sel_T_2[148]; // @[OneHot.scala:65:27]
wire d_sel_149 = _d_sel_T_2[149]; // @[OneHot.scala:65:27]
wire d_sel_150 = _d_sel_T_2[150]; // @[OneHot.scala:65:27]
wire d_sel_151 = _d_sel_T_2[151]; // @[OneHot.scala:65:27]
wire d_sel_152 = _d_sel_T_2[152]; // @[OneHot.scala:65:27]
wire d_sel_153 = _d_sel_T_2[153]; // @[OneHot.scala:65:27]
wire d_sel_154 = _d_sel_T_2[154]; // @[OneHot.scala:65:27]
wire d_sel_155 = _d_sel_T_2[155]; // @[OneHot.scala:65:27]
wire d_sel_156 = _d_sel_T_2[156]; // @[OneHot.scala:65:27]
wire d_sel_157 = _d_sel_T_2[157]; // @[OneHot.scala:65:27]
wire d_sel_158 = _d_sel_T_2[158]; // @[OneHot.scala:65:27]
wire d_sel_159 = _d_sel_T_2[159]; // @[OneHot.scala:65:27]
wire d_sel_160 = _d_sel_T_2[160]; // @[OneHot.scala:65:27]
wire d_sel_161 = _d_sel_T_2[161]; // @[OneHot.scala:65:27]
wire d_sel_162 = _d_sel_T_2[162]; // @[OneHot.scala:65:27]
wire d_sel_163 = _d_sel_T_2[163]; // @[OneHot.scala:65:27]
wire d_sel_164 = _d_sel_T_2[164]; // @[OneHot.scala:65:27]
wire d_sel_165 = _d_sel_T_2[165]; // @[OneHot.scala:65:27]
wire d_sel_166 = _d_sel_T_2[166]; // @[OneHot.scala:65:27]
wire d_sel_167 = _d_sel_T_2[167]; // @[OneHot.scala:65:27]
wire d_sel_168 = _d_sel_T_2[168]; // @[OneHot.scala:65:27]
wire d_sel_169 = _d_sel_T_2[169]; // @[OneHot.scala:65:27]
wire d_sel_170 = _d_sel_T_2[170]; // @[OneHot.scala:65:27]
wire d_sel_171 = _d_sel_T_2[171]; // @[OneHot.scala:65:27]
wire d_sel_172 = _d_sel_T_2[172]; // @[OneHot.scala:65:27]
wire d_sel_173 = _d_sel_T_2[173]; // @[OneHot.scala:65:27]
wire d_sel_174 = _d_sel_T_2[174]; // @[OneHot.scala:65:27]
wire d_sel_175 = _d_sel_T_2[175]; // @[OneHot.scala:65:27]
wire d_sel_176 = _d_sel_T_2[176]; // @[OneHot.scala:65:27]
wire d_sel_177 = _d_sel_T_2[177]; // @[OneHot.scala:65:27]
wire d_sel_178 = _d_sel_T_2[178]; // @[OneHot.scala:65:27]
wire d_sel_179 = _d_sel_T_2[179]; // @[OneHot.scala:65:27]
wire d_sel_180 = _d_sel_T_2[180]; // @[OneHot.scala:65:27]
wire d_sel_181 = _d_sel_T_2[181]; // @[OneHot.scala:65:27]
wire d_sel_182 = _d_sel_T_2[182]; // @[OneHot.scala:65:27]
wire d_sel_183 = _d_sel_T_2[183]; // @[OneHot.scala:65:27]
wire d_sel_184 = _d_sel_T_2[184]; // @[OneHot.scala:65:27]
wire d_sel_185 = _d_sel_T_2[185]; // @[OneHot.scala:65:27]
wire d_sel_186 = _d_sel_T_2[186]; // @[OneHot.scala:65:27]
wire d_sel_187 = _d_sel_T_2[187]; // @[OneHot.scala:65:27]
wire d_sel_188 = _d_sel_T_2[188]; // @[OneHot.scala:65:27]
wire d_sel_189 = _d_sel_T_2[189]; // @[OneHot.scala:65:27]
wire d_sel_190 = _d_sel_T_2[190]; // @[OneHot.scala:65:27]
wire d_sel_191 = _d_sel_T_2[191]; // @[OneHot.scala:65:27]
wire d_sel_192 = _d_sel_T_2[192]; // @[OneHot.scala:65:27]
wire d_sel_193 = _d_sel_T_2[193]; // @[OneHot.scala:65:27]
wire d_sel_194 = _d_sel_T_2[194]; // @[OneHot.scala:65:27]
wire d_sel_195 = _d_sel_T_2[195]; // @[OneHot.scala:65:27]
wire d_sel_196 = _d_sel_T_2[196]; // @[OneHot.scala:65:27]
wire d_sel_197 = _d_sel_T_2[197]; // @[OneHot.scala:65:27]
wire d_sel_198 = _d_sel_T_2[198]; // @[OneHot.scala:65:27]
wire d_sel_199 = _d_sel_T_2[199]; // @[OneHot.scala:65:27]
wire d_sel_200 = _d_sel_T_2[200]; // @[OneHot.scala:65:27]
wire d_sel_201 = _d_sel_T_2[201]; // @[OneHot.scala:65:27]
wire d_sel_202 = _d_sel_T_2[202]; // @[OneHot.scala:65:27]
wire d_sel_203 = _d_sel_T_2[203]; // @[OneHot.scala:65:27]
wire d_sel_204 = _d_sel_T_2[204]; // @[OneHot.scala:65:27]
wire d_sel_205 = _d_sel_T_2[205]; // @[OneHot.scala:65:27]
wire d_sel_206 = _d_sel_T_2[206]; // @[OneHot.scala:65:27]
wire d_sel_207 = _d_sel_T_2[207]; // @[OneHot.scala:65:27]
wire d_sel_208 = _d_sel_T_2[208]; // @[OneHot.scala:65:27]
wire d_sel_209 = _d_sel_T_2[209]; // @[OneHot.scala:65:27]
wire d_sel_210 = _d_sel_T_2[210]; // @[OneHot.scala:65:27]
wire d_sel_211 = _d_sel_T_2[211]; // @[OneHot.scala:65:27]
wire d_sel_212 = _d_sel_T_2[212]; // @[OneHot.scala:65:27]
wire d_sel_213 = _d_sel_T_2[213]; // @[OneHot.scala:65:27]
wire d_sel_214 = _d_sel_T_2[214]; // @[OneHot.scala:65:27]
wire d_sel_215 = _d_sel_T_2[215]; // @[OneHot.scala:65:27]
wire d_sel_216 = _d_sel_T_2[216]; // @[OneHot.scala:65:27]
wire d_sel_217 = _d_sel_T_2[217]; // @[OneHot.scala:65:27]
wire d_sel_218 = _d_sel_T_2[218]; // @[OneHot.scala:65:27]
wire d_sel_219 = _d_sel_T_2[219]; // @[OneHot.scala:65:27]
wire d_sel_220 = _d_sel_T_2[220]; // @[OneHot.scala:65:27]
wire d_sel_221 = _d_sel_T_2[221]; // @[OneHot.scala:65:27]
wire d_sel_222 = _d_sel_T_2[222]; // @[OneHot.scala:65:27]
wire d_sel_223 = _d_sel_T_2[223]; // @[OneHot.scala:65:27]
wire d_sel_224 = _d_sel_T_2[224]; // @[OneHot.scala:65:27]
wire d_sel_225 = _d_sel_T_2[225]; // @[OneHot.scala:65:27]
wire d_sel_226 = _d_sel_T_2[226]; // @[OneHot.scala:65:27]
wire d_sel_227 = _d_sel_T_2[227]; // @[OneHot.scala:65:27]
wire d_sel_228 = _d_sel_T_2[228]; // @[OneHot.scala:65:27]
wire d_sel_229 = _d_sel_T_2[229]; // @[OneHot.scala:65:27]
wire d_sel_230 = _d_sel_T_2[230]; // @[OneHot.scala:65:27]
wire d_sel_231 = _d_sel_T_2[231]; // @[OneHot.scala:65:27]
wire d_sel_232 = _d_sel_T_2[232]; // @[OneHot.scala:65:27]
wire d_sel_233 = _d_sel_T_2[233]; // @[OneHot.scala:65:27]
wire d_sel_234 = _d_sel_T_2[234]; // @[OneHot.scala:65:27]
wire d_sel_235 = _d_sel_T_2[235]; // @[OneHot.scala:65:27]
wire d_sel_236 = _d_sel_T_2[236]; // @[OneHot.scala:65:27]
wire d_sel_237 = _d_sel_T_2[237]; // @[OneHot.scala:65:27]
wire d_sel_238 = _d_sel_T_2[238]; // @[OneHot.scala:65:27]
wire d_sel_239 = _d_sel_T_2[239]; // @[OneHot.scala:65:27]
wire d_sel_240 = _d_sel_T_2[240]; // @[OneHot.scala:65:27]
wire d_sel_241 = _d_sel_T_2[241]; // @[OneHot.scala:65:27]
wire d_sel_242 = _d_sel_T_2[242]; // @[OneHot.scala:65:27]
wire d_sel_243 = _d_sel_T_2[243]; // @[OneHot.scala:65:27]
wire d_last = ~r_wins | nodeOut_r_bits_last; // @[ToAXI4.scala:225:53, :262:23]
reg count; // @[ToAXI4.scala:272:28]
wire _idStall_0_T_2 = count; // @[ToAXI4.scala:272:28, :286:44]
reg write; // @[ToAXI4.scala:273:24]
wire idle = ~count; // @[ToAXI4.scala:272:28, :274:26]
wire _GEN_2 = out_arw_ready & out_arw_valid; // @[Decoupled.scala:51:35]
wire _inc_T; // @[Decoupled.scala:51:35]
assign _inc_T = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_1; // @[Decoupled.scala:51:35]
assign _inc_T_1 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_2; // @[Decoupled.scala:51:35]
assign _inc_T_2 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_3; // @[Decoupled.scala:51:35]
assign _inc_T_3 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_4; // @[Decoupled.scala:51:35]
assign _inc_T_4 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_5; // @[Decoupled.scala:51:35]
assign _inc_T_5 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_6; // @[Decoupled.scala:51:35]
assign _inc_T_6 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_7; // @[Decoupled.scala:51:35]
assign _inc_T_7 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_8; // @[Decoupled.scala:51:35]
assign _inc_T_8 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_9; // @[Decoupled.scala:51:35]
assign _inc_T_9 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_10; // @[Decoupled.scala:51:35]
assign _inc_T_10 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_11; // @[Decoupled.scala:51:35]
assign _inc_T_11 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_12; // @[Decoupled.scala:51:35]
assign _inc_T_12 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_13; // @[Decoupled.scala:51:35]
assign _inc_T_13 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_14; // @[Decoupled.scala:51:35]
assign _inc_T_14 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_15; // @[Decoupled.scala:51:35]
assign _inc_T_15 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_16; // @[Decoupled.scala:51:35]
assign _inc_T_16 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_17; // @[Decoupled.scala:51:35]
assign _inc_T_17 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_18; // @[Decoupled.scala:51:35]
assign _inc_T_18 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_19; // @[Decoupled.scala:51:35]
assign _inc_T_19 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_20; // @[Decoupled.scala:51:35]
assign _inc_T_20 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_21; // @[Decoupled.scala:51:35]
assign _inc_T_21 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_22; // @[Decoupled.scala:51:35]
assign _inc_T_22 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_23; // @[Decoupled.scala:51:35]
assign _inc_T_23 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_24; // @[Decoupled.scala:51:35]
assign _inc_T_24 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_25; // @[Decoupled.scala:51:35]
assign _inc_T_25 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_26; // @[Decoupled.scala:51:35]
assign _inc_T_26 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_27; // @[Decoupled.scala:51:35]
assign _inc_T_27 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_28; // @[Decoupled.scala:51:35]
assign _inc_T_28 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_29; // @[Decoupled.scala:51:35]
assign _inc_T_29 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_30; // @[Decoupled.scala:51:35]
assign _inc_T_30 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_31; // @[Decoupled.scala:51:35]
assign _inc_T_31 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_32; // @[Decoupled.scala:51:35]
assign _inc_T_32 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_33; // @[Decoupled.scala:51:35]
assign _inc_T_33 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_34; // @[Decoupled.scala:51:35]
assign _inc_T_34 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_35; // @[Decoupled.scala:51:35]
assign _inc_T_35 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_36; // @[Decoupled.scala:51:35]
assign _inc_T_36 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_37; // @[Decoupled.scala:51:35]
assign _inc_T_37 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_38; // @[Decoupled.scala:51:35]
assign _inc_T_38 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_39; // @[Decoupled.scala:51:35]
assign _inc_T_39 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_40; // @[Decoupled.scala:51:35]
assign _inc_T_40 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_41; // @[Decoupled.scala:51:35]
assign _inc_T_41 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_42; // @[Decoupled.scala:51:35]
assign _inc_T_42 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_43; // @[Decoupled.scala:51:35]
assign _inc_T_43 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_44; // @[Decoupled.scala:51:35]
assign _inc_T_44 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_45; // @[Decoupled.scala:51:35]
assign _inc_T_45 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_46; // @[Decoupled.scala:51:35]
assign _inc_T_46 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_47; // @[Decoupled.scala:51:35]
assign _inc_T_47 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_48; // @[Decoupled.scala:51:35]
assign _inc_T_48 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_49; // @[Decoupled.scala:51:35]
assign _inc_T_49 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_50; // @[Decoupled.scala:51:35]
assign _inc_T_50 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_51; // @[Decoupled.scala:51:35]
assign _inc_T_51 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_52; // @[Decoupled.scala:51:35]
assign _inc_T_52 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_53; // @[Decoupled.scala:51:35]
assign _inc_T_53 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_54; // @[Decoupled.scala:51:35]
assign _inc_T_54 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_55; // @[Decoupled.scala:51:35]
assign _inc_T_55 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_56; // @[Decoupled.scala:51:35]
assign _inc_T_56 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_57; // @[Decoupled.scala:51:35]
assign _inc_T_57 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_58; // @[Decoupled.scala:51:35]
assign _inc_T_58 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_59; // @[Decoupled.scala:51:35]
assign _inc_T_59 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_60; // @[Decoupled.scala:51:35]
assign _inc_T_60 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_61; // @[Decoupled.scala:51:35]
assign _inc_T_61 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_62; // @[Decoupled.scala:51:35]
assign _inc_T_62 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_63; // @[Decoupled.scala:51:35]
assign _inc_T_63 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_64; // @[Decoupled.scala:51:35]
assign _inc_T_64 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_65; // @[Decoupled.scala:51:35]
assign _inc_T_65 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_66; // @[Decoupled.scala:51:35]
assign _inc_T_66 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_67; // @[Decoupled.scala:51:35]
assign _inc_T_67 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_68; // @[Decoupled.scala:51:35]
assign _inc_T_68 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_69; // @[Decoupled.scala:51:35]
assign _inc_T_69 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_70; // @[Decoupled.scala:51:35]
assign _inc_T_70 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_71; // @[Decoupled.scala:51:35]
assign _inc_T_71 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_72; // @[Decoupled.scala:51:35]
assign _inc_T_72 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_73; // @[Decoupled.scala:51:35]
assign _inc_T_73 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_74; // @[Decoupled.scala:51:35]
assign _inc_T_74 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_75; // @[Decoupled.scala:51:35]
assign _inc_T_75 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_76; // @[Decoupled.scala:51:35]
assign _inc_T_76 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_77; // @[Decoupled.scala:51:35]
assign _inc_T_77 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_78; // @[Decoupled.scala:51:35]
assign _inc_T_78 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_79; // @[Decoupled.scala:51:35]
assign _inc_T_79 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_80; // @[Decoupled.scala:51:35]
assign _inc_T_80 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_81; // @[Decoupled.scala:51:35]
assign _inc_T_81 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_82; // @[Decoupled.scala:51:35]
assign _inc_T_82 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_83; // @[Decoupled.scala:51:35]
assign _inc_T_83 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_84; // @[Decoupled.scala:51:35]
assign _inc_T_84 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_85; // @[Decoupled.scala:51:35]
assign _inc_T_85 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_86; // @[Decoupled.scala:51:35]
assign _inc_T_86 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_87; // @[Decoupled.scala:51:35]
assign _inc_T_87 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_88; // @[Decoupled.scala:51:35]
assign _inc_T_88 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_89; // @[Decoupled.scala:51:35]
assign _inc_T_89 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_90; // @[Decoupled.scala:51:35]
assign _inc_T_90 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_91; // @[Decoupled.scala:51:35]
assign _inc_T_91 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_92; // @[Decoupled.scala:51:35]
assign _inc_T_92 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_93; // @[Decoupled.scala:51:35]
assign _inc_T_93 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_94; // @[Decoupled.scala:51:35]
assign _inc_T_94 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_95; // @[Decoupled.scala:51:35]
assign _inc_T_95 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_96; // @[Decoupled.scala:51:35]
assign _inc_T_96 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_97; // @[Decoupled.scala:51:35]
assign _inc_T_97 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_98; // @[Decoupled.scala:51:35]
assign _inc_T_98 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_99; // @[Decoupled.scala:51:35]
assign _inc_T_99 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_100; // @[Decoupled.scala:51:35]
assign _inc_T_100 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_101; // @[Decoupled.scala:51:35]
assign _inc_T_101 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_102; // @[Decoupled.scala:51:35]
assign _inc_T_102 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_103; // @[Decoupled.scala:51:35]
assign _inc_T_103 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_104; // @[Decoupled.scala:51:35]
assign _inc_T_104 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_105; // @[Decoupled.scala:51:35]
assign _inc_T_105 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_106; // @[Decoupled.scala:51:35]
assign _inc_T_106 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_107; // @[Decoupled.scala:51:35]
assign _inc_T_107 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_108; // @[Decoupled.scala:51:35]
assign _inc_T_108 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_109; // @[Decoupled.scala:51:35]
assign _inc_T_109 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_110; // @[Decoupled.scala:51:35]
assign _inc_T_110 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_111; // @[Decoupled.scala:51:35]
assign _inc_T_111 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_112; // @[Decoupled.scala:51:35]
assign _inc_T_112 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_113; // @[Decoupled.scala:51:35]
assign _inc_T_113 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_114; // @[Decoupled.scala:51:35]
assign _inc_T_114 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_115; // @[Decoupled.scala:51:35]
assign _inc_T_115 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_116; // @[Decoupled.scala:51:35]
assign _inc_T_116 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_117; // @[Decoupled.scala:51:35]
assign _inc_T_117 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_118; // @[Decoupled.scala:51:35]
assign _inc_T_118 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_119; // @[Decoupled.scala:51:35]
assign _inc_T_119 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_120; // @[Decoupled.scala:51:35]
assign _inc_T_120 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_121; // @[Decoupled.scala:51:35]
assign _inc_T_121 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_122; // @[Decoupled.scala:51:35]
assign _inc_T_122 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_123; // @[Decoupled.scala:51:35]
assign _inc_T_123 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_124; // @[Decoupled.scala:51:35]
assign _inc_T_124 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_125; // @[Decoupled.scala:51:35]
assign _inc_T_125 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_126; // @[Decoupled.scala:51:35]
assign _inc_T_126 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_127; // @[Decoupled.scala:51:35]
assign _inc_T_127 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_128; // @[Decoupled.scala:51:35]
assign _inc_T_128 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_129; // @[Decoupled.scala:51:35]
assign _inc_T_129 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_130; // @[Decoupled.scala:51:35]
assign _inc_T_130 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_131; // @[Decoupled.scala:51:35]
assign _inc_T_131 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_132; // @[Decoupled.scala:51:35]
assign _inc_T_132 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_133; // @[Decoupled.scala:51:35]
assign _inc_T_133 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_134; // @[Decoupled.scala:51:35]
assign _inc_T_134 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_135; // @[Decoupled.scala:51:35]
assign _inc_T_135 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_136; // @[Decoupled.scala:51:35]
assign _inc_T_136 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_137; // @[Decoupled.scala:51:35]
assign _inc_T_137 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_138; // @[Decoupled.scala:51:35]
assign _inc_T_138 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_139; // @[Decoupled.scala:51:35]
assign _inc_T_139 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_140; // @[Decoupled.scala:51:35]
assign _inc_T_140 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_141; // @[Decoupled.scala:51:35]
assign _inc_T_141 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_142; // @[Decoupled.scala:51:35]
assign _inc_T_142 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_143; // @[Decoupled.scala:51:35]
assign _inc_T_143 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_144; // @[Decoupled.scala:51:35]
assign _inc_T_144 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_145; // @[Decoupled.scala:51:35]
assign _inc_T_145 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_146; // @[Decoupled.scala:51:35]
assign _inc_T_146 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_147; // @[Decoupled.scala:51:35]
assign _inc_T_147 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_148; // @[Decoupled.scala:51:35]
assign _inc_T_148 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_149; // @[Decoupled.scala:51:35]
assign _inc_T_149 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_150; // @[Decoupled.scala:51:35]
assign _inc_T_150 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_151; // @[Decoupled.scala:51:35]
assign _inc_T_151 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_152; // @[Decoupled.scala:51:35]
assign _inc_T_152 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_153; // @[Decoupled.scala:51:35]
assign _inc_T_153 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_154; // @[Decoupled.scala:51:35]
assign _inc_T_154 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_155; // @[Decoupled.scala:51:35]
assign _inc_T_155 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_156; // @[Decoupled.scala:51:35]
assign _inc_T_156 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_157; // @[Decoupled.scala:51:35]
assign _inc_T_157 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_158; // @[Decoupled.scala:51:35]
assign _inc_T_158 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_159; // @[Decoupled.scala:51:35]
assign _inc_T_159 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_160; // @[Decoupled.scala:51:35]
assign _inc_T_160 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_161; // @[Decoupled.scala:51:35]
assign _inc_T_161 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_162; // @[Decoupled.scala:51:35]
assign _inc_T_162 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_163; // @[Decoupled.scala:51:35]
assign _inc_T_163 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_164; // @[Decoupled.scala:51:35]
assign _inc_T_164 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_165; // @[Decoupled.scala:51:35]
assign _inc_T_165 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_166; // @[Decoupled.scala:51:35]
assign _inc_T_166 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_167; // @[Decoupled.scala:51:35]
assign _inc_T_167 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_168; // @[Decoupled.scala:51:35]
assign _inc_T_168 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_169; // @[Decoupled.scala:51:35]
assign _inc_T_169 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_170; // @[Decoupled.scala:51:35]
assign _inc_T_170 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_171; // @[Decoupled.scala:51:35]
assign _inc_T_171 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_172; // @[Decoupled.scala:51:35]
assign _inc_T_172 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_173; // @[Decoupled.scala:51:35]
assign _inc_T_173 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_174; // @[Decoupled.scala:51:35]
assign _inc_T_174 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_175; // @[Decoupled.scala:51:35]
assign _inc_T_175 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_176; // @[Decoupled.scala:51:35]
assign _inc_T_176 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_177; // @[Decoupled.scala:51:35]
assign _inc_T_177 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_178; // @[Decoupled.scala:51:35]
assign _inc_T_178 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_179; // @[Decoupled.scala:51:35]
assign _inc_T_179 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_180; // @[Decoupled.scala:51:35]
assign _inc_T_180 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_181; // @[Decoupled.scala:51:35]
assign _inc_T_181 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_182; // @[Decoupled.scala:51:35]
assign _inc_T_182 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_183; // @[Decoupled.scala:51:35]
assign _inc_T_183 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_184; // @[Decoupled.scala:51:35]
assign _inc_T_184 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_185; // @[Decoupled.scala:51:35]
assign _inc_T_185 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_186; // @[Decoupled.scala:51:35]
assign _inc_T_186 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_187; // @[Decoupled.scala:51:35]
assign _inc_T_187 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_188; // @[Decoupled.scala:51:35]
assign _inc_T_188 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_189; // @[Decoupled.scala:51:35]
assign _inc_T_189 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_190; // @[Decoupled.scala:51:35]
assign _inc_T_190 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_191; // @[Decoupled.scala:51:35]
assign _inc_T_191 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_192; // @[Decoupled.scala:51:35]
assign _inc_T_192 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_193; // @[Decoupled.scala:51:35]
assign _inc_T_193 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_194; // @[Decoupled.scala:51:35]
assign _inc_T_194 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_195; // @[Decoupled.scala:51:35]
assign _inc_T_195 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_196; // @[Decoupled.scala:51:35]
assign _inc_T_196 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_197; // @[Decoupled.scala:51:35]
assign _inc_T_197 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_198; // @[Decoupled.scala:51:35]
assign _inc_T_198 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_199; // @[Decoupled.scala:51:35]
assign _inc_T_199 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_200; // @[Decoupled.scala:51:35]
assign _inc_T_200 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_201; // @[Decoupled.scala:51:35]
assign _inc_T_201 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_202; // @[Decoupled.scala:51:35]
assign _inc_T_202 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_203; // @[Decoupled.scala:51:35]
assign _inc_T_203 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_204; // @[Decoupled.scala:51:35]
assign _inc_T_204 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_205; // @[Decoupled.scala:51:35]
assign _inc_T_205 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_206; // @[Decoupled.scala:51:35]
assign _inc_T_206 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_207; // @[Decoupled.scala:51:35]
assign _inc_T_207 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_208; // @[Decoupled.scala:51:35]
assign _inc_T_208 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_209; // @[Decoupled.scala:51:35]
assign _inc_T_209 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_210; // @[Decoupled.scala:51:35]
assign _inc_T_210 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_211; // @[Decoupled.scala:51:35]
assign _inc_T_211 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_212; // @[Decoupled.scala:51:35]
assign _inc_T_212 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_213; // @[Decoupled.scala:51:35]
assign _inc_T_213 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_214; // @[Decoupled.scala:51:35]
assign _inc_T_214 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_215; // @[Decoupled.scala:51:35]
assign _inc_T_215 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_216; // @[Decoupled.scala:51:35]
assign _inc_T_216 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_217; // @[Decoupled.scala:51:35]
assign _inc_T_217 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_218; // @[Decoupled.scala:51:35]
assign _inc_T_218 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_219; // @[Decoupled.scala:51:35]
assign _inc_T_219 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_220; // @[Decoupled.scala:51:35]
assign _inc_T_220 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_221; // @[Decoupled.scala:51:35]
assign _inc_T_221 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_222; // @[Decoupled.scala:51:35]
assign _inc_T_222 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_223; // @[Decoupled.scala:51:35]
assign _inc_T_223 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_224; // @[Decoupled.scala:51:35]
assign _inc_T_224 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_225; // @[Decoupled.scala:51:35]
assign _inc_T_225 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_226; // @[Decoupled.scala:51:35]
assign _inc_T_226 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_227; // @[Decoupled.scala:51:35]
assign _inc_T_227 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_228; // @[Decoupled.scala:51:35]
assign _inc_T_228 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_229; // @[Decoupled.scala:51:35]
assign _inc_T_229 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_230; // @[Decoupled.scala:51:35]
assign _inc_T_230 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_231; // @[Decoupled.scala:51:35]
assign _inc_T_231 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_232; // @[Decoupled.scala:51:35]
assign _inc_T_232 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_233; // @[Decoupled.scala:51:35]
assign _inc_T_233 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_234; // @[Decoupled.scala:51:35]
assign _inc_T_234 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_235; // @[Decoupled.scala:51:35]
assign _inc_T_235 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_236; // @[Decoupled.scala:51:35]
assign _inc_T_236 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_237; // @[Decoupled.scala:51:35]
assign _inc_T_237 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_238; // @[Decoupled.scala:51:35]
assign _inc_T_238 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_239; // @[Decoupled.scala:51:35]
assign _inc_T_239 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_240; // @[Decoupled.scala:51:35]
assign _inc_T_240 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_241; // @[Decoupled.scala:51:35]
assign _inc_T_241 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_242; // @[Decoupled.scala:51:35]
assign _inc_T_242 = _GEN_2; // @[Decoupled.scala:51:35]
wire _inc_T_243; // @[Decoupled.scala:51:35]
assign _inc_T_243 = _GEN_2; // @[Decoupled.scala:51:35]
wire inc = a_sel_0 & _inc_T; // @[Decoupled.scala:51:35]
wire _dec_T = d_sel_0 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire _GEN_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire _dec_T_1; // @[Decoupled.scala:51:35]
assign _dec_T_1 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_3; // @[Decoupled.scala:51:35]
assign _dec_T_3 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_5; // @[Decoupled.scala:51:35]
assign _dec_T_5 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_7; // @[Decoupled.scala:51:35]
assign _dec_T_7 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_9; // @[Decoupled.scala:51:35]
assign _dec_T_9 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_11; // @[Decoupled.scala:51:35]
assign _dec_T_11 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_13; // @[Decoupled.scala:51:35]
assign _dec_T_13 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_15; // @[Decoupled.scala:51:35]
assign _dec_T_15 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_17; // @[Decoupled.scala:51:35]
assign _dec_T_17 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_19; // @[Decoupled.scala:51:35]
assign _dec_T_19 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_21; // @[Decoupled.scala:51:35]
assign _dec_T_21 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_23; // @[Decoupled.scala:51:35]
assign _dec_T_23 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_25; // @[Decoupled.scala:51:35]
assign _dec_T_25 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_27; // @[Decoupled.scala:51:35]
assign _dec_T_27 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_29; // @[Decoupled.scala:51:35]
assign _dec_T_29 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_31; // @[Decoupled.scala:51:35]
assign _dec_T_31 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_33; // @[Decoupled.scala:51:35]
assign _dec_T_33 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_35; // @[Decoupled.scala:51:35]
assign _dec_T_35 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_37; // @[Decoupled.scala:51:35]
assign _dec_T_37 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_39; // @[Decoupled.scala:51:35]
assign _dec_T_39 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_41; // @[Decoupled.scala:51:35]
assign _dec_T_41 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_43; // @[Decoupled.scala:51:35]
assign _dec_T_43 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_45; // @[Decoupled.scala:51:35]
assign _dec_T_45 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_47; // @[Decoupled.scala:51:35]
assign _dec_T_47 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_49; // @[Decoupled.scala:51:35]
assign _dec_T_49 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_51; // @[Decoupled.scala:51:35]
assign _dec_T_51 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_53; // @[Decoupled.scala:51:35]
assign _dec_T_53 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_55; // @[Decoupled.scala:51:35]
assign _dec_T_55 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_57; // @[Decoupled.scala:51:35]
assign _dec_T_57 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_59; // @[Decoupled.scala:51:35]
assign _dec_T_59 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_61; // @[Decoupled.scala:51:35]
assign _dec_T_61 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_63; // @[Decoupled.scala:51:35]
assign _dec_T_63 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_65; // @[Decoupled.scala:51:35]
assign _dec_T_65 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_67; // @[Decoupled.scala:51:35]
assign _dec_T_67 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_69; // @[Decoupled.scala:51:35]
assign _dec_T_69 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_71; // @[Decoupled.scala:51:35]
assign _dec_T_71 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_73; // @[Decoupled.scala:51:35]
assign _dec_T_73 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_75; // @[Decoupled.scala:51:35]
assign _dec_T_75 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_77; // @[Decoupled.scala:51:35]
assign _dec_T_77 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_79; // @[Decoupled.scala:51:35]
assign _dec_T_79 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_81; // @[Decoupled.scala:51:35]
assign _dec_T_81 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_83; // @[Decoupled.scala:51:35]
assign _dec_T_83 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_85; // @[Decoupled.scala:51:35]
assign _dec_T_85 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_87; // @[Decoupled.scala:51:35]
assign _dec_T_87 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_89; // @[Decoupled.scala:51:35]
assign _dec_T_89 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_91; // @[Decoupled.scala:51:35]
assign _dec_T_91 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_93; // @[Decoupled.scala:51:35]
assign _dec_T_93 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_95; // @[Decoupled.scala:51:35]
assign _dec_T_95 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_97; // @[Decoupled.scala:51:35]
assign _dec_T_97 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_99; // @[Decoupled.scala:51:35]
assign _dec_T_99 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_101; // @[Decoupled.scala:51:35]
assign _dec_T_101 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_103; // @[Decoupled.scala:51:35]
assign _dec_T_103 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_105; // @[Decoupled.scala:51:35]
assign _dec_T_105 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_107; // @[Decoupled.scala:51:35]
assign _dec_T_107 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_109; // @[Decoupled.scala:51:35]
assign _dec_T_109 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_111; // @[Decoupled.scala:51:35]
assign _dec_T_111 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_113; // @[Decoupled.scala:51:35]
assign _dec_T_113 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_115; // @[Decoupled.scala:51:35]
assign _dec_T_115 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_117; // @[Decoupled.scala:51:35]
assign _dec_T_117 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_119; // @[Decoupled.scala:51:35]
assign _dec_T_119 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_121; // @[Decoupled.scala:51:35]
assign _dec_T_121 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_123; // @[Decoupled.scala:51:35]
assign _dec_T_123 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_125; // @[Decoupled.scala:51:35]
assign _dec_T_125 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_127; // @[Decoupled.scala:51:35]
assign _dec_T_127 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_129; // @[Decoupled.scala:51:35]
assign _dec_T_129 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_131; // @[Decoupled.scala:51:35]
assign _dec_T_131 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_133; // @[Decoupled.scala:51:35]
assign _dec_T_133 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_135; // @[Decoupled.scala:51:35]
assign _dec_T_135 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_137; // @[Decoupled.scala:51:35]
assign _dec_T_137 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_139; // @[Decoupled.scala:51:35]
assign _dec_T_139 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_141; // @[Decoupled.scala:51:35]
assign _dec_T_141 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_143; // @[Decoupled.scala:51:35]
assign _dec_T_143 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_145; // @[Decoupled.scala:51:35]
assign _dec_T_145 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_147; // @[Decoupled.scala:51:35]
assign _dec_T_147 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_149; // @[Decoupled.scala:51:35]
assign _dec_T_149 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_151; // @[Decoupled.scala:51:35]
assign _dec_T_151 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_153; // @[Decoupled.scala:51:35]
assign _dec_T_153 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_155; // @[Decoupled.scala:51:35]
assign _dec_T_155 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_157; // @[Decoupled.scala:51:35]
assign _dec_T_157 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_159; // @[Decoupled.scala:51:35]
assign _dec_T_159 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_161; // @[Decoupled.scala:51:35]
assign _dec_T_161 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_163; // @[Decoupled.scala:51:35]
assign _dec_T_163 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_165; // @[Decoupled.scala:51:35]
assign _dec_T_165 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_167; // @[Decoupled.scala:51:35]
assign _dec_T_167 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_169; // @[Decoupled.scala:51:35]
assign _dec_T_169 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_171; // @[Decoupled.scala:51:35]
assign _dec_T_171 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_173; // @[Decoupled.scala:51:35]
assign _dec_T_173 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_175; // @[Decoupled.scala:51:35]
assign _dec_T_175 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_177; // @[Decoupled.scala:51:35]
assign _dec_T_177 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_179; // @[Decoupled.scala:51:35]
assign _dec_T_179 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_181; // @[Decoupled.scala:51:35]
assign _dec_T_181 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_183; // @[Decoupled.scala:51:35]
assign _dec_T_183 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_185; // @[Decoupled.scala:51:35]
assign _dec_T_185 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_187; // @[Decoupled.scala:51:35]
assign _dec_T_187 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_189; // @[Decoupled.scala:51:35]
assign _dec_T_189 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_191; // @[Decoupled.scala:51:35]
assign _dec_T_191 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_193; // @[Decoupled.scala:51:35]
assign _dec_T_193 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_195; // @[Decoupled.scala:51:35]
assign _dec_T_195 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_197; // @[Decoupled.scala:51:35]
assign _dec_T_197 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_199; // @[Decoupled.scala:51:35]
assign _dec_T_199 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_201; // @[Decoupled.scala:51:35]
assign _dec_T_201 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_203; // @[Decoupled.scala:51:35]
assign _dec_T_203 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_205; // @[Decoupled.scala:51:35]
assign _dec_T_205 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_207; // @[Decoupled.scala:51:35]
assign _dec_T_207 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_209; // @[Decoupled.scala:51:35]
assign _dec_T_209 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_211; // @[Decoupled.scala:51:35]
assign _dec_T_211 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_213; // @[Decoupled.scala:51:35]
assign _dec_T_213 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_215; // @[Decoupled.scala:51:35]
assign _dec_T_215 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_217; // @[Decoupled.scala:51:35]
assign _dec_T_217 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_219; // @[Decoupled.scala:51:35]
assign _dec_T_219 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_221; // @[Decoupled.scala:51:35]
assign _dec_T_221 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_223; // @[Decoupled.scala:51:35]
assign _dec_T_223 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_225; // @[Decoupled.scala:51:35]
assign _dec_T_225 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_227; // @[Decoupled.scala:51:35]
assign _dec_T_227 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_229; // @[Decoupled.scala:51:35]
assign _dec_T_229 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_231; // @[Decoupled.scala:51:35]
assign _dec_T_231 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_233; // @[Decoupled.scala:51:35]
assign _dec_T_233 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_235; // @[Decoupled.scala:51:35]
assign _dec_T_235 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_237; // @[Decoupled.scala:51:35]
assign _dec_T_237 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_239; // @[Decoupled.scala:51:35]
assign _dec_T_239 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_241; // @[Decoupled.scala:51:35]
assign _dec_T_241 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_243; // @[Decoupled.scala:51:35]
assign _dec_T_243 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_245; // @[Decoupled.scala:51:35]
assign _dec_T_245 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_247; // @[Decoupled.scala:51:35]
assign _dec_T_247 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_249; // @[Decoupled.scala:51:35]
assign _dec_T_249 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_251; // @[Decoupled.scala:51:35]
assign _dec_T_251 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_253; // @[Decoupled.scala:51:35]
assign _dec_T_253 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_255; // @[Decoupled.scala:51:35]
assign _dec_T_255 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_257; // @[Decoupled.scala:51:35]
assign _dec_T_257 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_259; // @[Decoupled.scala:51:35]
assign _dec_T_259 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_261; // @[Decoupled.scala:51:35]
assign _dec_T_261 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_263; // @[Decoupled.scala:51:35]
assign _dec_T_263 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_265; // @[Decoupled.scala:51:35]
assign _dec_T_265 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_267; // @[Decoupled.scala:51:35]
assign _dec_T_267 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_269; // @[Decoupled.scala:51:35]
assign _dec_T_269 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_271; // @[Decoupled.scala:51:35]
assign _dec_T_271 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_273; // @[Decoupled.scala:51:35]
assign _dec_T_273 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_275; // @[Decoupled.scala:51:35]
assign _dec_T_275 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_277; // @[Decoupled.scala:51:35]
assign _dec_T_277 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_279; // @[Decoupled.scala:51:35]
assign _dec_T_279 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_281; // @[Decoupled.scala:51:35]
assign _dec_T_281 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_283; // @[Decoupled.scala:51:35]
assign _dec_T_283 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_285; // @[Decoupled.scala:51:35]
assign _dec_T_285 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_287; // @[Decoupled.scala:51:35]
assign _dec_T_287 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_289; // @[Decoupled.scala:51:35]
assign _dec_T_289 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_291; // @[Decoupled.scala:51:35]
assign _dec_T_291 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_293; // @[Decoupled.scala:51:35]
assign _dec_T_293 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_295; // @[Decoupled.scala:51:35]
assign _dec_T_295 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_297; // @[Decoupled.scala:51:35]
assign _dec_T_297 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_299; // @[Decoupled.scala:51:35]
assign _dec_T_299 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_301; // @[Decoupled.scala:51:35]
assign _dec_T_301 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_303; // @[Decoupled.scala:51:35]
assign _dec_T_303 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_305; // @[Decoupled.scala:51:35]
assign _dec_T_305 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_307; // @[Decoupled.scala:51:35]
assign _dec_T_307 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_309; // @[Decoupled.scala:51:35]
assign _dec_T_309 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_311; // @[Decoupled.scala:51:35]
assign _dec_T_311 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_313; // @[Decoupled.scala:51:35]
assign _dec_T_313 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_315; // @[Decoupled.scala:51:35]
assign _dec_T_315 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_317; // @[Decoupled.scala:51:35]
assign _dec_T_317 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_319; // @[Decoupled.scala:51:35]
assign _dec_T_319 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_321; // @[Decoupled.scala:51:35]
assign _dec_T_321 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_323; // @[Decoupled.scala:51:35]
assign _dec_T_323 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_325; // @[Decoupled.scala:51:35]
assign _dec_T_325 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_327; // @[Decoupled.scala:51:35]
assign _dec_T_327 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_329; // @[Decoupled.scala:51:35]
assign _dec_T_329 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_331; // @[Decoupled.scala:51:35]
assign _dec_T_331 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_333; // @[Decoupled.scala:51:35]
assign _dec_T_333 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_335; // @[Decoupled.scala:51:35]
assign _dec_T_335 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_337; // @[Decoupled.scala:51:35]
assign _dec_T_337 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_339; // @[Decoupled.scala:51:35]
assign _dec_T_339 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_341; // @[Decoupled.scala:51:35]
assign _dec_T_341 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_343; // @[Decoupled.scala:51:35]
assign _dec_T_343 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_345; // @[Decoupled.scala:51:35]
assign _dec_T_345 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_347; // @[Decoupled.scala:51:35]
assign _dec_T_347 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_349; // @[Decoupled.scala:51:35]
assign _dec_T_349 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_351; // @[Decoupled.scala:51:35]
assign _dec_T_351 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_353; // @[Decoupled.scala:51:35]
assign _dec_T_353 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_355; // @[Decoupled.scala:51:35]
assign _dec_T_355 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_357; // @[Decoupled.scala:51:35]
assign _dec_T_357 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_359; // @[Decoupled.scala:51:35]
assign _dec_T_359 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_361; // @[Decoupled.scala:51:35]
assign _dec_T_361 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_363; // @[Decoupled.scala:51:35]
assign _dec_T_363 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_365; // @[Decoupled.scala:51:35]
assign _dec_T_365 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_367; // @[Decoupled.scala:51:35]
assign _dec_T_367 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_369; // @[Decoupled.scala:51:35]
assign _dec_T_369 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_371; // @[Decoupled.scala:51:35]
assign _dec_T_371 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_373; // @[Decoupled.scala:51:35]
assign _dec_T_373 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_375; // @[Decoupled.scala:51:35]
assign _dec_T_375 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_377; // @[Decoupled.scala:51:35]
assign _dec_T_377 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_379; // @[Decoupled.scala:51:35]
assign _dec_T_379 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_381; // @[Decoupled.scala:51:35]
assign _dec_T_381 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_383; // @[Decoupled.scala:51:35]
assign _dec_T_383 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_385; // @[Decoupled.scala:51:35]
assign _dec_T_385 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_387; // @[Decoupled.scala:51:35]
assign _dec_T_387 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_389; // @[Decoupled.scala:51:35]
assign _dec_T_389 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_391; // @[Decoupled.scala:51:35]
assign _dec_T_391 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_393; // @[Decoupled.scala:51:35]
assign _dec_T_393 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_395; // @[Decoupled.scala:51:35]
assign _dec_T_395 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_397; // @[Decoupled.scala:51:35]
assign _dec_T_397 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_399; // @[Decoupled.scala:51:35]
assign _dec_T_399 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_401; // @[Decoupled.scala:51:35]
assign _dec_T_401 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_403; // @[Decoupled.scala:51:35]
assign _dec_T_403 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_405; // @[Decoupled.scala:51:35]
assign _dec_T_405 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_407; // @[Decoupled.scala:51:35]
assign _dec_T_407 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_409; // @[Decoupled.scala:51:35]
assign _dec_T_409 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_411; // @[Decoupled.scala:51:35]
assign _dec_T_411 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_413; // @[Decoupled.scala:51:35]
assign _dec_T_413 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_415; // @[Decoupled.scala:51:35]
assign _dec_T_415 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_417; // @[Decoupled.scala:51:35]
assign _dec_T_417 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_419; // @[Decoupled.scala:51:35]
assign _dec_T_419 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_421; // @[Decoupled.scala:51:35]
assign _dec_T_421 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_423; // @[Decoupled.scala:51:35]
assign _dec_T_423 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_425; // @[Decoupled.scala:51:35]
assign _dec_T_425 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_427; // @[Decoupled.scala:51:35]
assign _dec_T_427 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_429; // @[Decoupled.scala:51:35]
assign _dec_T_429 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_431; // @[Decoupled.scala:51:35]
assign _dec_T_431 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_433; // @[Decoupled.scala:51:35]
assign _dec_T_433 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_435; // @[Decoupled.scala:51:35]
assign _dec_T_435 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_437; // @[Decoupled.scala:51:35]
assign _dec_T_437 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_439; // @[Decoupled.scala:51:35]
assign _dec_T_439 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_441; // @[Decoupled.scala:51:35]
assign _dec_T_441 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_443; // @[Decoupled.scala:51:35]
assign _dec_T_443 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_445; // @[Decoupled.scala:51:35]
assign _dec_T_445 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_447; // @[Decoupled.scala:51:35]
assign _dec_T_447 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_449; // @[Decoupled.scala:51:35]
assign _dec_T_449 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_451; // @[Decoupled.scala:51:35]
assign _dec_T_451 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_453; // @[Decoupled.scala:51:35]
assign _dec_T_453 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_455; // @[Decoupled.scala:51:35]
assign _dec_T_455 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_457; // @[Decoupled.scala:51:35]
assign _dec_T_457 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_459; // @[Decoupled.scala:51:35]
assign _dec_T_459 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_461; // @[Decoupled.scala:51:35]
assign _dec_T_461 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_463; // @[Decoupled.scala:51:35]
assign _dec_T_463 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_465; // @[Decoupled.scala:51:35]
assign _dec_T_465 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_467; // @[Decoupled.scala:51:35]
assign _dec_T_467 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_469; // @[Decoupled.scala:51:35]
assign _dec_T_469 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_471; // @[Decoupled.scala:51:35]
assign _dec_T_471 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_473; // @[Decoupled.scala:51:35]
assign _dec_T_473 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_475; // @[Decoupled.scala:51:35]
assign _dec_T_475 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_477; // @[Decoupled.scala:51:35]
assign _dec_T_477 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_479; // @[Decoupled.scala:51:35]
assign _dec_T_479 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_481; // @[Decoupled.scala:51:35]
assign _dec_T_481 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_483; // @[Decoupled.scala:51:35]
assign _dec_T_483 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_485; // @[Decoupled.scala:51:35]
assign _dec_T_485 = _GEN_3; // @[Decoupled.scala:51:35]
wire _dec_T_487; // @[Decoupled.scala:51:35]
assign _dec_T_487 = _GEN_3; // @[Decoupled.scala:51:35]
wire dec = _dec_T & _dec_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _count_T = {1'h0, count} + {1'h0, inc}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_1 = _count_T[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_2 = {1'h0, _count_T_1} - {1'h0, dec}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_3 = _count_T_2[0]; // @[ToAXI4.scala:278:37]
wire _idStall_0_T = ~idle; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_0_T_3 = _idStall_0_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_0 = _idStall_0_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_1; // @[ToAXI4.scala:272:28]
wire _idStall_1_T_2 = count_1; // @[ToAXI4.scala:272:28, :286:44]
reg write_1; // @[ToAXI4.scala:273:24]
wire idle_1 = ~count_1; // @[ToAXI4.scala:272:28, :274:26]
wire inc_1 = a_sel_1 & _inc_T_1; // @[Decoupled.scala:51:35]
wire _dec_T_2 = d_sel_1 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_1 = _dec_T_2 & _dec_T_3; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_4 = {1'h0, count_1} + {1'h0, inc_1}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_5 = _count_T_4[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_6 = {1'h0, _count_T_5} - {1'h0, dec_1}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_7 = _count_T_6[0]; // @[ToAXI4.scala:278:37]
wire _idStall_1_T = ~idle_1; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_1_T_3 = _idStall_1_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_1 = _idStall_1_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_2; // @[ToAXI4.scala:272:28]
wire _idStall_2_T_2 = count_2; // @[ToAXI4.scala:272:28, :286:44]
reg write_2; // @[ToAXI4.scala:273:24]
wire idle_2 = ~count_2; // @[ToAXI4.scala:272:28, :274:26]
wire inc_2 = a_sel_2 & _inc_T_2; // @[Decoupled.scala:51:35]
wire _dec_T_4 = d_sel_2 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_2 = _dec_T_4 & _dec_T_5; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_8 = {1'h0, count_2} + {1'h0, inc_2}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_9 = _count_T_8[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_10 = {1'h0, _count_T_9} - {1'h0, dec_2}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_11 = _count_T_10[0]; // @[ToAXI4.scala:278:37]
wire _idStall_2_T = ~idle_2; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_2_T_3 = _idStall_2_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_2 = _idStall_2_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_3; // @[ToAXI4.scala:272:28]
wire _idStall_3_T_2 = count_3; // @[ToAXI4.scala:272:28, :286:44]
reg write_3; // @[ToAXI4.scala:273:24]
wire idle_3 = ~count_3; // @[ToAXI4.scala:272:28, :274:26]
wire inc_3 = a_sel_3 & _inc_T_3; // @[Decoupled.scala:51:35]
wire _dec_T_6 = d_sel_3 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_3 = _dec_T_6 & _dec_T_7; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_12 = {1'h0, count_3} + {1'h0, inc_3}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_13 = _count_T_12[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_14 = {1'h0, _count_T_13} - {1'h0, dec_3}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_15 = _count_T_14[0]; // @[ToAXI4.scala:278:37]
wire _idStall_3_T = ~idle_3; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_3_T_3 = _idStall_3_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_3 = _idStall_3_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_4; // @[ToAXI4.scala:272:28]
wire _idStall_4_T_2 = count_4; // @[ToAXI4.scala:272:28, :286:44]
reg write_4; // @[ToAXI4.scala:273:24]
wire idle_4 = ~count_4; // @[ToAXI4.scala:272:28, :274:26]
wire inc_4 = a_sel_4 & _inc_T_4; // @[Decoupled.scala:51:35]
wire _dec_T_8 = d_sel_4 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_4 = _dec_T_8 & _dec_T_9; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_16 = {1'h0, count_4} + {1'h0, inc_4}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_17 = _count_T_16[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_18 = {1'h0, _count_T_17} - {1'h0, dec_4}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_19 = _count_T_18[0]; // @[ToAXI4.scala:278:37]
wire _idStall_4_T = ~idle_4; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_4_T_3 = _idStall_4_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_4 = _idStall_4_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_5; // @[ToAXI4.scala:272:28]
wire _idStall_5_T_2 = count_5; // @[ToAXI4.scala:272:28, :286:44]
reg write_5; // @[ToAXI4.scala:273:24]
wire idle_5 = ~count_5; // @[ToAXI4.scala:272:28, :274:26]
wire inc_5 = a_sel_5 & _inc_T_5; // @[Decoupled.scala:51:35]
wire _dec_T_10 = d_sel_5 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_5 = _dec_T_10 & _dec_T_11; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_20 = {1'h0, count_5} + {1'h0, inc_5}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_21 = _count_T_20[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_22 = {1'h0, _count_T_21} - {1'h0, dec_5}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_23 = _count_T_22[0]; // @[ToAXI4.scala:278:37]
wire _idStall_5_T = ~idle_5; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_5_T_3 = _idStall_5_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_5 = _idStall_5_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_6; // @[ToAXI4.scala:272:28]
wire _idStall_6_T_2 = count_6; // @[ToAXI4.scala:272:28, :286:44]
reg write_6; // @[ToAXI4.scala:273:24]
wire idle_6 = ~count_6; // @[ToAXI4.scala:272:28, :274:26]
wire inc_6 = a_sel_6 & _inc_T_6; // @[Decoupled.scala:51:35]
wire _dec_T_12 = d_sel_6 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_6 = _dec_T_12 & _dec_T_13; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_24 = {1'h0, count_6} + {1'h0, inc_6}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_25 = _count_T_24[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_26 = {1'h0, _count_T_25} - {1'h0, dec_6}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_27 = _count_T_26[0]; // @[ToAXI4.scala:278:37]
wire _idStall_6_T = ~idle_6; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_6_T_3 = _idStall_6_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_6 = _idStall_6_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_7; // @[ToAXI4.scala:272:28]
wire _idStall_7_T_2 = count_7; // @[ToAXI4.scala:272:28, :286:44]
reg write_7; // @[ToAXI4.scala:273:24]
wire idle_7 = ~count_7; // @[ToAXI4.scala:272:28, :274:26]
wire inc_7 = a_sel_7 & _inc_T_7; // @[Decoupled.scala:51:35]
wire _dec_T_14 = d_sel_7 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_7 = _dec_T_14 & _dec_T_15; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_28 = {1'h0, count_7} + {1'h0, inc_7}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_29 = _count_T_28[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_30 = {1'h0, _count_T_29} - {1'h0, dec_7}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_31 = _count_T_30[0]; // @[ToAXI4.scala:278:37]
wire _idStall_7_T = ~idle_7; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_7_T_3 = _idStall_7_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_7 = _idStall_7_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_8; // @[ToAXI4.scala:272:28]
wire _idStall_8_T_2 = count_8; // @[ToAXI4.scala:272:28, :286:44]
reg write_8; // @[ToAXI4.scala:273:24]
wire idle_8 = ~count_8; // @[ToAXI4.scala:272:28, :274:26]
wire inc_8 = a_sel_8 & _inc_T_8; // @[Decoupled.scala:51:35]
wire _dec_T_16 = d_sel_8 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_8 = _dec_T_16 & _dec_T_17; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_32 = {1'h0, count_8} + {1'h0, inc_8}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_33 = _count_T_32[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_34 = {1'h0, _count_T_33} - {1'h0, dec_8}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_35 = _count_T_34[0]; // @[ToAXI4.scala:278:37]
wire _idStall_8_T = ~idle_8; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_8_T_3 = _idStall_8_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_8 = _idStall_8_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_9; // @[ToAXI4.scala:272:28]
wire _idStall_9_T_2 = count_9; // @[ToAXI4.scala:272:28, :286:44]
reg write_9; // @[ToAXI4.scala:273:24]
wire idle_9 = ~count_9; // @[ToAXI4.scala:272:28, :274:26]
wire inc_9 = a_sel_9 & _inc_T_9; // @[Decoupled.scala:51:35]
wire _dec_T_18 = d_sel_9 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_9 = _dec_T_18 & _dec_T_19; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_36 = {1'h0, count_9} + {1'h0, inc_9}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_37 = _count_T_36[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_38 = {1'h0, _count_T_37} - {1'h0, dec_9}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_39 = _count_T_38[0]; // @[ToAXI4.scala:278:37]
wire _idStall_9_T = ~idle_9; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_9_T_3 = _idStall_9_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_9 = _idStall_9_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_10; // @[ToAXI4.scala:272:28]
wire _idStall_10_T_2 = count_10; // @[ToAXI4.scala:272:28, :286:44]
reg write_10; // @[ToAXI4.scala:273:24]
wire idle_10 = ~count_10; // @[ToAXI4.scala:272:28, :274:26]
wire inc_10 = a_sel_10 & _inc_T_10; // @[Decoupled.scala:51:35]
wire _dec_T_20 = d_sel_10 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_10 = _dec_T_20 & _dec_T_21; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_40 = {1'h0, count_10} + {1'h0, inc_10}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_41 = _count_T_40[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_42 = {1'h0, _count_T_41} - {1'h0, dec_10}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_43 = _count_T_42[0]; // @[ToAXI4.scala:278:37]
wire _idStall_10_T = ~idle_10; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_10_T_3 = _idStall_10_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_10 = _idStall_10_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_11; // @[ToAXI4.scala:272:28]
wire _idStall_11_T_2 = count_11; // @[ToAXI4.scala:272:28, :286:44]
reg write_11; // @[ToAXI4.scala:273:24]
wire idle_11 = ~count_11; // @[ToAXI4.scala:272:28, :274:26]
wire inc_11 = a_sel_11 & _inc_T_11; // @[Decoupled.scala:51:35]
wire _dec_T_22 = d_sel_11 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_11 = _dec_T_22 & _dec_T_23; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_44 = {1'h0, count_11} + {1'h0, inc_11}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_45 = _count_T_44[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_46 = {1'h0, _count_T_45} - {1'h0, dec_11}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_47 = _count_T_46[0]; // @[ToAXI4.scala:278:37]
wire _idStall_11_T = ~idle_11; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_11_T_3 = _idStall_11_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_11 = _idStall_11_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_12; // @[ToAXI4.scala:272:28]
wire _idStall_12_T_2 = count_12; // @[ToAXI4.scala:272:28, :286:44]
reg write_12; // @[ToAXI4.scala:273:24]
wire idle_12 = ~count_12; // @[ToAXI4.scala:272:28, :274:26]
wire inc_12 = a_sel_12 & _inc_T_12; // @[Decoupled.scala:51:35]
wire _dec_T_24 = d_sel_12 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_12 = _dec_T_24 & _dec_T_25; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_48 = {1'h0, count_12} + {1'h0, inc_12}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_49 = _count_T_48[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_50 = {1'h0, _count_T_49} - {1'h0, dec_12}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_51 = _count_T_50[0]; // @[ToAXI4.scala:278:37]
wire _idStall_12_T = ~idle_12; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_12_T_3 = _idStall_12_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_12 = _idStall_12_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_13; // @[ToAXI4.scala:272:28]
wire _idStall_13_T_2 = count_13; // @[ToAXI4.scala:272:28, :286:44]
reg write_13; // @[ToAXI4.scala:273:24]
wire idle_13 = ~count_13; // @[ToAXI4.scala:272:28, :274:26]
wire inc_13 = a_sel_13 & _inc_T_13; // @[Decoupled.scala:51:35]
wire _dec_T_26 = d_sel_13 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_13 = _dec_T_26 & _dec_T_27; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_52 = {1'h0, count_13} + {1'h0, inc_13}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_53 = _count_T_52[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_54 = {1'h0, _count_T_53} - {1'h0, dec_13}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_55 = _count_T_54[0]; // @[ToAXI4.scala:278:37]
wire _idStall_13_T = ~idle_13; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_13_T_3 = _idStall_13_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_13 = _idStall_13_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_14; // @[ToAXI4.scala:272:28]
wire _idStall_14_T_2 = count_14; // @[ToAXI4.scala:272:28, :286:44]
reg write_14; // @[ToAXI4.scala:273:24]
wire idle_14 = ~count_14; // @[ToAXI4.scala:272:28, :274:26]
wire inc_14 = a_sel_14 & _inc_T_14; // @[Decoupled.scala:51:35]
wire _dec_T_28 = d_sel_14 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_14 = _dec_T_28 & _dec_T_29; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_56 = {1'h0, count_14} + {1'h0, inc_14}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_57 = _count_T_56[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_58 = {1'h0, _count_T_57} - {1'h0, dec_14}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_59 = _count_T_58[0]; // @[ToAXI4.scala:278:37]
wire _idStall_14_T = ~idle_14; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_14_T_3 = _idStall_14_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_14 = _idStall_14_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_15; // @[ToAXI4.scala:272:28]
wire _idStall_15_T_2 = count_15; // @[ToAXI4.scala:272:28, :286:44]
reg write_15; // @[ToAXI4.scala:273:24]
wire idle_15 = ~count_15; // @[ToAXI4.scala:272:28, :274:26]
wire inc_15 = a_sel_15 & _inc_T_15; // @[Decoupled.scala:51:35]
wire _dec_T_30 = d_sel_15 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_15 = _dec_T_30 & _dec_T_31; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_60 = {1'h0, count_15} + {1'h0, inc_15}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_61 = _count_T_60[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_62 = {1'h0, _count_T_61} - {1'h0, dec_15}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_63 = _count_T_62[0]; // @[ToAXI4.scala:278:37]
wire _idStall_15_T = ~idle_15; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_15_T_3 = _idStall_15_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_15 = _idStall_15_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_16; // @[ToAXI4.scala:272:28]
wire _idStall_16_T_2 = count_16; // @[ToAXI4.scala:272:28, :286:44]
reg write_16; // @[ToAXI4.scala:273:24]
wire idle_16 = ~count_16; // @[ToAXI4.scala:272:28, :274:26]
wire inc_16 = a_sel_16 & _inc_T_16; // @[Decoupled.scala:51:35]
wire _dec_T_32 = d_sel_16 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_16 = _dec_T_32 & _dec_T_33; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_64 = {1'h0, count_16} + {1'h0, inc_16}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_65 = _count_T_64[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_66 = {1'h0, _count_T_65} - {1'h0, dec_16}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_67 = _count_T_66[0]; // @[ToAXI4.scala:278:37]
wire _idStall_16_T = ~idle_16; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_16_T_3 = _idStall_16_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_16 = _idStall_16_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_17; // @[ToAXI4.scala:272:28]
wire _idStall_17_T_2 = count_17; // @[ToAXI4.scala:272:28, :286:44]
reg write_17; // @[ToAXI4.scala:273:24]
wire idle_17 = ~count_17; // @[ToAXI4.scala:272:28, :274:26]
wire inc_17 = a_sel_17 & _inc_T_17; // @[Decoupled.scala:51:35]
wire _dec_T_34 = d_sel_17 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_17 = _dec_T_34 & _dec_T_35; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_68 = {1'h0, count_17} + {1'h0, inc_17}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_69 = _count_T_68[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_70 = {1'h0, _count_T_69} - {1'h0, dec_17}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_71 = _count_T_70[0]; // @[ToAXI4.scala:278:37]
wire _idStall_17_T = ~idle_17; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_17_T_3 = _idStall_17_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_17 = _idStall_17_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_18; // @[ToAXI4.scala:272:28]
wire _idStall_18_T_2 = count_18; // @[ToAXI4.scala:272:28, :286:44]
reg write_18; // @[ToAXI4.scala:273:24]
wire idle_18 = ~count_18; // @[ToAXI4.scala:272:28, :274:26]
wire inc_18 = a_sel_18 & _inc_T_18; // @[Decoupled.scala:51:35]
wire _dec_T_36 = d_sel_18 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_18 = _dec_T_36 & _dec_T_37; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_72 = {1'h0, count_18} + {1'h0, inc_18}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_73 = _count_T_72[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_74 = {1'h0, _count_T_73} - {1'h0, dec_18}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_75 = _count_T_74[0]; // @[ToAXI4.scala:278:37]
wire _idStall_18_T = ~idle_18; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_18_T_3 = _idStall_18_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_18 = _idStall_18_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_19; // @[ToAXI4.scala:272:28]
wire _idStall_19_T_2 = count_19; // @[ToAXI4.scala:272:28, :286:44]
reg write_19; // @[ToAXI4.scala:273:24]
wire idle_19 = ~count_19; // @[ToAXI4.scala:272:28, :274:26]
wire inc_19 = a_sel_19 & _inc_T_19; // @[Decoupled.scala:51:35]
wire _dec_T_38 = d_sel_19 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_19 = _dec_T_38 & _dec_T_39; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_76 = {1'h0, count_19} + {1'h0, inc_19}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_77 = _count_T_76[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_78 = {1'h0, _count_T_77} - {1'h0, dec_19}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_79 = _count_T_78[0]; // @[ToAXI4.scala:278:37]
wire _idStall_19_T = ~idle_19; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_19_T_3 = _idStall_19_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_19 = _idStall_19_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_20; // @[ToAXI4.scala:272:28]
wire _idStall_20_T_2 = count_20; // @[ToAXI4.scala:272:28, :286:44]
reg write_20; // @[ToAXI4.scala:273:24]
wire idle_20 = ~count_20; // @[ToAXI4.scala:272:28, :274:26]
wire inc_20 = a_sel_20 & _inc_T_20; // @[Decoupled.scala:51:35]
wire _dec_T_40 = d_sel_20 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_20 = _dec_T_40 & _dec_T_41; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_80 = {1'h0, count_20} + {1'h0, inc_20}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_81 = _count_T_80[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_82 = {1'h0, _count_T_81} - {1'h0, dec_20}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_83 = _count_T_82[0]; // @[ToAXI4.scala:278:37]
wire _idStall_20_T = ~idle_20; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_20_T_3 = _idStall_20_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_20 = _idStall_20_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_21; // @[ToAXI4.scala:272:28]
wire _idStall_21_T_2 = count_21; // @[ToAXI4.scala:272:28, :286:44]
reg write_21; // @[ToAXI4.scala:273:24]
wire idle_21 = ~count_21; // @[ToAXI4.scala:272:28, :274:26]
wire inc_21 = a_sel_21 & _inc_T_21; // @[Decoupled.scala:51:35]
wire _dec_T_42 = d_sel_21 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_21 = _dec_T_42 & _dec_T_43; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_84 = {1'h0, count_21} + {1'h0, inc_21}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_85 = _count_T_84[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_86 = {1'h0, _count_T_85} - {1'h0, dec_21}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_87 = _count_T_86[0]; // @[ToAXI4.scala:278:37]
wire _idStall_21_T = ~idle_21; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_21_T_3 = _idStall_21_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_21 = _idStall_21_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_22; // @[ToAXI4.scala:272:28]
wire _idStall_22_T_2 = count_22; // @[ToAXI4.scala:272:28, :286:44]
reg write_22; // @[ToAXI4.scala:273:24]
wire idle_22 = ~count_22; // @[ToAXI4.scala:272:28, :274:26]
wire inc_22 = a_sel_22 & _inc_T_22; // @[Decoupled.scala:51:35]
wire _dec_T_44 = d_sel_22 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_22 = _dec_T_44 & _dec_T_45; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_88 = {1'h0, count_22} + {1'h0, inc_22}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_89 = _count_T_88[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_90 = {1'h0, _count_T_89} - {1'h0, dec_22}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_91 = _count_T_90[0]; // @[ToAXI4.scala:278:37]
wire _idStall_22_T = ~idle_22; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_22_T_3 = _idStall_22_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_22 = _idStall_22_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_23; // @[ToAXI4.scala:272:28]
wire _idStall_23_T_2 = count_23; // @[ToAXI4.scala:272:28, :286:44]
reg write_23; // @[ToAXI4.scala:273:24]
wire idle_23 = ~count_23; // @[ToAXI4.scala:272:28, :274:26]
wire inc_23 = a_sel_23 & _inc_T_23; // @[Decoupled.scala:51:35]
wire _dec_T_46 = d_sel_23 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_23 = _dec_T_46 & _dec_T_47; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_92 = {1'h0, count_23} + {1'h0, inc_23}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_93 = _count_T_92[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_94 = {1'h0, _count_T_93} - {1'h0, dec_23}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_95 = _count_T_94[0]; // @[ToAXI4.scala:278:37]
wire _idStall_23_T = ~idle_23; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_23_T_3 = _idStall_23_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_23 = _idStall_23_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_24; // @[ToAXI4.scala:272:28]
wire _idStall_24_T_2 = count_24; // @[ToAXI4.scala:272:28, :286:44]
reg write_24; // @[ToAXI4.scala:273:24]
wire idle_24 = ~count_24; // @[ToAXI4.scala:272:28, :274:26]
wire inc_24 = a_sel_24 & _inc_T_24; // @[Decoupled.scala:51:35]
wire _dec_T_48 = d_sel_24 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_24 = _dec_T_48 & _dec_T_49; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_96 = {1'h0, count_24} + {1'h0, inc_24}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_97 = _count_T_96[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_98 = {1'h0, _count_T_97} - {1'h0, dec_24}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_99 = _count_T_98[0]; // @[ToAXI4.scala:278:37]
wire _idStall_24_T = ~idle_24; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_24_T_3 = _idStall_24_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_24 = _idStall_24_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_25; // @[ToAXI4.scala:272:28]
wire _idStall_25_T_2 = count_25; // @[ToAXI4.scala:272:28, :286:44]
reg write_25; // @[ToAXI4.scala:273:24]
wire idle_25 = ~count_25; // @[ToAXI4.scala:272:28, :274:26]
wire inc_25 = a_sel_25 & _inc_T_25; // @[Decoupled.scala:51:35]
wire _dec_T_50 = d_sel_25 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_25 = _dec_T_50 & _dec_T_51; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_100 = {1'h0, count_25} + {1'h0, inc_25}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_101 = _count_T_100[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_102 = {1'h0, _count_T_101} - {1'h0, dec_25}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_103 = _count_T_102[0]; // @[ToAXI4.scala:278:37]
wire _idStall_25_T = ~idle_25; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_25_T_3 = _idStall_25_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_25 = _idStall_25_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_26; // @[ToAXI4.scala:272:28]
wire _idStall_26_T_2 = count_26; // @[ToAXI4.scala:272:28, :286:44]
reg write_26; // @[ToAXI4.scala:273:24]
wire idle_26 = ~count_26; // @[ToAXI4.scala:272:28, :274:26]
wire inc_26 = a_sel_26 & _inc_T_26; // @[Decoupled.scala:51:35]
wire _dec_T_52 = d_sel_26 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_26 = _dec_T_52 & _dec_T_53; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_104 = {1'h0, count_26} + {1'h0, inc_26}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_105 = _count_T_104[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_106 = {1'h0, _count_T_105} - {1'h0, dec_26}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_107 = _count_T_106[0]; // @[ToAXI4.scala:278:37]
wire _idStall_26_T = ~idle_26; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_26_T_3 = _idStall_26_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_26 = _idStall_26_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_27; // @[ToAXI4.scala:272:28]
wire _idStall_27_T_2 = count_27; // @[ToAXI4.scala:272:28, :286:44]
reg write_27; // @[ToAXI4.scala:273:24]
wire idle_27 = ~count_27; // @[ToAXI4.scala:272:28, :274:26]
wire inc_27 = a_sel_27 & _inc_T_27; // @[Decoupled.scala:51:35]
wire _dec_T_54 = d_sel_27 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_27 = _dec_T_54 & _dec_T_55; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_108 = {1'h0, count_27} + {1'h0, inc_27}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_109 = _count_T_108[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_110 = {1'h0, _count_T_109} - {1'h0, dec_27}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_111 = _count_T_110[0]; // @[ToAXI4.scala:278:37]
wire _idStall_27_T = ~idle_27; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_27_T_3 = _idStall_27_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_27 = _idStall_27_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_28; // @[ToAXI4.scala:272:28]
wire _idStall_28_T_2 = count_28; // @[ToAXI4.scala:272:28, :286:44]
reg write_28; // @[ToAXI4.scala:273:24]
wire idle_28 = ~count_28; // @[ToAXI4.scala:272:28, :274:26]
wire inc_28 = a_sel_28 & _inc_T_28; // @[Decoupled.scala:51:35]
wire _dec_T_56 = d_sel_28 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_28 = _dec_T_56 & _dec_T_57; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_112 = {1'h0, count_28} + {1'h0, inc_28}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_113 = _count_T_112[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_114 = {1'h0, _count_T_113} - {1'h0, dec_28}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_115 = _count_T_114[0]; // @[ToAXI4.scala:278:37]
wire _idStall_28_T = ~idle_28; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_28_T_3 = _idStall_28_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_28 = _idStall_28_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_29; // @[ToAXI4.scala:272:28]
wire _idStall_29_T_2 = count_29; // @[ToAXI4.scala:272:28, :286:44]
reg write_29; // @[ToAXI4.scala:273:24]
wire idle_29 = ~count_29; // @[ToAXI4.scala:272:28, :274:26]
wire inc_29 = a_sel_29 & _inc_T_29; // @[Decoupled.scala:51:35]
wire _dec_T_58 = d_sel_29 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_29 = _dec_T_58 & _dec_T_59; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_116 = {1'h0, count_29} + {1'h0, inc_29}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_117 = _count_T_116[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_118 = {1'h0, _count_T_117} - {1'h0, dec_29}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_119 = _count_T_118[0]; // @[ToAXI4.scala:278:37]
wire _idStall_29_T = ~idle_29; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_29_T_3 = _idStall_29_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_29 = _idStall_29_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_30; // @[ToAXI4.scala:272:28]
wire _idStall_30_T_2 = count_30; // @[ToAXI4.scala:272:28, :286:44]
reg write_30; // @[ToAXI4.scala:273:24]
wire idle_30 = ~count_30; // @[ToAXI4.scala:272:28, :274:26]
wire inc_30 = a_sel_30 & _inc_T_30; // @[Decoupled.scala:51:35]
wire _dec_T_60 = d_sel_30 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_30 = _dec_T_60 & _dec_T_61; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_120 = {1'h0, count_30} + {1'h0, inc_30}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_121 = _count_T_120[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_122 = {1'h0, _count_T_121} - {1'h0, dec_30}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_123 = _count_T_122[0]; // @[ToAXI4.scala:278:37]
wire _idStall_30_T = ~idle_30; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_30_T_3 = _idStall_30_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_30 = _idStall_30_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_31; // @[ToAXI4.scala:272:28]
wire _idStall_31_T_2 = count_31; // @[ToAXI4.scala:272:28, :286:44]
reg write_31; // @[ToAXI4.scala:273:24]
wire idle_31 = ~count_31; // @[ToAXI4.scala:272:28, :274:26]
wire inc_31 = a_sel_31 & _inc_T_31; // @[Decoupled.scala:51:35]
wire _dec_T_62 = d_sel_31 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_31 = _dec_T_62 & _dec_T_63; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_124 = {1'h0, count_31} + {1'h0, inc_31}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_125 = _count_T_124[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_126 = {1'h0, _count_T_125} - {1'h0, dec_31}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_127 = _count_T_126[0]; // @[ToAXI4.scala:278:37]
wire _idStall_31_T = ~idle_31; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_31_T_3 = _idStall_31_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_31 = _idStall_31_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_32; // @[ToAXI4.scala:272:28]
wire _idStall_32_T_2 = count_32; // @[ToAXI4.scala:272:28, :286:44]
reg write_32; // @[ToAXI4.scala:273:24]
wire idle_32 = ~count_32; // @[ToAXI4.scala:272:28, :274:26]
wire inc_32 = a_sel_32 & _inc_T_32; // @[Decoupled.scala:51:35]
wire _dec_T_64 = d_sel_32 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_32 = _dec_T_64 & _dec_T_65; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_128 = {1'h0, count_32} + {1'h0, inc_32}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_129 = _count_T_128[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_130 = {1'h0, _count_T_129} - {1'h0, dec_32}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_131 = _count_T_130[0]; // @[ToAXI4.scala:278:37]
wire _idStall_32_T = ~idle_32; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_32_T_3 = _idStall_32_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_32 = _idStall_32_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_33; // @[ToAXI4.scala:272:28]
wire _idStall_33_T_2 = count_33; // @[ToAXI4.scala:272:28, :286:44]
reg write_33; // @[ToAXI4.scala:273:24]
wire idle_33 = ~count_33; // @[ToAXI4.scala:272:28, :274:26]
wire inc_33 = a_sel_33 & _inc_T_33; // @[Decoupled.scala:51:35]
wire _dec_T_66 = d_sel_33 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_33 = _dec_T_66 & _dec_T_67; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_132 = {1'h0, count_33} + {1'h0, inc_33}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_133 = _count_T_132[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_134 = {1'h0, _count_T_133} - {1'h0, dec_33}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_135 = _count_T_134[0]; // @[ToAXI4.scala:278:37]
wire _idStall_33_T = ~idle_33; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_33_T_3 = _idStall_33_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_33 = _idStall_33_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_34; // @[ToAXI4.scala:272:28]
wire _idStall_34_T_2 = count_34; // @[ToAXI4.scala:272:28, :286:44]
reg write_34; // @[ToAXI4.scala:273:24]
wire idle_34 = ~count_34; // @[ToAXI4.scala:272:28, :274:26]
wire inc_34 = a_sel_34 & _inc_T_34; // @[Decoupled.scala:51:35]
wire _dec_T_68 = d_sel_34 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_34 = _dec_T_68 & _dec_T_69; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_136 = {1'h0, count_34} + {1'h0, inc_34}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_137 = _count_T_136[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_138 = {1'h0, _count_T_137} - {1'h0, dec_34}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_139 = _count_T_138[0]; // @[ToAXI4.scala:278:37]
wire _idStall_34_T = ~idle_34; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_34_T_3 = _idStall_34_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_34 = _idStall_34_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_35; // @[ToAXI4.scala:272:28]
wire _idStall_35_T_2 = count_35; // @[ToAXI4.scala:272:28, :286:44]
reg write_35; // @[ToAXI4.scala:273:24]
wire idle_35 = ~count_35; // @[ToAXI4.scala:272:28, :274:26]
wire inc_35 = a_sel_35 & _inc_T_35; // @[Decoupled.scala:51:35]
wire _dec_T_70 = d_sel_35 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_35 = _dec_T_70 & _dec_T_71; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_140 = {1'h0, count_35} + {1'h0, inc_35}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_141 = _count_T_140[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_142 = {1'h0, _count_T_141} - {1'h0, dec_35}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_143 = _count_T_142[0]; // @[ToAXI4.scala:278:37]
wire _idStall_35_T = ~idle_35; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_35_T_3 = _idStall_35_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_35 = _idStall_35_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_36; // @[ToAXI4.scala:272:28]
wire _idStall_36_T_2 = count_36; // @[ToAXI4.scala:272:28, :286:44]
reg write_36; // @[ToAXI4.scala:273:24]
wire idle_36 = ~count_36; // @[ToAXI4.scala:272:28, :274:26]
wire inc_36 = a_sel_36 & _inc_T_36; // @[Decoupled.scala:51:35]
wire _dec_T_72 = d_sel_36 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_36 = _dec_T_72 & _dec_T_73; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_144 = {1'h0, count_36} + {1'h0, inc_36}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_145 = _count_T_144[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_146 = {1'h0, _count_T_145} - {1'h0, dec_36}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_147 = _count_T_146[0]; // @[ToAXI4.scala:278:37]
wire _idStall_36_T = ~idle_36; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_36_T_3 = _idStall_36_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_36 = _idStall_36_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_37; // @[ToAXI4.scala:272:28]
wire _idStall_37_T_2 = count_37; // @[ToAXI4.scala:272:28, :286:44]
reg write_37; // @[ToAXI4.scala:273:24]
wire idle_37 = ~count_37; // @[ToAXI4.scala:272:28, :274:26]
wire inc_37 = a_sel_37 & _inc_T_37; // @[Decoupled.scala:51:35]
wire _dec_T_74 = d_sel_37 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_37 = _dec_T_74 & _dec_T_75; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_148 = {1'h0, count_37} + {1'h0, inc_37}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_149 = _count_T_148[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_150 = {1'h0, _count_T_149} - {1'h0, dec_37}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_151 = _count_T_150[0]; // @[ToAXI4.scala:278:37]
wire _idStall_37_T = ~idle_37; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_37_T_3 = _idStall_37_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_37 = _idStall_37_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_38; // @[ToAXI4.scala:272:28]
wire _idStall_38_T_2 = count_38; // @[ToAXI4.scala:272:28, :286:44]
reg write_38; // @[ToAXI4.scala:273:24]
wire idle_38 = ~count_38; // @[ToAXI4.scala:272:28, :274:26]
wire inc_38 = a_sel_38 & _inc_T_38; // @[Decoupled.scala:51:35]
wire _dec_T_76 = d_sel_38 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_38 = _dec_T_76 & _dec_T_77; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_152 = {1'h0, count_38} + {1'h0, inc_38}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_153 = _count_T_152[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_154 = {1'h0, _count_T_153} - {1'h0, dec_38}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_155 = _count_T_154[0]; // @[ToAXI4.scala:278:37]
wire _idStall_38_T = ~idle_38; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_38_T_3 = _idStall_38_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_38 = _idStall_38_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_39; // @[ToAXI4.scala:272:28]
wire _idStall_39_T_2 = count_39; // @[ToAXI4.scala:272:28, :286:44]
reg write_39; // @[ToAXI4.scala:273:24]
wire idle_39 = ~count_39; // @[ToAXI4.scala:272:28, :274:26]
wire inc_39 = a_sel_39 & _inc_T_39; // @[Decoupled.scala:51:35]
wire _dec_T_78 = d_sel_39 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_39 = _dec_T_78 & _dec_T_79; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_156 = {1'h0, count_39} + {1'h0, inc_39}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_157 = _count_T_156[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_158 = {1'h0, _count_T_157} - {1'h0, dec_39}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_159 = _count_T_158[0]; // @[ToAXI4.scala:278:37]
wire _idStall_39_T = ~idle_39; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_39_T_3 = _idStall_39_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_39 = _idStall_39_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_40; // @[ToAXI4.scala:272:28]
wire _idStall_40_T_2 = count_40; // @[ToAXI4.scala:272:28, :286:44]
reg write_40; // @[ToAXI4.scala:273:24]
wire idle_40 = ~count_40; // @[ToAXI4.scala:272:28, :274:26]
wire inc_40 = a_sel_40 & _inc_T_40; // @[Decoupled.scala:51:35]
wire _dec_T_80 = d_sel_40 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_40 = _dec_T_80 & _dec_T_81; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_160 = {1'h0, count_40} + {1'h0, inc_40}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_161 = _count_T_160[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_162 = {1'h0, _count_T_161} - {1'h0, dec_40}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_163 = _count_T_162[0]; // @[ToAXI4.scala:278:37]
wire _idStall_40_T = ~idle_40; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_40_T_3 = _idStall_40_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_40 = _idStall_40_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_41; // @[ToAXI4.scala:272:28]
wire _idStall_41_T_2 = count_41; // @[ToAXI4.scala:272:28, :286:44]
reg write_41; // @[ToAXI4.scala:273:24]
wire idle_41 = ~count_41; // @[ToAXI4.scala:272:28, :274:26]
wire inc_41 = a_sel_41 & _inc_T_41; // @[Decoupled.scala:51:35]
wire _dec_T_82 = d_sel_41 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_41 = _dec_T_82 & _dec_T_83; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_164 = {1'h0, count_41} + {1'h0, inc_41}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_165 = _count_T_164[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_166 = {1'h0, _count_T_165} - {1'h0, dec_41}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_167 = _count_T_166[0]; // @[ToAXI4.scala:278:37]
wire _idStall_41_T = ~idle_41; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_41_T_3 = _idStall_41_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_41 = _idStall_41_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_42; // @[ToAXI4.scala:272:28]
wire _idStall_42_T_2 = count_42; // @[ToAXI4.scala:272:28, :286:44]
reg write_42; // @[ToAXI4.scala:273:24]
wire idle_42 = ~count_42; // @[ToAXI4.scala:272:28, :274:26]
wire inc_42 = a_sel_42 & _inc_T_42; // @[Decoupled.scala:51:35]
wire _dec_T_84 = d_sel_42 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_42 = _dec_T_84 & _dec_T_85; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_168 = {1'h0, count_42} + {1'h0, inc_42}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_169 = _count_T_168[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_170 = {1'h0, _count_T_169} - {1'h0, dec_42}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_171 = _count_T_170[0]; // @[ToAXI4.scala:278:37]
wire _idStall_42_T = ~idle_42; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_42_T_3 = _idStall_42_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_42 = _idStall_42_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_43; // @[ToAXI4.scala:272:28]
wire _idStall_43_T_2 = count_43; // @[ToAXI4.scala:272:28, :286:44]
reg write_43; // @[ToAXI4.scala:273:24]
wire idle_43 = ~count_43; // @[ToAXI4.scala:272:28, :274:26]
wire inc_43 = a_sel_43 & _inc_T_43; // @[Decoupled.scala:51:35]
wire _dec_T_86 = d_sel_43 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_43 = _dec_T_86 & _dec_T_87; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_172 = {1'h0, count_43} + {1'h0, inc_43}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_173 = _count_T_172[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_174 = {1'h0, _count_T_173} - {1'h0, dec_43}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_175 = _count_T_174[0]; // @[ToAXI4.scala:278:37]
wire _idStall_43_T = ~idle_43; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_43_T_3 = _idStall_43_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_43 = _idStall_43_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_44; // @[ToAXI4.scala:272:28]
wire _idStall_44_T_2 = count_44; // @[ToAXI4.scala:272:28, :286:44]
reg write_44; // @[ToAXI4.scala:273:24]
wire idle_44 = ~count_44; // @[ToAXI4.scala:272:28, :274:26]
wire inc_44 = a_sel_44 & _inc_T_44; // @[Decoupled.scala:51:35]
wire _dec_T_88 = d_sel_44 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_44 = _dec_T_88 & _dec_T_89; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_176 = {1'h0, count_44} + {1'h0, inc_44}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_177 = _count_T_176[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_178 = {1'h0, _count_T_177} - {1'h0, dec_44}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_179 = _count_T_178[0]; // @[ToAXI4.scala:278:37]
wire _idStall_44_T = ~idle_44; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_44_T_3 = _idStall_44_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_44 = _idStall_44_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_45; // @[ToAXI4.scala:272:28]
wire _idStall_45_T_2 = count_45; // @[ToAXI4.scala:272:28, :286:44]
reg write_45; // @[ToAXI4.scala:273:24]
wire idle_45 = ~count_45; // @[ToAXI4.scala:272:28, :274:26]
wire inc_45 = a_sel_45 & _inc_T_45; // @[Decoupled.scala:51:35]
wire _dec_T_90 = d_sel_45 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_45 = _dec_T_90 & _dec_T_91; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_180 = {1'h0, count_45} + {1'h0, inc_45}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_181 = _count_T_180[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_182 = {1'h0, _count_T_181} - {1'h0, dec_45}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_183 = _count_T_182[0]; // @[ToAXI4.scala:278:37]
wire _idStall_45_T = ~idle_45; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_45_T_3 = _idStall_45_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_45 = _idStall_45_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_46; // @[ToAXI4.scala:272:28]
wire _idStall_46_T_2 = count_46; // @[ToAXI4.scala:272:28, :286:44]
reg write_46; // @[ToAXI4.scala:273:24]
wire idle_46 = ~count_46; // @[ToAXI4.scala:272:28, :274:26]
wire inc_46 = a_sel_46 & _inc_T_46; // @[Decoupled.scala:51:35]
wire _dec_T_92 = d_sel_46 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_46 = _dec_T_92 & _dec_T_93; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_184 = {1'h0, count_46} + {1'h0, inc_46}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_185 = _count_T_184[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_186 = {1'h0, _count_T_185} - {1'h0, dec_46}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_187 = _count_T_186[0]; // @[ToAXI4.scala:278:37]
wire _idStall_46_T = ~idle_46; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_46_T_3 = _idStall_46_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_46 = _idStall_46_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_47; // @[ToAXI4.scala:272:28]
wire _idStall_47_T_2 = count_47; // @[ToAXI4.scala:272:28, :286:44]
reg write_47; // @[ToAXI4.scala:273:24]
wire idle_47 = ~count_47; // @[ToAXI4.scala:272:28, :274:26]
wire inc_47 = a_sel_47 & _inc_T_47; // @[Decoupled.scala:51:35]
wire _dec_T_94 = d_sel_47 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_47 = _dec_T_94 & _dec_T_95; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_188 = {1'h0, count_47} + {1'h0, inc_47}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_189 = _count_T_188[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_190 = {1'h0, _count_T_189} - {1'h0, dec_47}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_191 = _count_T_190[0]; // @[ToAXI4.scala:278:37]
wire _idStall_47_T = ~idle_47; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_47_T_3 = _idStall_47_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_47 = _idStall_47_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_48; // @[ToAXI4.scala:272:28]
wire _idStall_48_T_2 = count_48; // @[ToAXI4.scala:272:28, :286:44]
reg write_48; // @[ToAXI4.scala:273:24]
wire idle_48 = ~count_48; // @[ToAXI4.scala:272:28, :274:26]
wire inc_48 = a_sel_48 & _inc_T_48; // @[Decoupled.scala:51:35]
wire _dec_T_96 = d_sel_48 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_48 = _dec_T_96 & _dec_T_97; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_192 = {1'h0, count_48} + {1'h0, inc_48}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_193 = _count_T_192[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_194 = {1'h0, _count_T_193} - {1'h0, dec_48}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_195 = _count_T_194[0]; // @[ToAXI4.scala:278:37]
wire _idStall_48_T = ~idle_48; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_48_T_3 = _idStall_48_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_48 = _idStall_48_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_49; // @[ToAXI4.scala:272:28]
wire _idStall_49_T_2 = count_49; // @[ToAXI4.scala:272:28, :286:44]
reg write_49; // @[ToAXI4.scala:273:24]
wire idle_49 = ~count_49; // @[ToAXI4.scala:272:28, :274:26]
wire inc_49 = a_sel_49 & _inc_T_49; // @[Decoupled.scala:51:35]
wire _dec_T_98 = d_sel_49 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_49 = _dec_T_98 & _dec_T_99; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_196 = {1'h0, count_49} + {1'h0, inc_49}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_197 = _count_T_196[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_198 = {1'h0, _count_T_197} - {1'h0, dec_49}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_199 = _count_T_198[0]; // @[ToAXI4.scala:278:37]
wire _idStall_49_T = ~idle_49; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_49_T_3 = _idStall_49_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_49 = _idStall_49_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_50; // @[ToAXI4.scala:272:28]
wire _idStall_50_T_2 = count_50; // @[ToAXI4.scala:272:28, :286:44]
reg write_50; // @[ToAXI4.scala:273:24]
wire idle_50 = ~count_50; // @[ToAXI4.scala:272:28, :274:26]
wire inc_50 = a_sel_50 & _inc_T_50; // @[Decoupled.scala:51:35]
wire _dec_T_100 = d_sel_50 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_50 = _dec_T_100 & _dec_T_101; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_200 = {1'h0, count_50} + {1'h0, inc_50}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_201 = _count_T_200[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_202 = {1'h0, _count_T_201} - {1'h0, dec_50}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_203 = _count_T_202[0]; // @[ToAXI4.scala:278:37]
wire _idStall_50_T = ~idle_50; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_50_T_3 = _idStall_50_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_50 = _idStall_50_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_51; // @[ToAXI4.scala:272:28]
wire _idStall_51_T_2 = count_51; // @[ToAXI4.scala:272:28, :286:44]
reg write_51; // @[ToAXI4.scala:273:24]
wire idle_51 = ~count_51; // @[ToAXI4.scala:272:28, :274:26]
wire inc_51 = a_sel_51 & _inc_T_51; // @[Decoupled.scala:51:35]
wire _dec_T_102 = d_sel_51 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_51 = _dec_T_102 & _dec_T_103; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_204 = {1'h0, count_51} + {1'h0, inc_51}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_205 = _count_T_204[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_206 = {1'h0, _count_T_205} - {1'h0, dec_51}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_207 = _count_T_206[0]; // @[ToAXI4.scala:278:37]
wire _idStall_51_T = ~idle_51; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_51_T_3 = _idStall_51_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_51 = _idStall_51_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_52; // @[ToAXI4.scala:272:28]
wire _idStall_52_T_2 = count_52; // @[ToAXI4.scala:272:28, :286:44]
reg write_52; // @[ToAXI4.scala:273:24]
wire idle_52 = ~count_52; // @[ToAXI4.scala:272:28, :274:26]
wire inc_52 = a_sel_52 & _inc_T_52; // @[Decoupled.scala:51:35]
wire _dec_T_104 = d_sel_52 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_52 = _dec_T_104 & _dec_T_105; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_208 = {1'h0, count_52} + {1'h0, inc_52}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_209 = _count_T_208[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_210 = {1'h0, _count_T_209} - {1'h0, dec_52}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_211 = _count_T_210[0]; // @[ToAXI4.scala:278:37]
wire _idStall_52_T = ~idle_52; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_52_T_3 = _idStall_52_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_52 = _idStall_52_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_53; // @[ToAXI4.scala:272:28]
wire _idStall_53_T_2 = count_53; // @[ToAXI4.scala:272:28, :286:44]
reg write_53; // @[ToAXI4.scala:273:24]
wire idle_53 = ~count_53; // @[ToAXI4.scala:272:28, :274:26]
wire inc_53 = a_sel_53 & _inc_T_53; // @[Decoupled.scala:51:35]
wire _dec_T_106 = d_sel_53 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_53 = _dec_T_106 & _dec_T_107; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_212 = {1'h0, count_53} + {1'h0, inc_53}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_213 = _count_T_212[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_214 = {1'h0, _count_T_213} - {1'h0, dec_53}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_215 = _count_T_214[0]; // @[ToAXI4.scala:278:37]
wire _idStall_53_T = ~idle_53; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_53_T_3 = _idStall_53_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_53 = _idStall_53_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_54; // @[ToAXI4.scala:272:28]
wire _idStall_54_T_2 = count_54; // @[ToAXI4.scala:272:28, :286:44]
reg write_54; // @[ToAXI4.scala:273:24]
wire idle_54 = ~count_54; // @[ToAXI4.scala:272:28, :274:26]
wire inc_54 = a_sel_54 & _inc_T_54; // @[Decoupled.scala:51:35]
wire _dec_T_108 = d_sel_54 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_54 = _dec_T_108 & _dec_T_109; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_216 = {1'h0, count_54} + {1'h0, inc_54}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_217 = _count_T_216[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_218 = {1'h0, _count_T_217} - {1'h0, dec_54}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_219 = _count_T_218[0]; // @[ToAXI4.scala:278:37]
wire _idStall_54_T = ~idle_54; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_54_T_3 = _idStall_54_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_54 = _idStall_54_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_55; // @[ToAXI4.scala:272:28]
wire _idStall_55_T_2 = count_55; // @[ToAXI4.scala:272:28, :286:44]
reg write_55; // @[ToAXI4.scala:273:24]
wire idle_55 = ~count_55; // @[ToAXI4.scala:272:28, :274:26]
wire inc_55 = a_sel_55 & _inc_T_55; // @[Decoupled.scala:51:35]
wire _dec_T_110 = d_sel_55 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_55 = _dec_T_110 & _dec_T_111; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_220 = {1'h0, count_55} + {1'h0, inc_55}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_221 = _count_T_220[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_222 = {1'h0, _count_T_221} - {1'h0, dec_55}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_223 = _count_T_222[0]; // @[ToAXI4.scala:278:37]
wire _idStall_55_T = ~idle_55; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_55_T_3 = _idStall_55_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_55 = _idStall_55_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_56; // @[ToAXI4.scala:272:28]
wire _idStall_56_T_2 = count_56; // @[ToAXI4.scala:272:28, :286:44]
reg write_56; // @[ToAXI4.scala:273:24]
wire idle_56 = ~count_56; // @[ToAXI4.scala:272:28, :274:26]
wire inc_56 = a_sel_56 & _inc_T_56; // @[Decoupled.scala:51:35]
wire _dec_T_112 = d_sel_56 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_56 = _dec_T_112 & _dec_T_113; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_224 = {1'h0, count_56} + {1'h0, inc_56}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_225 = _count_T_224[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_226 = {1'h0, _count_T_225} - {1'h0, dec_56}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_227 = _count_T_226[0]; // @[ToAXI4.scala:278:37]
wire _idStall_56_T = ~idle_56; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_56_T_3 = _idStall_56_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_56 = _idStall_56_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_57; // @[ToAXI4.scala:272:28]
wire _idStall_57_T_2 = count_57; // @[ToAXI4.scala:272:28, :286:44]
reg write_57; // @[ToAXI4.scala:273:24]
wire idle_57 = ~count_57; // @[ToAXI4.scala:272:28, :274:26]
wire inc_57 = a_sel_57 & _inc_T_57; // @[Decoupled.scala:51:35]
wire _dec_T_114 = d_sel_57 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_57 = _dec_T_114 & _dec_T_115; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_228 = {1'h0, count_57} + {1'h0, inc_57}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_229 = _count_T_228[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_230 = {1'h0, _count_T_229} - {1'h0, dec_57}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_231 = _count_T_230[0]; // @[ToAXI4.scala:278:37]
wire _idStall_57_T = ~idle_57; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_57_T_3 = _idStall_57_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_57 = _idStall_57_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_58; // @[ToAXI4.scala:272:28]
wire _idStall_58_T_2 = count_58; // @[ToAXI4.scala:272:28, :286:44]
reg write_58; // @[ToAXI4.scala:273:24]
wire idle_58 = ~count_58; // @[ToAXI4.scala:272:28, :274:26]
wire inc_58 = a_sel_58 & _inc_T_58; // @[Decoupled.scala:51:35]
wire _dec_T_116 = d_sel_58 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_58 = _dec_T_116 & _dec_T_117; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_232 = {1'h0, count_58} + {1'h0, inc_58}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_233 = _count_T_232[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_234 = {1'h0, _count_T_233} - {1'h0, dec_58}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_235 = _count_T_234[0]; // @[ToAXI4.scala:278:37]
wire _idStall_58_T = ~idle_58; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_58_T_3 = _idStall_58_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_58 = _idStall_58_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_59; // @[ToAXI4.scala:272:28]
wire _idStall_59_T_2 = count_59; // @[ToAXI4.scala:272:28, :286:44]
reg write_59; // @[ToAXI4.scala:273:24]
wire idle_59 = ~count_59; // @[ToAXI4.scala:272:28, :274:26]
wire inc_59 = a_sel_59 & _inc_T_59; // @[Decoupled.scala:51:35]
wire _dec_T_118 = d_sel_59 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_59 = _dec_T_118 & _dec_T_119; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_236 = {1'h0, count_59} + {1'h0, inc_59}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_237 = _count_T_236[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_238 = {1'h0, _count_T_237} - {1'h0, dec_59}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_239 = _count_T_238[0]; // @[ToAXI4.scala:278:37]
wire _idStall_59_T = ~idle_59; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_59_T_3 = _idStall_59_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_59 = _idStall_59_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_60; // @[ToAXI4.scala:272:28]
wire _idStall_60_T_2 = count_60; // @[ToAXI4.scala:272:28, :286:44]
reg write_60; // @[ToAXI4.scala:273:24]
wire idle_60 = ~count_60; // @[ToAXI4.scala:272:28, :274:26]
wire inc_60 = a_sel_60 & _inc_T_60; // @[Decoupled.scala:51:35]
wire _dec_T_120 = d_sel_60 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_60 = _dec_T_120 & _dec_T_121; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_240 = {1'h0, count_60} + {1'h0, inc_60}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_241 = _count_T_240[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_242 = {1'h0, _count_T_241} - {1'h0, dec_60}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_243 = _count_T_242[0]; // @[ToAXI4.scala:278:37]
wire _idStall_60_T = ~idle_60; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_60_T_3 = _idStall_60_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_60 = _idStall_60_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_61; // @[ToAXI4.scala:272:28]
wire _idStall_61_T_2 = count_61; // @[ToAXI4.scala:272:28, :286:44]
reg write_61; // @[ToAXI4.scala:273:24]
wire idle_61 = ~count_61; // @[ToAXI4.scala:272:28, :274:26]
wire inc_61 = a_sel_61 & _inc_T_61; // @[Decoupled.scala:51:35]
wire _dec_T_122 = d_sel_61 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_61 = _dec_T_122 & _dec_T_123; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_244 = {1'h0, count_61} + {1'h0, inc_61}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_245 = _count_T_244[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_246 = {1'h0, _count_T_245} - {1'h0, dec_61}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_247 = _count_T_246[0]; // @[ToAXI4.scala:278:37]
wire _idStall_61_T = ~idle_61; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_61_T_3 = _idStall_61_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_61 = _idStall_61_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_62; // @[ToAXI4.scala:272:28]
wire _idStall_62_T_2 = count_62; // @[ToAXI4.scala:272:28, :286:44]
reg write_62; // @[ToAXI4.scala:273:24]
wire idle_62 = ~count_62; // @[ToAXI4.scala:272:28, :274:26]
wire inc_62 = a_sel_62 & _inc_T_62; // @[Decoupled.scala:51:35]
wire _dec_T_124 = d_sel_62 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_62 = _dec_T_124 & _dec_T_125; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_248 = {1'h0, count_62} + {1'h0, inc_62}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_249 = _count_T_248[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_250 = {1'h0, _count_T_249} - {1'h0, dec_62}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_251 = _count_T_250[0]; // @[ToAXI4.scala:278:37]
wire _idStall_62_T = ~idle_62; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_62_T_3 = _idStall_62_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_62 = _idStall_62_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_63; // @[ToAXI4.scala:272:28]
wire _idStall_63_T_2 = count_63; // @[ToAXI4.scala:272:28, :286:44]
reg write_63; // @[ToAXI4.scala:273:24]
wire idle_63 = ~count_63; // @[ToAXI4.scala:272:28, :274:26]
wire inc_63 = a_sel_63 & _inc_T_63; // @[Decoupled.scala:51:35]
wire _dec_T_126 = d_sel_63 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_63 = _dec_T_126 & _dec_T_127; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_252 = {1'h0, count_63} + {1'h0, inc_63}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_253 = _count_T_252[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_254 = {1'h0, _count_T_253} - {1'h0, dec_63}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_255 = _count_T_254[0]; // @[ToAXI4.scala:278:37]
wire _idStall_63_T = ~idle_63; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_63_T_3 = _idStall_63_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_63 = _idStall_63_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_64; // @[ToAXI4.scala:272:28]
wire _idStall_64_T_2 = count_64; // @[ToAXI4.scala:272:28, :286:44]
reg write_64; // @[ToAXI4.scala:273:24]
wire idle_64 = ~count_64; // @[ToAXI4.scala:272:28, :274:26]
wire inc_64 = a_sel_64 & _inc_T_64; // @[Decoupled.scala:51:35]
wire _dec_T_128 = d_sel_64 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_64 = _dec_T_128 & _dec_T_129; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_256 = {1'h0, count_64} + {1'h0, inc_64}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_257 = _count_T_256[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_258 = {1'h0, _count_T_257} - {1'h0, dec_64}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_259 = _count_T_258[0]; // @[ToAXI4.scala:278:37]
wire _idStall_64_T = ~idle_64; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_64_T_3 = _idStall_64_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_64 = _idStall_64_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_65; // @[ToAXI4.scala:272:28]
wire _idStall_65_T_2 = count_65; // @[ToAXI4.scala:272:28, :286:44]
reg write_65; // @[ToAXI4.scala:273:24]
wire idle_65 = ~count_65; // @[ToAXI4.scala:272:28, :274:26]
wire inc_65 = a_sel_65 & _inc_T_65; // @[Decoupled.scala:51:35]
wire _dec_T_130 = d_sel_65 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_65 = _dec_T_130 & _dec_T_131; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_260 = {1'h0, count_65} + {1'h0, inc_65}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_261 = _count_T_260[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_262 = {1'h0, _count_T_261} - {1'h0, dec_65}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_263 = _count_T_262[0]; // @[ToAXI4.scala:278:37]
wire _idStall_65_T = ~idle_65; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_65_T_3 = _idStall_65_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_65 = _idStall_65_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_66; // @[ToAXI4.scala:272:28]
wire _idStall_66_T_2 = count_66; // @[ToAXI4.scala:272:28, :286:44]
reg write_66; // @[ToAXI4.scala:273:24]
wire idle_66 = ~count_66; // @[ToAXI4.scala:272:28, :274:26]
wire inc_66 = a_sel_66 & _inc_T_66; // @[Decoupled.scala:51:35]
wire _dec_T_132 = d_sel_66 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_66 = _dec_T_132 & _dec_T_133; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_264 = {1'h0, count_66} + {1'h0, inc_66}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_265 = _count_T_264[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_266 = {1'h0, _count_T_265} - {1'h0, dec_66}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_267 = _count_T_266[0]; // @[ToAXI4.scala:278:37]
wire _idStall_66_T = ~idle_66; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_66_T_3 = _idStall_66_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_66 = _idStall_66_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_67; // @[ToAXI4.scala:272:28]
wire _idStall_67_T_2 = count_67; // @[ToAXI4.scala:272:28, :286:44]
reg write_67; // @[ToAXI4.scala:273:24]
wire idle_67 = ~count_67; // @[ToAXI4.scala:272:28, :274:26]
wire inc_67 = a_sel_67 & _inc_T_67; // @[Decoupled.scala:51:35]
wire _dec_T_134 = d_sel_67 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_67 = _dec_T_134 & _dec_T_135; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_268 = {1'h0, count_67} + {1'h0, inc_67}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_269 = _count_T_268[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_270 = {1'h0, _count_T_269} - {1'h0, dec_67}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_271 = _count_T_270[0]; // @[ToAXI4.scala:278:37]
wire _idStall_67_T = ~idle_67; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_67_T_3 = _idStall_67_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_67 = _idStall_67_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_68; // @[ToAXI4.scala:272:28]
wire _idStall_68_T_2 = count_68; // @[ToAXI4.scala:272:28, :286:44]
reg write_68; // @[ToAXI4.scala:273:24]
wire idle_68 = ~count_68; // @[ToAXI4.scala:272:28, :274:26]
wire inc_68 = a_sel_68 & _inc_T_68; // @[Decoupled.scala:51:35]
wire _dec_T_136 = d_sel_68 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_68 = _dec_T_136 & _dec_T_137; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_272 = {1'h0, count_68} + {1'h0, inc_68}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_273 = _count_T_272[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_274 = {1'h0, _count_T_273} - {1'h0, dec_68}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_275 = _count_T_274[0]; // @[ToAXI4.scala:278:37]
wire _idStall_68_T = ~idle_68; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_68_T_3 = _idStall_68_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_68 = _idStall_68_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_69; // @[ToAXI4.scala:272:28]
wire _idStall_69_T_2 = count_69; // @[ToAXI4.scala:272:28, :286:44]
reg write_69; // @[ToAXI4.scala:273:24]
wire idle_69 = ~count_69; // @[ToAXI4.scala:272:28, :274:26]
wire inc_69 = a_sel_69 & _inc_T_69; // @[Decoupled.scala:51:35]
wire _dec_T_138 = d_sel_69 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_69 = _dec_T_138 & _dec_T_139; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_276 = {1'h0, count_69} + {1'h0, inc_69}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_277 = _count_T_276[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_278 = {1'h0, _count_T_277} - {1'h0, dec_69}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_279 = _count_T_278[0]; // @[ToAXI4.scala:278:37]
wire _idStall_69_T = ~idle_69; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_69_T_3 = _idStall_69_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_69 = _idStall_69_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_70; // @[ToAXI4.scala:272:28]
wire _idStall_70_T_2 = count_70; // @[ToAXI4.scala:272:28, :286:44]
reg write_70; // @[ToAXI4.scala:273:24]
wire idle_70 = ~count_70; // @[ToAXI4.scala:272:28, :274:26]
wire inc_70 = a_sel_70 & _inc_T_70; // @[Decoupled.scala:51:35]
wire _dec_T_140 = d_sel_70 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_70 = _dec_T_140 & _dec_T_141; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_280 = {1'h0, count_70} + {1'h0, inc_70}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_281 = _count_T_280[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_282 = {1'h0, _count_T_281} - {1'h0, dec_70}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_283 = _count_T_282[0]; // @[ToAXI4.scala:278:37]
wire _idStall_70_T = ~idle_70; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_70_T_3 = _idStall_70_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_70 = _idStall_70_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_71; // @[ToAXI4.scala:272:28]
wire _idStall_71_T_2 = count_71; // @[ToAXI4.scala:272:28, :286:44]
reg write_71; // @[ToAXI4.scala:273:24]
wire idle_71 = ~count_71; // @[ToAXI4.scala:272:28, :274:26]
wire inc_71 = a_sel_71 & _inc_T_71; // @[Decoupled.scala:51:35]
wire _dec_T_142 = d_sel_71 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_71 = _dec_T_142 & _dec_T_143; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_284 = {1'h0, count_71} + {1'h0, inc_71}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_285 = _count_T_284[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_286 = {1'h0, _count_T_285} - {1'h0, dec_71}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_287 = _count_T_286[0]; // @[ToAXI4.scala:278:37]
wire _idStall_71_T = ~idle_71; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_71_T_3 = _idStall_71_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_71 = _idStall_71_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_72; // @[ToAXI4.scala:272:28]
wire _idStall_72_T_2 = count_72; // @[ToAXI4.scala:272:28, :286:44]
reg write_72; // @[ToAXI4.scala:273:24]
wire idle_72 = ~count_72; // @[ToAXI4.scala:272:28, :274:26]
wire inc_72 = a_sel_72 & _inc_T_72; // @[Decoupled.scala:51:35]
wire _dec_T_144 = d_sel_72 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_72 = _dec_T_144 & _dec_T_145; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_288 = {1'h0, count_72} + {1'h0, inc_72}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_289 = _count_T_288[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_290 = {1'h0, _count_T_289} - {1'h0, dec_72}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_291 = _count_T_290[0]; // @[ToAXI4.scala:278:37]
wire _idStall_72_T = ~idle_72; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_72_T_3 = _idStall_72_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_72 = _idStall_72_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_73; // @[ToAXI4.scala:272:28]
wire _idStall_73_T_2 = count_73; // @[ToAXI4.scala:272:28, :286:44]
reg write_73; // @[ToAXI4.scala:273:24]
wire idle_73 = ~count_73; // @[ToAXI4.scala:272:28, :274:26]
wire inc_73 = a_sel_73 & _inc_T_73; // @[Decoupled.scala:51:35]
wire _dec_T_146 = d_sel_73 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_73 = _dec_T_146 & _dec_T_147; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_292 = {1'h0, count_73} + {1'h0, inc_73}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_293 = _count_T_292[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_294 = {1'h0, _count_T_293} - {1'h0, dec_73}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_295 = _count_T_294[0]; // @[ToAXI4.scala:278:37]
wire _idStall_73_T = ~idle_73; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_73_T_3 = _idStall_73_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_73 = _idStall_73_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_74; // @[ToAXI4.scala:272:28]
wire _idStall_74_T_2 = count_74; // @[ToAXI4.scala:272:28, :286:44]
reg write_74; // @[ToAXI4.scala:273:24]
wire idle_74 = ~count_74; // @[ToAXI4.scala:272:28, :274:26]
wire inc_74 = a_sel_74 & _inc_T_74; // @[Decoupled.scala:51:35]
wire _dec_T_148 = d_sel_74 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_74 = _dec_T_148 & _dec_T_149; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_296 = {1'h0, count_74} + {1'h0, inc_74}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_297 = _count_T_296[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_298 = {1'h0, _count_T_297} - {1'h0, dec_74}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_299 = _count_T_298[0]; // @[ToAXI4.scala:278:37]
wire _idStall_74_T = ~idle_74; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_74_T_3 = _idStall_74_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_74 = _idStall_74_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_75; // @[ToAXI4.scala:272:28]
wire _idStall_75_T_2 = count_75; // @[ToAXI4.scala:272:28, :286:44]
reg write_75; // @[ToAXI4.scala:273:24]
wire idle_75 = ~count_75; // @[ToAXI4.scala:272:28, :274:26]
wire inc_75 = a_sel_75 & _inc_T_75; // @[Decoupled.scala:51:35]
wire _dec_T_150 = d_sel_75 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_75 = _dec_T_150 & _dec_T_151; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_300 = {1'h0, count_75} + {1'h0, inc_75}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_301 = _count_T_300[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_302 = {1'h0, _count_T_301} - {1'h0, dec_75}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_303 = _count_T_302[0]; // @[ToAXI4.scala:278:37]
wire _idStall_75_T = ~idle_75; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_75_T_3 = _idStall_75_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_75 = _idStall_75_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_76; // @[ToAXI4.scala:272:28]
wire _idStall_76_T_2 = count_76; // @[ToAXI4.scala:272:28, :286:44]
reg write_76; // @[ToAXI4.scala:273:24]
wire idle_76 = ~count_76; // @[ToAXI4.scala:272:28, :274:26]
wire inc_76 = a_sel_76 & _inc_T_76; // @[Decoupled.scala:51:35]
wire _dec_T_152 = d_sel_76 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_76 = _dec_T_152 & _dec_T_153; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_304 = {1'h0, count_76} + {1'h0, inc_76}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_305 = _count_T_304[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_306 = {1'h0, _count_T_305} - {1'h0, dec_76}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_307 = _count_T_306[0]; // @[ToAXI4.scala:278:37]
wire _idStall_76_T = ~idle_76; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_76_T_3 = _idStall_76_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_76 = _idStall_76_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_77; // @[ToAXI4.scala:272:28]
wire _idStall_77_T_2 = count_77; // @[ToAXI4.scala:272:28, :286:44]
reg write_77; // @[ToAXI4.scala:273:24]
wire idle_77 = ~count_77; // @[ToAXI4.scala:272:28, :274:26]
wire inc_77 = a_sel_77 & _inc_T_77; // @[Decoupled.scala:51:35]
wire _dec_T_154 = d_sel_77 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_77 = _dec_T_154 & _dec_T_155; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_308 = {1'h0, count_77} + {1'h0, inc_77}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_309 = _count_T_308[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_310 = {1'h0, _count_T_309} - {1'h0, dec_77}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_311 = _count_T_310[0]; // @[ToAXI4.scala:278:37]
wire _idStall_77_T = ~idle_77; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_77_T_3 = _idStall_77_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_77 = _idStall_77_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_78; // @[ToAXI4.scala:272:28]
wire _idStall_78_T_2 = count_78; // @[ToAXI4.scala:272:28, :286:44]
reg write_78; // @[ToAXI4.scala:273:24]
wire idle_78 = ~count_78; // @[ToAXI4.scala:272:28, :274:26]
wire inc_78 = a_sel_78 & _inc_T_78; // @[Decoupled.scala:51:35]
wire _dec_T_156 = d_sel_78 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_78 = _dec_T_156 & _dec_T_157; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_312 = {1'h0, count_78} + {1'h0, inc_78}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_313 = _count_T_312[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_314 = {1'h0, _count_T_313} - {1'h0, dec_78}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_315 = _count_T_314[0]; // @[ToAXI4.scala:278:37]
wire _idStall_78_T = ~idle_78; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_78_T_3 = _idStall_78_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_78 = _idStall_78_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_79; // @[ToAXI4.scala:272:28]
wire _idStall_79_T_2 = count_79; // @[ToAXI4.scala:272:28, :286:44]
reg write_79; // @[ToAXI4.scala:273:24]
wire idle_79 = ~count_79; // @[ToAXI4.scala:272:28, :274:26]
wire inc_79 = a_sel_79 & _inc_T_79; // @[Decoupled.scala:51:35]
wire _dec_T_158 = d_sel_79 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_79 = _dec_T_158 & _dec_T_159; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_316 = {1'h0, count_79} + {1'h0, inc_79}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_317 = _count_T_316[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_318 = {1'h0, _count_T_317} - {1'h0, dec_79}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_319 = _count_T_318[0]; // @[ToAXI4.scala:278:37]
wire _idStall_79_T = ~idle_79; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_79_T_3 = _idStall_79_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_79 = _idStall_79_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_80; // @[ToAXI4.scala:272:28]
wire _idStall_80_T_2 = count_80; // @[ToAXI4.scala:272:28, :286:44]
reg write_80; // @[ToAXI4.scala:273:24]
wire idle_80 = ~count_80; // @[ToAXI4.scala:272:28, :274:26]
wire inc_80 = a_sel_80 & _inc_T_80; // @[Decoupled.scala:51:35]
wire _dec_T_160 = d_sel_80 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_80 = _dec_T_160 & _dec_T_161; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_320 = {1'h0, count_80} + {1'h0, inc_80}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_321 = _count_T_320[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_322 = {1'h0, _count_T_321} - {1'h0, dec_80}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_323 = _count_T_322[0]; // @[ToAXI4.scala:278:37]
wire _idStall_80_T = ~idle_80; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_80_T_3 = _idStall_80_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_80 = _idStall_80_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_81; // @[ToAXI4.scala:272:28]
wire _idStall_81_T_2 = count_81; // @[ToAXI4.scala:272:28, :286:44]
reg write_81; // @[ToAXI4.scala:273:24]
wire idle_81 = ~count_81; // @[ToAXI4.scala:272:28, :274:26]
wire inc_81 = a_sel_81 & _inc_T_81; // @[Decoupled.scala:51:35]
wire _dec_T_162 = d_sel_81 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_81 = _dec_T_162 & _dec_T_163; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_324 = {1'h0, count_81} + {1'h0, inc_81}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_325 = _count_T_324[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_326 = {1'h0, _count_T_325} - {1'h0, dec_81}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_327 = _count_T_326[0]; // @[ToAXI4.scala:278:37]
wire _idStall_81_T = ~idle_81; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_81_T_3 = _idStall_81_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_81 = _idStall_81_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_82; // @[ToAXI4.scala:272:28]
wire _idStall_82_T_2 = count_82; // @[ToAXI4.scala:272:28, :286:44]
reg write_82; // @[ToAXI4.scala:273:24]
wire idle_82 = ~count_82; // @[ToAXI4.scala:272:28, :274:26]
wire inc_82 = a_sel_82 & _inc_T_82; // @[Decoupled.scala:51:35]
wire _dec_T_164 = d_sel_82 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_82 = _dec_T_164 & _dec_T_165; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_328 = {1'h0, count_82} + {1'h0, inc_82}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_329 = _count_T_328[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_330 = {1'h0, _count_T_329} - {1'h0, dec_82}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_331 = _count_T_330[0]; // @[ToAXI4.scala:278:37]
wire _idStall_82_T = ~idle_82; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_82_T_3 = _idStall_82_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_82 = _idStall_82_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_83; // @[ToAXI4.scala:272:28]
wire _idStall_83_T_2 = count_83; // @[ToAXI4.scala:272:28, :286:44]
reg write_83; // @[ToAXI4.scala:273:24]
wire idle_83 = ~count_83; // @[ToAXI4.scala:272:28, :274:26]
wire inc_83 = a_sel_83 & _inc_T_83; // @[Decoupled.scala:51:35]
wire _dec_T_166 = d_sel_83 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_83 = _dec_T_166 & _dec_T_167; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_332 = {1'h0, count_83} + {1'h0, inc_83}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_333 = _count_T_332[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_334 = {1'h0, _count_T_333} - {1'h0, dec_83}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_335 = _count_T_334[0]; // @[ToAXI4.scala:278:37]
wire _idStall_83_T = ~idle_83; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_83_T_3 = _idStall_83_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_83 = _idStall_83_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_84; // @[ToAXI4.scala:272:28]
wire _idStall_84_T_2 = count_84; // @[ToAXI4.scala:272:28, :286:44]
reg write_84; // @[ToAXI4.scala:273:24]
wire idle_84 = ~count_84; // @[ToAXI4.scala:272:28, :274:26]
wire inc_84 = a_sel_84 & _inc_T_84; // @[Decoupled.scala:51:35]
wire _dec_T_168 = d_sel_84 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_84 = _dec_T_168 & _dec_T_169; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_336 = {1'h0, count_84} + {1'h0, inc_84}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_337 = _count_T_336[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_338 = {1'h0, _count_T_337} - {1'h0, dec_84}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_339 = _count_T_338[0]; // @[ToAXI4.scala:278:37]
wire _idStall_84_T = ~idle_84; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_84_T_3 = _idStall_84_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_84 = _idStall_84_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_85; // @[ToAXI4.scala:272:28]
wire _idStall_85_T_2 = count_85; // @[ToAXI4.scala:272:28, :286:44]
reg write_85; // @[ToAXI4.scala:273:24]
wire idle_85 = ~count_85; // @[ToAXI4.scala:272:28, :274:26]
wire inc_85 = a_sel_85 & _inc_T_85; // @[Decoupled.scala:51:35]
wire _dec_T_170 = d_sel_85 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_85 = _dec_T_170 & _dec_T_171; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_340 = {1'h0, count_85} + {1'h0, inc_85}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_341 = _count_T_340[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_342 = {1'h0, _count_T_341} - {1'h0, dec_85}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_343 = _count_T_342[0]; // @[ToAXI4.scala:278:37]
wire _idStall_85_T = ~idle_85; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_85_T_3 = _idStall_85_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_85 = _idStall_85_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_86; // @[ToAXI4.scala:272:28]
wire _idStall_86_T_2 = count_86; // @[ToAXI4.scala:272:28, :286:44]
reg write_86; // @[ToAXI4.scala:273:24]
wire idle_86 = ~count_86; // @[ToAXI4.scala:272:28, :274:26]
wire inc_86 = a_sel_86 & _inc_T_86; // @[Decoupled.scala:51:35]
wire _dec_T_172 = d_sel_86 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_86 = _dec_T_172 & _dec_T_173; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_344 = {1'h0, count_86} + {1'h0, inc_86}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_345 = _count_T_344[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_346 = {1'h0, _count_T_345} - {1'h0, dec_86}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_347 = _count_T_346[0]; // @[ToAXI4.scala:278:37]
wire _idStall_86_T = ~idle_86; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_86_T_3 = _idStall_86_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_86 = _idStall_86_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_87; // @[ToAXI4.scala:272:28]
wire _idStall_87_T_2 = count_87; // @[ToAXI4.scala:272:28, :286:44]
reg write_87; // @[ToAXI4.scala:273:24]
wire idle_87 = ~count_87; // @[ToAXI4.scala:272:28, :274:26]
wire inc_87 = a_sel_87 & _inc_T_87; // @[Decoupled.scala:51:35]
wire _dec_T_174 = d_sel_87 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_87 = _dec_T_174 & _dec_T_175; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_348 = {1'h0, count_87} + {1'h0, inc_87}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_349 = _count_T_348[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_350 = {1'h0, _count_T_349} - {1'h0, dec_87}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_351 = _count_T_350[0]; // @[ToAXI4.scala:278:37]
wire _idStall_87_T = ~idle_87; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_87_T_3 = _idStall_87_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_87 = _idStall_87_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_88; // @[ToAXI4.scala:272:28]
wire _idStall_88_T_2 = count_88; // @[ToAXI4.scala:272:28, :286:44]
reg write_88; // @[ToAXI4.scala:273:24]
wire idle_88 = ~count_88; // @[ToAXI4.scala:272:28, :274:26]
wire inc_88 = a_sel_88 & _inc_T_88; // @[Decoupled.scala:51:35]
wire _dec_T_176 = d_sel_88 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_88 = _dec_T_176 & _dec_T_177; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_352 = {1'h0, count_88} + {1'h0, inc_88}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_353 = _count_T_352[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_354 = {1'h0, _count_T_353} - {1'h0, dec_88}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_355 = _count_T_354[0]; // @[ToAXI4.scala:278:37]
wire _idStall_88_T = ~idle_88; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_88_T_3 = _idStall_88_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_88 = _idStall_88_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_89; // @[ToAXI4.scala:272:28]
wire _idStall_89_T_2 = count_89; // @[ToAXI4.scala:272:28, :286:44]
reg write_89; // @[ToAXI4.scala:273:24]
wire idle_89 = ~count_89; // @[ToAXI4.scala:272:28, :274:26]
wire inc_89 = a_sel_89 & _inc_T_89; // @[Decoupled.scala:51:35]
wire _dec_T_178 = d_sel_89 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_89 = _dec_T_178 & _dec_T_179; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_356 = {1'h0, count_89} + {1'h0, inc_89}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_357 = _count_T_356[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_358 = {1'h0, _count_T_357} - {1'h0, dec_89}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_359 = _count_T_358[0]; // @[ToAXI4.scala:278:37]
wire _idStall_89_T = ~idle_89; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_89_T_3 = _idStall_89_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_89 = _idStall_89_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_90; // @[ToAXI4.scala:272:28]
wire _idStall_90_T_2 = count_90; // @[ToAXI4.scala:272:28, :286:44]
reg write_90; // @[ToAXI4.scala:273:24]
wire idle_90 = ~count_90; // @[ToAXI4.scala:272:28, :274:26]
wire inc_90 = a_sel_90 & _inc_T_90; // @[Decoupled.scala:51:35]
wire _dec_T_180 = d_sel_90 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_90 = _dec_T_180 & _dec_T_181; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_360 = {1'h0, count_90} + {1'h0, inc_90}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_361 = _count_T_360[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_362 = {1'h0, _count_T_361} - {1'h0, dec_90}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_363 = _count_T_362[0]; // @[ToAXI4.scala:278:37]
wire _idStall_90_T = ~idle_90; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_90_T_3 = _idStall_90_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_90 = _idStall_90_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_91; // @[ToAXI4.scala:272:28]
wire _idStall_91_T_2 = count_91; // @[ToAXI4.scala:272:28, :286:44]
reg write_91; // @[ToAXI4.scala:273:24]
wire idle_91 = ~count_91; // @[ToAXI4.scala:272:28, :274:26]
wire inc_91 = a_sel_91 & _inc_T_91; // @[Decoupled.scala:51:35]
wire _dec_T_182 = d_sel_91 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_91 = _dec_T_182 & _dec_T_183; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_364 = {1'h0, count_91} + {1'h0, inc_91}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_365 = _count_T_364[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_366 = {1'h0, _count_T_365} - {1'h0, dec_91}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_367 = _count_T_366[0]; // @[ToAXI4.scala:278:37]
wire _idStall_91_T = ~idle_91; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_91_T_3 = _idStall_91_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_91 = _idStall_91_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_92; // @[ToAXI4.scala:272:28]
wire _idStall_92_T_2 = count_92; // @[ToAXI4.scala:272:28, :286:44]
reg write_92; // @[ToAXI4.scala:273:24]
wire idle_92 = ~count_92; // @[ToAXI4.scala:272:28, :274:26]
wire inc_92 = a_sel_92 & _inc_T_92; // @[Decoupled.scala:51:35]
wire _dec_T_184 = d_sel_92 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_92 = _dec_T_184 & _dec_T_185; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_368 = {1'h0, count_92} + {1'h0, inc_92}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_369 = _count_T_368[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_370 = {1'h0, _count_T_369} - {1'h0, dec_92}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_371 = _count_T_370[0]; // @[ToAXI4.scala:278:37]
wire _idStall_92_T = ~idle_92; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_92_T_3 = _idStall_92_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_92 = _idStall_92_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_93; // @[ToAXI4.scala:272:28]
wire _idStall_93_T_2 = count_93; // @[ToAXI4.scala:272:28, :286:44]
reg write_93; // @[ToAXI4.scala:273:24]
wire idle_93 = ~count_93; // @[ToAXI4.scala:272:28, :274:26]
wire inc_93 = a_sel_93 & _inc_T_93; // @[Decoupled.scala:51:35]
wire _dec_T_186 = d_sel_93 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_93 = _dec_T_186 & _dec_T_187; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_372 = {1'h0, count_93} + {1'h0, inc_93}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_373 = _count_T_372[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_374 = {1'h0, _count_T_373} - {1'h0, dec_93}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_375 = _count_T_374[0]; // @[ToAXI4.scala:278:37]
wire _idStall_93_T = ~idle_93; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_93_T_3 = _idStall_93_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_93 = _idStall_93_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_94; // @[ToAXI4.scala:272:28]
wire _idStall_94_T_2 = count_94; // @[ToAXI4.scala:272:28, :286:44]
reg write_94; // @[ToAXI4.scala:273:24]
wire idle_94 = ~count_94; // @[ToAXI4.scala:272:28, :274:26]
wire inc_94 = a_sel_94 & _inc_T_94; // @[Decoupled.scala:51:35]
wire _dec_T_188 = d_sel_94 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_94 = _dec_T_188 & _dec_T_189; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_376 = {1'h0, count_94} + {1'h0, inc_94}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_377 = _count_T_376[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_378 = {1'h0, _count_T_377} - {1'h0, dec_94}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_379 = _count_T_378[0]; // @[ToAXI4.scala:278:37]
wire _idStall_94_T = ~idle_94; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_94_T_3 = _idStall_94_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_94 = _idStall_94_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_95; // @[ToAXI4.scala:272:28]
wire _idStall_95_T_2 = count_95; // @[ToAXI4.scala:272:28, :286:44]
reg write_95; // @[ToAXI4.scala:273:24]
wire idle_95 = ~count_95; // @[ToAXI4.scala:272:28, :274:26]
wire inc_95 = a_sel_95 & _inc_T_95; // @[Decoupled.scala:51:35]
wire _dec_T_190 = d_sel_95 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_95 = _dec_T_190 & _dec_T_191; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_380 = {1'h0, count_95} + {1'h0, inc_95}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_381 = _count_T_380[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_382 = {1'h0, _count_T_381} - {1'h0, dec_95}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_383 = _count_T_382[0]; // @[ToAXI4.scala:278:37]
wire _idStall_95_T = ~idle_95; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_95_T_3 = _idStall_95_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_95 = _idStall_95_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_96; // @[ToAXI4.scala:272:28]
wire _idStall_96_T_2 = count_96; // @[ToAXI4.scala:272:28, :286:44]
reg write_96; // @[ToAXI4.scala:273:24]
wire idle_96 = ~count_96; // @[ToAXI4.scala:272:28, :274:26]
wire inc_96 = a_sel_96 & _inc_T_96; // @[Decoupled.scala:51:35]
wire _dec_T_192 = d_sel_96 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_96 = _dec_T_192 & _dec_T_193; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_384 = {1'h0, count_96} + {1'h0, inc_96}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_385 = _count_T_384[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_386 = {1'h0, _count_T_385} - {1'h0, dec_96}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_387 = _count_T_386[0]; // @[ToAXI4.scala:278:37]
wire _idStall_96_T = ~idle_96; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_96_T_3 = _idStall_96_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_96 = _idStall_96_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_97; // @[ToAXI4.scala:272:28]
wire _idStall_97_T_2 = count_97; // @[ToAXI4.scala:272:28, :286:44]
reg write_97; // @[ToAXI4.scala:273:24]
wire idle_97 = ~count_97; // @[ToAXI4.scala:272:28, :274:26]
wire inc_97 = a_sel_97 & _inc_T_97; // @[Decoupled.scala:51:35]
wire _dec_T_194 = d_sel_97 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_97 = _dec_T_194 & _dec_T_195; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_388 = {1'h0, count_97} + {1'h0, inc_97}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_389 = _count_T_388[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_390 = {1'h0, _count_T_389} - {1'h0, dec_97}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_391 = _count_T_390[0]; // @[ToAXI4.scala:278:37]
wire _idStall_97_T = ~idle_97; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_97_T_3 = _idStall_97_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_97 = _idStall_97_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_98; // @[ToAXI4.scala:272:28]
wire _idStall_98_T_2 = count_98; // @[ToAXI4.scala:272:28, :286:44]
reg write_98; // @[ToAXI4.scala:273:24]
wire idle_98 = ~count_98; // @[ToAXI4.scala:272:28, :274:26]
wire inc_98 = a_sel_98 & _inc_T_98; // @[Decoupled.scala:51:35]
wire _dec_T_196 = d_sel_98 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_98 = _dec_T_196 & _dec_T_197; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_392 = {1'h0, count_98} + {1'h0, inc_98}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_393 = _count_T_392[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_394 = {1'h0, _count_T_393} - {1'h0, dec_98}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_395 = _count_T_394[0]; // @[ToAXI4.scala:278:37]
wire _idStall_98_T = ~idle_98; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_98_T_3 = _idStall_98_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_98 = _idStall_98_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_99; // @[ToAXI4.scala:272:28]
wire _idStall_99_T_2 = count_99; // @[ToAXI4.scala:272:28, :286:44]
reg write_99; // @[ToAXI4.scala:273:24]
wire idle_99 = ~count_99; // @[ToAXI4.scala:272:28, :274:26]
wire inc_99 = a_sel_99 & _inc_T_99; // @[Decoupled.scala:51:35]
wire _dec_T_198 = d_sel_99 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_99 = _dec_T_198 & _dec_T_199; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_396 = {1'h0, count_99} + {1'h0, inc_99}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_397 = _count_T_396[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_398 = {1'h0, _count_T_397} - {1'h0, dec_99}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_399 = _count_T_398[0]; // @[ToAXI4.scala:278:37]
wire _idStall_99_T = ~idle_99; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_99_T_3 = _idStall_99_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_99 = _idStall_99_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_100; // @[ToAXI4.scala:272:28]
wire _idStall_100_T_2 = count_100; // @[ToAXI4.scala:272:28, :286:44]
reg write_100; // @[ToAXI4.scala:273:24]
wire idle_100 = ~count_100; // @[ToAXI4.scala:272:28, :274:26]
wire inc_100 = a_sel_100 & _inc_T_100; // @[Decoupled.scala:51:35]
wire _dec_T_200 = d_sel_100 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_100 = _dec_T_200 & _dec_T_201; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_400 = {1'h0, count_100} + {1'h0, inc_100}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_401 = _count_T_400[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_402 = {1'h0, _count_T_401} - {1'h0, dec_100}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_403 = _count_T_402[0]; // @[ToAXI4.scala:278:37]
wire _idStall_100_T = ~idle_100; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_100_T_3 = _idStall_100_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_100 = _idStall_100_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_101; // @[ToAXI4.scala:272:28]
wire _idStall_101_T_2 = count_101; // @[ToAXI4.scala:272:28, :286:44]
reg write_101; // @[ToAXI4.scala:273:24]
wire idle_101 = ~count_101; // @[ToAXI4.scala:272:28, :274:26]
wire inc_101 = a_sel_101 & _inc_T_101; // @[Decoupled.scala:51:35]
wire _dec_T_202 = d_sel_101 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_101 = _dec_T_202 & _dec_T_203; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_404 = {1'h0, count_101} + {1'h0, inc_101}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_405 = _count_T_404[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_406 = {1'h0, _count_T_405} - {1'h0, dec_101}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_407 = _count_T_406[0]; // @[ToAXI4.scala:278:37]
wire _idStall_101_T = ~idle_101; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_101_T_3 = _idStall_101_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_101 = _idStall_101_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_102; // @[ToAXI4.scala:272:28]
wire _idStall_102_T_2 = count_102; // @[ToAXI4.scala:272:28, :286:44]
reg write_102; // @[ToAXI4.scala:273:24]
wire idle_102 = ~count_102; // @[ToAXI4.scala:272:28, :274:26]
wire inc_102 = a_sel_102 & _inc_T_102; // @[Decoupled.scala:51:35]
wire _dec_T_204 = d_sel_102 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_102 = _dec_T_204 & _dec_T_205; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_408 = {1'h0, count_102} + {1'h0, inc_102}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_409 = _count_T_408[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_410 = {1'h0, _count_T_409} - {1'h0, dec_102}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_411 = _count_T_410[0]; // @[ToAXI4.scala:278:37]
wire _idStall_102_T = ~idle_102; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_102_T_3 = _idStall_102_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_102 = _idStall_102_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_103; // @[ToAXI4.scala:272:28]
wire _idStall_103_T_2 = count_103; // @[ToAXI4.scala:272:28, :286:44]
reg write_103; // @[ToAXI4.scala:273:24]
wire idle_103 = ~count_103; // @[ToAXI4.scala:272:28, :274:26]
wire inc_103 = a_sel_103 & _inc_T_103; // @[Decoupled.scala:51:35]
wire _dec_T_206 = d_sel_103 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_103 = _dec_T_206 & _dec_T_207; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_412 = {1'h0, count_103} + {1'h0, inc_103}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_413 = _count_T_412[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_414 = {1'h0, _count_T_413} - {1'h0, dec_103}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_415 = _count_T_414[0]; // @[ToAXI4.scala:278:37]
wire _idStall_103_T = ~idle_103; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_103_T_3 = _idStall_103_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_103 = _idStall_103_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_104; // @[ToAXI4.scala:272:28]
wire _idStall_104_T_2 = count_104; // @[ToAXI4.scala:272:28, :286:44]
reg write_104; // @[ToAXI4.scala:273:24]
wire idle_104 = ~count_104; // @[ToAXI4.scala:272:28, :274:26]
wire inc_104 = a_sel_104 & _inc_T_104; // @[Decoupled.scala:51:35]
wire _dec_T_208 = d_sel_104 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_104 = _dec_T_208 & _dec_T_209; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_416 = {1'h0, count_104} + {1'h0, inc_104}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_417 = _count_T_416[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_418 = {1'h0, _count_T_417} - {1'h0, dec_104}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_419 = _count_T_418[0]; // @[ToAXI4.scala:278:37]
wire _idStall_104_T = ~idle_104; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_104_T_3 = _idStall_104_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_104 = _idStall_104_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_105; // @[ToAXI4.scala:272:28]
wire _idStall_105_T_2 = count_105; // @[ToAXI4.scala:272:28, :286:44]
reg write_105; // @[ToAXI4.scala:273:24]
wire idle_105 = ~count_105; // @[ToAXI4.scala:272:28, :274:26]
wire inc_105 = a_sel_105 & _inc_T_105; // @[Decoupled.scala:51:35]
wire _dec_T_210 = d_sel_105 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_105 = _dec_T_210 & _dec_T_211; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_420 = {1'h0, count_105} + {1'h0, inc_105}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_421 = _count_T_420[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_422 = {1'h0, _count_T_421} - {1'h0, dec_105}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_423 = _count_T_422[0]; // @[ToAXI4.scala:278:37]
wire _idStall_105_T = ~idle_105; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_105_T_3 = _idStall_105_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_105 = _idStall_105_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_106; // @[ToAXI4.scala:272:28]
wire _idStall_106_T_2 = count_106; // @[ToAXI4.scala:272:28, :286:44]
reg write_106; // @[ToAXI4.scala:273:24]
wire idle_106 = ~count_106; // @[ToAXI4.scala:272:28, :274:26]
wire inc_106 = a_sel_106 & _inc_T_106; // @[Decoupled.scala:51:35]
wire _dec_T_212 = d_sel_106 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_106 = _dec_T_212 & _dec_T_213; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_424 = {1'h0, count_106} + {1'h0, inc_106}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_425 = _count_T_424[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_426 = {1'h0, _count_T_425} - {1'h0, dec_106}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_427 = _count_T_426[0]; // @[ToAXI4.scala:278:37]
wire _idStall_106_T = ~idle_106; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_106_T_3 = _idStall_106_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_106 = _idStall_106_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_107; // @[ToAXI4.scala:272:28]
wire _idStall_107_T_2 = count_107; // @[ToAXI4.scala:272:28, :286:44]
reg write_107; // @[ToAXI4.scala:273:24]
wire idle_107 = ~count_107; // @[ToAXI4.scala:272:28, :274:26]
wire inc_107 = a_sel_107 & _inc_T_107; // @[Decoupled.scala:51:35]
wire _dec_T_214 = d_sel_107 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_107 = _dec_T_214 & _dec_T_215; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_428 = {1'h0, count_107} + {1'h0, inc_107}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_429 = _count_T_428[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_430 = {1'h0, _count_T_429} - {1'h0, dec_107}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_431 = _count_T_430[0]; // @[ToAXI4.scala:278:37]
wire _idStall_107_T = ~idle_107; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_107_T_3 = _idStall_107_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_107 = _idStall_107_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_108; // @[ToAXI4.scala:272:28]
wire _idStall_108_T_2 = count_108; // @[ToAXI4.scala:272:28, :286:44]
reg write_108; // @[ToAXI4.scala:273:24]
wire idle_108 = ~count_108; // @[ToAXI4.scala:272:28, :274:26]
wire inc_108 = a_sel_108 & _inc_T_108; // @[Decoupled.scala:51:35]
wire _dec_T_216 = d_sel_108 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_108 = _dec_T_216 & _dec_T_217; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_432 = {1'h0, count_108} + {1'h0, inc_108}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_433 = _count_T_432[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_434 = {1'h0, _count_T_433} - {1'h0, dec_108}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_435 = _count_T_434[0]; // @[ToAXI4.scala:278:37]
wire _idStall_108_T = ~idle_108; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_108_T_3 = _idStall_108_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_108 = _idStall_108_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_109; // @[ToAXI4.scala:272:28]
wire _idStall_109_T_2 = count_109; // @[ToAXI4.scala:272:28, :286:44]
reg write_109; // @[ToAXI4.scala:273:24]
wire idle_109 = ~count_109; // @[ToAXI4.scala:272:28, :274:26]
wire inc_109 = a_sel_109 & _inc_T_109; // @[Decoupled.scala:51:35]
wire _dec_T_218 = d_sel_109 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_109 = _dec_T_218 & _dec_T_219; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_436 = {1'h0, count_109} + {1'h0, inc_109}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_437 = _count_T_436[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_438 = {1'h0, _count_T_437} - {1'h0, dec_109}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_439 = _count_T_438[0]; // @[ToAXI4.scala:278:37]
wire _idStall_109_T = ~idle_109; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_109_T_3 = _idStall_109_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_109 = _idStall_109_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_110; // @[ToAXI4.scala:272:28]
wire _idStall_110_T_2 = count_110; // @[ToAXI4.scala:272:28, :286:44]
reg write_110; // @[ToAXI4.scala:273:24]
wire idle_110 = ~count_110; // @[ToAXI4.scala:272:28, :274:26]
wire inc_110 = a_sel_110 & _inc_T_110; // @[Decoupled.scala:51:35]
wire _dec_T_220 = d_sel_110 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_110 = _dec_T_220 & _dec_T_221; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_440 = {1'h0, count_110} + {1'h0, inc_110}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_441 = _count_T_440[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_442 = {1'h0, _count_T_441} - {1'h0, dec_110}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_443 = _count_T_442[0]; // @[ToAXI4.scala:278:37]
wire _idStall_110_T = ~idle_110; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_110_T_3 = _idStall_110_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_110 = _idStall_110_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_111; // @[ToAXI4.scala:272:28]
wire _idStall_111_T_2 = count_111; // @[ToAXI4.scala:272:28, :286:44]
reg write_111; // @[ToAXI4.scala:273:24]
wire idle_111 = ~count_111; // @[ToAXI4.scala:272:28, :274:26]
wire inc_111 = a_sel_111 & _inc_T_111; // @[Decoupled.scala:51:35]
wire _dec_T_222 = d_sel_111 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_111 = _dec_T_222 & _dec_T_223; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_444 = {1'h0, count_111} + {1'h0, inc_111}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_445 = _count_T_444[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_446 = {1'h0, _count_T_445} - {1'h0, dec_111}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_447 = _count_T_446[0]; // @[ToAXI4.scala:278:37]
wire _idStall_111_T = ~idle_111; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_111_T_3 = _idStall_111_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_111 = _idStall_111_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_112; // @[ToAXI4.scala:272:28]
wire _idStall_112_T_2 = count_112; // @[ToAXI4.scala:272:28, :286:44]
reg write_112; // @[ToAXI4.scala:273:24]
wire idle_112 = ~count_112; // @[ToAXI4.scala:272:28, :274:26]
wire inc_112 = a_sel_112 & _inc_T_112; // @[Decoupled.scala:51:35]
wire _dec_T_224 = d_sel_112 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_112 = _dec_T_224 & _dec_T_225; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_448 = {1'h0, count_112} + {1'h0, inc_112}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_449 = _count_T_448[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_450 = {1'h0, _count_T_449} - {1'h0, dec_112}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_451 = _count_T_450[0]; // @[ToAXI4.scala:278:37]
wire _idStall_112_T = ~idle_112; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_112_T_3 = _idStall_112_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_112 = _idStall_112_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_113; // @[ToAXI4.scala:272:28]
wire _idStall_113_T_2 = count_113; // @[ToAXI4.scala:272:28, :286:44]
reg write_113; // @[ToAXI4.scala:273:24]
wire idle_113 = ~count_113; // @[ToAXI4.scala:272:28, :274:26]
wire inc_113 = a_sel_113 & _inc_T_113; // @[Decoupled.scala:51:35]
wire _dec_T_226 = d_sel_113 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_113 = _dec_T_226 & _dec_T_227; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_452 = {1'h0, count_113} + {1'h0, inc_113}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_453 = _count_T_452[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_454 = {1'h0, _count_T_453} - {1'h0, dec_113}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_455 = _count_T_454[0]; // @[ToAXI4.scala:278:37]
wire _idStall_113_T = ~idle_113; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_113_T_3 = _idStall_113_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_113 = _idStall_113_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_114; // @[ToAXI4.scala:272:28]
wire _idStall_114_T_2 = count_114; // @[ToAXI4.scala:272:28, :286:44]
reg write_114; // @[ToAXI4.scala:273:24]
wire idle_114 = ~count_114; // @[ToAXI4.scala:272:28, :274:26]
wire inc_114 = a_sel_114 & _inc_T_114; // @[Decoupled.scala:51:35]
wire _dec_T_228 = d_sel_114 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_114 = _dec_T_228 & _dec_T_229; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_456 = {1'h0, count_114} + {1'h0, inc_114}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_457 = _count_T_456[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_458 = {1'h0, _count_T_457} - {1'h0, dec_114}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_459 = _count_T_458[0]; // @[ToAXI4.scala:278:37]
wire _idStall_114_T = ~idle_114; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_114_T_3 = _idStall_114_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_114 = _idStall_114_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_115; // @[ToAXI4.scala:272:28]
wire _idStall_115_T_2 = count_115; // @[ToAXI4.scala:272:28, :286:44]
reg write_115; // @[ToAXI4.scala:273:24]
wire idle_115 = ~count_115; // @[ToAXI4.scala:272:28, :274:26]
wire inc_115 = a_sel_115 & _inc_T_115; // @[Decoupled.scala:51:35]
wire _dec_T_230 = d_sel_115 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_115 = _dec_T_230 & _dec_T_231; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_460 = {1'h0, count_115} + {1'h0, inc_115}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_461 = _count_T_460[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_462 = {1'h0, _count_T_461} - {1'h0, dec_115}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_463 = _count_T_462[0]; // @[ToAXI4.scala:278:37]
wire _idStall_115_T = ~idle_115; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_115_T_3 = _idStall_115_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_115 = _idStall_115_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_116; // @[ToAXI4.scala:272:28]
wire _idStall_116_T_2 = count_116; // @[ToAXI4.scala:272:28, :286:44]
reg write_116; // @[ToAXI4.scala:273:24]
wire idle_116 = ~count_116; // @[ToAXI4.scala:272:28, :274:26]
wire inc_116 = a_sel_116 & _inc_T_116; // @[Decoupled.scala:51:35]
wire _dec_T_232 = d_sel_116 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_116 = _dec_T_232 & _dec_T_233; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_464 = {1'h0, count_116} + {1'h0, inc_116}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_465 = _count_T_464[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_466 = {1'h0, _count_T_465} - {1'h0, dec_116}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_467 = _count_T_466[0]; // @[ToAXI4.scala:278:37]
wire _idStall_116_T = ~idle_116; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_116_T_3 = _idStall_116_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_116 = _idStall_116_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_117; // @[ToAXI4.scala:272:28]
wire _idStall_117_T_2 = count_117; // @[ToAXI4.scala:272:28, :286:44]
reg write_117; // @[ToAXI4.scala:273:24]
wire idle_117 = ~count_117; // @[ToAXI4.scala:272:28, :274:26]
wire inc_117 = a_sel_117 & _inc_T_117; // @[Decoupled.scala:51:35]
wire _dec_T_234 = d_sel_117 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_117 = _dec_T_234 & _dec_T_235; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_468 = {1'h0, count_117} + {1'h0, inc_117}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_469 = _count_T_468[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_470 = {1'h0, _count_T_469} - {1'h0, dec_117}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_471 = _count_T_470[0]; // @[ToAXI4.scala:278:37]
wire _idStall_117_T = ~idle_117; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_117_T_3 = _idStall_117_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_117 = _idStall_117_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_118; // @[ToAXI4.scala:272:28]
wire _idStall_118_T_2 = count_118; // @[ToAXI4.scala:272:28, :286:44]
reg write_118; // @[ToAXI4.scala:273:24]
wire idle_118 = ~count_118; // @[ToAXI4.scala:272:28, :274:26]
wire inc_118 = a_sel_118 & _inc_T_118; // @[Decoupled.scala:51:35]
wire _dec_T_236 = d_sel_118 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_118 = _dec_T_236 & _dec_T_237; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_472 = {1'h0, count_118} + {1'h0, inc_118}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_473 = _count_T_472[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_474 = {1'h0, _count_T_473} - {1'h0, dec_118}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_475 = _count_T_474[0]; // @[ToAXI4.scala:278:37]
wire _idStall_118_T = ~idle_118; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_118_T_3 = _idStall_118_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_118 = _idStall_118_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_119; // @[ToAXI4.scala:272:28]
wire _idStall_119_T_2 = count_119; // @[ToAXI4.scala:272:28, :286:44]
reg write_119; // @[ToAXI4.scala:273:24]
wire idle_119 = ~count_119; // @[ToAXI4.scala:272:28, :274:26]
wire inc_119 = a_sel_119 & _inc_T_119; // @[Decoupled.scala:51:35]
wire _dec_T_238 = d_sel_119 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_119 = _dec_T_238 & _dec_T_239; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_476 = {1'h0, count_119} + {1'h0, inc_119}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_477 = _count_T_476[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_478 = {1'h0, _count_T_477} - {1'h0, dec_119}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_479 = _count_T_478[0]; // @[ToAXI4.scala:278:37]
wire _idStall_119_T = ~idle_119; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_119_T_3 = _idStall_119_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_119 = _idStall_119_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_120; // @[ToAXI4.scala:272:28]
wire _idStall_120_T_2 = count_120; // @[ToAXI4.scala:272:28, :286:44]
reg write_120; // @[ToAXI4.scala:273:24]
wire idle_120 = ~count_120; // @[ToAXI4.scala:272:28, :274:26]
wire inc_120 = a_sel_120 & _inc_T_120; // @[Decoupled.scala:51:35]
wire _dec_T_240 = d_sel_120 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_120 = _dec_T_240 & _dec_T_241; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_480 = {1'h0, count_120} + {1'h0, inc_120}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_481 = _count_T_480[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_482 = {1'h0, _count_T_481} - {1'h0, dec_120}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_483 = _count_T_482[0]; // @[ToAXI4.scala:278:37]
wire _idStall_120_T = ~idle_120; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_120_T_3 = _idStall_120_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_120 = _idStall_120_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_121; // @[ToAXI4.scala:272:28]
wire _idStall_121_T_2 = count_121; // @[ToAXI4.scala:272:28, :286:44]
reg write_121; // @[ToAXI4.scala:273:24]
wire idle_121 = ~count_121; // @[ToAXI4.scala:272:28, :274:26]
wire inc_121 = a_sel_121 & _inc_T_121; // @[Decoupled.scala:51:35]
wire _dec_T_242 = d_sel_121 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_121 = _dec_T_242 & _dec_T_243; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_484 = {1'h0, count_121} + {1'h0, inc_121}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_485 = _count_T_484[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_486 = {1'h0, _count_T_485} - {1'h0, dec_121}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_487 = _count_T_486[0]; // @[ToAXI4.scala:278:37]
wire _idStall_121_T = ~idle_121; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_121_T_3 = _idStall_121_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_121 = _idStall_121_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_122; // @[ToAXI4.scala:272:28]
wire _idStall_122_T_2 = count_122; // @[ToAXI4.scala:272:28, :286:44]
reg write_122; // @[ToAXI4.scala:273:24]
wire idle_122 = ~count_122; // @[ToAXI4.scala:272:28, :274:26]
wire inc_122 = a_sel_122 & _inc_T_122; // @[Decoupled.scala:51:35]
wire _dec_T_244 = d_sel_122 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_122 = _dec_T_244 & _dec_T_245; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_488 = {1'h0, count_122} + {1'h0, inc_122}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_489 = _count_T_488[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_490 = {1'h0, _count_T_489} - {1'h0, dec_122}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_491 = _count_T_490[0]; // @[ToAXI4.scala:278:37]
wire _idStall_122_T = ~idle_122; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_122_T_3 = _idStall_122_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_122 = _idStall_122_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_123; // @[ToAXI4.scala:272:28]
wire _idStall_123_T_2 = count_123; // @[ToAXI4.scala:272:28, :286:44]
reg write_123; // @[ToAXI4.scala:273:24]
wire idle_123 = ~count_123; // @[ToAXI4.scala:272:28, :274:26]
wire inc_123 = a_sel_123 & _inc_T_123; // @[Decoupled.scala:51:35]
wire _dec_T_246 = d_sel_123 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_123 = _dec_T_246 & _dec_T_247; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_492 = {1'h0, count_123} + {1'h0, inc_123}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_493 = _count_T_492[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_494 = {1'h0, _count_T_493} - {1'h0, dec_123}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_495 = _count_T_494[0]; // @[ToAXI4.scala:278:37]
wire _idStall_123_T = ~idle_123; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_123_T_3 = _idStall_123_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_123 = _idStall_123_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_124; // @[ToAXI4.scala:272:28]
wire _idStall_124_T_2 = count_124; // @[ToAXI4.scala:272:28, :286:44]
reg write_124; // @[ToAXI4.scala:273:24]
wire idle_124 = ~count_124; // @[ToAXI4.scala:272:28, :274:26]
wire inc_124 = a_sel_124 & _inc_T_124; // @[Decoupled.scala:51:35]
wire _dec_T_248 = d_sel_124 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_124 = _dec_T_248 & _dec_T_249; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_496 = {1'h0, count_124} + {1'h0, inc_124}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_497 = _count_T_496[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_498 = {1'h0, _count_T_497} - {1'h0, dec_124}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_499 = _count_T_498[0]; // @[ToAXI4.scala:278:37]
wire _idStall_124_T = ~idle_124; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_124_T_3 = _idStall_124_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_124 = _idStall_124_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_125; // @[ToAXI4.scala:272:28]
wire _idStall_125_T_2 = count_125; // @[ToAXI4.scala:272:28, :286:44]
reg write_125; // @[ToAXI4.scala:273:24]
wire idle_125 = ~count_125; // @[ToAXI4.scala:272:28, :274:26]
wire inc_125 = a_sel_125 & _inc_T_125; // @[Decoupled.scala:51:35]
wire _dec_T_250 = d_sel_125 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_125 = _dec_T_250 & _dec_T_251; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_500 = {1'h0, count_125} + {1'h0, inc_125}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_501 = _count_T_500[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_502 = {1'h0, _count_T_501} - {1'h0, dec_125}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_503 = _count_T_502[0]; // @[ToAXI4.scala:278:37]
wire _idStall_125_T = ~idle_125; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_125_T_3 = _idStall_125_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_125 = _idStall_125_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_126; // @[ToAXI4.scala:272:28]
wire _idStall_126_T_2 = count_126; // @[ToAXI4.scala:272:28, :286:44]
reg write_126; // @[ToAXI4.scala:273:24]
wire idle_126 = ~count_126; // @[ToAXI4.scala:272:28, :274:26]
wire inc_126 = a_sel_126 & _inc_T_126; // @[Decoupled.scala:51:35]
wire _dec_T_252 = d_sel_126 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_126 = _dec_T_252 & _dec_T_253; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_504 = {1'h0, count_126} + {1'h0, inc_126}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_505 = _count_T_504[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_506 = {1'h0, _count_T_505} - {1'h0, dec_126}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_507 = _count_T_506[0]; // @[ToAXI4.scala:278:37]
wire _idStall_126_T = ~idle_126; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_126_T_3 = _idStall_126_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_126 = _idStall_126_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_127; // @[ToAXI4.scala:272:28]
wire _idStall_127_T_2 = count_127; // @[ToAXI4.scala:272:28, :286:44]
reg write_127; // @[ToAXI4.scala:273:24]
wire idle_127 = ~count_127; // @[ToAXI4.scala:272:28, :274:26]
wire inc_127 = a_sel_127 & _inc_T_127; // @[Decoupled.scala:51:35]
wire _dec_T_254 = d_sel_127 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_127 = _dec_T_254 & _dec_T_255; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_508 = {1'h0, count_127} + {1'h0, inc_127}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_509 = _count_T_508[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_510 = {1'h0, _count_T_509} - {1'h0, dec_127}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_511 = _count_T_510[0]; // @[ToAXI4.scala:278:37]
wire _idStall_127_T = ~idle_127; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_127_T_3 = _idStall_127_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_127 = _idStall_127_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_128; // @[ToAXI4.scala:272:28]
wire _idStall_128_T_2 = count_128; // @[ToAXI4.scala:272:28, :286:44]
reg write_128; // @[ToAXI4.scala:273:24]
wire idle_128 = ~count_128; // @[ToAXI4.scala:272:28, :274:26]
wire inc_128 = a_sel_128 & _inc_T_128; // @[Decoupled.scala:51:35]
wire _dec_T_256 = d_sel_128 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_128 = _dec_T_256 & _dec_T_257; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_512 = {1'h0, count_128} + {1'h0, inc_128}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_513 = _count_T_512[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_514 = {1'h0, _count_T_513} - {1'h0, dec_128}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_515 = _count_T_514[0]; // @[ToAXI4.scala:278:37]
wire _idStall_128_T = ~idle_128; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_128_T_3 = _idStall_128_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_128 = _idStall_128_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_129; // @[ToAXI4.scala:272:28]
wire _idStall_129_T_2 = count_129; // @[ToAXI4.scala:272:28, :286:44]
reg write_129; // @[ToAXI4.scala:273:24]
wire idle_129 = ~count_129; // @[ToAXI4.scala:272:28, :274:26]
wire inc_129 = a_sel_129 & _inc_T_129; // @[Decoupled.scala:51:35]
wire _dec_T_258 = d_sel_129 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_129 = _dec_T_258 & _dec_T_259; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_516 = {1'h0, count_129} + {1'h0, inc_129}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_517 = _count_T_516[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_518 = {1'h0, _count_T_517} - {1'h0, dec_129}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_519 = _count_T_518[0]; // @[ToAXI4.scala:278:37]
wire _idStall_129_T = ~idle_129; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_129_T_3 = _idStall_129_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_129 = _idStall_129_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_130; // @[ToAXI4.scala:272:28]
wire _idStall_130_T_2 = count_130; // @[ToAXI4.scala:272:28, :286:44]
reg write_130; // @[ToAXI4.scala:273:24]
wire idle_130 = ~count_130; // @[ToAXI4.scala:272:28, :274:26]
wire inc_130 = a_sel_130 & _inc_T_130; // @[Decoupled.scala:51:35]
wire _dec_T_260 = d_sel_130 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_130 = _dec_T_260 & _dec_T_261; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_520 = {1'h0, count_130} + {1'h0, inc_130}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_521 = _count_T_520[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_522 = {1'h0, _count_T_521} - {1'h0, dec_130}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_523 = _count_T_522[0]; // @[ToAXI4.scala:278:37]
wire _idStall_130_T = ~idle_130; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_130_T_3 = _idStall_130_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_130 = _idStall_130_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_131; // @[ToAXI4.scala:272:28]
wire _idStall_131_T_2 = count_131; // @[ToAXI4.scala:272:28, :286:44]
reg write_131; // @[ToAXI4.scala:273:24]
wire idle_131 = ~count_131; // @[ToAXI4.scala:272:28, :274:26]
wire inc_131 = a_sel_131 & _inc_T_131; // @[Decoupled.scala:51:35]
wire _dec_T_262 = d_sel_131 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_131 = _dec_T_262 & _dec_T_263; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_524 = {1'h0, count_131} + {1'h0, inc_131}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_525 = _count_T_524[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_526 = {1'h0, _count_T_525} - {1'h0, dec_131}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_527 = _count_T_526[0]; // @[ToAXI4.scala:278:37]
wire _idStall_131_T = ~idle_131; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_131_T_3 = _idStall_131_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_131 = _idStall_131_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_132; // @[ToAXI4.scala:272:28]
wire _idStall_132_T_2 = count_132; // @[ToAXI4.scala:272:28, :286:44]
reg write_132; // @[ToAXI4.scala:273:24]
wire idle_132 = ~count_132; // @[ToAXI4.scala:272:28, :274:26]
wire inc_132 = a_sel_132 & _inc_T_132; // @[Decoupled.scala:51:35]
wire _dec_T_264 = d_sel_132 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_132 = _dec_T_264 & _dec_T_265; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_528 = {1'h0, count_132} + {1'h0, inc_132}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_529 = _count_T_528[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_530 = {1'h0, _count_T_529} - {1'h0, dec_132}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_531 = _count_T_530[0]; // @[ToAXI4.scala:278:37]
wire _idStall_132_T = ~idle_132; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_132_T_3 = _idStall_132_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_132 = _idStall_132_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_133; // @[ToAXI4.scala:272:28]
wire _idStall_133_T_2 = count_133; // @[ToAXI4.scala:272:28, :286:44]
reg write_133; // @[ToAXI4.scala:273:24]
wire idle_133 = ~count_133; // @[ToAXI4.scala:272:28, :274:26]
wire inc_133 = a_sel_133 & _inc_T_133; // @[Decoupled.scala:51:35]
wire _dec_T_266 = d_sel_133 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_133 = _dec_T_266 & _dec_T_267; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_532 = {1'h0, count_133} + {1'h0, inc_133}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_533 = _count_T_532[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_534 = {1'h0, _count_T_533} - {1'h0, dec_133}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_535 = _count_T_534[0]; // @[ToAXI4.scala:278:37]
wire _idStall_133_T = ~idle_133; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_133_T_3 = _idStall_133_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_133 = _idStall_133_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_134; // @[ToAXI4.scala:272:28]
wire _idStall_134_T_2 = count_134; // @[ToAXI4.scala:272:28, :286:44]
reg write_134; // @[ToAXI4.scala:273:24]
wire idle_134 = ~count_134; // @[ToAXI4.scala:272:28, :274:26]
wire inc_134 = a_sel_134 & _inc_T_134; // @[Decoupled.scala:51:35]
wire _dec_T_268 = d_sel_134 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_134 = _dec_T_268 & _dec_T_269; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_536 = {1'h0, count_134} + {1'h0, inc_134}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_537 = _count_T_536[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_538 = {1'h0, _count_T_537} - {1'h0, dec_134}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_539 = _count_T_538[0]; // @[ToAXI4.scala:278:37]
wire _idStall_134_T = ~idle_134; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_134_T_3 = _idStall_134_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_134 = _idStall_134_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_135; // @[ToAXI4.scala:272:28]
wire _idStall_135_T_2 = count_135; // @[ToAXI4.scala:272:28, :286:44]
reg write_135; // @[ToAXI4.scala:273:24]
wire idle_135 = ~count_135; // @[ToAXI4.scala:272:28, :274:26]
wire inc_135 = a_sel_135 & _inc_T_135; // @[Decoupled.scala:51:35]
wire _dec_T_270 = d_sel_135 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_135 = _dec_T_270 & _dec_T_271; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_540 = {1'h0, count_135} + {1'h0, inc_135}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_541 = _count_T_540[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_542 = {1'h0, _count_T_541} - {1'h0, dec_135}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_543 = _count_T_542[0]; // @[ToAXI4.scala:278:37]
wire _idStall_135_T = ~idle_135; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_135_T_3 = _idStall_135_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_135 = _idStall_135_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_136; // @[ToAXI4.scala:272:28]
wire _idStall_136_T_2 = count_136; // @[ToAXI4.scala:272:28, :286:44]
reg write_136; // @[ToAXI4.scala:273:24]
wire idle_136 = ~count_136; // @[ToAXI4.scala:272:28, :274:26]
wire inc_136 = a_sel_136 & _inc_T_136; // @[Decoupled.scala:51:35]
wire _dec_T_272 = d_sel_136 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_136 = _dec_T_272 & _dec_T_273; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_544 = {1'h0, count_136} + {1'h0, inc_136}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_545 = _count_T_544[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_546 = {1'h0, _count_T_545} - {1'h0, dec_136}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_547 = _count_T_546[0]; // @[ToAXI4.scala:278:37]
wire _idStall_136_T = ~idle_136; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_136_T_3 = _idStall_136_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_136 = _idStall_136_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_137; // @[ToAXI4.scala:272:28]
wire _idStall_137_T_2 = count_137; // @[ToAXI4.scala:272:28, :286:44]
reg write_137; // @[ToAXI4.scala:273:24]
wire idle_137 = ~count_137; // @[ToAXI4.scala:272:28, :274:26]
wire inc_137 = a_sel_137 & _inc_T_137; // @[Decoupled.scala:51:35]
wire _dec_T_274 = d_sel_137 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_137 = _dec_T_274 & _dec_T_275; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_548 = {1'h0, count_137} + {1'h0, inc_137}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_549 = _count_T_548[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_550 = {1'h0, _count_T_549} - {1'h0, dec_137}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_551 = _count_T_550[0]; // @[ToAXI4.scala:278:37]
wire _idStall_137_T = ~idle_137; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_137_T_3 = _idStall_137_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_137 = _idStall_137_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_138; // @[ToAXI4.scala:272:28]
wire _idStall_138_T_2 = count_138; // @[ToAXI4.scala:272:28, :286:44]
reg write_138; // @[ToAXI4.scala:273:24]
wire idle_138 = ~count_138; // @[ToAXI4.scala:272:28, :274:26]
wire inc_138 = a_sel_138 & _inc_T_138; // @[Decoupled.scala:51:35]
wire _dec_T_276 = d_sel_138 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_138 = _dec_T_276 & _dec_T_277; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_552 = {1'h0, count_138} + {1'h0, inc_138}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_553 = _count_T_552[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_554 = {1'h0, _count_T_553} - {1'h0, dec_138}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_555 = _count_T_554[0]; // @[ToAXI4.scala:278:37]
wire _idStall_138_T = ~idle_138; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_138_T_3 = _idStall_138_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_138 = _idStall_138_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_139; // @[ToAXI4.scala:272:28]
wire _idStall_139_T_2 = count_139; // @[ToAXI4.scala:272:28, :286:44]
reg write_139; // @[ToAXI4.scala:273:24]
wire idle_139 = ~count_139; // @[ToAXI4.scala:272:28, :274:26]
wire inc_139 = a_sel_139 & _inc_T_139; // @[Decoupled.scala:51:35]
wire _dec_T_278 = d_sel_139 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_139 = _dec_T_278 & _dec_T_279; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_556 = {1'h0, count_139} + {1'h0, inc_139}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_557 = _count_T_556[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_558 = {1'h0, _count_T_557} - {1'h0, dec_139}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_559 = _count_T_558[0]; // @[ToAXI4.scala:278:37]
wire _idStall_139_T = ~idle_139; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_139_T_3 = _idStall_139_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_139 = _idStall_139_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_140; // @[ToAXI4.scala:272:28]
wire _idStall_140_T_2 = count_140; // @[ToAXI4.scala:272:28, :286:44]
reg write_140; // @[ToAXI4.scala:273:24]
wire idle_140 = ~count_140; // @[ToAXI4.scala:272:28, :274:26]
wire inc_140 = a_sel_140 & _inc_T_140; // @[Decoupled.scala:51:35]
wire _dec_T_280 = d_sel_140 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_140 = _dec_T_280 & _dec_T_281; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_560 = {1'h0, count_140} + {1'h0, inc_140}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_561 = _count_T_560[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_562 = {1'h0, _count_T_561} - {1'h0, dec_140}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_563 = _count_T_562[0]; // @[ToAXI4.scala:278:37]
wire _idStall_140_T = ~idle_140; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_140_T_3 = _idStall_140_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_140 = _idStall_140_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_141; // @[ToAXI4.scala:272:28]
wire _idStall_141_T_2 = count_141; // @[ToAXI4.scala:272:28, :286:44]
reg write_141; // @[ToAXI4.scala:273:24]
wire idle_141 = ~count_141; // @[ToAXI4.scala:272:28, :274:26]
wire inc_141 = a_sel_141 & _inc_T_141; // @[Decoupled.scala:51:35]
wire _dec_T_282 = d_sel_141 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_141 = _dec_T_282 & _dec_T_283; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_564 = {1'h0, count_141} + {1'h0, inc_141}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_565 = _count_T_564[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_566 = {1'h0, _count_T_565} - {1'h0, dec_141}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_567 = _count_T_566[0]; // @[ToAXI4.scala:278:37]
wire _idStall_141_T = ~idle_141; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_141_T_3 = _idStall_141_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_141 = _idStall_141_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_142; // @[ToAXI4.scala:272:28]
wire _idStall_142_T_2 = count_142; // @[ToAXI4.scala:272:28, :286:44]
reg write_142; // @[ToAXI4.scala:273:24]
wire idle_142 = ~count_142; // @[ToAXI4.scala:272:28, :274:26]
wire inc_142 = a_sel_142 & _inc_T_142; // @[Decoupled.scala:51:35]
wire _dec_T_284 = d_sel_142 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_142 = _dec_T_284 & _dec_T_285; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_568 = {1'h0, count_142} + {1'h0, inc_142}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_569 = _count_T_568[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_570 = {1'h0, _count_T_569} - {1'h0, dec_142}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_571 = _count_T_570[0]; // @[ToAXI4.scala:278:37]
wire _idStall_142_T = ~idle_142; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_142_T_3 = _idStall_142_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_142 = _idStall_142_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_143; // @[ToAXI4.scala:272:28]
wire _idStall_143_T_2 = count_143; // @[ToAXI4.scala:272:28, :286:44]
reg write_143; // @[ToAXI4.scala:273:24]
wire idle_143 = ~count_143; // @[ToAXI4.scala:272:28, :274:26]
wire inc_143 = a_sel_143 & _inc_T_143; // @[Decoupled.scala:51:35]
wire _dec_T_286 = d_sel_143 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_143 = _dec_T_286 & _dec_T_287; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_572 = {1'h0, count_143} + {1'h0, inc_143}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_573 = _count_T_572[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_574 = {1'h0, _count_T_573} - {1'h0, dec_143}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_575 = _count_T_574[0]; // @[ToAXI4.scala:278:37]
wire _idStall_143_T = ~idle_143; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_143_T_3 = _idStall_143_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_143 = _idStall_143_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_144; // @[ToAXI4.scala:272:28]
wire _idStall_144_T_2 = count_144; // @[ToAXI4.scala:272:28, :286:44]
reg write_144; // @[ToAXI4.scala:273:24]
wire idle_144 = ~count_144; // @[ToAXI4.scala:272:28, :274:26]
wire inc_144 = a_sel_144 & _inc_T_144; // @[Decoupled.scala:51:35]
wire _dec_T_288 = d_sel_144 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_144 = _dec_T_288 & _dec_T_289; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_576 = {1'h0, count_144} + {1'h0, inc_144}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_577 = _count_T_576[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_578 = {1'h0, _count_T_577} - {1'h0, dec_144}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_579 = _count_T_578[0]; // @[ToAXI4.scala:278:37]
wire _idStall_144_T = ~idle_144; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_144_T_3 = _idStall_144_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_144 = _idStall_144_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_145; // @[ToAXI4.scala:272:28]
wire _idStall_145_T_2 = count_145; // @[ToAXI4.scala:272:28, :286:44]
reg write_145; // @[ToAXI4.scala:273:24]
wire idle_145 = ~count_145; // @[ToAXI4.scala:272:28, :274:26]
wire inc_145 = a_sel_145 & _inc_T_145; // @[Decoupled.scala:51:35]
wire _dec_T_290 = d_sel_145 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_145 = _dec_T_290 & _dec_T_291; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_580 = {1'h0, count_145} + {1'h0, inc_145}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_581 = _count_T_580[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_582 = {1'h0, _count_T_581} - {1'h0, dec_145}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_583 = _count_T_582[0]; // @[ToAXI4.scala:278:37]
wire _idStall_145_T = ~idle_145; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_145_T_3 = _idStall_145_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_145 = _idStall_145_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_146; // @[ToAXI4.scala:272:28]
wire _idStall_146_T_2 = count_146; // @[ToAXI4.scala:272:28, :286:44]
reg write_146; // @[ToAXI4.scala:273:24]
wire idle_146 = ~count_146; // @[ToAXI4.scala:272:28, :274:26]
wire inc_146 = a_sel_146 & _inc_T_146; // @[Decoupled.scala:51:35]
wire _dec_T_292 = d_sel_146 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_146 = _dec_T_292 & _dec_T_293; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_584 = {1'h0, count_146} + {1'h0, inc_146}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_585 = _count_T_584[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_586 = {1'h0, _count_T_585} - {1'h0, dec_146}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_587 = _count_T_586[0]; // @[ToAXI4.scala:278:37]
wire _idStall_146_T = ~idle_146; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_146_T_3 = _idStall_146_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_146 = _idStall_146_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_147; // @[ToAXI4.scala:272:28]
wire _idStall_147_T_2 = count_147; // @[ToAXI4.scala:272:28, :286:44]
reg write_147; // @[ToAXI4.scala:273:24]
wire idle_147 = ~count_147; // @[ToAXI4.scala:272:28, :274:26]
wire inc_147 = a_sel_147 & _inc_T_147; // @[Decoupled.scala:51:35]
wire _dec_T_294 = d_sel_147 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_147 = _dec_T_294 & _dec_T_295; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_588 = {1'h0, count_147} + {1'h0, inc_147}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_589 = _count_T_588[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_590 = {1'h0, _count_T_589} - {1'h0, dec_147}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_591 = _count_T_590[0]; // @[ToAXI4.scala:278:37]
wire _idStall_147_T = ~idle_147; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_147_T_3 = _idStall_147_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_147 = _idStall_147_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_148; // @[ToAXI4.scala:272:28]
wire _idStall_148_T_2 = count_148; // @[ToAXI4.scala:272:28, :286:44]
reg write_148; // @[ToAXI4.scala:273:24]
wire idle_148 = ~count_148; // @[ToAXI4.scala:272:28, :274:26]
wire inc_148 = a_sel_148 & _inc_T_148; // @[Decoupled.scala:51:35]
wire _dec_T_296 = d_sel_148 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_148 = _dec_T_296 & _dec_T_297; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_592 = {1'h0, count_148} + {1'h0, inc_148}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_593 = _count_T_592[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_594 = {1'h0, _count_T_593} - {1'h0, dec_148}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_595 = _count_T_594[0]; // @[ToAXI4.scala:278:37]
wire _idStall_148_T = ~idle_148; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_148_T_3 = _idStall_148_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_148 = _idStall_148_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_149; // @[ToAXI4.scala:272:28]
wire _idStall_149_T_2 = count_149; // @[ToAXI4.scala:272:28, :286:44]
reg write_149; // @[ToAXI4.scala:273:24]
wire idle_149 = ~count_149; // @[ToAXI4.scala:272:28, :274:26]
wire inc_149 = a_sel_149 & _inc_T_149; // @[Decoupled.scala:51:35]
wire _dec_T_298 = d_sel_149 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_149 = _dec_T_298 & _dec_T_299; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_596 = {1'h0, count_149} + {1'h0, inc_149}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_597 = _count_T_596[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_598 = {1'h0, _count_T_597} - {1'h0, dec_149}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_599 = _count_T_598[0]; // @[ToAXI4.scala:278:37]
wire _idStall_149_T = ~idle_149; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_149_T_3 = _idStall_149_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_149 = _idStall_149_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_150; // @[ToAXI4.scala:272:28]
wire _idStall_150_T_2 = count_150; // @[ToAXI4.scala:272:28, :286:44]
reg write_150; // @[ToAXI4.scala:273:24]
wire idle_150 = ~count_150; // @[ToAXI4.scala:272:28, :274:26]
wire inc_150 = a_sel_150 & _inc_T_150; // @[Decoupled.scala:51:35]
wire _dec_T_300 = d_sel_150 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_150 = _dec_T_300 & _dec_T_301; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_600 = {1'h0, count_150} + {1'h0, inc_150}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_601 = _count_T_600[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_602 = {1'h0, _count_T_601} - {1'h0, dec_150}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_603 = _count_T_602[0]; // @[ToAXI4.scala:278:37]
wire _idStall_150_T = ~idle_150; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_150_T_3 = _idStall_150_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_150 = _idStall_150_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_151; // @[ToAXI4.scala:272:28]
wire _idStall_151_T_2 = count_151; // @[ToAXI4.scala:272:28, :286:44]
reg write_151; // @[ToAXI4.scala:273:24]
wire idle_151 = ~count_151; // @[ToAXI4.scala:272:28, :274:26]
wire inc_151 = a_sel_151 & _inc_T_151; // @[Decoupled.scala:51:35]
wire _dec_T_302 = d_sel_151 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_151 = _dec_T_302 & _dec_T_303; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_604 = {1'h0, count_151} + {1'h0, inc_151}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_605 = _count_T_604[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_606 = {1'h0, _count_T_605} - {1'h0, dec_151}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_607 = _count_T_606[0]; // @[ToAXI4.scala:278:37]
wire _idStall_151_T = ~idle_151; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_151_T_3 = _idStall_151_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_151 = _idStall_151_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_152; // @[ToAXI4.scala:272:28]
wire _idStall_152_T_2 = count_152; // @[ToAXI4.scala:272:28, :286:44]
reg write_152; // @[ToAXI4.scala:273:24]
wire idle_152 = ~count_152; // @[ToAXI4.scala:272:28, :274:26]
wire inc_152 = a_sel_152 & _inc_T_152; // @[Decoupled.scala:51:35]
wire _dec_T_304 = d_sel_152 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_152 = _dec_T_304 & _dec_T_305; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_608 = {1'h0, count_152} + {1'h0, inc_152}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_609 = _count_T_608[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_610 = {1'h0, _count_T_609} - {1'h0, dec_152}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_611 = _count_T_610[0]; // @[ToAXI4.scala:278:37]
wire _idStall_152_T = ~idle_152; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_152_T_3 = _idStall_152_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_152 = _idStall_152_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_153; // @[ToAXI4.scala:272:28]
wire _idStall_153_T_2 = count_153; // @[ToAXI4.scala:272:28, :286:44]
reg write_153; // @[ToAXI4.scala:273:24]
wire idle_153 = ~count_153; // @[ToAXI4.scala:272:28, :274:26]
wire inc_153 = a_sel_153 & _inc_T_153; // @[Decoupled.scala:51:35]
wire _dec_T_306 = d_sel_153 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_153 = _dec_T_306 & _dec_T_307; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_612 = {1'h0, count_153} + {1'h0, inc_153}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_613 = _count_T_612[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_614 = {1'h0, _count_T_613} - {1'h0, dec_153}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_615 = _count_T_614[0]; // @[ToAXI4.scala:278:37]
wire _idStall_153_T = ~idle_153; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_153_T_3 = _idStall_153_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_153 = _idStall_153_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_154; // @[ToAXI4.scala:272:28]
wire _idStall_154_T_2 = count_154; // @[ToAXI4.scala:272:28, :286:44]
reg write_154; // @[ToAXI4.scala:273:24]
wire idle_154 = ~count_154; // @[ToAXI4.scala:272:28, :274:26]
wire inc_154 = a_sel_154 & _inc_T_154; // @[Decoupled.scala:51:35]
wire _dec_T_308 = d_sel_154 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_154 = _dec_T_308 & _dec_T_309; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_616 = {1'h0, count_154} + {1'h0, inc_154}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_617 = _count_T_616[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_618 = {1'h0, _count_T_617} - {1'h0, dec_154}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_619 = _count_T_618[0]; // @[ToAXI4.scala:278:37]
wire _idStall_154_T = ~idle_154; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_154_T_3 = _idStall_154_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_154 = _idStall_154_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_155; // @[ToAXI4.scala:272:28]
wire _idStall_155_T_2 = count_155; // @[ToAXI4.scala:272:28, :286:44]
reg write_155; // @[ToAXI4.scala:273:24]
wire idle_155 = ~count_155; // @[ToAXI4.scala:272:28, :274:26]
wire inc_155 = a_sel_155 & _inc_T_155; // @[Decoupled.scala:51:35]
wire _dec_T_310 = d_sel_155 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_155 = _dec_T_310 & _dec_T_311; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_620 = {1'h0, count_155} + {1'h0, inc_155}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_621 = _count_T_620[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_622 = {1'h0, _count_T_621} - {1'h0, dec_155}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_623 = _count_T_622[0]; // @[ToAXI4.scala:278:37]
wire _idStall_155_T = ~idle_155; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_155_T_3 = _idStall_155_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_155 = _idStall_155_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_156; // @[ToAXI4.scala:272:28]
wire _idStall_156_T_2 = count_156; // @[ToAXI4.scala:272:28, :286:44]
reg write_156; // @[ToAXI4.scala:273:24]
wire idle_156 = ~count_156; // @[ToAXI4.scala:272:28, :274:26]
wire inc_156 = a_sel_156 & _inc_T_156; // @[Decoupled.scala:51:35]
wire _dec_T_312 = d_sel_156 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_156 = _dec_T_312 & _dec_T_313; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_624 = {1'h0, count_156} + {1'h0, inc_156}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_625 = _count_T_624[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_626 = {1'h0, _count_T_625} - {1'h0, dec_156}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_627 = _count_T_626[0]; // @[ToAXI4.scala:278:37]
wire _idStall_156_T = ~idle_156; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_156_T_3 = _idStall_156_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_156 = _idStall_156_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_157; // @[ToAXI4.scala:272:28]
wire _idStall_157_T_2 = count_157; // @[ToAXI4.scala:272:28, :286:44]
reg write_157; // @[ToAXI4.scala:273:24]
wire idle_157 = ~count_157; // @[ToAXI4.scala:272:28, :274:26]
wire inc_157 = a_sel_157 & _inc_T_157; // @[Decoupled.scala:51:35]
wire _dec_T_314 = d_sel_157 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_157 = _dec_T_314 & _dec_T_315; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_628 = {1'h0, count_157} + {1'h0, inc_157}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_629 = _count_T_628[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_630 = {1'h0, _count_T_629} - {1'h0, dec_157}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_631 = _count_T_630[0]; // @[ToAXI4.scala:278:37]
wire _idStall_157_T = ~idle_157; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_157_T_3 = _idStall_157_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_157 = _idStall_157_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_158; // @[ToAXI4.scala:272:28]
wire _idStall_158_T_2 = count_158; // @[ToAXI4.scala:272:28, :286:44]
reg write_158; // @[ToAXI4.scala:273:24]
wire idle_158 = ~count_158; // @[ToAXI4.scala:272:28, :274:26]
wire inc_158 = a_sel_158 & _inc_T_158; // @[Decoupled.scala:51:35]
wire _dec_T_316 = d_sel_158 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_158 = _dec_T_316 & _dec_T_317; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_632 = {1'h0, count_158} + {1'h0, inc_158}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_633 = _count_T_632[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_634 = {1'h0, _count_T_633} - {1'h0, dec_158}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_635 = _count_T_634[0]; // @[ToAXI4.scala:278:37]
wire _idStall_158_T = ~idle_158; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_158_T_3 = _idStall_158_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_158 = _idStall_158_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_159; // @[ToAXI4.scala:272:28]
wire _idStall_159_T_2 = count_159; // @[ToAXI4.scala:272:28, :286:44]
reg write_159; // @[ToAXI4.scala:273:24]
wire idle_159 = ~count_159; // @[ToAXI4.scala:272:28, :274:26]
wire inc_159 = a_sel_159 & _inc_T_159; // @[Decoupled.scala:51:35]
wire _dec_T_318 = d_sel_159 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_159 = _dec_T_318 & _dec_T_319; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_636 = {1'h0, count_159} + {1'h0, inc_159}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_637 = _count_T_636[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_638 = {1'h0, _count_T_637} - {1'h0, dec_159}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_639 = _count_T_638[0]; // @[ToAXI4.scala:278:37]
wire _idStall_159_T = ~idle_159; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_159_T_3 = _idStall_159_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_159 = _idStall_159_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_160; // @[ToAXI4.scala:272:28]
wire _idStall_160_T_2 = count_160; // @[ToAXI4.scala:272:28, :286:44]
reg write_160; // @[ToAXI4.scala:273:24]
wire idle_160 = ~count_160; // @[ToAXI4.scala:272:28, :274:26]
wire inc_160 = a_sel_160 & _inc_T_160; // @[Decoupled.scala:51:35]
wire _dec_T_320 = d_sel_160 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_160 = _dec_T_320 & _dec_T_321; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_640 = {1'h0, count_160} + {1'h0, inc_160}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_641 = _count_T_640[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_642 = {1'h0, _count_T_641} - {1'h0, dec_160}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_643 = _count_T_642[0]; // @[ToAXI4.scala:278:37]
wire _idStall_160_T = ~idle_160; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_160_T_3 = _idStall_160_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_160 = _idStall_160_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_161; // @[ToAXI4.scala:272:28]
wire _idStall_161_T_2 = count_161; // @[ToAXI4.scala:272:28, :286:44]
reg write_161; // @[ToAXI4.scala:273:24]
wire idle_161 = ~count_161; // @[ToAXI4.scala:272:28, :274:26]
wire inc_161 = a_sel_161 & _inc_T_161; // @[Decoupled.scala:51:35]
wire _dec_T_322 = d_sel_161 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_161 = _dec_T_322 & _dec_T_323; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_644 = {1'h0, count_161} + {1'h0, inc_161}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_645 = _count_T_644[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_646 = {1'h0, _count_T_645} - {1'h0, dec_161}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_647 = _count_T_646[0]; // @[ToAXI4.scala:278:37]
wire _idStall_161_T = ~idle_161; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_161_T_3 = _idStall_161_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_161 = _idStall_161_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_162; // @[ToAXI4.scala:272:28]
wire _idStall_162_T_2 = count_162; // @[ToAXI4.scala:272:28, :286:44]
reg write_162; // @[ToAXI4.scala:273:24]
wire idle_162 = ~count_162; // @[ToAXI4.scala:272:28, :274:26]
wire inc_162 = a_sel_162 & _inc_T_162; // @[Decoupled.scala:51:35]
wire _dec_T_324 = d_sel_162 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_162 = _dec_T_324 & _dec_T_325; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_648 = {1'h0, count_162} + {1'h0, inc_162}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_649 = _count_T_648[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_650 = {1'h0, _count_T_649} - {1'h0, dec_162}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_651 = _count_T_650[0]; // @[ToAXI4.scala:278:37]
wire _idStall_162_T = ~idle_162; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_162_T_3 = _idStall_162_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_162 = _idStall_162_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_163; // @[ToAXI4.scala:272:28]
wire _idStall_163_T_2 = count_163; // @[ToAXI4.scala:272:28, :286:44]
reg write_163; // @[ToAXI4.scala:273:24]
wire idle_163 = ~count_163; // @[ToAXI4.scala:272:28, :274:26]
wire inc_163 = a_sel_163 & _inc_T_163; // @[Decoupled.scala:51:35]
wire _dec_T_326 = d_sel_163 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_163 = _dec_T_326 & _dec_T_327; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_652 = {1'h0, count_163} + {1'h0, inc_163}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_653 = _count_T_652[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_654 = {1'h0, _count_T_653} - {1'h0, dec_163}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_655 = _count_T_654[0]; // @[ToAXI4.scala:278:37]
wire _idStall_163_T = ~idle_163; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_163_T_3 = _idStall_163_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_163 = _idStall_163_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_164; // @[ToAXI4.scala:272:28]
wire _idStall_164_T_2 = count_164; // @[ToAXI4.scala:272:28, :286:44]
reg write_164; // @[ToAXI4.scala:273:24]
wire idle_164 = ~count_164; // @[ToAXI4.scala:272:28, :274:26]
wire inc_164 = a_sel_164 & _inc_T_164; // @[Decoupled.scala:51:35]
wire _dec_T_328 = d_sel_164 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_164 = _dec_T_328 & _dec_T_329; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_656 = {1'h0, count_164} + {1'h0, inc_164}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_657 = _count_T_656[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_658 = {1'h0, _count_T_657} - {1'h0, dec_164}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_659 = _count_T_658[0]; // @[ToAXI4.scala:278:37]
wire _idStall_164_T = ~idle_164; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_164_T_3 = _idStall_164_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_164 = _idStall_164_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_165; // @[ToAXI4.scala:272:28]
wire _idStall_165_T_2 = count_165; // @[ToAXI4.scala:272:28, :286:44]
reg write_165; // @[ToAXI4.scala:273:24]
wire idle_165 = ~count_165; // @[ToAXI4.scala:272:28, :274:26]
wire inc_165 = a_sel_165 & _inc_T_165; // @[Decoupled.scala:51:35]
wire _dec_T_330 = d_sel_165 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_165 = _dec_T_330 & _dec_T_331; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_660 = {1'h0, count_165} + {1'h0, inc_165}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_661 = _count_T_660[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_662 = {1'h0, _count_T_661} - {1'h0, dec_165}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_663 = _count_T_662[0]; // @[ToAXI4.scala:278:37]
wire _idStall_165_T = ~idle_165; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_165_T_3 = _idStall_165_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_165 = _idStall_165_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_166; // @[ToAXI4.scala:272:28]
wire _idStall_166_T_2 = count_166; // @[ToAXI4.scala:272:28, :286:44]
reg write_166; // @[ToAXI4.scala:273:24]
wire idle_166 = ~count_166; // @[ToAXI4.scala:272:28, :274:26]
wire inc_166 = a_sel_166 & _inc_T_166; // @[Decoupled.scala:51:35]
wire _dec_T_332 = d_sel_166 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_166 = _dec_T_332 & _dec_T_333; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_664 = {1'h0, count_166} + {1'h0, inc_166}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_665 = _count_T_664[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_666 = {1'h0, _count_T_665} - {1'h0, dec_166}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_667 = _count_T_666[0]; // @[ToAXI4.scala:278:37]
wire _idStall_166_T = ~idle_166; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_166_T_3 = _idStall_166_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_166 = _idStall_166_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_167; // @[ToAXI4.scala:272:28]
wire _idStall_167_T_2 = count_167; // @[ToAXI4.scala:272:28, :286:44]
reg write_167; // @[ToAXI4.scala:273:24]
wire idle_167 = ~count_167; // @[ToAXI4.scala:272:28, :274:26]
wire inc_167 = a_sel_167 & _inc_T_167; // @[Decoupled.scala:51:35]
wire _dec_T_334 = d_sel_167 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_167 = _dec_T_334 & _dec_T_335; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_668 = {1'h0, count_167} + {1'h0, inc_167}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_669 = _count_T_668[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_670 = {1'h0, _count_T_669} - {1'h0, dec_167}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_671 = _count_T_670[0]; // @[ToAXI4.scala:278:37]
wire _idStall_167_T = ~idle_167; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_167_T_3 = _idStall_167_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_167 = _idStall_167_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_168; // @[ToAXI4.scala:272:28]
wire _idStall_168_T_2 = count_168; // @[ToAXI4.scala:272:28, :286:44]
reg write_168; // @[ToAXI4.scala:273:24]
wire idle_168 = ~count_168; // @[ToAXI4.scala:272:28, :274:26]
wire inc_168 = a_sel_168 & _inc_T_168; // @[Decoupled.scala:51:35]
wire _dec_T_336 = d_sel_168 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_168 = _dec_T_336 & _dec_T_337; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_672 = {1'h0, count_168} + {1'h0, inc_168}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_673 = _count_T_672[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_674 = {1'h0, _count_T_673} - {1'h0, dec_168}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_675 = _count_T_674[0]; // @[ToAXI4.scala:278:37]
wire _idStall_168_T = ~idle_168; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_168_T_3 = _idStall_168_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_168 = _idStall_168_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_169; // @[ToAXI4.scala:272:28]
wire _idStall_169_T_2 = count_169; // @[ToAXI4.scala:272:28, :286:44]
reg write_169; // @[ToAXI4.scala:273:24]
wire idle_169 = ~count_169; // @[ToAXI4.scala:272:28, :274:26]
wire inc_169 = a_sel_169 & _inc_T_169; // @[Decoupled.scala:51:35]
wire _dec_T_338 = d_sel_169 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_169 = _dec_T_338 & _dec_T_339; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_676 = {1'h0, count_169} + {1'h0, inc_169}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_677 = _count_T_676[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_678 = {1'h0, _count_T_677} - {1'h0, dec_169}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_679 = _count_T_678[0]; // @[ToAXI4.scala:278:37]
wire _idStall_169_T = ~idle_169; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_169_T_3 = _idStall_169_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_169 = _idStall_169_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_170; // @[ToAXI4.scala:272:28]
wire _idStall_170_T_2 = count_170; // @[ToAXI4.scala:272:28, :286:44]
reg write_170; // @[ToAXI4.scala:273:24]
wire idle_170 = ~count_170; // @[ToAXI4.scala:272:28, :274:26]
wire inc_170 = a_sel_170 & _inc_T_170; // @[Decoupled.scala:51:35]
wire _dec_T_340 = d_sel_170 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_170 = _dec_T_340 & _dec_T_341; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_680 = {1'h0, count_170} + {1'h0, inc_170}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_681 = _count_T_680[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_682 = {1'h0, _count_T_681} - {1'h0, dec_170}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_683 = _count_T_682[0]; // @[ToAXI4.scala:278:37]
wire _idStall_170_T = ~idle_170; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_170_T_3 = _idStall_170_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_170 = _idStall_170_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_171; // @[ToAXI4.scala:272:28]
wire _idStall_171_T_2 = count_171; // @[ToAXI4.scala:272:28, :286:44]
reg write_171; // @[ToAXI4.scala:273:24]
wire idle_171 = ~count_171; // @[ToAXI4.scala:272:28, :274:26]
wire inc_171 = a_sel_171 & _inc_T_171; // @[Decoupled.scala:51:35]
wire _dec_T_342 = d_sel_171 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_171 = _dec_T_342 & _dec_T_343; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_684 = {1'h0, count_171} + {1'h0, inc_171}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_685 = _count_T_684[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_686 = {1'h0, _count_T_685} - {1'h0, dec_171}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_687 = _count_T_686[0]; // @[ToAXI4.scala:278:37]
wire _idStall_171_T = ~idle_171; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_171_T_3 = _idStall_171_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_171 = _idStall_171_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_172; // @[ToAXI4.scala:272:28]
wire _idStall_172_T_2 = count_172; // @[ToAXI4.scala:272:28, :286:44]
reg write_172; // @[ToAXI4.scala:273:24]
wire idle_172 = ~count_172; // @[ToAXI4.scala:272:28, :274:26]
wire inc_172 = a_sel_172 & _inc_T_172; // @[Decoupled.scala:51:35]
wire _dec_T_344 = d_sel_172 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_172 = _dec_T_344 & _dec_T_345; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_688 = {1'h0, count_172} + {1'h0, inc_172}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_689 = _count_T_688[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_690 = {1'h0, _count_T_689} - {1'h0, dec_172}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_691 = _count_T_690[0]; // @[ToAXI4.scala:278:37]
wire _idStall_172_T = ~idle_172; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_172_T_3 = _idStall_172_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_172 = _idStall_172_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_173; // @[ToAXI4.scala:272:28]
wire _idStall_173_T_2 = count_173; // @[ToAXI4.scala:272:28, :286:44]
reg write_173; // @[ToAXI4.scala:273:24]
wire idle_173 = ~count_173; // @[ToAXI4.scala:272:28, :274:26]
wire inc_173 = a_sel_173 & _inc_T_173; // @[Decoupled.scala:51:35]
wire _dec_T_346 = d_sel_173 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_173 = _dec_T_346 & _dec_T_347; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_692 = {1'h0, count_173} + {1'h0, inc_173}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_693 = _count_T_692[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_694 = {1'h0, _count_T_693} - {1'h0, dec_173}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_695 = _count_T_694[0]; // @[ToAXI4.scala:278:37]
wire _idStall_173_T = ~idle_173; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_173_T_3 = _idStall_173_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_173 = _idStall_173_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_174; // @[ToAXI4.scala:272:28]
wire _idStall_174_T_2 = count_174; // @[ToAXI4.scala:272:28, :286:44]
reg write_174; // @[ToAXI4.scala:273:24]
wire idle_174 = ~count_174; // @[ToAXI4.scala:272:28, :274:26]
wire inc_174 = a_sel_174 & _inc_T_174; // @[Decoupled.scala:51:35]
wire _dec_T_348 = d_sel_174 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_174 = _dec_T_348 & _dec_T_349; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_696 = {1'h0, count_174} + {1'h0, inc_174}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_697 = _count_T_696[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_698 = {1'h0, _count_T_697} - {1'h0, dec_174}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_699 = _count_T_698[0]; // @[ToAXI4.scala:278:37]
wire _idStall_174_T = ~idle_174; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_174_T_3 = _idStall_174_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_174 = _idStall_174_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_175; // @[ToAXI4.scala:272:28]
wire _idStall_175_T_2 = count_175; // @[ToAXI4.scala:272:28, :286:44]
reg write_175; // @[ToAXI4.scala:273:24]
wire idle_175 = ~count_175; // @[ToAXI4.scala:272:28, :274:26]
wire inc_175 = a_sel_175 & _inc_T_175; // @[Decoupled.scala:51:35]
wire _dec_T_350 = d_sel_175 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_175 = _dec_T_350 & _dec_T_351; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_700 = {1'h0, count_175} + {1'h0, inc_175}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_701 = _count_T_700[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_702 = {1'h0, _count_T_701} - {1'h0, dec_175}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_703 = _count_T_702[0]; // @[ToAXI4.scala:278:37]
wire _idStall_175_T = ~idle_175; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_175_T_3 = _idStall_175_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_175 = _idStall_175_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_176; // @[ToAXI4.scala:272:28]
wire _idStall_176_T_2 = count_176; // @[ToAXI4.scala:272:28, :286:44]
reg write_176; // @[ToAXI4.scala:273:24]
wire idle_176 = ~count_176; // @[ToAXI4.scala:272:28, :274:26]
wire inc_176 = a_sel_176 & _inc_T_176; // @[Decoupled.scala:51:35]
wire _dec_T_352 = d_sel_176 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_176 = _dec_T_352 & _dec_T_353; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_704 = {1'h0, count_176} + {1'h0, inc_176}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_705 = _count_T_704[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_706 = {1'h0, _count_T_705} - {1'h0, dec_176}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_707 = _count_T_706[0]; // @[ToAXI4.scala:278:37]
wire _idStall_176_T = ~idle_176; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_176_T_3 = _idStall_176_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_176 = _idStall_176_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_177; // @[ToAXI4.scala:272:28]
wire _idStall_177_T_2 = count_177; // @[ToAXI4.scala:272:28, :286:44]
reg write_177; // @[ToAXI4.scala:273:24]
wire idle_177 = ~count_177; // @[ToAXI4.scala:272:28, :274:26]
wire inc_177 = a_sel_177 & _inc_T_177; // @[Decoupled.scala:51:35]
wire _dec_T_354 = d_sel_177 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_177 = _dec_T_354 & _dec_T_355; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_708 = {1'h0, count_177} + {1'h0, inc_177}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_709 = _count_T_708[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_710 = {1'h0, _count_T_709} - {1'h0, dec_177}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_711 = _count_T_710[0]; // @[ToAXI4.scala:278:37]
wire _idStall_177_T = ~idle_177; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_177_T_3 = _idStall_177_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_177 = _idStall_177_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_178; // @[ToAXI4.scala:272:28]
wire _idStall_178_T_2 = count_178; // @[ToAXI4.scala:272:28, :286:44]
reg write_178; // @[ToAXI4.scala:273:24]
wire idle_178 = ~count_178; // @[ToAXI4.scala:272:28, :274:26]
wire inc_178 = a_sel_178 & _inc_T_178; // @[Decoupled.scala:51:35]
wire _dec_T_356 = d_sel_178 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_178 = _dec_T_356 & _dec_T_357; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_712 = {1'h0, count_178} + {1'h0, inc_178}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_713 = _count_T_712[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_714 = {1'h0, _count_T_713} - {1'h0, dec_178}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_715 = _count_T_714[0]; // @[ToAXI4.scala:278:37]
wire _idStall_178_T = ~idle_178; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_178_T_3 = _idStall_178_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_178 = _idStall_178_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_179; // @[ToAXI4.scala:272:28]
wire _idStall_179_T_2 = count_179; // @[ToAXI4.scala:272:28, :286:44]
reg write_179; // @[ToAXI4.scala:273:24]
wire idle_179 = ~count_179; // @[ToAXI4.scala:272:28, :274:26]
wire inc_179 = a_sel_179 & _inc_T_179; // @[Decoupled.scala:51:35]
wire _dec_T_358 = d_sel_179 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_179 = _dec_T_358 & _dec_T_359; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_716 = {1'h0, count_179} + {1'h0, inc_179}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_717 = _count_T_716[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_718 = {1'h0, _count_T_717} - {1'h0, dec_179}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_719 = _count_T_718[0]; // @[ToAXI4.scala:278:37]
wire _idStall_179_T = ~idle_179; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_179_T_3 = _idStall_179_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_179 = _idStall_179_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_180; // @[ToAXI4.scala:272:28]
wire _idStall_180_T_2 = count_180; // @[ToAXI4.scala:272:28, :286:44]
reg write_180; // @[ToAXI4.scala:273:24]
wire idle_180 = ~count_180; // @[ToAXI4.scala:272:28, :274:26]
wire inc_180 = a_sel_180 & _inc_T_180; // @[Decoupled.scala:51:35]
wire _dec_T_360 = d_sel_180 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_180 = _dec_T_360 & _dec_T_361; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_720 = {1'h0, count_180} + {1'h0, inc_180}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_721 = _count_T_720[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_722 = {1'h0, _count_T_721} - {1'h0, dec_180}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_723 = _count_T_722[0]; // @[ToAXI4.scala:278:37]
wire _idStall_180_T = ~idle_180; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_180_T_3 = _idStall_180_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_180 = _idStall_180_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_181; // @[ToAXI4.scala:272:28]
wire _idStall_181_T_2 = count_181; // @[ToAXI4.scala:272:28, :286:44]
reg write_181; // @[ToAXI4.scala:273:24]
wire idle_181 = ~count_181; // @[ToAXI4.scala:272:28, :274:26]
wire inc_181 = a_sel_181 & _inc_T_181; // @[Decoupled.scala:51:35]
wire _dec_T_362 = d_sel_181 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_181 = _dec_T_362 & _dec_T_363; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_724 = {1'h0, count_181} + {1'h0, inc_181}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_725 = _count_T_724[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_726 = {1'h0, _count_T_725} - {1'h0, dec_181}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_727 = _count_T_726[0]; // @[ToAXI4.scala:278:37]
wire _idStall_181_T = ~idle_181; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_181_T_3 = _idStall_181_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_181 = _idStall_181_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_182; // @[ToAXI4.scala:272:28]
wire _idStall_182_T_2 = count_182; // @[ToAXI4.scala:272:28, :286:44]
reg write_182; // @[ToAXI4.scala:273:24]
wire idle_182 = ~count_182; // @[ToAXI4.scala:272:28, :274:26]
wire inc_182 = a_sel_182 & _inc_T_182; // @[Decoupled.scala:51:35]
wire _dec_T_364 = d_sel_182 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_182 = _dec_T_364 & _dec_T_365; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_728 = {1'h0, count_182} + {1'h0, inc_182}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_729 = _count_T_728[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_730 = {1'h0, _count_T_729} - {1'h0, dec_182}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_731 = _count_T_730[0]; // @[ToAXI4.scala:278:37]
wire _idStall_182_T = ~idle_182; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_182_T_3 = _idStall_182_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_182 = _idStall_182_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_183; // @[ToAXI4.scala:272:28]
wire _idStall_183_T_2 = count_183; // @[ToAXI4.scala:272:28, :286:44]
reg write_183; // @[ToAXI4.scala:273:24]
wire idle_183 = ~count_183; // @[ToAXI4.scala:272:28, :274:26]
wire inc_183 = a_sel_183 & _inc_T_183; // @[Decoupled.scala:51:35]
wire _dec_T_366 = d_sel_183 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_183 = _dec_T_366 & _dec_T_367; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_732 = {1'h0, count_183} + {1'h0, inc_183}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_733 = _count_T_732[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_734 = {1'h0, _count_T_733} - {1'h0, dec_183}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_735 = _count_T_734[0]; // @[ToAXI4.scala:278:37]
wire _idStall_183_T = ~idle_183; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_183_T_3 = _idStall_183_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_183 = _idStall_183_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_184; // @[ToAXI4.scala:272:28]
wire _idStall_184_T_2 = count_184; // @[ToAXI4.scala:272:28, :286:44]
reg write_184; // @[ToAXI4.scala:273:24]
wire idle_184 = ~count_184; // @[ToAXI4.scala:272:28, :274:26]
wire inc_184 = a_sel_184 & _inc_T_184; // @[Decoupled.scala:51:35]
wire _dec_T_368 = d_sel_184 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_184 = _dec_T_368 & _dec_T_369; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_736 = {1'h0, count_184} + {1'h0, inc_184}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_737 = _count_T_736[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_738 = {1'h0, _count_T_737} - {1'h0, dec_184}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_739 = _count_T_738[0]; // @[ToAXI4.scala:278:37]
wire _idStall_184_T = ~idle_184; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_184_T_3 = _idStall_184_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_184 = _idStall_184_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_185; // @[ToAXI4.scala:272:28]
wire _idStall_185_T_2 = count_185; // @[ToAXI4.scala:272:28, :286:44]
reg write_185; // @[ToAXI4.scala:273:24]
wire idle_185 = ~count_185; // @[ToAXI4.scala:272:28, :274:26]
wire inc_185 = a_sel_185 & _inc_T_185; // @[Decoupled.scala:51:35]
wire _dec_T_370 = d_sel_185 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_185 = _dec_T_370 & _dec_T_371; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_740 = {1'h0, count_185} + {1'h0, inc_185}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_741 = _count_T_740[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_742 = {1'h0, _count_T_741} - {1'h0, dec_185}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_743 = _count_T_742[0]; // @[ToAXI4.scala:278:37]
wire _idStall_185_T = ~idle_185; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_185_T_3 = _idStall_185_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_185 = _idStall_185_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_186; // @[ToAXI4.scala:272:28]
wire _idStall_186_T_2 = count_186; // @[ToAXI4.scala:272:28, :286:44]
reg write_186; // @[ToAXI4.scala:273:24]
wire idle_186 = ~count_186; // @[ToAXI4.scala:272:28, :274:26]
wire inc_186 = a_sel_186 & _inc_T_186; // @[Decoupled.scala:51:35]
wire _dec_T_372 = d_sel_186 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_186 = _dec_T_372 & _dec_T_373; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_744 = {1'h0, count_186} + {1'h0, inc_186}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_745 = _count_T_744[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_746 = {1'h0, _count_T_745} - {1'h0, dec_186}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_747 = _count_T_746[0]; // @[ToAXI4.scala:278:37]
wire _idStall_186_T = ~idle_186; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_186_T_3 = _idStall_186_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_186 = _idStall_186_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_187; // @[ToAXI4.scala:272:28]
wire _idStall_187_T_2 = count_187; // @[ToAXI4.scala:272:28, :286:44]
reg write_187; // @[ToAXI4.scala:273:24]
wire idle_187 = ~count_187; // @[ToAXI4.scala:272:28, :274:26]
wire inc_187 = a_sel_187 & _inc_T_187; // @[Decoupled.scala:51:35]
wire _dec_T_374 = d_sel_187 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_187 = _dec_T_374 & _dec_T_375; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_748 = {1'h0, count_187} + {1'h0, inc_187}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_749 = _count_T_748[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_750 = {1'h0, _count_T_749} - {1'h0, dec_187}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_751 = _count_T_750[0]; // @[ToAXI4.scala:278:37]
wire _idStall_187_T = ~idle_187; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_187_T_3 = _idStall_187_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_187 = _idStall_187_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_188; // @[ToAXI4.scala:272:28]
wire _idStall_188_T_2 = count_188; // @[ToAXI4.scala:272:28, :286:44]
reg write_188; // @[ToAXI4.scala:273:24]
wire idle_188 = ~count_188; // @[ToAXI4.scala:272:28, :274:26]
wire inc_188 = a_sel_188 & _inc_T_188; // @[Decoupled.scala:51:35]
wire _dec_T_376 = d_sel_188 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_188 = _dec_T_376 & _dec_T_377; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_752 = {1'h0, count_188} + {1'h0, inc_188}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_753 = _count_T_752[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_754 = {1'h0, _count_T_753} - {1'h0, dec_188}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_755 = _count_T_754[0]; // @[ToAXI4.scala:278:37]
wire _idStall_188_T = ~idle_188; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_188_T_3 = _idStall_188_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_188 = _idStall_188_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_189; // @[ToAXI4.scala:272:28]
wire _idStall_189_T_2 = count_189; // @[ToAXI4.scala:272:28, :286:44]
reg write_189; // @[ToAXI4.scala:273:24]
wire idle_189 = ~count_189; // @[ToAXI4.scala:272:28, :274:26]
wire inc_189 = a_sel_189 & _inc_T_189; // @[Decoupled.scala:51:35]
wire _dec_T_378 = d_sel_189 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_189 = _dec_T_378 & _dec_T_379; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_756 = {1'h0, count_189} + {1'h0, inc_189}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_757 = _count_T_756[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_758 = {1'h0, _count_T_757} - {1'h0, dec_189}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_759 = _count_T_758[0]; // @[ToAXI4.scala:278:37]
wire _idStall_189_T = ~idle_189; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_189_T_3 = _idStall_189_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_189 = _idStall_189_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_190; // @[ToAXI4.scala:272:28]
wire _idStall_190_T_2 = count_190; // @[ToAXI4.scala:272:28, :286:44]
reg write_190; // @[ToAXI4.scala:273:24]
wire idle_190 = ~count_190; // @[ToAXI4.scala:272:28, :274:26]
wire inc_190 = a_sel_190 & _inc_T_190; // @[Decoupled.scala:51:35]
wire _dec_T_380 = d_sel_190 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_190 = _dec_T_380 & _dec_T_381; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_760 = {1'h0, count_190} + {1'h0, inc_190}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_761 = _count_T_760[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_762 = {1'h0, _count_T_761} - {1'h0, dec_190}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_763 = _count_T_762[0]; // @[ToAXI4.scala:278:37]
wire _idStall_190_T = ~idle_190; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_190_T_3 = _idStall_190_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_190 = _idStall_190_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_191; // @[ToAXI4.scala:272:28]
wire _idStall_191_T_2 = count_191; // @[ToAXI4.scala:272:28, :286:44]
reg write_191; // @[ToAXI4.scala:273:24]
wire idle_191 = ~count_191; // @[ToAXI4.scala:272:28, :274:26]
wire inc_191 = a_sel_191 & _inc_T_191; // @[Decoupled.scala:51:35]
wire _dec_T_382 = d_sel_191 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_191 = _dec_T_382 & _dec_T_383; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_764 = {1'h0, count_191} + {1'h0, inc_191}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_765 = _count_T_764[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_766 = {1'h0, _count_T_765} - {1'h0, dec_191}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_767 = _count_T_766[0]; // @[ToAXI4.scala:278:37]
wire _idStall_191_T = ~idle_191; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_191_T_3 = _idStall_191_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_191 = _idStall_191_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_192; // @[ToAXI4.scala:272:28]
wire _idStall_192_T_2 = count_192; // @[ToAXI4.scala:272:28, :286:44]
reg write_192; // @[ToAXI4.scala:273:24]
wire idle_192 = ~count_192; // @[ToAXI4.scala:272:28, :274:26]
wire inc_192 = a_sel_192 & _inc_T_192; // @[Decoupled.scala:51:35]
wire _dec_T_384 = d_sel_192 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_192 = _dec_T_384 & _dec_T_385; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_768 = {1'h0, count_192} + {1'h0, inc_192}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_769 = _count_T_768[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_770 = {1'h0, _count_T_769} - {1'h0, dec_192}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_771 = _count_T_770[0]; // @[ToAXI4.scala:278:37]
wire _idStall_192_T = ~idle_192; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_192_T_3 = _idStall_192_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_192 = _idStall_192_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_193; // @[ToAXI4.scala:272:28]
wire _idStall_193_T_2 = count_193; // @[ToAXI4.scala:272:28, :286:44]
reg write_193; // @[ToAXI4.scala:273:24]
wire idle_193 = ~count_193; // @[ToAXI4.scala:272:28, :274:26]
wire inc_193 = a_sel_193 & _inc_T_193; // @[Decoupled.scala:51:35]
wire _dec_T_386 = d_sel_193 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_193 = _dec_T_386 & _dec_T_387; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_772 = {1'h0, count_193} + {1'h0, inc_193}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_773 = _count_T_772[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_774 = {1'h0, _count_T_773} - {1'h0, dec_193}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_775 = _count_T_774[0]; // @[ToAXI4.scala:278:37]
wire _idStall_193_T = ~idle_193; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_193_T_3 = _idStall_193_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_193 = _idStall_193_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_194; // @[ToAXI4.scala:272:28]
wire _idStall_194_T_2 = count_194; // @[ToAXI4.scala:272:28, :286:44]
reg write_194; // @[ToAXI4.scala:273:24]
wire idle_194 = ~count_194; // @[ToAXI4.scala:272:28, :274:26]
wire inc_194 = a_sel_194 & _inc_T_194; // @[Decoupled.scala:51:35]
wire _dec_T_388 = d_sel_194 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_194 = _dec_T_388 & _dec_T_389; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_776 = {1'h0, count_194} + {1'h0, inc_194}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_777 = _count_T_776[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_778 = {1'h0, _count_T_777} - {1'h0, dec_194}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_779 = _count_T_778[0]; // @[ToAXI4.scala:278:37]
wire _idStall_194_T = ~idle_194; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_194_T_3 = _idStall_194_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_194 = _idStall_194_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_195; // @[ToAXI4.scala:272:28]
wire _idStall_195_T_2 = count_195; // @[ToAXI4.scala:272:28, :286:44]
reg write_195; // @[ToAXI4.scala:273:24]
wire idle_195 = ~count_195; // @[ToAXI4.scala:272:28, :274:26]
wire inc_195 = a_sel_195 & _inc_T_195; // @[Decoupled.scala:51:35]
wire _dec_T_390 = d_sel_195 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_195 = _dec_T_390 & _dec_T_391; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_780 = {1'h0, count_195} + {1'h0, inc_195}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_781 = _count_T_780[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_782 = {1'h0, _count_T_781} - {1'h0, dec_195}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_783 = _count_T_782[0]; // @[ToAXI4.scala:278:37]
wire _idStall_195_T = ~idle_195; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_195_T_3 = _idStall_195_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_195 = _idStall_195_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_196; // @[ToAXI4.scala:272:28]
wire _idStall_196_T_2 = count_196; // @[ToAXI4.scala:272:28, :286:44]
reg write_196; // @[ToAXI4.scala:273:24]
wire idle_196 = ~count_196; // @[ToAXI4.scala:272:28, :274:26]
wire inc_196 = a_sel_196 & _inc_T_196; // @[Decoupled.scala:51:35]
wire _dec_T_392 = d_sel_196 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_196 = _dec_T_392 & _dec_T_393; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_784 = {1'h0, count_196} + {1'h0, inc_196}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_785 = _count_T_784[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_786 = {1'h0, _count_T_785} - {1'h0, dec_196}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_787 = _count_T_786[0]; // @[ToAXI4.scala:278:37]
wire _idStall_196_T = ~idle_196; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_196_T_3 = _idStall_196_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_196 = _idStall_196_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_197; // @[ToAXI4.scala:272:28]
wire _idStall_197_T_2 = count_197; // @[ToAXI4.scala:272:28, :286:44]
reg write_197; // @[ToAXI4.scala:273:24]
wire idle_197 = ~count_197; // @[ToAXI4.scala:272:28, :274:26]
wire inc_197 = a_sel_197 & _inc_T_197; // @[Decoupled.scala:51:35]
wire _dec_T_394 = d_sel_197 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_197 = _dec_T_394 & _dec_T_395; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_788 = {1'h0, count_197} + {1'h0, inc_197}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_789 = _count_T_788[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_790 = {1'h0, _count_T_789} - {1'h0, dec_197}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_791 = _count_T_790[0]; // @[ToAXI4.scala:278:37]
wire _idStall_197_T = ~idle_197; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_197_T_3 = _idStall_197_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_197 = _idStall_197_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_198; // @[ToAXI4.scala:272:28]
wire _idStall_198_T_2 = count_198; // @[ToAXI4.scala:272:28, :286:44]
reg write_198; // @[ToAXI4.scala:273:24]
wire idle_198 = ~count_198; // @[ToAXI4.scala:272:28, :274:26]
wire inc_198 = a_sel_198 & _inc_T_198; // @[Decoupled.scala:51:35]
wire _dec_T_396 = d_sel_198 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_198 = _dec_T_396 & _dec_T_397; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_792 = {1'h0, count_198} + {1'h0, inc_198}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_793 = _count_T_792[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_794 = {1'h0, _count_T_793} - {1'h0, dec_198}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_795 = _count_T_794[0]; // @[ToAXI4.scala:278:37]
wire _idStall_198_T = ~idle_198; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_198_T_3 = _idStall_198_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_198 = _idStall_198_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_199; // @[ToAXI4.scala:272:28]
wire _idStall_199_T_2 = count_199; // @[ToAXI4.scala:272:28, :286:44]
reg write_199; // @[ToAXI4.scala:273:24]
wire idle_199 = ~count_199; // @[ToAXI4.scala:272:28, :274:26]
wire inc_199 = a_sel_199 & _inc_T_199; // @[Decoupled.scala:51:35]
wire _dec_T_398 = d_sel_199 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_199 = _dec_T_398 & _dec_T_399; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_796 = {1'h0, count_199} + {1'h0, inc_199}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_797 = _count_T_796[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_798 = {1'h0, _count_T_797} - {1'h0, dec_199}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_799 = _count_T_798[0]; // @[ToAXI4.scala:278:37]
wire _idStall_199_T = ~idle_199; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_199_T_3 = _idStall_199_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_199 = _idStall_199_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_200; // @[ToAXI4.scala:272:28]
wire _idStall_200_T_2 = count_200; // @[ToAXI4.scala:272:28, :286:44]
reg write_200; // @[ToAXI4.scala:273:24]
wire idle_200 = ~count_200; // @[ToAXI4.scala:272:28, :274:26]
wire inc_200 = a_sel_200 & _inc_T_200; // @[Decoupled.scala:51:35]
wire _dec_T_400 = d_sel_200 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_200 = _dec_T_400 & _dec_T_401; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_800 = {1'h0, count_200} + {1'h0, inc_200}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_801 = _count_T_800[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_802 = {1'h0, _count_T_801} - {1'h0, dec_200}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_803 = _count_T_802[0]; // @[ToAXI4.scala:278:37]
wire _idStall_200_T = ~idle_200; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_200_T_3 = _idStall_200_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_200 = _idStall_200_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_201; // @[ToAXI4.scala:272:28]
wire _idStall_201_T_2 = count_201; // @[ToAXI4.scala:272:28, :286:44]
reg write_201; // @[ToAXI4.scala:273:24]
wire idle_201 = ~count_201; // @[ToAXI4.scala:272:28, :274:26]
wire inc_201 = a_sel_201 & _inc_T_201; // @[Decoupled.scala:51:35]
wire _dec_T_402 = d_sel_201 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_201 = _dec_T_402 & _dec_T_403; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_804 = {1'h0, count_201} + {1'h0, inc_201}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_805 = _count_T_804[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_806 = {1'h0, _count_T_805} - {1'h0, dec_201}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_807 = _count_T_806[0]; // @[ToAXI4.scala:278:37]
wire _idStall_201_T = ~idle_201; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_201_T_3 = _idStall_201_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_201 = _idStall_201_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_202; // @[ToAXI4.scala:272:28]
wire _idStall_202_T_2 = count_202; // @[ToAXI4.scala:272:28, :286:44]
reg write_202; // @[ToAXI4.scala:273:24]
wire idle_202 = ~count_202; // @[ToAXI4.scala:272:28, :274:26]
wire inc_202 = a_sel_202 & _inc_T_202; // @[Decoupled.scala:51:35]
wire _dec_T_404 = d_sel_202 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_202 = _dec_T_404 & _dec_T_405; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_808 = {1'h0, count_202} + {1'h0, inc_202}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_809 = _count_T_808[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_810 = {1'h0, _count_T_809} - {1'h0, dec_202}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_811 = _count_T_810[0]; // @[ToAXI4.scala:278:37]
wire _idStall_202_T = ~idle_202; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_202_T_3 = _idStall_202_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_202 = _idStall_202_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_203; // @[ToAXI4.scala:272:28]
wire _idStall_203_T_2 = count_203; // @[ToAXI4.scala:272:28, :286:44]
reg write_203; // @[ToAXI4.scala:273:24]
wire idle_203 = ~count_203; // @[ToAXI4.scala:272:28, :274:26]
wire inc_203 = a_sel_203 & _inc_T_203; // @[Decoupled.scala:51:35]
wire _dec_T_406 = d_sel_203 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_203 = _dec_T_406 & _dec_T_407; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_812 = {1'h0, count_203} + {1'h0, inc_203}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_813 = _count_T_812[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_814 = {1'h0, _count_T_813} - {1'h0, dec_203}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_815 = _count_T_814[0]; // @[ToAXI4.scala:278:37]
wire _idStall_203_T = ~idle_203; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_203_T_3 = _idStall_203_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_203 = _idStall_203_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_204; // @[ToAXI4.scala:272:28]
wire _idStall_204_T_2 = count_204; // @[ToAXI4.scala:272:28, :286:44]
reg write_204; // @[ToAXI4.scala:273:24]
wire idle_204 = ~count_204; // @[ToAXI4.scala:272:28, :274:26]
wire inc_204 = a_sel_204 & _inc_T_204; // @[Decoupled.scala:51:35]
wire _dec_T_408 = d_sel_204 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_204 = _dec_T_408 & _dec_T_409; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_816 = {1'h0, count_204} + {1'h0, inc_204}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_817 = _count_T_816[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_818 = {1'h0, _count_T_817} - {1'h0, dec_204}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_819 = _count_T_818[0]; // @[ToAXI4.scala:278:37]
wire _idStall_204_T = ~idle_204; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_204_T_3 = _idStall_204_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_204 = _idStall_204_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_205; // @[ToAXI4.scala:272:28]
wire _idStall_205_T_2 = count_205; // @[ToAXI4.scala:272:28, :286:44]
reg write_205; // @[ToAXI4.scala:273:24]
wire idle_205 = ~count_205; // @[ToAXI4.scala:272:28, :274:26]
wire inc_205 = a_sel_205 & _inc_T_205; // @[Decoupled.scala:51:35]
wire _dec_T_410 = d_sel_205 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_205 = _dec_T_410 & _dec_T_411; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_820 = {1'h0, count_205} + {1'h0, inc_205}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_821 = _count_T_820[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_822 = {1'h0, _count_T_821} - {1'h0, dec_205}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_823 = _count_T_822[0]; // @[ToAXI4.scala:278:37]
wire _idStall_205_T = ~idle_205; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_205_T_3 = _idStall_205_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_205 = _idStall_205_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_206; // @[ToAXI4.scala:272:28]
wire _idStall_206_T_2 = count_206; // @[ToAXI4.scala:272:28, :286:44]
reg write_206; // @[ToAXI4.scala:273:24]
wire idle_206 = ~count_206; // @[ToAXI4.scala:272:28, :274:26]
wire inc_206 = a_sel_206 & _inc_T_206; // @[Decoupled.scala:51:35]
wire _dec_T_412 = d_sel_206 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_206 = _dec_T_412 & _dec_T_413; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_824 = {1'h0, count_206} + {1'h0, inc_206}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_825 = _count_T_824[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_826 = {1'h0, _count_T_825} - {1'h0, dec_206}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_827 = _count_T_826[0]; // @[ToAXI4.scala:278:37]
wire _idStall_206_T = ~idle_206; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_206_T_3 = _idStall_206_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_206 = _idStall_206_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_207; // @[ToAXI4.scala:272:28]
wire _idStall_207_T_2 = count_207; // @[ToAXI4.scala:272:28, :286:44]
reg write_207; // @[ToAXI4.scala:273:24]
wire idle_207 = ~count_207; // @[ToAXI4.scala:272:28, :274:26]
wire inc_207 = a_sel_207 & _inc_T_207; // @[Decoupled.scala:51:35]
wire _dec_T_414 = d_sel_207 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_207 = _dec_T_414 & _dec_T_415; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_828 = {1'h0, count_207} + {1'h0, inc_207}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_829 = _count_T_828[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_830 = {1'h0, _count_T_829} - {1'h0, dec_207}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_831 = _count_T_830[0]; // @[ToAXI4.scala:278:37]
wire _idStall_207_T = ~idle_207; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_207_T_3 = _idStall_207_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_207 = _idStall_207_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_208; // @[ToAXI4.scala:272:28]
wire _idStall_208_T_2 = count_208; // @[ToAXI4.scala:272:28, :286:44]
reg write_208; // @[ToAXI4.scala:273:24]
wire idle_208 = ~count_208; // @[ToAXI4.scala:272:28, :274:26]
wire inc_208 = a_sel_208 & _inc_T_208; // @[Decoupled.scala:51:35]
wire _dec_T_416 = d_sel_208 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_208 = _dec_T_416 & _dec_T_417; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_832 = {1'h0, count_208} + {1'h0, inc_208}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_833 = _count_T_832[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_834 = {1'h0, _count_T_833} - {1'h0, dec_208}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_835 = _count_T_834[0]; // @[ToAXI4.scala:278:37]
wire _idStall_208_T = ~idle_208; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_208_T_3 = _idStall_208_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_208 = _idStall_208_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_209; // @[ToAXI4.scala:272:28]
wire _idStall_209_T_2 = count_209; // @[ToAXI4.scala:272:28, :286:44]
reg write_209; // @[ToAXI4.scala:273:24]
wire idle_209 = ~count_209; // @[ToAXI4.scala:272:28, :274:26]
wire inc_209 = a_sel_209 & _inc_T_209; // @[Decoupled.scala:51:35]
wire _dec_T_418 = d_sel_209 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_209 = _dec_T_418 & _dec_T_419; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_836 = {1'h0, count_209} + {1'h0, inc_209}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_837 = _count_T_836[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_838 = {1'h0, _count_T_837} - {1'h0, dec_209}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_839 = _count_T_838[0]; // @[ToAXI4.scala:278:37]
wire _idStall_209_T = ~idle_209; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_209_T_3 = _idStall_209_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_209 = _idStall_209_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_210; // @[ToAXI4.scala:272:28]
wire _idStall_210_T_2 = count_210; // @[ToAXI4.scala:272:28, :286:44]
reg write_210; // @[ToAXI4.scala:273:24]
wire idle_210 = ~count_210; // @[ToAXI4.scala:272:28, :274:26]
wire inc_210 = a_sel_210 & _inc_T_210; // @[Decoupled.scala:51:35]
wire _dec_T_420 = d_sel_210 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_210 = _dec_T_420 & _dec_T_421; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_840 = {1'h0, count_210} + {1'h0, inc_210}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_841 = _count_T_840[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_842 = {1'h0, _count_T_841} - {1'h0, dec_210}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_843 = _count_T_842[0]; // @[ToAXI4.scala:278:37]
wire _idStall_210_T = ~idle_210; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_210_T_3 = _idStall_210_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_210 = _idStall_210_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_211; // @[ToAXI4.scala:272:28]
wire _idStall_211_T_2 = count_211; // @[ToAXI4.scala:272:28, :286:44]
reg write_211; // @[ToAXI4.scala:273:24]
wire idle_211 = ~count_211; // @[ToAXI4.scala:272:28, :274:26]
wire inc_211 = a_sel_211 & _inc_T_211; // @[Decoupled.scala:51:35]
wire _dec_T_422 = d_sel_211 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_211 = _dec_T_422 & _dec_T_423; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_844 = {1'h0, count_211} + {1'h0, inc_211}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_845 = _count_T_844[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_846 = {1'h0, _count_T_845} - {1'h0, dec_211}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_847 = _count_T_846[0]; // @[ToAXI4.scala:278:37]
wire _idStall_211_T = ~idle_211; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_211_T_3 = _idStall_211_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_211 = _idStall_211_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_212; // @[ToAXI4.scala:272:28]
wire _idStall_212_T_2 = count_212; // @[ToAXI4.scala:272:28, :286:44]
reg write_212; // @[ToAXI4.scala:273:24]
wire idle_212 = ~count_212; // @[ToAXI4.scala:272:28, :274:26]
wire inc_212 = a_sel_212 & _inc_T_212; // @[Decoupled.scala:51:35]
wire _dec_T_424 = d_sel_212 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_212 = _dec_T_424 & _dec_T_425; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_848 = {1'h0, count_212} + {1'h0, inc_212}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_849 = _count_T_848[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_850 = {1'h0, _count_T_849} - {1'h0, dec_212}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_851 = _count_T_850[0]; // @[ToAXI4.scala:278:37]
wire _idStall_212_T = ~idle_212; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_212_T_3 = _idStall_212_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_212 = _idStall_212_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_213; // @[ToAXI4.scala:272:28]
wire _idStall_213_T_2 = count_213; // @[ToAXI4.scala:272:28, :286:44]
reg write_213; // @[ToAXI4.scala:273:24]
wire idle_213 = ~count_213; // @[ToAXI4.scala:272:28, :274:26]
wire inc_213 = a_sel_213 & _inc_T_213; // @[Decoupled.scala:51:35]
wire _dec_T_426 = d_sel_213 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_213 = _dec_T_426 & _dec_T_427; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_852 = {1'h0, count_213} + {1'h0, inc_213}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_853 = _count_T_852[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_854 = {1'h0, _count_T_853} - {1'h0, dec_213}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_855 = _count_T_854[0]; // @[ToAXI4.scala:278:37]
wire _idStall_213_T = ~idle_213; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_213_T_3 = _idStall_213_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_213 = _idStall_213_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_214; // @[ToAXI4.scala:272:28]
wire _idStall_214_T_2 = count_214; // @[ToAXI4.scala:272:28, :286:44]
reg write_214; // @[ToAXI4.scala:273:24]
wire idle_214 = ~count_214; // @[ToAXI4.scala:272:28, :274:26]
wire inc_214 = a_sel_214 & _inc_T_214; // @[Decoupled.scala:51:35]
wire _dec_T_428 = d_sel_214 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_214 = _dec_T_428 & _dec_T_429; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_856 = {1'h0, count_214} + {1'h0, inc_214}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_857 = _count_T_856[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_858 = {1'h0, _count_T_857} - {1'h0, dec_214}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_859 = _count_T_858[0]; // @[ToAXI4.scala:278:37]
wire _idStall_214_T = ~idle_214; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_214_T_3 = _idStall_214_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_214 = _idStall_214_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_215; // @[ToAXI4.scala:272:28]
wire _idStall_215_T_2 = count_215; // @[ToAXI4.scala:272:28, :286:44]
reg write_215; // @[ToAXI4.scala:273:24]
wire idle_215 = ~count_215; // @[ToAXI4.scala:272:28, :274:26]
wire inc_215 = a_sel_215 & _inc_T_215; // @[Decoupled.scala:51:35]
wire _dec_T_430 = d_sel_215 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_215 = _dec_T_430 & _dec_T_431; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_860 = {1'h0, count_215} + {1'h0, inc_215}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_861 = _count_T_860[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_862 = {1'h0, _count_T_861} - {1'h0, dec_215}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_863 = _count_T_862[0]; // @[ToAXI4.scala:278:37]
wire _idStall_215_T = ~idle_215; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_215_T_3 = _idStall_215_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_215 = _idStall_215_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_216; // @[ToAXI4.scala:272:28]
wire _idStall_216_T_2 = count_216; // @[ToAXI4.scala:272:28, :286:44]
reg write_216; // @[ToAXI4.scala:273:24]
wire idle_216 = ~count_216; // @[ToAXI4.scala:272:28, :274:26]
wire inc_216 = a_sel_216 & _inc_T_216; // @[Decoupled.scala:51:35]
wire _dec_T_432 = d_sel_216 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_216 = _dec_T_432 & _dec_T_433; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_864 = {1'h0, count_216} + {1'h0, inc_216}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_865 = _count_T_864[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_866 = {1'h0, _count_T_865} - {1'h0, dec_216}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_867 = _count_T_866[0]; // @[ToAXI4.scala:278:37]
wire _idStall_216_T = ~idle_216; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_216_T_3 = _idStall_216_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_216 = _idStall_216_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_217; // @[ToAXI4.scala:272:28]
wire _idStall_217_T_2 = count_217; // @[ToAXI4.scala:272:28, :286:44]
reg write_217; // @[ToAXI4.scala:273:24]
wire idle_217 = ~count_217; // @[ToAXI4.scala:272:28, :274:26]
wire inc_217 = a_sel_217 & _inc_T_217; // @[Decoupled.scala:51:35]
wire _dec_T_434 = d_sel_217 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_217 = _dec_T_434 & _dec_T_435; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_868 = {1'h0, count_217} + {1'h0, inc_217}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_869 = _count_T_868[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_870 = {1'h0, _count_T_869} - {1'h0, dec_217}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_871 = _count_T_870[0]; // @[ToAXI4.scala:278:37]
wire _idStall_217_T = ~idle_217; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_217_T_3 = _idStall_217_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_217 = _idStall_217_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_218; // @[ToAXI4.scala:272:28]
wire _idStall_218_T_2 = count_218; // @[ToAXI4.scala:272:28, :286:44]
reg write_218; // @[ToAXI4.scala:273:24]
wire idle_218 = ~count_218; // @[ToAXI4.scala:272:28, :274:26]
wire inc_218 = a_sel_218 & _inc_T_218; // @[Decoupled.scala:51:35]
wire _dec_T_436 = d_sel_218 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_218 = _dec_T_436 & _dec_T_437; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_872 = {1'h0, count_218} + {1'h0, inc_218}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_873 = _count_T_872[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_874 = {1'h0, _count_T_873} - {1'h0, dec_218}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_875 = _count_T_874[0]; // @[ToAXI4.scala:278:37]
wire _idStall_218_T = ~idle_218; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_218_T_3 = _idStall_218_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_218 = _idStall_218_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_219; // @[ToAXI4.scala:272:28]
wire _idStall_219_T_2 = count_219; // @[ToAXI4.scala:272:28, :286:44]
reg write_219; // @[ToAXI4.scala:273:24]
wire idle_219 = ~count_219; // @[ToAXI4.scala:272:28, :274:26]
wire inc_219 = a_sel_219 & _inc_T_219; // @[Decoupled.scala:51:35]
wire _dec_T_438 = d_sel_219 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_219 = _dec_T_438 & _dec_T_439; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_876 = {1'h0, count_219} + {1'h0, inc_219}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_877 = _count_T_876[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_878 = {1'h0, _count_T_877} - {1'h0, dec_219}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_879 = _count_T_878[0]; // @[ToAXI4.scala:278:37]
wire _idStall_219_T = ~idle_219; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_219_T_3 = _idStall_219_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_219 = _idStall_219_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_220; // @[ToAXI4.scala:272:28]
wire _idStall_220_T_2 = count_220; // @[ToAXI4.scala:272:28, :286:44]
reg write_220; // @[ToAXI4.scala:273:24]
wire idle_220 = ~count_220; // @[ToAXI4.scala:272:28, :274:26]
wire inc_220 = a_sel_220 & _inc_T_220; // @[Decoupled.scala:51:35]
wire _dec_T_440 = d_sel_220 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_220 = _dec_T_440 & _dec_T_441; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_880 = {1'h0, count_220} + {1'h0, inc_220}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_881 = _count_T_880[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_882 = {1'h0, _count_T_881} - {1'h0, dec_220}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_883 = _count_T_882[0]; // @[ToAXI4.scala:278:37]
wire _idStall_220_T = ~idle_220; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_220_T_3 = _idStall_220_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_220 = _idStall_220_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_221; // @[ToAXI4.scala:272:28]
wire _idStall_221_T_2 = count_221; // @[ToAXI4.scala:272:28, :286:44]
reg write_221; // @[ToAXI4.scala:273:24]
wire idle_221 = ~count_221; // @[ToAXI4.scala:272:28, :274:26]
wire inc_221 = a_sel_221 & _inc_T_221; // @[Decoupled.scala:51:35]
wire _dec_T_442 = d_sel_221 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_221 = _dec_T_442 & _dec_T_443; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_884 = {1'h0, count_221} + {1'h0, inc_221}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_885 = _count_T_884[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_886 = {1'h0, _count_T_885} - {1'h0, dec_221}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_887 = _count_T_886[0]; // @[ToAXI4.scala:278:37]
wire _idStall_221_T = ~idle_221; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_221_T_3 = _idStall_221_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_221 = _idStall_221_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_222; // @[ToAXI4.scala:272:28]
wire _idStall_222_T_2 = count_222; // @[ToAXI4.scala:272:28, :286:44]
reg write_222; // @[ToAXI4.scala:273:24]
wire idle_222 = ~count_222; // @[ToAXI4.scala:272:28, :274:26]
wire inc_222 = a_sel_222 & _inc_T_222; // @[Decoupled.scala:51:35]
wire _dec_T_444 = d_sel_222 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_222 = _dec_T_444 & _dec_T_445; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_888 = {1'h0, count_222} + {1'h0, inc_222}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_889 = _count_T_888[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_890 = {1'h0, _count_T_889} - {1'h0, dec_222}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_891 = _count_T_890[0]; // @[ToAXI4.scala:278:37]
wire _idStall_222_T = ~idle_222; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_222_T_3 = _idStall_222_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_222 = _idStall_222_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_223; // @[ToAXI4.scala:272:28]
wire _idStall_223_T_2 = count_223; // @[ToAXI4.scala:272:28, :286:44]
reg write_223; // @[ToAXI4.scala:273:24]
wire idle_223 = ~count_223; // @[ToAXI4.scala:272:28, :274:26]
wire inc_223 = a_sel_223 & _inc_T_223; // @[Decoupled.scala:51:35]
wire _dec_T_446 = d_sel_223 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_223 = _dec_T_446 & _dec_T_447; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_892 = {1'h0, count_223} + {1'h0, inc_223}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_893 = _count_T_892[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_894 = {1'h0, _count_T_893} - {1'h0, dec_223}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_895 = _count_T_894[0]; // @[ToAXI4.scala:278:37]
wire _idStall_223_T = ~idle_223; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_223_T_3 = _idStall_223_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_223 = _idStall_223_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_224; // @[ToAXI4.scala:272:28]
wire _idStall_224_T_2 = count_224; // @[ToAXI4.scala:272:28, :286:44]
reg write_224; // @[ToAXI4.scala:273:24]
wire idle_224 = ~count_224; // @[ToAXI4.scala:272:28, :274:26]
wire inc_224 = a_sel_224 & _inc_T_224; // @[Decoupled.scala:51:35]
wire _dec_T_448 = d_sel_224 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_224 = _dec_T_448 & _dec_T_449; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_896 = {1'h0, count_224} + {1'h0, inc_224}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_897 = _count_T_896[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_898 = {1'h0, _count_T_897} - {1'h0, dec_224}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_899 = _count_T_898[0]; // @[ToAXI4.scala:278:37]
wire _idStall_224_T = ~idle_224; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_224_T_3 = _idStall_224_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_224 = _idStall_224_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_225; // @[ToAXI4.scala:272:28]
wire _idStall_225_T_2 = count_225; // @[ToAXI4.scala:272:28, :286:44]
reg write_225; // @[ToAXI4.scala:273:24]
wire idle_225 = ~count_225; // @[ToAXI4.scala:272:28, :274:26]
wire inc_225 = a_sel_225 & _inc_T_225; // @[Decoupled.scala:51:35]
wire _dec_T_450 = d_sel_225 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_225 = _dec_T_450 & _dec_T_451; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_900 = {1'h0, count_225} + {1'h0, inc_225}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_901 = _count_T_900[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_902 = {1'h0, _count_T_901} - {1'h0, dec_225}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_903 = _count_T_902[0]; // @[ToAXI4.scala:278:37]
wire _idStall_225_T = ~idle_225; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_225_T_3 = _idStall_225_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_225 = _idStall_225_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_226; // @[ToAXI4.scala:272:28]
wire _idStall_226_T_2 = count_226; // @[ToAXI4.scala:272:28, :286:44]
reg write_226; // @[ToAXI4.scala:273:24]
wire idle_226 = ~count_226; // @[ToAXI4.scala:272:28, :274:26]
wire inc_226 = a_sel_226 & _inc_T_226; // @[Decoupled.scala:51:35]
wire _dec_T_452 = d_sel_226 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_226 = _dec_T_452 & _dec_T_453; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_904 = {1'h0, count_226} + {1'h0, inc_226}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_905 = _count_T_904[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_906 = {1'h0, _count_T_905} - {1'h0, dec_226}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_907 = _count_T_906[0]; // @[ToAXI4.scala:278:37]
wire _idStall_226_T = ~idle_226; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_226_T_3 = _idStall_226_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_226 = _idStall_226_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_227; // @[ToAXI4.scala:272:28]
wire _idStall_227_T_2 = count_227; // @[ToAXI4.scala:272:28, :286:44]
reg write_227; // @[ToAXI4.scala:273:24]
wire idle_227 = ~count_227; // @[ToAXI4.scala:272:28, :274:26]
wire inc_227 = a_sel_227 & _inc_T_227; // @[Decoupled.scala:51:35]
wire _dec_T_454 = d_sel_227 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_227 = _dec_T_454 & _dec_T_455; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_908 = {1'h0, count_227} + {1'h0, inc_227}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_909 = _count_T_908[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_910 = {1'h0, _count_T_909} - {1'h0, dec_227}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_911 = _count_T_910[0]; // @[ToAXI4.scala:278:37]
wire _idStall_227_T = ~idle_227; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_227_T_3 = _idStall_227_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_227 = _idStall_227_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_228; // @[ToAXI4.scala:272:28]
wire _idStall_228_T_2 = count_228; // @[ToAXI4.scala:272:28, :286:44]
reg write_228; // @[ToAXI4.scala:273:24]
wire idle_228 = ~count_228; // @[ToAXI4.scala:272:28, :274:26]
wire inc_228 = a_sel_228 & _inc_T_228; // @[Decoupled.scala:51:35]
wire _dec_T_456 = d_sel_228 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_228 = _dec_T_456 & _dec_T_457; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_912 = {1'h0, count_228} + {1'h0, inc_228}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_913 = _count_T_912[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_914 = {1'h0, _count_T_913} - {1'h0, dec_228}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_915 = _count_T_914[0]; // @[ToAXI4.scala:278:37]
wire _idStall_228_T = ~idle_228; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_228_T_3 = _idStall_228_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_228 = _idStall_228_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_229; // @[ToAXI4.scala:272:28]
wire _idStall_229_T_2 = count_229; // @[ToAXI4.scala:272:28, :286:44]
reg write_229; // @[ToAXI4.scala:273:24]
wire idle_229 = ~count_229; // @[ToAXI4.scala:272:28, :274:26]
wire inc_229 = a_sel_229 & _inc_T_229; // @[Decoupled.scala:51:35]
wire _dec_T_458 = d_sel_229 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_229 = _dec_T_458 & _dec_T_459; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_916 = {1'h0, count_229} + {1'h0, inc_229}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_917 = _count_T_916[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_918 = {1'h0, _count_T_917} - {1'h0, dec_229}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_919 = _count_T_918[0]; // @[ToAXI4.scala:278:37]
wire _idStall_229_T = ~idle_229; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_229_T_3 = _idStall_229_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_229 = _idStall_229_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_230; // @[ToAXI4.scala:272:28]
wire _idStall_230_T_2 = count_230; // @[ToAXI4.scala:272:28, :286:44]
reg write_230; // @[ToAXI4.scala:273:24]
wire idle_230 = ~count_230; // @[ToAXI4.scala:272:28, :274:26]
wire inc_230 = a_sel_230 & _inc_T_230; // @[Decoupled.scala:51:35]
wire _dec_T_460 = d_sel_230 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_230 = _dec_T_460 & _dec_T_461; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_920 = {1'h0, count_230} + {1'h0, inc_230}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_921 = _count_T_920[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_922 = {1'h0, _count_T_921} - {1'h0, dec_230}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_923 = _count_T_922[0]; // @[ToAXI4.scala:278:37]
wire _idStall_230_T = ~idle_230; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_230_T_3 = _idStall_230_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_230 = _idStall_230_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_231; // @[ToAXI4.scala:272:28]
wire _idStall_231_T_2 = count_231; // @[ToAXI4.scala:272:28, :286:44]
reg write_231; // @[ToAXI4.scala:273:24]
wire idle_231 = ~count_231; // @[ToAXI4.scala:272:28, :274:26]
wire inc_231 = a_sel_231 & _inc_T_231; // @[Decoupled.scala:51:35]
wire _dec_T_462 = d_sel_231 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_231 = _dec_T_462 & _dec_T_463; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_924 = {1'h0, count_231} + {1'h0, inc_231}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_925 = _count_T_924[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_926 = {1'h0, _count_T_925} - {1'h0, dec_231}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_927 = _count_T_926[0]; // @[ToAXI4.scala:278:37]
wire _idStall_231_T = ~idle_231; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_231_T_3 = _idStall_231_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_231 = _idStall_231_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_232; // @[ToAXI4.scala:272:28]
wire _idStall_232_T_2 = count_232; // @[ToAXI4.scala:272:28, :286:44]
reg write_232; // @[ToAXI4.scala:273:24]
wire idle_232 = ~count_232; // @[ToAXI4.scala:272:28, :274:26]
wire inc_232 = a_sel_232 & _inc_T_232; // @[Decoupled.scala:51:35]
wire _dec_T_464 = d_sel_232 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_232 = _dec_T_464 & _dec_T_465; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_928 = {1'h0, count_232} + {1'h0, inc_232}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_929 = _count_T_928[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_930 = {1'h0, _count_T_929} - {1'h0, dec_232}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_931 = _count_T_930[0]; // @[ToAXI4.scala:278:37]
wire _idStall_232_T = ~idle_232; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_232_T_3 = _idStall_232_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_232 = _idStall_232_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_233; // @[ToAXI4.scala:272:28]
wire _idStall_233_T_2 = count_233; // @[ToAXI4.scala:272:28, :286:44]
reg write_233; // @[ToAXI4.scala:273:24]
wire idle_233 = ~count_233; // @[ToAXI4.scala:272:28, :274:26]
wire inc_233 = a_sel_233 & _inc_T_233; // @[Decoupled.scala:51:35]
wire _dec_T_466 = d_sel_233 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_233 = _dec_T_466 & _dec_T_467; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_932 = {1'h0, count_233} + {1'h0, inc_233}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_933 = _count_T_932[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_934 = {1'h0, _count_T_933} - {1'h0, dec_233}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_935 = _count_T_934[0]; // @[ToAXI4.scala:278:37]
wire _idStall_233_T = ~idle_233; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_233_T_3 = _idStall_233_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_233 = _idStall_233_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_234; // @[ToAXI4.scala:272:28]
wire _idStall_234_T_2 = count_234; // @[ToAXI4.scala:272:28, :286:44]
reg write_234; // @[ToAXI4.scala:273:24]
wire idle_234 = ~count_234; // @[ToAXI4.scala:272:28, :274:26]
wire inc_234 = a_sel_234 & _inc_T_234; // @[Decoupled.scala:51:35]
wire _dec_T_468 = d_sel_234 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_234 = _dec_T_468 & _dec_T_469; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_936 = {1'h0, count_234} + {1'h0, inc_234}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_937 = _count_T_936[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_938 = {1'h0, _count_T_937} - {1'h0, dec_234}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_939 = _count_T_938[0]; // @[ToAXI4.scala:278:37]
wire _idStall_234_T = ~idle_234; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_234_T_3 = _idStall_234_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_234 = _idStall_234_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_235; // @[ToAXI4.scala:272:28]
wire _idStall_235_T_2 = count_235; // @[ToAXI4.scala:272:28, :286:44]
reg write_235; // @[ToAXI4.scala:273:24]
wire idle_235 = ~count_235; // @[ToAXI4.scala:272:28, :274:26]
wire inc_235 = a_sel_235 & _inc_T_235; // @[Decoupled.scala:51:35]
wire _dec_T_470 = d_sel_235 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_235 = _dec_T_470 & _dec_T_471; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_940 = {1'h0, count_235} + {1'h0, inc_235}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_941 = _count_T_940[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_942 = {1'h0, _count_T_941} - {1'h0, dec_235}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_943 = _count_T_942[0]; // @[ToAXI4.scala:278:37]
wire _idStall_235_T = ~idle_235; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_235_T_3 = _idStall_235_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_235 = _idStall_235_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_236; // @[ToAXI4.scala:272:28]
wire _idStall_236_T_2 = count_236; // @[ToAXI4.scala:272:28, :286:44]
reg write_236; // @[ToAXI4.scala:273:24]
wire idle_236 = ~count_236; // @[ToAXI4.scala:272:28, :274:26]
wire inc_236 = a_sel_236 & _inc_T_236; // @[Decoupled.scala:51:35]
wire _dec_T_472 = d_sel_236 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_236 = _dec_T_472 & _dec_T_473; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_944 = {1'h0, count_236} + {1'h0, inc_236}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_945 = _count_T_944[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_946 = {1'h0, _count_T_945} - {1'h0, dec_236}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_947 = _count_T_946[0]; // @[ToAXI4.scala:278:37]
wire _idStall_236_T = ~idle_236; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_236_T_3 = _idStall_236_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_236 = _idStall_236_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_237; // @[ToAXI4.scala:272:28]
wire _idStall_237_T_2 = count_237; // @[ToAXI4.scala:272:28, :286:44]
reg write_237; // @[ToAXI4.scala:273:24]
wire idle_237 = ~count_237; // @[ToAXI4.scala:272:28, :274:26]
wire inc_237 = a_sel_237 & _inc_T_237; // @[Decoupled.scala:51:35]
wire _dec_T_474 = d_sel_237 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_237 = _dec_T_474 & _dec_T_475; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_948 = {1'h0, count_237} + {1'h0, inc_237}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_949 = _count_T_948[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_950 = {1'h0, _count_T_949} - {1'h0, dec_237}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_951 = _count_T_950[0]; // @[ToAXI4.scala:278:37]
wire _idStall_237_T = ~idle_237; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_237_T_3 = _idStall_237_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_237 = _idStall_237_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_238; // @[ToAXI4.scala:272:28]
wire _idStall_238_T_2 = count_238; // @[ToAXI4.scala:272:28, :286:44]
reg write_238; // @[ToAXI4.scala:273:24]
wire idle_238 = ~count_238; // @[ToAXI4.scala:272:28, :274:26]
wire inc_238 = a_sel_238 & _inc_T_238; // @[Decoupled.scala:51:35]
wire _dec_T_476 = d_sel_238 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_238 = _dec_T_476 & _dec_T_477; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_952 = {1'h0, count_238} + {1'h0, inc_238}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_953 = _count_T_952[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_954 = {1'h0, _count_T_953} - {1'h0, dec_238}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_955 = _count_T_954[0]; // @[ToAXI4.scala:278:37]
wire _idStall_238_T = ~idle_238; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_238_T_3 = _idStall_238_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_238 = _idStall_238_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_239; // @[ToAXI4.scala:272:28]
wire _idStall_239_T_2 = count_239; // @[ToAXI4.scala:272:28, :286:44]
reg write_239; // @[ToAXI4.scala:273:24]
wire idle_239 = ~count_239; // @[ToAXI4.scala:272:28, :274:26]
wire inc_239 = a_sel_239 & _inc_T_239; // @[Decoupled.scala:51:35]
wire _dec_T_478 = d_sel_239 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_239 = _dec_T_478 & _dec_T_479; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_956 = {1'h0, count_239} + {1'h0, inc_239}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_957 = _count_T_956[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_958 = {1'h0, _count_T_957} - {1'h0, dec_239}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_959 = _count_T_958[0]; // @[ToAXI4.scala:278:37]
wire _idStall_239_T = ~idle_239; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_239_T_3 = _idStall_239_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_239 = _idStall_239_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_240; // @[ToAXI4.scala:272:28]
wire _idStall_240_T_2 = count_240; // @[ToAXI4.scala:272:28, :286:44]
reg write_240; // @[ToAXI4.scala:273:24]
wire idle_240 = ~count_240; // @[ToAXI4.scala:272:28, :274:26]
wire inc_240 = a_sel_240 & _inc_T_240; // @[Decoupled.scala:51:35]
wire _dec_T_480 = d_sel_240 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_240 = _dec_T_480 & _dec_T_481; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_960 = {1'h0, count_240} + {1'h0, inc_240}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_961 = _count_T_960[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_962 = {1'h0, _count_T_961} - {1'h0, dec_240}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_963 = _count_T_962[0]; // @[ToAXI4.scala:278:37]
wire _idStall_240_T = ~idle_240; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_240_T_3 = _idStall_240_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_240 = _idStall_240_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_241; // @[ToAXI4.scala:272:28]
wire _idStall_241_T_2 = count_241; // @[ToAXI4.scala:272:28, :286:44]
reg write_241; // @[ToAXI4.scala:273:24]
wire idle_241 = ~count_241; // @[ToAXI4.scala:272:28, :274:26]
wire inc_241 = a_sel_241 & _inc_T_241; // @[Decoupled.scala:51:35]
wire _dec_T_482 = d_sel_241 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_241 = _dec_T_482 & _dec_T_483; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_964 = {1'h0, count_241} + {1'h0, inc_241}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_965 = _count_T_964[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_966 = {1'h0, _count_T_965} - {1'h0, dec_241}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_967 = _count_T_966[0]; // @[ToAXI4.scala:278:37]
wire _idStall_241_T = ~idle_241; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_241_T_3 = _idStall_241_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_241 = _idStall_241_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_242; // @[ToAXI4.scala:272:28]
wire _idStall_242_T_2 = count_242; // @[ToAXI4.scala:272:28, :286:44]
reg write_242; // @[ToAXI4.scala:273:24]
wire idle_242 = ~count_242; // @[ToAXI4.scala:272:28, :274:26]
wire inc_242 = a_sel_242 & _inc_T_242; // @[Decoupled.scala:51:35]
wire _dec_T_484 = d_sel_242 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_242 = _dec_T_484 & _dec_T_485; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_968 = {1'h0, count_242} + {1'h0, inc_242}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_969 = _count_T_968[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_970 = {1'h0, _count_T_969} - {1'h0, dec_242}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_971 = _count_T_970[0]; // @[ToAXI4.scala:278:37]
wire _idStall_242_T = ~idle_242; // @[ToAXI4.scala:274:26, :286:15]
assign _idStall_242_T_3 = _idStall_242_T_2; // @[ToAXI4.scala:286:{34,44}]
assign idStall_242 = _idStall_242_T_3; // @[ToAXI4.scala:115:32, :286:34]
reg count_243; // @[ToAXI4.scala:272:28]
wire _idStall_243_T_2 = count_243; // @[ToAXI4.scala:272:28, :286:44]
reg write_243; // @[ToAXI4.scala:273:24]
wire idle_243 = ~count_243; // @[ToAXI4.scala:272:28, :274:26]
wire inc_243 = a_sel_243 & _inc_T_243; // @[Decoupled.scala:51:35]
wire _dec_T_486 = d_sel_243 & d_last; // @[ToAXI4.scala:261:93, :262:23, :277:22]
wire dec_243 = _dec_T_486 & _dec_T_487; // @[Decoupled.scala:51:35]
wire [1:0] _count_T_972 = {1'h0, count_243} + {1'h0, inc_243}; // @[ToAXI4.scala:272:28, :276:22, :278:24]
wire _count_T_973 = _count_T_972[0]; // @[ToAXI4.scala:278:24]
wire [1:0] _count_T_974 = {1'h0, _count_T_973} - {1'h0, dec_243}; // @[ToAXI4.scala:277:32, :278:{24,37}]
wire _count_T_975 = _count_T_974[0]; // @[ToAXI4.scala:278:37] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_180( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_201 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_424( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncQueue_8( // @[AsyncQueue.scala:226:7]
input io_enq_clock, // @[AsyncQueue.scala:227:14]
input io_enq_reset, // @[AsyncQueue.scala:227:14]
output io_enq_ready, // @[AsyncQueue.scala:227:14]
input io_enq_valid, // @[AsyncQueue.scala:227:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14]
input io_deq_clock, // @[AsyncQueue.scala:227:14]
input io_deq_reset, // @[AsyncQueue.scala:227:14]
input io_deq_ready, // @[AsyncQueue.scala:227:14]
output io_deq_valid, // @[AsyncQueue.scala:227:14]
output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14]
);
wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70]
wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70]
wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70]
wire io_enq_clock_0 = io_enq_clock; // @[AsyncQueue.scala:226:7]
wire io_enq_reset_0 = io_enq_reset; // @[AsyncQueue.scala:226:7]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:226:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:226:7]
wire io_deq_clock_0 = io_deq_clock; // @[AsyncQueue.scala:226:7]
wire io_deq_reset_0 = io_deq_reset; // @[AsyncQueue.scala:226:7]
wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:226:7]
wire io_enq_ready_0; // @[AsyncQueue.scala:226:7]
wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
wire io_deq_valid_0; // @[AsyncQueue.scala:226:7]
AsyncQueueSource_Phit_8 source ( // @[AsyncQueue.scala:228:70]
.clock (io_enq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_enq_reset_0), // @[AsyncQueue.scala:226:7]
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[AsyncQueue.scala:226:7]
.io_enq_bits_phit (io_enq_bits_phit_0), // @[AsyncQueue.scala:226:7]
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70]
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70]
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70]
); // @[AsyncQueue.scala:228:70]
AsyncQueueSink_Phit_8 sink ( // @[AsyncQueue.scala:229:70]
.clock (io_deq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_deq_reset_0), // @[AsyncQueue.scala:226:7]
.io_deq_ready (io_deq_ready_0), // @[AsyncQueue.scala:226:7]
.io_deq_valid (io_deq_valid_0),
.io_deq_bits_phit (io_deq_bits_phit_0),
.io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70]
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70]
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70]
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70]
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
); // @[AsyncQueue.scala:229:70]
assign io_enq_ready = io_enq_ready_0; // @[AsyncQueue.scala:226:7]
assign io_deq_valid = io_deq_valid_0; // @[AsyncQueue.scala:226:7]
assign io_deq_bits_phit = io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_22( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1282 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1282; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1282; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_1355 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1355; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1208 = _T_1282 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1208 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1208 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1208 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1208 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1208 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1254 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1254 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1223 = _T_1355 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1223 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1223 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1223 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2055:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1326 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1326 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1308 = _T_1355 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1308 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1308 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1308 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Multiplier.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
import freechips.rocketchip.util._
import ALU._
class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
val fn = Bits(SZ_ALU_FN.W)
val dw = Bits(SZ_DW.W)
val in1 = Bits(dataBits.W)
val in2 = Bits(dataBits.W)
val tag = UInt(tagBits.W)
}
class MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {
val data = Bits(dataBits.W)
val full_data = Bits((2*dataBits).W)
val tag = UInt(tagBits.W)
}
class MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {
val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))
val kill = Input(Bool())
val resp = Decoupled(new MultiplierResp(dataBits, tagBits))
}
case class MulDivParams(
mulUnroll: Int = 1,
divUnroll: Int = 1,
mulEarlyOut: Boolean = false,
divEarlyOut: Boolean = false,
divEarlyOutGranularity: Int = 1
)
class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {
private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)
private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)
def minLatency: Int = (minDivLatency ++ minMulLatency).min
val io = IO(new MultiplierIO(width, log2Up(nXpr)))
val w = io.req.bits.in1.getWidth
val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll
val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0
val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)
val state = RegInit(s_ready)
val req = Reg(chiselTypeOf(io.req.bits))
val count = Reg(UInt(log2Ceil(
((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++
(cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))
val neg_out = Reg(Bool())
val isHi = Reg(Bool())
val resHi = Reg(Bool())
val divisor = Reg(Bits((w+1).W)) // div only needs w bits
val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits
val mulDecode = List(
FN_MUL -> List(Y, N, X, X),
FN_MULH -> List(Y, Y, Y, Y),
FN_MULHU -> List(Y, Y, N, N),
FN_MULHSU -> List(Y, Y, Y, N))
val divDecode = List(
FN_DIV -> List(N, N, Y, Y),
FN_REM -> List(N, Y, Y, Y),
FN_DIVU -> List(N, N, N, N),
FN_REMU -> List(N, Y, N, N))
val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(io.req.bits.fn, List(X, X, X, X),
(if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)
require(w == 32 || w == 64)
def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32
def sext(x: Bits, halfW: Bool, signed: Bool) = {
val sign = signed && Mux(halfW, x(w/2-1), x(w-1))
val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))
(Cat(hi, x(w/2-1,0)), sign)
}
val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)
val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)
val subtractor = remainder(2*w,w) - divisor
val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))
val negated_remainder = -result
if (cfg.divUnroll != 0) when (state === s_neg_inputs) {
when (remainder(w-1)) {
remainder := negated_remainder
}
when (divisor(w-1)) {
divisor := subtractor
}
state := s_div
}
if (cfg.divUnroll != 0) when (state === s_neg_output) {
remainder := negated_remainder
state := s_done_div
resHi := false.B
}
if (cfg.mulUnroll != 0) when (state === s_mul) {
val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
val mplierSign = remainder(w)
val mplier = mulReg(mulw-1,0)
val accum = mulReg(2*mulw,mulw).asSInt
val mpcand = divisor.asSInt
val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum
val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))
val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out
val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)
val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&
!isHi && (mplier & ~eOutMask) === 0.U
val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))
val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))
count := count + 1.U
when (eOut || count === (mulw/cfg.mulUnroll-1).U) {
state := s_done_mul
resHi := isHi
}
}
if (cfg.divUnroll != 0) when (state === s_div) {
val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>
// the special case for iteration 0 is to save HW, not for correctness
val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)
val less = difference(w)
Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)
}.tail
remainder := unrolls.last
when (count === (w/cfg.divUnroll).U) {
state := Mux(neg_out, s_neg_output, s_done_div)
resHi := isHi
if (w % cfg.divUnroll < cfg.divUnroll - 1)
remainder := unrolls(w % cfg.divUnroll)
}
count := count + 1.U
val divby0 = count === 0.U && !subtractor(w)
if (cfg.divEarlyOut) {
val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)
val alignMask = ~((align-1).U(log2Ceil(w).W))
val divisorMSB = Log2(divisor(w-1,0), w) & alignMask
val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask
val eOutPos = ~(dividendMSB - divisorMSB)
val eOut = count === 0.U && !divby0 && eOutPos >= align.U
when (eOut) {
remainder := remainder(w-1,0) << eOutPos
count := eOutPos >> log2Floor(cfg.divUnroll)
}
}
when (divby0 && !isHi) { neg_out := false.B }
}
when (io.resp.fire || io.kill) {
state := s_ready
}
when (io.req.fire) {
state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))
isHi := cmdHi
resHi := false.B
count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)
neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)
divisor := Cat(rhs_sign, rhs_in)
remainder := lhs_in
req := io.req.bits
}
val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)
val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))
val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))
io.resp.bits.tag := req.tag
io.resp.bits.data := Cat(hiOut, loOut)
io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))
io.resp.valid := (state === s_done_mul || state === s_done_div)
io.req.ready := state === s_ready
}
class PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {
val io = IO(new Bundle {
val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))
val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))
})
val in = Pipe(io.req)
val decode = List(
FN_MUL -> List(N, X, X),
FN_MULH -> List(Y, Y, Y),
FN_MULHU -> List(Y, N, N),
FN_MULHSU -> List(Y, Y, N))
val cmdHi :: lhsSigned :: rhsSigned :: Nil =
DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)
val cmdHalf = (width > 32).B && in.bits.dw === DW_32
val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt
val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt
val prod = lhs * rhs
val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))
val resp = Pipe(in, latency-1)
io.resp.valid := resp.valid
io.resp.bits.tag := resp.bits.tag
io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits
io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt
}
| module MulDiv_2( // @[Multiplier.scala:40:7]
input clock, // @[Multiplier.scala:40:7]
input reset, // @[Multiplier.scala:40:7]
output io_req_ready, // @[Multiplier.scala:45:14]
input io_req_valid, // @[Multiplier.scala:45:14]
input [4:0] io_req_bits_fn, // @[Multiplier.scala:45:14]
input io_req_bits_dw, // @[Multiplier.scala:45:14]
input [63:0] io_req_bits_in1, // @[Multiplier.scala:45:14]
input [63:0] io_req_bits_in2, // @[Multiplier.scala:45:14]
input io_kill, // @[Multiplier.scala:45:14]
input io_resp_ready, // @[Multiplier.scala:45:14]
output io_resp_valid, // @[Multiplier.scala:45:14]
output [63:0] io_resp_bits_data // @[Multiplier.scala:45:14]
);
wire io_req_valid_0 = io_req_valid; // @[Multiplier.scala:40:7]
wire [4:0] io_req_bits_fn_0 = io_req_bits_fn; // @[Multiplier.scala:40:7]
wire io_req_bits_dw_0 = io_req_bits_dw; // @[Multiplier.scala:40:7]
wire [63:0] io_req_bits_in1_0 = io_req_bits_in1; // @[Multiplier.scala:40:7]
wire [63:0] io_req_bits_in2_0 = io_req_bits_in2; // @[Multiplier.scala:40:7]
wire io_kill_0 = io_kill; // @[Multiplier.scala:40:7]
wire io_resp_ready_0 = io_resp_ready; // @[Multiplier.scala:40:7]
wire _eOut_T_1 = 1'h0; // @[Multiplier.scala:117:36]
wire _eOut_T_3 = 1'h0; // @[Multiplier.scala:117:74]
wire _eOut_T_5 = 1'h0; // @[Multiplier.scala:117:91]
wire eOut = 1'h0; // @[Multiplier.scala:118:13]
wire [5:0] alignMask = 6'h3F; // @[Multiplier.scala:149:23]
wire [5:0] _dividendMSB_T_111 = 6'h0; // @[Multiplier.scala:151:53]
wire [2:0] _outMul_T = 3'h1; // @[Multiplier.scala:175:37]
wire [2:0] _outMul_T_2 = 3'h0; // @[Multiplier.scala:175:70]
wire [2:0] _outMul_T_3 = 3'h0; // @[Multiplier.scala:175:68]
wire [4:0] io_req_bits_tag = 5'h0; // @[Multiplier.scala:40:7]
wire [4:0] io_resp_bits_tag = 5'h0; // @[Multiplier.scala:40:7]
wire _io_req_ready_T; // @[Multiplier.scala:183:25]
wire _io_resp_valid_T_2; // @[Multiplier.scala:182:42]
wire [63:0] _io_resp_bits_data_T; // @[Multiplier.scala:180:27]
wire [127:0] _io_resp_bits_full_data_T_2; // @[Multiplier.scala:181:32]
wire io_req_ready_0; // @[Multiplier.scala:40:7]
wire [63:0] io_resp_bits_data_0; // @[Multiplier.scala:40:7]
wire [127:0] io_resp_bits_full_data; // @[Multiplier.scala:40:7]
wire io_resp_valid_0; // @[Multiplier.scala:40:7]
reg [2:0] state; // @[Multiplier.scala:51:22]
reg [4:0] req_fn; // @[Multiplier.scala:53:16]
reg req_dw; // @[Multiplier.scala:53:16]
reg [63:0] req_in1; // @[Multiplier.scala:53:16]
reg [63:0] req_in2; // @[Multiplier.scala:53:16]
reg [6:0] count; // @[Multiplier.scala:54:18]
reg neg_out; // @[Multiplier.scala:57:20]
reg isHi; // @[Multiplier.scala:58:17]
reg resHi; // @[Multiplier.scala:59:18]
reg [64:0] divisor; // @[Multiplier.scala:60:20]
wire [64:0] mpcand = divisor; // @[Multiplier.scala:60:20, :111:26]
reg [129:0] remainder; // @[Multiplier.scala:61:22]
wire [2:0] decoded_plaInput; // @[pla.scala:77:22]
wire [2:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [3:0] decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [3:0] decoded; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_3_2 = decoded_andMatrixOutputs_andMatrixInput_0; // @[pla.scala:91:29, :98:70]
wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_4_2 = decoded_andMatrixOutputs_andMatrixInput_0_1; // @[pla.scala:91:29, :98:70]
wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire [1:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_1_2 = decoded_andMatrixOutputs_andMatrixInput_0_4; // @[pla.scala:90:45, :98:70]
wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T = {decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_1 = |_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_3 = |_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] _decoded_orMatrixOutputs_T_4 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_5 = |_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo = {_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoded_plaInput = io_req_bits_fn_0[2:0]; // @[pla.scala:77:22]
wire cmdMul = decoded[3]; // @[pla.scala:81:23]
wire cmdHi = decoded[2]; // @[pla.scala:81:23]
wire lhsSigned = decoded[1]; // @[pla.scala:81:23]
wire rhsSigned = decoded[0]; // @[pla.scala:81:23]
wire _count_T_5 = ~io_req_bits_dw_0; // @[Multiplier.scala:40:7, :78:60]
wire _sign_T = io_req_bits_in1_0[31]; // @[Multiplier.scala:40:7, :81:38]
wire _sign_T_1 = io_req_bits_in1_0[63]; // @[Multiplier.scala:40:7, :81:48]
wire _sign_T_2 = io_req_bits_dw_0 ? _sign_T_1 : _sign_T; // @[Multiplier.scala:40:7, :81:{29,38,48}]
wire lhs_sign = lhsSigned & _sign_T_2; // @[Multiplier.scala:75:107, :81:{23,29}]
wire [31:0] _hi_T = {32{lhs_sign}}; // @[Multiplier.scala:81:23, :82:29]
wire [31:0] _hi_T_1 = io_req_bits_in1_0[63:32]; // @[Multiplier.scala:40:7, :82:43]
wire [31:0] hi = io_req_bits_dw_0 ? _hi_T_1 : _hi_T; // @[Multiplier.scala:40:7, :82:{17,29,43}]
wire [63:0] lhs_in = {hi, io_req_bits_in1_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}]
wire _sign_T_3 = io_req_bits_in2_0[31]; // @[Multiplier.scala:40:7, :81:38]
wire _sign_T_4 = io_req_bits_in2_0[63]; // @[Multiplier.scala:40:7, :81:48]
wire _sign_T_5 = io_req_bits_dw_0 ? _sign_T_4 : _sign_T_3; // @[Multiplier.scala:40:7, :81:{29,38,48}]
wire rhs_sign = rhsSigned & _sign_T_5; // @[Multiplier.scala:75:107, :81:{23,29}]
wire [31:0] _hi_T_2 = {32{rhs_sign}}; // @[Multiplier.scala:81:23, :82:29]
wire [31:0] _hi_T_3 = io_req_bits_in2_0[63:32]; // @[Multiplier.scala:40:7, :82:43]
wire [31:0] hi_1 = io_req_bits_dw_0 ? _hi_T_3 : _hi_T_2; // @[Multiplier.scala:40:7, :82:{17,29,43}]
wire [63:0] rhs_in = {hi_1, io_req_bits_in2_0[31:0]}; // @[Multiplier.scala:40:7, :82:17, :83:{9,15}]
wire [64:0] _subtractor_T = remainder[128:64]; // @[Multiplier.scala:61:22, :88:29]
wire [65:0] _subtractor_T_1 = {1'h0, _subtractor_T} - {1'h0, divisor}; // @[Multiplier.scala:60:20, :88:{29,37}]
wire [64:0] subtractor = _subtractor_T_1[64:0]; // @[Multiplier.scala:88:37]
wire [63:0] _result_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36]
wire [63:0] _io_resp_bits_full_data_T = remainder[128:65]; // @[Multiplier.scala:61:22, :89:36, :181:42]
wire [63:0] _result_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57]
wire [63:0] _mulReg_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :107:55]
wire [63:0] _unrolls_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :134:58]
wire [63:0] _dividendMSB_T = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :151:39]
wire [63:0] _remainder_T_3 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :155:31]
wire [63:0] _io_resp_bits_full_data_T_1 = remainder[63:0]; // @[Multiplier.scala:61:22, :89:57, :181:63]
wire [63:0] result = resHi ? _result_T : _result_T_1; // @[Multiplier.scala:59:18, :89:{19,36,57}]
wire [64:0] _negated_remainder_T = 65'h0 - {1'h0, result}; // @[Multiplier.scala:89:19, :90:27]
wire [63:0] negated_remainder = _negated_remainder_T[63:0]; // @[Multiplier.scala:90:27]
wire [64:0] _mulReg_T = remainder[129:65]; // @[Multiplier.scala:61:22, :107:31]
wire [128:0] mulReg = {_mulReg_T, _mulReg_T_1}; // @[Multiplier.scala:107:{21,31,55}]
wire mplierSign = remainder[64]; // @[Multiplier.scala:61:22, :108:31]
wire [63:0] mplier = mulReg[63:0]; // @[Multiplier.scala:107:21, :109:24]
wire [64:0] _accum_T = mulReg[128:64]; // @[Multiplier.scala:107:21, :110:23]
wire [64:0] accum = _accum_T; // @[Multiplier.scala:110:{23,37}]
wire _prod_T = mplier[0]; // @[Multiplier.scala:109:24, :112:38]
wire [1:0] _prod_T_1 = {mplierSign, _prod_T}; // @[Multiplier.scala:108:31, :112:{19,38}]
wire [1:0] _prod_T_2 = _prod_T_1; // @[Multiplier.scala:112:{19,60}]
wire [66:0] _prod_T_3 = {{65{_prod_T_2[1]}}, _prod_T_2} * {{2{mpcand[64]}}, mpcand}; // @[Multiplier.scala:111:26, :112:{60,67}]
wire [67:0] _prod_T_4 = {_prod_T_3[66], _prod_T_3} + {{3{accum[64]}}, accum}; // @[Multiplier.scala:110:37, :112:{67,76}]
wire [66:0] _prod_T_5 = _prod_T_4[66:0]; // @[Multiplier.scala:112:76]
wire [66:0] prod = _prod_T_5; // @[Multiplier.scala:112:76]
wire [66:0] nextMulReg_hi = prod; // @[Multiplier.scala:112:76, :113:25]
wire [62:0] _nextMulReg_T = mplier[63:1]; // @[Multiplier.scala:109:24, :113:38]
wire [129:0] nextMulReg = {nextMulReg_hi, _nextMulReg_T}; // @[Multiplier.scala:113:{25,38}]
wire [129:0] _nextMulReg1_T_1 = nextMulReg; // @[Multiplier.scala:113:25, :120:55]
wire _nextMplierSign_T = count == 7'h3E; // @[Multiplier.scala:54:18, :114:32]
wire nextMplierSign = _nextMplierSign_T & neg_out; // @[Multiplier.scala:57:20, :114:{32,61}]
wire [7:0] _GEN = {1'h0, count}; // @[Multiplier.scala:54:18, :116:54]
wire [7:0] _eOutMask_T; // @[Multiplier.scala:116:54]
assign _eOutMask_T = _GEN; // @[Multiplier.scala:116:54]
wire [7:0] _eOutRes_T; // @[Multiplier.scala:119:46]
assign _eOutRes_T = _GEN; // @[Multiplier.scala:116:54, :119:46]
wire [5:0] _eOutMask_T_1 = _eOutMask_T[5:0]; // @[Multiplier.scala:116:{54,72}]
wire [64:0] _eOutMask_T_2 = $signed(65'sh10000000000000000 >>> _eOutMask_T_1); // @[Multiplier.scala:116:{44,72}]
wire [63:0] eOutMask = _eOutMask_T_2[63:0]; // @[Multiplier.scala:116:{44,91}]
wire _eOut_T = count != 7'h3F; // @[Multiplier.scala:54:18, :117:45]
wire _eOut_T_2 = |count; // @[Multiplier.scala:54:18, :117:83]
wire _eOut_T_4 = ~isHi; // @[Multiplier.scala:58:17, :118:7]
wire [63:0] _eOut_T_6 = ~eOutMask; // @[Multiplier.scala:116:91, :118:26]
wire [63:0] _eOut_T_7 = mplier & _eOut_T_6; // @[Multiplier.scala:109:24, :118:{24,26}]
wire _eOut_T_8 = _eOut_T_7 == 64'h0; // @[Multiplier.scala:118:{24,37}]
wire [8:0] _eOutRes_T_1 = 9'h40 - {1'h0, _eOutRes_T}; // @[Multiplier.scala:119:{38,46}]
wire [7:0] _eOutRes_T_2 = _eOutRes_T_1[7:0]; // @[Multiplier.scala:119:38]
wire [5:0] _eOutRes_T_3 = _eOutRes_T_2[5:0]; // @[Multiplier.scala:119:{38,64}]
wire [128:0] eOutRes = mulReg >> _eOutRes_T_3; // @[Multiplier.scala:107:21, :119:{27,64}]
wire [64:0] _nextMulReg1_T = nextMulReg[128:64]; // @[Multiplier.scala:113:25, :120:37]
wire [63:0] _nextMulReg1_T_2 = _nextMulReg1_T_1[63:0]; // @[Multiplier.scala:120:{55,82}]
wire [128:0] nextMulReg1 = {_nextMulReg1_T, _nextMulReg1_T_2}; // @[Multiplier.scala:120:{26,37,82}]
wire [64:0] _remainder_T = nextMulReg1[128:64]; // @[Multiplier.scala:120:26, :121:34]
wire [63:0] _remainder_T_1 = nextMulReg1[63:0]; // @[Multiplier.scala:120:26, :121:67]
wire [65:0] remainder_hi = {_remainder_T, nextMplierSign}; // @[Multiplier.scala:114:61, :121:{21,34}]
wire [129:0] _remainder_T_2 = {remainder_hi, _remainder_T_1}; // @[Multiplier.scala:121:{21,67}]
wire [7:0] _GEN_0 = _GEN + 8'h1; // @[Multiplier.scala:116:54, :123:20]
wire [7:0] _count_T; // @[Multiplier.scala:123:20]
assign _count_T = _GEN_0; // @[Multiplier.scala:123:20]
wire [7:0] _count_T_2; // @[Multiplier.scala:144:20]
assign _count_T_2 = _GEN_0; // @[Multiplier.scala:123:20, :144:20]
wire [6:0] _count_T_1 = _count_T[6:0]; // @[Multiplier.scala:123:20]
wire unrolls_less = subtractor[64]; // @[Multiplier.scala:88:37, :133:28]
wire _divby0_T_1 = subtractor[64]; // @[Multiplier.scala:88:37, :133:28, :146:46]
wire [63:0] _unrolls_T = remainder[127:64]; // @[Multiplier.scala:61:22, :134:24]
wire [63:0] _unrolls_T_1 = subtractor[63:0]; // @[Multiplier.scala:88:37, :134:45]
wire [63:0] _unrolls_T_2 = unrolls_less ? _unrolls_T : _unrolls_T_1; // @[Multiplier.scala:133:28, :134:{14,24,45}]
wire _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala:133:28, :134:67]
wire [127:0] unrolls_hi = {_unrolls_T_2, _unrolls_T_3}; // @[Multiplier.scala:134:{10,14,58}]
wire [128:0] unrolls_0 = {unrolls_hi, _unrolls_T_4}; // @[Multiplier.scala:134:{10,67}]
wire [2:0] _state_T = {1'h1, ~neg_out, 1'h1}; // @[Multiplier.scala:57:20, :139:19]
wire [6:0] _count_T_3 = _count_T_2[6:0]; // @[Multiplier.scala:144:20]
wire _divby0_T = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24]
wire _divby0_T_2 = ~_divby0_T_1; // @[Multiplier.scala:146:{35,46}]
wire divby0 = _divby0_T & _divby0_T_2; // @[Multiplier.scala:146:{24,32,35}]
wire [63:0] _divisorMSB_T = divisor[63:0]; // @[Multiplier.scala:60:20, :150:36]
wire [31:0] divisorMSB_hi = _divisorMSB_T[63:32]; // @[CircuitMath.scala:33:17]
wire [31:0] divisorMSB_lo = _divisorMSB_T[31:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi = |divisorMSB_hi; // @[CircuitMath.scala:33:17, :35:22]
wire [15:0] divisorMSB_hi_1 = divisorMSB_hi[31:16]; // @[CircuitMath.scala:33:17]
wire [15:0] divisorMSB_lo_1 = divisorMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_1 = |divisorMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] divisorMSB_hi_2 = divisorMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] divisorMSB_lo_2 = divisorMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_2 = |divisorMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_3 = divisorMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_3 = divisorMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_3 = |divisorMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_1 = divisorMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_2 = divisorMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_3 = divisorMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_4 = _divisorMSB_T_2 ? 2'h2 : {1'h0, _divisorMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_5 = _divisorMSB_T_1 ? 2'h3 : _divisorMSB_T_4; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_6 = divisorMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_7 = divisorMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_8 = divisorMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_9 = _divisorMSB_T_7 ? 2'h2 : {1'h0, _divisorMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_10 = _divisorMSB_T_6 ? 2'h3 : _divisorMSB_T_9; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_11 = divisorMSB_useHi_3 ? _divisorMSB_T_5 : _divisorMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_12 = {divisorMSB_useHi_3, _divisorMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_4 = divisorMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_4 = divisorMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_4 = |divisorMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_13 = divisorMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_14 = divisorMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_15 = divisorMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_16 = _divisorMSB_T_14 ? 2'h2 : {1'h0, _divisorMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_17 = _divisorMSB_T_13 ? 2'h3 : _divisorMSB_T_16; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_18 = divisorMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_19 = divisorMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_20 = divisorMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_21 = _divisorMSB_T_19 ? 2'h2 : {1'h0, _divisorMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_22 = _divisorMSB_T_18 ? 2'h3 : _divisorMSB_T_21; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_23 = divisorMSB_useHi_4 ? _divisorMSB_T_17 : _divisorMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_24 = {divisorMSB_useHi_4, _divisorMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_25 = divisorMSB_useHi_2 ? _divisorMSB_T_12 : _divisorMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_26 = {divisorMSB_useHi_2, _divisorMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] divisorMSB_hi_5 = divisorMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] divisorMSB_lo_5 = divisorMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_5 = |divisorMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_6 = divisorMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_6 = divisorMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_6 = |divisorMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_27 = divisorMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_28 = divisorMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_29 = divisorMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_30 = _divisorMSB_T_28 ? 2'h2 : {1'h0, _divisorMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_31 = _divisorMSB_T_27 ? 2'h3 : _divisorMSB_T_30; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_32 = divisorMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_33 = divisorMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_34 = divisorMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_35 = _divisorMSB_T_33 ? 2'h2 : {1'h0, _divisorMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_36 = _divisorMSB_T_32 ? 2'h3 : _divisorMSB_T_35; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_37 = divisorMSB_useHi_6 ? _divisorMSB_T_31 : _divisorMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_38 = {divisorMSB_useHi_6, _divisorMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_7 = divisorMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_7 = divisorMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_7 = |divisorMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_39 = divisorMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_40 = divisorMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_41 = divisorMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_42 = _divisorMSB_T_40 ? 2'h2 : {1'h0, _divisorMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_43 = _divisorMSB_T_39 ? 2'h3 : _divisorMSB_T_42; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_44 = divisorMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_45 = divisorMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_46 = divisorMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_47 = _divisorMSB_T_45 ? 2'h2 : {1'h0, _divisorMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_48 = _divisorMSB_T_44 ? 2'h3 : _divisorMSB_T_47; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_49 = divisorMSB_useHi_7 ? _divisorMSB_T_43 : _divisorMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_50 = {divisorMSB_useHi_7, _divisorMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_51 = divisorMSB_useHi_5 ? _divisorMSB_T_38 : _divisorMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_52 = {divisorMSB_useHi_5, _divisorMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_53 = divisorMSB_useHi_1 ? _divisorMSB_T_26 : _divisorMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _divisorMSB_T_54 = {divisorMSB_useHi_1, _divisorMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [15:0] divisorMSB_hi_8 = divisorMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17]
wire [15:0] divisorMSB_lo_8 = divisorMSB_lo[15:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_8 = |divisorMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] divisorMSB_hi_9 = divisorMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] divisorMSB_lo_9 = divisorMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_9 = |divisorMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_10 = divisorMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_10 = divisorMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_10 = |divisorMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_55 = divisorMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_56 = divisorMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_57 = divisorMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_58 = _divisorMSB_T_56 ? 2'h2 : {1'h0, _divisorMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_59 = _divisorMSB_T_55 ? 2'h3 : _divisorMSB_T_58; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_60 = divisorMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_61 = divisorMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_62 = divisorMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_63 = _divisorMSB_T_61 ? 2'h2 : {1'h0, _divisorMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_64 = _divisorMSB_T_60 ? 2'h3 : _divisorMSB_T_63; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_65 = divisorMSB_useHi_10 ? _divisorMSB_T_59 : _divisorMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_66 = {divisorMSB_useHi_10, _divisorMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_11 = divisorMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_11 = divisorMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_11 = |divisorMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_67 = divisorMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_68 = divisorMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_69 = divisorMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_70 = _divisorMSB_T_68 ? 2'h2 : {1'h0, _divisorMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_71 = _divisorMSB_T_67 ? 2'h3 : _divisorMSB_T_70; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_72 = divisorMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_73 = divisorMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_74 = divisorMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_75 = _divisorMSB_T_73 ? 2'h2 : {1'h0, _divisorMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_76 = _divisorMSB_T_72 ? 2'h3 : _divisorMSB_T_75; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_77 = divisorMSB_useHi_11 ? _divisorMSB_T_71 : _divisorMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_78 = {divisorMSB_useHi_11, _divisorMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_79 = divisorMSB_useHi_9 ? _divisorMSB_T_66 : _divisorMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_80 = {divisorMSB_useHi_9, _divisorMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] divisorMSB_hi_12 = divisorMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] divisorMSB_lo_12 = divisorMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_12 = |divisorMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] divisorMSB_hi_13 = divisorMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] divisorMSB_lo_13 = divisorMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire divisorMSB_useHi_13 = |divisorMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_81 = divisorMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_82 = divisorMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_83 = divisorMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_84 = _divisorMSB_T_82 ? 2'h2 : {1'h0, _divisorMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_85 = _divisorMSB_T_81 ? 2'h3 : _divisorMSB_T_84; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_86 = divisorMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_87 = divisorMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_88 = divisorMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_89 = _divisorMSB_T_87 ? 2'h2 : {1'h0, _divisorMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_90 = _divisorMSB_T_86 ? 2'h3 : _divisorMSB_T_89; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_91 = divisorMSB_useHi_13 ? _divisorMSB_T_85 : _divisorMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_92 = {divisorMSB_useHi_13, _divisorMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] divisorMSB_hi_14 = divisorMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] divisorMSB_lo_14 = divisorMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17]
wire divisorMSB_useHi_14 = |divisorMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22]
wire _divisorMSB_T_93 = divisorMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_94 = divisorMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _divisorMSB_T_95 = divisorMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _divisorMSB_T_96 = _divisorMSB_T_94 ? 2'h2 : {1'h0, _divisorMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_97 = _divisorMSB_T_93 ? 2'h3 : _divisorMSB_T_96; // @[CircuitMath.scala:30:{10,12}]
wire _divisorMSB_T_98 = divisorMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_99 = divisorMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _divisorMSB_T_100 = divisorMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _divisorMSB_T_101 = _divisorMSB_T_99 ? 2'h2 : {1'h0, _divisorMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _divisorMSB_T_102 = _divisorMSB_T_98 ? 2'h3 : _divisorMSB_T_101; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _divisorMSB_T_103 = divisorMSB_useHi_14 ? _divisorMSB_T_97 : _divisorMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _divisorMSB_T_104 = {divisorMSB_useHi_14, _divisorMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _divisorMSB_T_105 = divisorMSB_useHi_12 ? _divisorMSB_T_92 : _divisorMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_106 = {divisorMSB_useHi_12, _divisorMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _divisorMSB_T_107 = divisorMSB_useHi_8 ? _divisorMSB_T_80 : _divisorMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _divisorMSB_T_108 = {divisorMSB_useHi_8, _divisorMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _divisorMSB_T_109 = divisorMSB_useHi ? _divisorMSB_T_54 : _divisorMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] _divisorMSB_T_110 = {divisorMSB_useHi, _divisorMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] divisorMSB = _divisorMSB_T_110; // @[CircuitMath.scala:36:10]
wire [31:0] dividendMSB_hi = _dividendMSB_T[63:32]; // @[CircuitMath.scala:33:17]
wire [31:0] dividendMSB_lo = _dividendMSB_T[31:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi = |dividendMSB_hi; // @[CircuitMath.scala:33:17, :35:22]
wire [15:0] dividendMSB_hi_1 = dividendMSB_hi[31:16]; // @[CircuitMath.scala:33:17]
wire [15:0] dividendMSB_lo_1 = dividendMSB_hi[15:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_1 = |dividendMSB_hi_1; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] dividendMSB_hi_2 = dividendMSB_hi_1[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] dividendMSB_lo_2 = dividendMSB_hi_1[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_2 = |dividendMSB_hi_2; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_3 = dividendMSB_hi_2[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_3 = dividendMSB_hi_2[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_3 = |dividendMSB_hi_3; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_1 = dividendMSB_hi_3[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_2 = dividendMSB_hi_3[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_3 = dividendMSB_hi_3[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_4 = _dividendMSB_T_2 ? 2'h2 : {1'h0, _dividendMSB_T_3}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_5 = _dividendMSB_T_1 ? 2'h3 : _dividendMSB_T_4; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_6 = dividendMSB_lo_3[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_7 = dividendMSB_lo_3[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_8 = dividendMSB_lo_3[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_9 = _dividendMSB_T_7 ? 2'h2 : {1'h0, _dividendMSB_T_8}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_10 = _dividendMSB_T_6 ? 2'h3 : _dividendMSB_T_9; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_11 = dividendMSB_useHi_3 ? _dividendMSB_T_5 : _dividendMSB_T_10; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_12 = {dividendMSB_useHi_3, _dividendMSB_T_11}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_4 = dividendMSB_lo_2[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_4 = dividendMSB_lo_2[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_4 = |dividendMSB_hi_4; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_13 = dividendMSB_hi_4[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_14 = dividendMSB_hi_4[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_15 = dividendMSB_hi_4[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_16 = _dividendMSB_T_14 ? 2'h2 : {1'h0, _dividendMSB_T_15}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_17 = _dividendMSB_T_13 ? 2'h3 : _dividendMSB_T_16; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_18 = dividendMSB_lo_4[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_19 = dividendMSB_lo_4[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_20 = dividendMSB_lo_4[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_21 = _dividendMSB_T_19 ? 2'h2 : {1'h0, _dividendMSB_T_20}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_22 = _dividendMSB_T_18 ? 2'h3 : _dividendMSB_T_21; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_23 = dividendMSB_useHi_4 ? _dividendMSB_T_17 : _dividendMSB_T_22; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_24 = {dividendMSB_useHi_4, _dividendMSB_T_23}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_25 = dividendMSB_useHi_2 ? _dividendMSB_T_12 : _dividendMSB_T_24; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_26 = {dividendMSB_useHi_2, _dividendMSB_T_25}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] dividendMSB_hi_5 = dividendMSB_lo_1[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] dividendMSB_lo_5 = dividendMSB_lo_1[7:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_5 = |dividendMSB_hi_5; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_6 = dividendMSB_hi_5[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_6 = dividendMSB_hi_5[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_6 = |dividendMSB_hi_6; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_27 = dividendMSB_hi_6[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_28 = dividendMSB_hi_6[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_29 = dividendMSB_hi_6[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_30 = _dividendMSB_T_28 ? 2'h2 : {1'h0, _dividendMSB_T_29}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_31 = _dividendMSB_T_27 ? 2'h3 : _dividendMSB_T_30; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_32 = dividendMSB_lo_6[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_33 = dividendMSB_lo_6[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_34 = dividendMSB_lo_6[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_35 = _dividendMSB_T_33 ? 2'h2 : {1'h0, _dividendMSB_T_34}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_36 = _dividendMSB_T_32 ? 2'h3 : _dividendMSB_T_35; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_37 = dividendMSB_useHi_6 ? _dividendMSB_T_31 : _dividendMSB_T_36; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_38 = {dividendMSB_useHi_6, _dividendMSB_T_37}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_7 = dividendMSB_lo_5[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_7 = dividendMSB_lo_5[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_7 = |dividendMSB_hi_7; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_39 = dividendMSB_hi_7[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_40 = dividendMSB_hi_7[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_41 = dividendMSB_hi_7[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_42 = _dividendMSB_T_40 ? 2'h2 : {1'h0, _dividendMSB_T_41}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_43 = _dividendMSB_T_39 ? 2'h3 : _dividendMSB_T_42; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_44 = dividendMSB_lo_7[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_45 = dividendMSB_lo_7[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_46 = dividendMSB_lo_7[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_47 = _dividendMSB_T_45 ? 2'h2 : {1'h0, _dividendMSB_T_46}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_48 = _dividendMSB_T_44 ? 2'h3 : _dividendMSB_T_47; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_49 = dividendMSB_useHi_7 ? _dividendMSB_T_43 : _dividendMSB_T_48; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_50 = {dividendMSB_useHi_7, _dividendMSB_T_49}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_51 = dividendMSB_useHi_5 ? _dividendMSB_T_38 : _dividendMSB_T_50; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_52 = {dividendMSB_useHi_5, _dividendMSB_T_51}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_53 = dividendMSB_useHi_1 ? _dividendMSB_T_26 : _dividendMSB_T_52; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _dividendMSB_T_54 = {dividendMSB_useHi_1, _dividendMSB_T_53}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [15:0] dividendMSB_hi_8 = dividendMSB_lo[31:16]; // @[CircuitMath.scala:33:17, :34:17]
wire [15:0] dividendMSB_lo_8 = dividendMSB_lo[15:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_8 = |dividendMSB_hi_8; // @[CircuitMath.scala:33:17, :35:22]
wire [7:0] dividendMSB_hi_9 = dividendMSB_hi_8[15:8]; // @[CircuitMath.scala:33:17]
wire [7:0] dividendMSB_lo_9 = dividendMSB_hi_8[7:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_9 = |dividendMSB_hi_9; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_10 = dividendMSB_hi_9[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_10 = dividendMSB_hi_9[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_10 = |dividendMSB_hi_10; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_55 = dividendMSB_hi_10[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_56 = dividendMSB_hi_10[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_57 = dividendMSB_hi_10[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_58 = _dividendMSB_T_56 ? 2'h2 : {1'h0, _dividendMSB_T_57}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_59 = _dividendMSB_T_55 ? 2'h3 : _dividendMSB_T_58; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_60 = dividendMSB_lo_10[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_61 = dividendMSB_lo_10[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_62 = dividendMSB_lo_10[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_63 = _dividendMSB_T_61 ? 2'h2 : {1'h0, _dividendMSB_T_62}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_64 = _dividendMSB_T_60 ? 2'h3 : _dividendMSB_T_63; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_65 = dividendMSB_useHi_10 ? _dividendMSB_T_59 : _dividendMSB_T_64; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_66 = {dividendMSB_useHi_10, _dividendMSB_T_65}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_11 = dividendMSB_lo_9[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_11 = dividendMSB_lo_9[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_11 = |dividendMSB_hi_11; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_67 = dividendMSB_hi_11[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_68 = dividendMSB_hi_11[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_69 = dividendMSB_hi_11[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_70 = _dividendMSB_T_68 ? 2'h2 : {1'h0, _dividendMSB_T_69}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_71 = _dividendMSB_T_67 ? 2'h3 : _dividendMSB_T_70; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_72 = dividendMSB_lo_11[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_73 = dividendMSB_lo_11[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_74 = dividendMSB_lo_11[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_75 = _dividendMSB_T_73 ? 2'h2 : {1'h0, _dividendMSB_T_74}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_76 = _dividendMSB_T_72 ? 2'h3 : _dividendMSB_T_75; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_77 = dividendMSB_useHi_11 ? _dividendMSB_T_71 : _dividendMSB_T_76; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_78 = {dividendMSB_useHi_11, _dividendMSB_T_77}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_79 = dividendMSB_useHi_9 ? _dividendMSB_T_66 : _dividendMSB_T_78; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_80 = {dividendMSB_useHi_9, _dividendMSB_T_79}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [7:0] dividendMSB_hi_12 = dividendMSB_lo_8[15:8]; // @[CircuitMath.scala:33:17, :34:17]
wire [7:0] dividendMSB_lo_12 = dividendMSB_lo_8[7:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_12 = |dividendMSB_hi_12; // @[CircuitMath.scala:33:17, :35:22]
wire [3:0] dividendMSB_hi_13 = dividendMSB_hi_12[7:4]; // @[CircuitMath.scala:33:17]
wire [3:0] dividendMSB_lo_13 = dividendMSB_hi_12[3:0]; // @[CircuitMath.scala:33:17, :34:17]
wire dividendMSB_useHi_13 = |dividendMSB_hi_13; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_81 = dividendMSB_hi_13[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_82 = dividendMSB_hi_13[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_83 = dividendMSB_hi_13[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_84 = _dividendMSB_T_82 ? 2'h2 : {1'h0, _dividendMSB_T_83}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_85 = _dividendMSB_T_81 ? 2'h3 : _dividendMSB_T_84; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_86 = dividendMSB_lo_13[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_87 = dividendMSB_lo_13[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_88 = dividendMSB_lo_13[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_89 = _dividendMSB_T_87 ? 2'h2 : {1'h0, _dividendMSB_T_88}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_90 = _dividendMSB_T_86 ? 2'h3 : _dividendMSB_T_89; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_91 = dividendMSB_useHi_13 ? _dividendMSB_T_85 : _dividendMSB_T_90; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_92 = {dividendMSB_useHi_13, _dividendMSB_T_91}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] dividendMSB_hi_14 = dividendMSB_lo_12[7:4]; // @[CircuitMath.scala:33:17, :34:17]
wire [3:0] dividendMSB_lo_14 = dividendMSB_lo_12[3:0]; // @[CircuitMath.scala:34:17]
wire dividendMSB_useHi_14 = |dividendMSB_hi_14; // @[CircuitMath.scala:33:17, :35:22]
wire _dividendMSB_T_93 = dividendMSB_hi_14[3]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_94 = dividendMSB_hi_14[2]; // @[CircuitMath.scala:30:12, :33:17]
wire _dividendMSB_T_95 = dividendMSB_hi_14[1]; // @[CircuitMath.scala:28:8, :33:17]
wire [1:0] _dividendMSB_T_96 = _dividendMSB_T_94 ? 2'h2 : {1'h0, _dividendMSB_T_95}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_97 = _dividendMSB_T_93 ? 2'h3 : _dividendMSB_T_96; // @[CircuitMath.scala:30:{10,12}]
wire _dividendMSB_T_98 = dividendMSB_lo_14[3]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_99 = dividendMSB_lo_14[2]; // @[CircuitMath.scala:30:12, :34:17]
wire _dividendMSB_T_100 = dividendMSB_lo_14[1]; // @[CircuitMath.scala:28:8, :34:17]
wire [1:0] _dividendMSB_T_101 = _dividendMSB_T_99 ? 2'h2 : {1'h0, _dividendMSB_T_100}; // @[CircuitMath.scala:28:8, :30:{10,12}]
wire [1:0] _dividendMSB_T_102 = _dividendMSB_T_98 ? 2'h3 : _dividendMSB_T_101; // @[CircuitMath.scala:30:{10,12}]
wire [1:0] _dividendMSB_T_103 = dividendMSB_useHi_14 ? _dividendMSB_T_97 : _dividendMSB_T_102; // @[CircuitMath.scala:30:10, :35:22, :36:21]
wire [2:0] _dividendMSB_T_104 = {dividendMSB_useHi_14, _dividendMSB_T_103}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [2:0] _dividendMSB_T_105 = dividendMSB_useHi_12 ? _dividendMSB_T_92 : _dividendMSB_T_104; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_106 = {dividendMSB_useHi_12, _dividendMSB_T_105}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [3:0] _dividendMSB_T_107 = dividendMSB_useHi_8 ? _dividendMSB_T_80 : _dividendMSB_T_106; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _dividendMSB_T_108 = {dividendMSB_useHi_8, _dividendMSB_T_107}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [4:0] _dividendMSB_T_109 = dividendMSB_useHi ? _dividendMSB_T_54 : _dividendMSB_T_108; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] _dividendMSB_T_110 = {dividendMSB_useHi, _dividendMSB_T_109}; // @[CircuitMath.scala:35:22, :36:{10,21}]
wire [5:0] dividendMSB = _dividendMSB_T_110; // @[CircuitMath.scala:36:10]
wire [6:0] _eOutPos_T = {1'h0, dividendMSB} - {1'h0, divisorMSB}; // @[Multiplier.scala:150:48, :151:51, :152:35]
wire [5:0] _eOutPos_T_1 = _eOutPos_T[5:0]; // @[Multiplier.scala:152:35]
wire [5:0] eOutPos = ~_eOutPos_T_1; // @[Multiplier.scala:152:{21,35}]
wire [5:0] _count_T_4 = eOutPos; // @[Multiplier.scala:152:21, :156:26]
wire _eOut_T_9 = ~(|count); // @[Multiplier.scala:54:18, :117:83, :146:24, :153:24]
wire _eOut_T_10 = ~divby0; // @[Multiplier.scala:146:32, :153:35]
wire _eOut_T_11 = _eOut_T_9 & _eOut_T_10; // @[Multiplier.scala:153:{24,32,35}]
wire _eOut_T_12 = |eOutPos; // @[Multiplier.scala:152:21, :153:54]
wire eOut_1 = _eOut_T_11 & _eOut_T_12; // @[Multiplier.scala:153:{32,43,54}]
wire [126:0] _remainder_T_4 = {63'h0, _remainder_T_3} << eOutPos; // @[Multiplier.scala:152:21, :155:{31,39}]
wire _state_T_1 = lhs_sign | rhs_sign; // @[Multiplier.scala:81:23, :165:46]
wire [2:0] _state_T_2 = {1'h0, ~_state_T_1, 1'h1}; // @[Multiplier.scala:165:{36,46}]
wire [2:0] _state_T_3 = cmdMul ? 3'h2 : _state_T_2; // @[Multiplier.scala:75:107, :165:{17,36}]
wire _count_T_6 = _count_T_5; // @[Multiplier.scala:78:{50,60}]
wire _count_T_7 = cmdMul & _count_T_6; // @[Multiplier.scala:75:107, :78:50, :168:46]
wire [5:0] _count_T_8 = {_count_T_7, 5'h0}; // @[Multiplier.scala:168:{38,46}]
wire _neg_out_T = lhs_sign != rhs_sign; // @[Multiplier.scala:81:23, :169:46]
wire _neg_out_T_1 = cmdHi ? lhs_sign : _neg_out_T; // @[Multiplier.scala:75:107, :81:23, :169:{19,46}]
wire [64:0] _divisor_T = {rhs_sign, rhs_in}; // @[Multiplier.scala:81:23, :83:9, :170:19]
wire [2:0] _outMul_T_1 = state & 3'h1; // @[Multiplier.scala:51:22, :175:23]
wire outMul = _outMul_T_1 == 3'h0; // @[Multiplier.scala:175:{23,52}]
wire _loOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60]
wire _loOut_T_1 = _loOut_T; // @[Multiplier.scala:78:{50,60}]
wire _loOut_T_2 = _loOut_T_1; // @[Multiplier.scala:78:50, :176:30]
wire _loOut_T_3 = _loOut_T_2 & outMul; // @[Multiplier.scala:175:52, :176:{30,48}]
wire [31:0] _loOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65]
wire [31:0] _hiOut_T_4 = result[63:32]; // @[Multiplier.scala:89:19, :176:65, :177:66]
wire [31:0] _loOut_T_5 = result[31:0]; // @[Multiplier.scala:89:19, :176:82]
wire [31:0] loOut = _loOut_T_3 ? _loOut_T_4 : _loOut_T_5; // @[Multiplier.scala:176:{18,48,65,82}]
wire _hiOut_T = ~req_dw; // @[Multiplier.scala:53:16, :78:60]
wire _hiOut_T_1 = _hiOut_T; // @[Multiplier.scala:78:{50,60}]
wire _hiOut_T_2 = loOut[31]; // @[Multiplier.scala:176:18, :177:50]
wire [31:0] _hiOut_T_3 = {32{_hiOut_T_2}}; // @[Multiplier.scala:177:{39,50}]
wire [31:0] hiOut = _hiOut_T_1 ? _hiOut_T_3 : _hiOut_T_4; // @[Multiplier.scala:78:50, :177:{18,39,66}]
assign _io_resp_bits_data_T = {hiOut, loOut}; // @[Multiplier.scala:176:18, :177:18, :180:27]
assign io_resp_bits_data_0 = _io_resp_bits_data_T; // @[Multiplier.scala:40:7, :180:27]
assign _io_resp_bits_full_data_T_2 = {_io_resp_bits_full_data_T, _io_resp_bits_full_data_T_1}; // @[Multiplier.scala:181:{32,42,63}]
assign io_resp_bits_full_data = _io_resp_bits_full_data_T_2; // @[Multiplier.scala:40:7, :181:32]
wire _io_resp_valid_T = state == 3'h6; // @[Multiplier.scala:51:22, :182:27]
wire _io_resp_valid_T_1 = &state; // @[Multiplier.scala:51:22, :182:51]
assign _io_resp_valid_T_2 = _io_resp_valid_T | _io_resp_valid_T_1; // @[Multiplier.scala:182:{27,42,51}]
assign io_resp_valid_0 = _io_resp_valid_T_2; // @[Multiplier.scala:40:7, :182:42]
assign _io_req_ready_T = state == 3'h0; // @[Multiplier.scala:51:22, :183:25]
assign io_req_ready_0 = _io_req_ready_T; // @[Multiplier.scala:40:7, :183:25]
wire _T_10 = state == 3'h1; // @[Multiplier.scala:51:22, :92:39]
wire _T_13 = state == 3'h5; // @[Multiplier.scala:51:22, :101:39]
wire _T_14 = state == 3'h2; // @[Multiplier.scala:51:22, :106:39]
wire _GEN_1 = _T_14 & count == 7'h3F; // @[Multiplier.scala:54:18, :101:57, :106:{39,50}, :124:{25,55}, :125:13]
wire _T_17 = state == 3'h3; // @[Multiplier.scala:51:22, :129:39]
wire _T_18 = count == 7'h40; // @[Multiplier.scala:54:18, :138:17]
wire _T_23 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Multiplier.scala:40:7]
if (reset) // @[Multiplier.scala:40:7]
state <= 3'h0; // @[Multiplier.scala:51:22]
else if (_T_23) // @[Decoupled.scala:51:35]
state <= _state_T_3; // @[Multiplier.scala:51:22, :165:17]
else if (io_resp_ready_0 & io_resp_valid_0 | io_kill_0) // @[Decoupled.scala:51:35]
state <= 3'h0; // @[Multiplier.scala:51:22]
else if (_T_17 & _T_18) // @[Multiplier.scala:106:50, :129:{39,50}, :138:{17,42}, :139:13]
state <= _state_T; // @[Multiplier.scala:51:22, :139:19]
else if (_GEN_1) // @[Multiplier.scala:101:57, :106:50, :124:55, :125:13]
state <= 3'h6; // @[Multiplier.scala:51:22]
else if (_T_13) // @[Multiplier.scala:101:39]
state <= 3'h7; // @[Multiplier.scala:51:22]
else if (_T_10) // @[Multiplier.scala:92:39]
state <= 3'h3; // @[Multiplier.scala:51:22]
if (_T_23) begin // @[Decoupled.scala:51:35]
req_fn <= io_req_bits_fn_0; // @[Multiplier.scala:40:7, :53:16]
req_dw <= io_req_bits_dw_0; // @[Multiplier.scala:40:7, :53:16]
req_in1 <= io_req_bits_in1_0; // @[Multiplier.scala:40:7, :53:16]
req_in2 <= io_req_bits_in2_0; // @[Multiplier.scala:40:7, :53:16]
count <= {1'h0, _count_T_8}; // @[Multiplier.scala:54:18, :168:{11,38}]
isHi <= cmdHi; // @[Multiplier.scala:58:17, :75:107]
divisor <= _divisor_T; // @[Multiplier.scala:60:20, :170:19]
remainder <= {66'h0, lhs_in}; // @[Multiplier.scala:61:22, :83:9, :94:17, :171:15]
end
else begin // @[Decoupled.scala:51:35]
if (_T_17) begin // @[Multiplier.scala:129:39]
count <= eOut_1 ? {1'h0, _count_T_4} : _count_T_3; // @[Multiplier.scala:54:18, :144:{11,20}, :153:43, :154:19, :156:{15,26}]
remainder <= eOut_1 ? {3'h0, _remainder_T_4} : {1'h0, unrolls_0}; // @[Multiplier.scala:61:22, :134:10, :137:15, :153:43, :154:19, :155:{19,39}]
end
else if (_T_14) begin // @[Multiplier.scala:106:39]
count <= _count_T_1; // @[Multiplier.scala:54:18, :123:20]
remainder <= _remainder_T_2; // @[Multiplier.scala:61:22, :121:21]
end
else if (_T_13 | _T_10 & remainder[63]) // @[Multiplier.scala:61:22, :92:{39,57}, :93:{20,27}, :94:17, :101:{39,57}, :102:15]
remainder <= {66'h0, negated_remainder}; // @[Multiplier.scala:61:22, :90:27, :94:17]
if (_T_10 & divisor[63]) // @[Multiplier.scala:60:20, :92:{39,57}, :96:{18,25}, :97:15]
divisor <= subtractor; // @[Multiplier.scala:60:20, :88:37]
end
neg_out <= _T_23 ? _neg_out_T_1 : ~(_T_17 & divby0 & ~isHi) & neg_out; // @[Decoupled.scala:51:35]
resHi <= ~_T_23 & (_T_17 & _T_18 | _GEN_1 ? isHi : ~_T_13 & resHi); // @[Decoupled.scala:51:35]
always @(posedge)
assign io_req_ready = io_req_ready_0; // @[Multiplier.scala:40:7]
assign io_resp_valid = io_resp_valid_0; // @[Multiplier.scala:40:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[Multiplier.scala:40:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncQueue_10( // @[AsyncQueue.scala:226:7]
input io_enq_clock, // @[AsyncQueue.scala:227:14]
input io_enq_reset, // @[AsyncQueue.scala:227:14]
output io_enq_ready, // @[AsyncQueue.scala:227:14]
input io_enq_valid, // @[AsyncQueue.scala:227:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14]
input io_deq_clock, // @[AsyncQueue.scala:227:14]
input io_deq_reset, // @[AsyncQueue.scala:227:14]
input io_deq_ready, // @[AsyncQueue.scala:227:14]
output io_deq_valid, // @[AsyncQueue.scala:227:14]
output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14]
);
wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70]
wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70]
wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70]
wire io_enq_clock_0 = io_enq_clock; // @[AsyncQueue.scala:226:7]
wire io_enq_reset_0 = io_enq_reset; // @[AsyncQueue.scala:226:7]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:226:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:226:7]
wire io_deq_clock_0 = io_deq_clock; // @[AsyncQueue.scala:226:7]
wire io_deq_reset_0 = io_deq_reset; // @[AsyncQueue.scala:226:7]
wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:226:7]
wire io_enq_ready_0; // @[AsyncQueue.scala:226:7]
wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
wire io_deq_valid_0; // @[AsyncQueue.scala:226:7]
AsyncQueueSource_Phit_10 source ( // @[AsyncQueue.scala:228:70]
.clock (io_enq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_enq_reset_0), // @[AsyncQueue.scala:226:7]
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[AsyncQueue.scala:226:7]
.io_enq_bits_phit (io_enq_bits_phit_0), // @[AsyncQueue.scala:226:7]
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70]
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70]
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70]
); // @[AsyncQueue.scala:228:70]
AsyncQueueSink_Phit_10 sink ( // @[AsyncQueue.scala:229:70]
.clock (io_deq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_deq_reset_0), // @[AsyncQueue.scala:226:7]
.io_deq_ready (io_deq_ready_0), // @[AsyncQueue.scala:226:7]
.io_deq_valid (io_deq_valid_0),
.io_deq_bits_phit (io_deq_bits_phit_0),
.io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70]
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70]
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70]
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70]
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
); // @[AsyncQueue.scala:229:70]
assign io_enq_ready = io_enq_ready_0; // @[AsyncQueue.scala:226:7]
assign io_deq_valid = io_deq_valid_0; // @[AsyncQueue.scala:226:7]
assign io_deq_bits_phit = io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_49( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_62 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_315( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_36( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_45( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_24( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Metadata.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.util._
object ClientStates {
val width = 2
def Nothing = 0.U(width.W)
def Branch = 1.U(width.W)
def Trunk = 2.U(width.W)
def Dirty = 3.U(width.W)
def hasReadPermission(state: UInt): Bool = state > Nothing
def hasWritePermission(state: UInt): Bool = state > Branch
}
object MemoryOpCategories extends MemoryOpConstants {
def wr = Cat(true.B, true.B) // Op actually writes
def wi = Cat(false.B, true.B) // Future op will write
def rd = Cat(false.B, false.B) // Op only reads
def categorize(cmd: UInt): UInt = {
val cat = Cat(isWrite(cmd), isWriteIntent(cmd))
//assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.")
cat
}
}
/** Stores the client-side coherence information,
* such as permissions on the data and whether the data is dirty.
* Its API can be used to make TileLink messages in response to
* memory operations, cache control oeprations, or Probe messages.
*/
class ClientMetadata extends Bundle {
/** Actual state information stored in this bundle */
val state = UInt(ClientStates.width.W)
/** Metadata equality */
def ===(rhs: UInt): Bool = state === rhs
def ===(rhs: ClientMetadata): Bool = state === rhs.state
def =/=(rhs: ClientMetadata): Bool = !this.===(rhs)
/** Is the block's data present in this cache */
def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing
/** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */
private def growStarter(cmd: UInt): (Bool, UInt) = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
MuxTLookup(Cat(c, state), (false.B, 0.U), Seq(
//(effect, am now) -> (was a hit, next)
Cat(rd, Dirty) -> (true.B, Dirty),
Cat(rd, Trunk) -> (true.B, Trunk),
Cat(rd, Branch) -> (true.B, Branch),
Cat(wi, Dirty) -> (true.B, Dirty),
Cat(wi, Trunk) -> (true.B, Trunk),
Cat(wr, Dirty) -> (true.B, Dirty),
Cat(wr, Trunk) -> (true.B, Dirty),
//(effect, am now) -> (was a miss, param)
Cat(rd, Nothing) -> (false.B, NtoB),
Cat(wi, Branch) -> (false.B, BtoT),
Cat(wi, Nothing) -> (false.B, NtoT),
Cat(wr, Branch) -> (false.B, BtoT),
Cat(wr, Nothing) -> (false.B, NtoT)))
}
/** Determine what state to go to after miss based on Grant param
* For now, doesn't depend on state (which may have been Probed).
*/
private def growFinisher(cmd: UInt, param: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
import ClientStates._
val c = categorize(cmd)
//assert(c === rd || param === toT, "Client was expecting trunk permissions.")
MuxLookup(Cat(c, param), Nothing)(Seq(
//(effect param) -> (next)
Cat(rd, toB) -> Branch,
Cat(rd, toT) -> Trunk,
Cat(wi, toT) -> Trunk,
Cat(wr, toT) -> Dirty))
}
/** Does this cache have permissions on this block sufficient to perform op,
* and what to do next (Acquire message param or updated metadata). */
def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = growStarter(cmd)
(r._1, r._2, ClientMetadata(r._2))
}
/** Does a secondary miss on the block require another Acquire message */
def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = {
import MemoryOpCategories._
val r1 = growStarter(first_cmd)
val r2 = growStarter(second_cmd)
val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd)
val hit_again = r1._1 && r2._1
val dirties = categorize(second_cmd) === wr
val biggest_grow_param = Mux(dirties, r2._2, r1._2)
val dirtiest_state = ClientMetadata(biggest_grow_param)
val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd)
(needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd)
}
/** Metadata change on a returned Grant */
def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param))
/** Determine what state to go to based on Probe param */
private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = {
import ClientStates._
import TLPermissions._
MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq(
//(wanted, am now) -> (hasDirtyData resp, next)
Cat(toT, Dirty) -> (true.B, TtoT, Trunk),
Cat(toT, Trunk) -> (false.B, TtoT, Trunk),
Cat(toT, Branch) -> (false.B, BtoB, Branch),
Cat(toT, Nothing) -> (false.B, NtoN, Nothing),
Cat(toB, Dirty) -> (true.B, TtoB, Branch),
Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade
Cat(toB, Branch) -> (false.B, BtoB, Branch),
Cat(toB, Nothing) -> (false.B, NtoN, Nothing),
Cat(toN, Dirty) -> (true.B, TtoN, Nothing),
Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade
Cat(toN, Nothing) -> (false.B, NtoN, Nothing)))
}
/** Translate cache control cmds into Probe param */
private def cmdToPermCap(cmd: UInt): UInt = {
import MemoryOpCategories._
import TLPermissions._
MuxLookup(cmd, toN)(Seq(
M_FLUSH -> toN,
M_PRODUCE -> toB,
M_CLEAN -> toT))
}
def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(cmdToPermCap(cmd))
(r._1, r._2, ClientMetadata(r._3))
}
def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = {
val r = shrinkHelper(param)
(r._1, r._2, ClientMetadata(r._3))
}
}
/** Factories for ClientMetadata, including on reset */
object ClientMetadata {
def apply(perm: UInt) = {
val meta = Wire(new ClientMetadata)
meta.state := perm
meta
}
def onReset = ClientMetadata(ClientStates.Nothing)
def maximum = ClientMetadata(ClientStates.Dirty)
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File mshrs.scala:
//******************************************************************************
// Ported from Rocket-Chip
// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import boom.v3.common._
import boom.v3.exu.BrUpdateInfo
import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc}
class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p)
with HasL1HellaCacheParameters
{
// miss info
val tag_match = Bool()
val old_meta = new L1Metadata
val way_en = UInt(nWays.W)
// Used in the MSHRs
val sdq_id = UInt(log2Ceil(cfg.nSDQ).W)
}
class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val id = Input(UInt())
val req_pri_val = Input(Bool())
val req_pri_rdy = Output(Bool())
val req_sec_val = Input(Bool())
val req_sec_rdy = Output(Bool())
val clear_prefetch = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val req = Input(new BoomDCacheReqInternal)
val req_is_probe = Input(Bool())
val idx = Output(Valid(UInt()))
val way = Output(Valid(UInt()))
val tag = Output(Valid(UInt()))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val wb_req = Decoupled(new WritebackReq(edge.bundle))
// To inform the prefetcher when we are commiting the fetch of this line
val commit_val = Output(Bool())
val commit_addr = Output(UInt(coreMaxAddrBits.W))
val commit_coh = Output(new ClientMetadata)
// Reading from the line buffer
val lb_read = Decoupled(new LineBufferReadReq)
val lb_resp = Input(UInt(encRowBits.W))
val lb_write = Decoupled(new LineBufferWriteReq)
// Replays go through the cache pipeline again
val replay = Decoupled(new BoomDCacheReqInternal)
// Resp go straight out to the core
val resp = Decoupled(new BoomDCacheResp)
// Writeback unit tells us when it is done processing our wb
val wb_resp = Input(Bool())
val probe_rdy = Output(Bool())
})
// TODO: Optimize this. We don't want to mess with cache during speculation
// s_refill_req : Make a request for a new cache line
// s_refill_resp : Store the refill response into our buffer
// s_drain_rpq_loads : Drain out loads from the rpq
// : If miss was misspeculated, go to s_invalid
// s_wb_req : Write back the evicted cache line
// s_wb_resp : Finish writing back the evicted cache line
// s_meta_write_req : Write the metadata for new cache lne
// s_meta_write_resp :
val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18)
val state = RegInit(s_invalid)
val req = Reg(new BoomDCacheReqInternal)
val req_idx = req.addr(untagBits-1, blockOffBits)
val req_tag = req.addr >> untagBits
val req_block_addr = (req.addr >> blockOffBits) << blockOffBits
val req_needs_wb = RegInit(false.B)
val new_coh = RegInit(ClientMetadata.onReset)
val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)
val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2
val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param)
// We only accept secondary misses if the original request had sufficient permissions
val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =
new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd)
val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)
val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe &&
!state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses
val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false))
rpq.io.brupdate := io.brupdate
rpq.io.flush := io.exception
assert(!(state === s_invalid && !rpq.io.empty))
rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd)
rpq.io.enq.bits := io.req
rpq.io.deq.ready := false.B
val grantack = Reg(Valid(new TLBundleE(edge.bundle)))
val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W))
val commit_line = Reg(Bool())
val grant_had_data = Reg(Bool())
val finish_to_prefetch = Reg(Bool())
// Block probes if a tag write we started is still in the pipeline
val meta_hazard = RegInit(0.U(2.W))
when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }
when (io.meta_write.fire) { meta_hazard := 1.U }
io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid)))
io.idx.valid := state =/= s_invalid
io.tag.valid := state =/= s_invalid
io.way.valid := !state.isOneOf(s_invalid, s_prefetch)
io.idx.bits := req_idx
io.tag.bits := req_tag
io.way.bits := req.way_en
io.meta_write.valid := false.B
io.meta_write.bits := DontCare
io.req_pri_rdy := false.B
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
io.mem_acquire.valid := false.B
io.mem_acquire.bits := DontCare
io.refill.valid := false.B
io.refill.bits := DontCare
io.replay.valid := false.B
io.replay.bits := DontCare
io.wb_req.valid := false.B
io.wb_req.bits := DontCare
io.resp.valid := false.B
io.resp.bits := DontCare
io.commit_val := false.B
io.commit_addr := req.addr
io.commit_coh := coh_on_grant
io.meta_read.valid := false.B
io.meta_read.bits := DontCare
io.mem_finish.valid := false.B
io.mem_finish.bits := DontCare
io.lb_write.valid := false.B
io.lb_write.bits := DontCare
io.lb_read.valid := false.B
io.lb_read.bits := DontCare
io.mem_grant.ready := false.B
when (io.req_sec_val && io.req_sec_rdy) {
req.uop.mem_cmd := dirtier_cmd
when (is_hit_again) {
new_coh := dirtier_coh
}
}
def handle_pri_req(old_state: UInt): UInt = {
val new_state = WireInit(old_state)
grantack.valid := false.B
refill_ctr := 0.U
assert(rpq.io.enq.ready)
req := io.req
val old_coh = io.req.old_meta.coh
req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back
when (io.req.tag_match) {
val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // set dirty bit
assert(isWrite(io.req.uop.mem_cmd))
new_coh := coh_on_hit
new_state := s_drain_rpq
} .otherwise { // upgrade permissions
new_coh := old_coh
new_state := s_refill_req
}
} .otherwise { // refill and writeback if necessary
new_coh := ClientMetadata.onReset
new_state := s_refill_req
}
new_state
}
when (state === s_invalid) {
io.req_pri_rdy := true.B
grant_had_data := false.B
when (io.req_pri_val && io.req_pri_rdy) {
state := handle_pri_req(state)
}
} .elsewhen (state === s_refill_req) {
io.mem_acquire.valid := true.B
// TODO: Use AcquirePerm if just doing permissions acquire
io.mem_acquire.bits := edge.AcquireBlock(
fromSource = io.id,
toAddress = Cat(req_tag, req_idx) << blockOffBits,
lgSize = lgCacheBlockBytes.U,
growPermissions = grow_param)._2
when (io.mem_acquire.fire) {
state := s_refill_resp
}
} .elsewhen (state === s_refill_resp) {
when (edge.hasData(io.mem_grant.bits)) {
io.mem_grant.ready := io.lb_write.ready
io.lb_write.valid := io.mem_grant.valid
io.lb_write.bits.id := io.id
io.lb_write.bits.offset := refill_address_inc >> rowOffBits
io.lb_write.bits.data := io.mem_grant.bits.data
} .otherwise {
io.mem_grant.ready := true.B
}
when (io.mem_grant.fire) {
grant_had_data := edge.hasData(io.mem_grant.bits)
}
when (refill_done) {
grantack.valid := edge.isRequest(io.mem_grant.bits)
grantack.bits := edge.GrantAck(io.mem_grant.bits)
state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq)
assert(!(!grant_had_data && req_needs_wb))
commit_line := false.B
new_coh := coh_on_grant
}
} .elsewhen (state === s_drain_rpq_loads) {
val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) &&
!isWrite(rpq.io.deq.bits.uop.mem_cmd) &&
(rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay
// drain all loads for now
val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))
val data = io.lb_resp
val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W))
val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed,
Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)),
data_word, false.B, wordBytes)
rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load
io.lb_read.valid := rpq.io.deq.valid && drain_load
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits
io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load
io.resp.bits.uop := rpq.io.deq.bits.uop
io.resp.bits.data := loadgen.data
io.resp.bits.is_hella := rpq.io.deq.bits.is_hella
when (rpq.io.deq.fire) {
commit_line := true.B
}
.elsewhen (rpq.io.empty && !commit_line)
{
when (!rpq.io.enq.fire) {
state := s_mem_finish_1
finish_to_prefetch := enablePrefetching.B
}
} .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) {
// io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired
// The prefetcher should consider fetching the next line
io.commit_val := true.B
state := s_meta_read
}
} .elsewhen (state === s_meta_read) {
io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req_tag
io.meta_read.bits.way_en := req.way_en
when (io.meta_read.fire) {
state := s_meta_resp_1
}
} .elsewhen (state === s_meta_resp_1) {
state := s_meta_resp_2
} .elsewhen (state === s_meta_resp_2) {
val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1
state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read
Mux(needs_wb, s_meta_clear, s_commit_line))
} .elsewhen (state === s_meta_clear) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := coh_on_clear
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_wb_req
}
} .elsewhen (state === s_wb_req) {
io.wb_req.valid := true.B
io.wb_req.bits.tag := req.old_meta.tag
io.wb_req.bits.idx := req_idx
io.wb_req.bits.param := shrink_param
io.wb_req.bits.way_en := req.way_en
io.wb_req.bits.source := io.id
io.wb_req.bits.voluntary := true.B
when (io.wb_req.fire) {
state := s_wb_resp
}
} .elsewhen (state === s_wb_resp) {
when (io.wb_resp) {
state := s_commit_line
}
} .elsewhen (state === s_commit_line) {
io.lb_read.valid := true.B
io.lb_read.bits.id := io.id
io.lb_read.bits.offset := refill_ctr
io.refill.valid := io.lb_read.fire
io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits)
io.refill.bits.way_en := req.way_en
io.refill.bits.wmask := ~(0.U(rowWords.W))
io.refill.bits.data := io.lb_resp
when (io.refill.fire) {
refill_ctr := refill_ctr + 1.U
when (refill_ctr === (cacheDataBeats - 1).U) {
state := s_drain_rpq
}
}
} .elsewhen (state === s_drain_rpq) {
io.replay <> rpq.io.deq
io.replay.bits.way_en := req.way_en
io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))
when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) {
// Set dirty bit
val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd)
assert(is_hit, "We still don't have permissions for this store")
new_coh := coh_on_hit
}
when (rpq.io.empty && !rpq.io.enq.valid) {
state := s_meta_write_req
}
} .elsewhen (state === s_meta_write_req) {
io.meta_write.valid := true.B
io.meta_write.bits.idx := req_idx
io.meta_write.bits.data.coh := new_coh
io.meta_write.bits.data.tag := req_tag
io.meta_write.bits.way_en := req.way_en
when (io.meta_write.fire) {
state := s_mem_finish_1
finish_to_prefetch := false.B
}
} .elsewhen (state === s_mem_finish_1) {
io.mem_finish.valid := grantack.valid
io.mem_finish.bits := grantack.bits
when (io.mem_finish.fire || !grantack.valid) {
grantack.valid := false.B
state := s_mem_finish_2
}
} .elsewhen (state === s_mem_finish_2) {
state := Mux(finish_to_prefetch, s_prefetch, s_invalid)
} .elsewhen (state === s_prefetch) {
io.req_pri_rdy := true.B
when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) {
state := s_invalid
} .elsewhen (io.req_sec_val && io.req_sec_rdy) {
val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd)
when (is_hit) { // Proceed with refill
new_coh := coh_on_hit
state := s_meta_read
} .otherwise { // Reacquire this line
new_coh := ClientMetadata.onReset
state := s_refill_req
}
} .elsewhen (io.req_pri_val && io.req_pri_rdy) {
grant_had_data := false.B
state := handle_pri_req(state)
}
}
}
class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Decoupled(new BoomDCacheReq))
val resp = Decoupled(new BoomDCacheResp)
val mem_access = Decoupled(new TLBundleA(edge.bundle))
val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))
// We don't need brupdate in here because uncacheable operations are guaranteed non-speculative
})
def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits)
def wordFromBeat(addr: UInt, dat: UInt) = {
val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W))
(dat >> shift)(wordBits-1, 0)
}
val req = Reg(new BoomDCacheReq)
val grant_word = Reg(UInt(wordBits.W))
val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)
val state = RegInit(s_idle)
io.req.ready := state === s_idle
val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes)
val a_source = id.U
val a_address = req.addr
val a_size = req.uop.mem_size
val a_data = Fill(beatWords, req.data)
val get = edge.Get(a_source, a_address, a_size)._2
val put = edge.Put(a_source, a_address, a_size, a_data)._2
val atomics = if (edge.manager.anySupportLogical) {
MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(
M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,
M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,
M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,
M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,
M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,
M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,
M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,
M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,
M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))
} else {
// If no managers support atomics, assert fail if processor asks for them
assert(state === s_idle || !isAMO(req.uop.mem_cmd))
(0.U).asTypeOf(new TLBundleA(edge.bundle))
}
assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)
io.mem_access.valid := state === s_mem_access
io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put))
val send_resp = isRead(req.uop.mem_cmd)
io.resp.valid := (state === s_resp) && send_resp
io.resp.bits.is_hella := req.is_hella
io.resp.bits.uop := req.uop
io.resp.bits.data := loadgen.data
when (io.req.fire) {
req := io.req.bits
state := s_mem_access
}
when (io.mem_access.fire) {
state := s_mem_ack
}
when (state === s_mem_ack && io.mem_ack.valid) {
state := s_resp
when (isRead(req.uop.mem_cmd)) {
grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)
}
}
when (state === s_resp) {
when (!send_resp || io.resp.fire) {
state := s_idle
}
}
}
class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val id = UInt(log2Ceil(nLBEntries).W)
val offset = UInt(log2Ceil(cacheDataBeats).W)
def lb_addr = Cat(id, offset)
}
class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p)
{
val data = UInt(encRowBits.W)
}
class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p)
{
val id = UInt(log2Ceil(nLBEntries).W)
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p)
with HasL1HellaCacheParameters
{
val coh = new ClientMetadata
val addr = UInt(coreMaxAddrBits.W)
}
class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
with HasL1HellaCacheParameters
{
val io = IO(new Bundle {
val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe
val req_is_probe = Input(Vec(memWidth, Bool()))
val resp = Decoupled(new BoomDCacheResp)
val secondary_miss = Output(Vec(memWidth, Bool()))
val block_hit = Output(Vec(memWidth, Bool()))
val brupdate = Input(new BrUpdateInfo)
val exception = Input(Bool())
val rob_pnr_idx = Input(UInt(robAddrSz.W))
val rob_head_idx = Input(UInt(robAddrSz.W))
val mem_acquire = Decoupled(new TLBundleA(edge.bundle))
val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))
val mem_finish = Decoupled(new TLBundleE(edge.bundle))
val refill = Decoupled(new L1DataWriteReq)
val meta_write = Decoupled(new L1MetaWriteReq)
val meta_read = Decoupled(new L1MetaReadReq)
val meta_resp = Input(Valid(new L1Metadata))
val replay = Decoupled(new BoomDCacheReqInternal)
val prefetch = Decoupled(new BoomDCacheReq)
val wb_req = Decoupled(new WritebackReq(edge.bundle))
val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence
val wb_resp = Input(Bool())
val fence_rdy = Output(Bool())
val probe_rdy = Output(Bool())
})
val req_idx = OHToUInt(io.req.map(_.valid))
val req = io.req(req_idx)
val req_is_probe = io.req_is_probe(0)
for (w <- 0 until memWidth)
io.req(w).ready := false.B
val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher)
else Module(new NullPrefetcher)
io.prefetch <> prefetcher.io.prefetch
val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U)
// --------------------
// The MSHR SDQ
val sdq_val = RegInit(0.U(cfg.nSDQ.W))
val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))
val sdq_rdy = !sdq_val.andR
val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd)
val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))
when (sdq_enq) {
sdq(sdq_alloc_id) := req.bits.data
}
// --------------------
// The LineBuffer Data
// Holds refilling lines, prefetched lines
val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W))
val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs))
val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs))
lb_read_arb.io.out.ready := false.B
lb_write_arb.io.out.ready := true.B
val lb_read_data = WireInit(0.U(encRowBits.W))
when (lb_write_arb.io.out.fire) {
lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data)
} .otherwise {
lb_read_arb.io.out.ready := true.B
when (lb_read_arb.io.out.fire) {
lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr)
}
}
def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))
val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))
val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w)))
val idx_match = widthMap(w => idx_matches(w).reduce(_||_))
val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w)))
val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W)))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs))
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs))
val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))
val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs))
val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs))
val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs))
val commit_vals = Wire(Vec(cfg.nMSHRs, Bool()))
val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W)))
val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata))
var sec_rdy = false.B
io.fence_rdy := true.B
io.probe_rdy := true.B
io.mem_grant.ready := false.B
val mshr_alloc_idx = Wire(UInt())
val pri_rdy = WireInit(false.B)
val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx)
val mshrs = (0 until cfg.nMSHRs) map { i =>
val mshr = Module(new BoomMSHR)
mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W)
for (w <- 0 until memWidth) {
idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits)
tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits
way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en
}
wb_tag_list(i) := mshr.io.wb_req.bits.tag
mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val
when (i.U === mshr_alloc_idx) {
pri_rdy := mshr.io.req_pri_rdy
}
mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable
mshr.io.req := req.bits
mshr.io.req_is_probe := req_is_probe
mshr.io.req.sdq_id := sdq_alloc_id
// Clear because of a FENCE, a request to the same idx as a prefetched line,
// a probe to that prefetched line, all mshrs are in use
mshr.io.clear_prefetch := ((io.clear_all && !req.valid)||
(req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) ||
(req_is_probe && idx_matches(req_idx)(i)))
mshr.io.brupdate := io.brupdate
mshr.io.exception := io.exception
mshr.io.rob_pnr_idx := io.rob_pnr_idx
mshr.io.rob_head_idx := io.rob_head_idx
mshr.io.prober_state := io.prober_state
mshr.io.wb_resp := io.wb_resp
meta_write_arb.io.in(i) <> mshr.io.meta_write
meta_read_arb.io.in(i) <> mshr.io.meta_read
mshr.io.meta_resp := io.meta_resp
wb_req_arb.io.in(i) <> mshr.io.wb_req
replay_arb.io.in(i) <> mshr.io.replay
refill_arb.io.in(i) <> mshr.io.refill
lb_read_arb.io.in(i) <> mshr.io.lb_read
mshr.io.lb_resp := lb_read_data
lb_write_arb.io.in(i) <> mshr.io.lb_write
commit_vals(i) := mshr.io.commit_val
commit_addrs(i) := mshr.io.commit_addr
commit_cohs(i) := mshr.io.commit_coh
mshr.io.mem_grant.valid := false.B
mshr.io.mem_grant.bits := DontCare
when (io.mem_grant.bits.source === i.U) {
mshr.io.mem_grant <> io.mem_grant
}
sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val)
resp_arb.io.in(i) <> mshr.io.resp
when (!mshr.io.req_pri_rdy) {
io.fence_rdy := false.B
}
for (w <- 0 until memWidth) {
when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) {
io.probe_rdy := false.B
}
}
mshr
}
// Try to round-robin the MSHRs
val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W))
mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head))
when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) }
io.meta_write <> meta_write_arb.io.out
io.meta_read <> meta_read_arb.io.out
io.wb_req <> wb_req_arb.io.out
val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
var mmio_rdy = false.B
val mmios = (0 until nIOMSHRs) map { i =>
val id = cfg.nMSHRs + 1 + i // +1 for wb unit
val mshr = Module(new BoomIOMSHR(id))
mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready
mmio_alloc_arb.io.in(i).bits := DontCare
mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready
mshr.io.req.bits := req.bits
mmio_rdy = mmio_rdy || mshr.io.req.ready
mshr.io.mem_ack.bits := io.mem_grant.bits
mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U
when (io.mem_grant.bits.source === id.U) {
io.mem_grant.ready := true.B
}
resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp
when (!mshr.io.req.ready) {
io.fence_rdy := false.B
}
mshr
}
mmio_alloc_arb.io.out.ready := req.valid && !cacheable
TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))
TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))
val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false))
respq.io.brupdate := io.brupdate
respq.io.flush := io.exception
respq.io.enq <> resp_arb.io.out
io.resp <> respq.io.deq
for (w <- 0 until memWidth) {
io.req(w).ready := (w.U === req_idx) &&
Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy))
io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w)
io.block_hit(w) := idx_match(w) && tag_match(w)
}
io.refill <> refill_arb.io.out
val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd)
io.replay <> replay_arb.io.out
io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id)
when (io.replay.valid || sdq_enq) {
sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |
PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)
}
prefetcher.io.mshr_avail := RegNext(pri_rdy)
prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_))
prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs))
prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs))
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File AMOALU.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))
size := typ
val dat_padded = dat.pad(maxSize*8)
def misaligned: Bool =
(addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR
def mask = {
var res = 1.U
for (i <- 0 until log2Up(maxSize)) {
val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U)
val lower = Mux(addr(i), 0.U, res)
res = Cat(upper, lower)
}
res
}
protected def genData(i: Int): UInt =
if (i >= log2Up(maxSize)) dat_padded
else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))
def data = genData(0)
def wordData = genData(2)
}
class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
private val size = new StoreGen(typ, addr, dat, maxSize).size
private def genData(logMinSize: Int): UInt = {
var res = dat
for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
val pos = 8 << i
val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
val doZero = (i == 0).B && zero
val zeroed = Mux(doZero, 0.U, shifted)
res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
}
res
}
def wordData = genData(2)
def data = genData(0)
}
class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {
val minXLen = 32
val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _)
val io = IO(new Bundle {
val mask = Input(UInt((operandBits / 8).W))
val cmd = Input(UInt(M_SZ.W))
val lhs = Input(UInt(operandBits.W))
val rhs = Input(UInt(operandBits.W))
val out = Output(UInt(operandBits.W))
val out_unmasked = Output(UInt(operandBits.W))
})
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
val add = io.cmd === M_XA_ADD
val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
val adder_out = {
// partition the carry chain to support sub-xLen addition
val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)
(io.lhs & mask) + (io.rhs & mask)
}
val less = {
// break up the comparator so the lower parts will be CSE'd
def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = {
if (n == minXLen) x(n-1, 0) < y(n-1, 0)
else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2)
}
def isLess(x: UInt, y: UInt, n: Int): Bool = {
val signed = {
val mask = M_XA_MIN ^ M_XA_MINU
(io.cmd & mask) === (M_XA_MIN & mask)
}
Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1)))
}
PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w))))
}
val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)
val logic =
Mux(logic_and, io.lhs & io.rhs, 0.U) |
Mux(logic_xor, io.lhs ^ io.rhs, 0.U)
val out =
Mux(add, adder_out,
Mux(logic_and || logic_xor, logic,
minmax))
val wmask = FillInterleaved(8, io.mask)
io.out := wmask & out | ~wmask & io.lhs
io.out_unmasked := out
}
| module BoomMSHR_7( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [33:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [1:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [3:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [1:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [23:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [33:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
input io_lb_write_ready, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire [2:0] io_id = 3'h7; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_id = 3'h7; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_id = 3'h7; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_source = 4'h7; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_source = 4'h7; // @[mshrs.scala:36:7]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] io_mem_acquire_bits_a_source = 4'h7; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [3:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [23:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26]
wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [33:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [1:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34]
wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [27:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59]
wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File recFNFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object recFNFromFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val rawIn = rawFloatFromFN(expWidth, sigWidth, in)
rawIn.sign ##
(Mux(rawIn.isZero, 0.U(3.W), rawIn.sExp(expWidth, expWidth - 2)) |
Mux(rawIn.isNaN, 1.U, 0.U)) ##
rawIn.sExp(expWidth - 3, 0) ##
rawIn.sig(sigWidth - 2, 0)
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
File fNFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object fNFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in)
val isSubnormal = rawIn.sExp < minNormExp.S
val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0)
val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0)
val expOut =
Mux(isSubnormal,
0.U,
rawIn.sExp(expWidth - 1, 0) -
((BigInt(1)<<(expWidth - 1)) + 1).U
) | Fill(expWidth, rawIn.isNaN || rawIn.isInf)
val fractOut =
Mux(isSubnormal,
denormFract,
Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0))
)
Cat(rawIn.sign, expOut, fractOut)
}
}
File rawFloatFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object rawFloatFromFN {
def apply(expWidth: Int, sigWidth: Int, in: Bits) = {
val sign = in(expWidth + sigWidth - 1)
val expIn = in(expWidth + sigWidth - 2, sigWidth - 1)
val fractIn = in(sigWidth - 2, 0)
val isZeroExpIn = (expIn === 0.U)
val isZeroFractIn = (fractIn === 0.U)
val normDist = countLeadingZeros(fractIn)
val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1
val adjustedExp =
Mux(isZeroExpIn,
normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U,
expIn
) + ((BigInt(1) << (expWidth - 1)).U
| Mux(isZeroExpIn, 2.U, 1.U))
val isZero = isZeroExpIn && isZeroFractIn
val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && !isZeroFractIn
out.isInf := isSpecial && isZeroFractIn
out.isZero := isZero
out.sign := sign
out.sExp := adjustedExp(expWidth, 0).zext
out.sig :=
0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn)
out
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module PE_19( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [31:0] io_in_a_bits, // @[PE.scala:35:14]
input [31:0] io_in_b_bits, // @[PE.scala:35:14]
input [31:0] io_in_d_bits, // @[PE.scala:35:14]
output [31:0] io_out_a_bits, // @[PE.scala:35:14]
output [31:0] io_out_b_bits, // @[PE.scala:35:14]
output [31:0] io_out_c_bits, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [3:0] io_in_id, // @[PE.scala:35:14]
output [3:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30]
wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29]
wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29]
wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30]
wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24]
wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7]
wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7]
wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15]
wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7]
wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37]
wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37]
wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7]
wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7]
reg [31:0] c1_bits; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38]
reg [31:0] c2_bits; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] | _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29]
wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34]
assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34]
wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34]
assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34]
wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34]
assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}]
wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27]
wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27]
wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] | _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire _io_out_c_T = |io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26]
wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15]
wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}]
wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26]
wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN | io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 | _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] | _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26]
wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN | io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 | _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12]
wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37]
assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37]
wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] | _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26]
wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN | c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 | _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12]
wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] | _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29]
wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34]
assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}]
wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27]
wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27]
wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] | _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire _io_out_c_T_4 = |io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26]
wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15]
wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
| module IssueSlot_51( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
| module MSHR_4( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [4:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [11:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14]
input [11:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [11:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [4:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [11:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [11:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [4:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [11:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [11:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [4:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [11:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [11:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [11:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [4:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [11:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire [11:0] invalid_tag = 12'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [4:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [11:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [11:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [11:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [4:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [4:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [11:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [4:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [11:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [4:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
wire [4:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29]
wire [4:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29]
reg [11:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg [1:0] meta_clients; // @[MSHR.scala:100:17]
reg [11:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg [1:0] probes_done; // @[MSHR.scala:150:24]
reg [1:0] probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire [11:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire [3:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _req_clientBit_T = request_source[4]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_6 = request_source[4]; // @[Parameters.scala:54:10]
wire _req_clientBit_T_1 = _req_clientBit_T; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [3:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _req_clientBit_T_7 = ~_req_clientBit_T_6; // @[Parameters.scala:54:{10,32}]
wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}]
wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66]
wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}]
wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10]
wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10]
wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire [1:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire [1:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 12'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire [3:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _probe_bit_T = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10]
wire _probe_bit_T_6 = io_sinkc_bits_source_0[4]; // @[Parameters.scala:54:10]
wire _probe_bit_T_1 = _probe_bit_T; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_4 = probe_bit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [3:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _probe_bit_T_7 = ~_probe_bit_T_6; // @[Parameters.scala:54:{10,32}]
wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}]
wire _probe_bit_T_10 = probe_bit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48]
wire [1:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10]
wire [1:0] _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire [1:0] _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire [1:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire [1:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66]
wire [1:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [11:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [4:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [11:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [4:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29]
wire [4:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_631 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_631; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_631; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire [3:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _new_clientBit_T = new_request_source[4]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_6 = new_request_source[4]; // @[Parameters.scala:54:10]
wire _new_clientBit_T_1 = _new_clientBit_T; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [3:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _new_clientBit_T_7 = ~_new_clientBit_T_6; // @[Parameters.scala:54:{10,32}]
wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}]
wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_590 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_109( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_365 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a32d64s5k4z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_13 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s5k4z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s5k4z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR_18( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a32d128s4k4z4u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_46 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d128s4k4z4u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d128s4k4z4u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ResetCatchAndSync.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.{withClockAndReset, withReset}
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = IO(new Bundle {
val sync_reset = Output(Bool())
val psd = Input(new PSDTestMode())
})
// Bypass both the resets to the flops themselves (to prevent DFT holes on
// those flops) and on the output of the synchronizer circuit (to control
// reset to any flops this circuit drives).
val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool)
withReset(post_psd_reset) {
io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(true.B, sync))
}
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode())))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, name = Some(name), psd = Some(psd))
}
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
| module ResetCatchAndSync_d3( // @[ResetCatchAndSync.scala:13:7]
input clock, // @[ResetCatchAndSync.scala:13:7]
input reset // @[ResetCatchAndSync.scala:13:7]
);
wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76]
wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14]
wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25]
wire io_sync_reset; // @[ResetCatchAndSync.scala:13:7]
wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}]
wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24]
assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7]
assign io_sync_reset = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25]
AsyncResetSynchronizerShiftReg_w1_d3_i0_33 io_sync_reset_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27]
.io_q (_io_sync_reset_WIRE)
); // @[ShiftReg.scala:45:23]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File TileResetSetter.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
// Currently only works if all tiles are already driven by independent clock groups
// TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should
// always put all tiles on independent clock groups
class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters)
extends LazyModule {
val device = new SimpleDevice("tile-reset-setter", Nil)
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
val clockNode = ClockGroupIdentityNode()
lazy val module = new LazyModuleImp(this) {
val nTiles = p(TilesLocated(InSubsystem)).size
require (nTiles <= 4096 / 4)
val tile_async_resets = Wire(Vec(nTiles, Reset()))
val r_tile_resets = (0 until nTiles).map({ i =>
tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842
withReset (tile_async_resets(i)) {
Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0)))
}
})
if (nTiles > 0)
tlNode.regmap((0 until nTiles).map({ i =>
i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
}): _*)
val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>
n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4)
})
(clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) =>
(o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) =>
oD.clock := iD.clock
oD.reset := iD.reset
for ((n, (rIn, rOut, addr)) <- tileMap) {
if (name.contains(n)) {
println(s"${addr.toString(16)}: Tile $name reset control")
// Async because the reset coming out of the AsyncResetRegVec is
// clocked to the bus this is attached to, not the clock in this
// clock bundle. We expect a ClockGroupResetSynchronizer downstream
// to synchronize the resets
// Also, this or enforces that the tiles come out of reset after the reset of the system
oD.reset := (rOut.asBool || iD.reset.asBool).asAsyncReset
rIn := iD.reset
}
}
}
}
}
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TileResetSetter( // @[TileResetSetter.scala:26:25]
input clock, // @[TileResetSetter.scala:26:25]
input reset, // @[TileResetSetter.scala:26:25]
input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25]
wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25]
wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25]
wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25]
wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24]
wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33]
wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38]
wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25]
wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25]
wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10]
wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24]
wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25]
wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}]
assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
TLMonitor_47 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncResetRegVec_w1_i0_5 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15]
.clock (clock),
.io_d (_out_T_2), // @[RegisterRouter.scala:87:24]
.io_en (out_f_woready) // @[RegisterRouter.scala:87:24]
); // @[TileResetSetter.scala:33:15]
assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_141( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_362( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_106 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLBuffer_a32d128s5k4z4u_2( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_1_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_1_b_ready_0 = auto_in_1_b_ready; // @[Buffer.scala:40:9]
wire auto_in_1_c_valid_0 = auto_in_1_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_1_c_bits_opcode_0 = auto_in_1_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_1_c_bits_param_0 = auto_in_1_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_1_c_bits_size_0 = auto_in_1_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_1_c_bits_source_0 = auto_in_1_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_1_c_bits_address_0 = auto_in_1_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] auto_in_1_c_bits_data_0 = auto_in_1_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[Buffer.scala:40:9]
wire auto_in_1_e_valid_0 = auto_in_1_e_valid; // @[Buffer.scala:40:9]
wire [3:0] auto_in_1_e_bits_sink_0 = auto_in_1_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[Buffer.scala:40:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[Buffer.scala:40:9]
wire auto_out_1_b_valid_0 = auto_out_1_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_1_b_bits_param_0 = auto_out_1_b_bits_param; // @[Buffer.scala:40:9]
wire [31:0] auto_out_1_b_bits_address_0 = auto_out_1_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_1_c_ready_0 = auto_out_1_c_ready; // @[Buffer.scala:40:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[Buffer.scala:40:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[Buffer.scala:40:9]
wire [4:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_0_d_bits_sink_0 = auto_out_0_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_1_e_ready = 1'h1; // @[Decoupled.scala:362:21]
wire x1_nodeOut_e_ready = 1'h1; // @[Decoupled.scala:362:21]
wire [127:0] auto_out_1_b_bits_data = 128'h0; // @[Decoupled.scala:362:21]
wire [127:0] x1_nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21]
wire [15:0] auto_out_1_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21]
wire [15:0] x1_nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_1_b_bits_source = 2'h0; // @[Decoupled.scala:362:21]
wire [1:0] x1_nodeOut_b_bits_source = 2'h0; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_1_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] x1_nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_1_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire [2:0] x1_nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire auto_in_1_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_1_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_1_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_1_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_1_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire x1_nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_1_b_ready = auto_in_1_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_1_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_1_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_1_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] nodeIn_1_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_1_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_1_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_1_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_1_c_valid = auto_in_1_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_1_c_bits_opcode = auto_in_1_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_1_c_bits_param = auto_in_1_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_1_c_bits_size = auto_in_1_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_1_c_bits_source = auto_in_1_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_1_c_bits_address = auto_in_1_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_1_c_bits_data = auto_in_1_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_1_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_1_e_valid = auto_in_1_e_valid_0; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_1_e_bits_sink = auto_in_1_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[Buffer.scala:40:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_b_valid = auto_out_1_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] x1_nodeOut_b_bits_param = auto_out_1_b_bits_param_0; // @[Buffer.scala:40:9]
wire [31:0] x1_nodeOut_b_bits_address = auto_out_1_b_bits_address_0; // @[Buffer.scala:40:9]
wire x1_nodeOut_c_ready = auto_out_1_c_ready_0; // @[Buffer.scala:40:9]
wire x1_nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] x1_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] x1_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] x1_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] x1_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[Buffer.scala:40:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[Buffer.scala:40:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire x1_nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] x1_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_0_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_1_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_1_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_1_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_1_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_1_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_1_b_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_in_1_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_1_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_1_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_1_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_1_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_1_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_1_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_1_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_1_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_1_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_1_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_1_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_1_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_1_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_1_e_ready_0; // @[Buffer.scala:40:9]
wire auto_in_0_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_0_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_0_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_0_d_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_in_0_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_0_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_0_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_0_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_0_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_0_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_1_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_1_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_1_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_1_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_out_1_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_1_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_1_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_1_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_1_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_1_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_1_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_1_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_1_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_1_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_1_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_1_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_1_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_1_d_ready_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_1_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_1_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_0_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_0_a_bits_size_0; // @[Buffer.scala:40:9]
wire [4:0] auto_out_0_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_0_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_out_0_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_0_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_0_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_0_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_0_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[Buffer.scala:40:9]
assign auto_in_1_b_valid_0 = nodeIn_1_b_valid; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_opcode_0 = nodeIn_1_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_param_0 = nodeIn_1_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_size_0 = nodeIn_1_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_source_0 = nodeIn_1_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_address_0 = nodeIn_1_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_mask_0 = nodeIn_1_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_data_0 = nodeIn_1_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_corrupt_0 = nodeIn_1_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_1_c_ready_0 = nodeIn_1_c_ready; // @[Buffer.scala:40:9]
assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_1_e_ready_0 = nodeIn_1_e_ready; // @[Buffer.scala:40:9]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_1_b_ready_0 = x1_nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_1_c_valid_0 = x1_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_opcode_0 = x1_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_param_0 = x1_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_size_0 = x1_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_source_0 = x1_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_address_0 = x1_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_data_0 = x1_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_corrupt_0 = x1_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_1_e_valid_0 = x1_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_1_e_bits_sink_0 = x1_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_48 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_49 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_1_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_1_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_1_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_1_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_1_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_1_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_1_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_1_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_1_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_1_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_1_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_1_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_1_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_1_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_1_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_1_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_1_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_1_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_1_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_1_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_1_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_1_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d128s5k4z4u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d128s5k4z4u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleA_a32d128s2k4z4c nodeOut_a_q_1 ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_1_a_ready),
.io_enq_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (x1_nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (x1_nodeOut_a_valid),
.io_deq_bits_opcode (x1_nodeOut_a_bits_opcode),
.io_deq_bits_param (x1_nodeOut_a_bits_param),
.io_deq_bits_size (x1_nodeOut_a_bits_size),
.io_deq_bits_source (x1_nodeOut_a_bits_source),
.io_deq_bits_address (x1_nodeOut_a_bits_address),
.io_deq_bits_mask (x1_nodeOut_a_bits_mask),
.io_deq_bits_data (x1_nodeOut_a_bits_data),
.io_deq_bits_corrupt (x1_nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d128s2k4z4c nodeIn_d_q_1 ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (x1_nodeOut_d_ready),
.io_enq_valid (x1_nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (x1_nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (x1_nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (x1_nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (x1_nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (x1_nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (x1_nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (x1_nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (x1_nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_1_d_valid),
.io_deq_bits_opcode (nodeIn_1_d_bits_opcode),
.io_deq_bits_param (nodeIn_1_d_bits_param),
.io_deq_bits_size (nodeIn_1_d_bits_size),
.io_deq_bits_source (nodeIn_1_d_bits_source),
.io_deq_bits_sink (nodeIn_1_d_bits_sink),
.io_deq_bits_denied (nodeIn_1_d_bits_denied),
.io_deq_bits_data (nodeIn_1_d_bits_data),
.io_deq_bits_corrupt (nodeIn_1_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d128s2k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (x1_nodeOut_b_ready),
.io_enq_valid (x1_nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (x1_nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_address (x1_nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_1_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_1_b_valid),
.io_deq_bits_opcode (nodeIn_1_b_bits_opcode),
.io_deq_bits_param (nodeIn_1_b_bits_param),
.io_deq_bits_size (nodeIn_1_b_bits_size),
.io_deq_bits_source (nodeIn_1_b_bits_source),
.io_deq_bits_address (nodeIn_1_b_bits_address),
.io_deq_bits_mask (nodeIn_1_b_bits_mask),
.io_deq_bits_data (nodeIn_1_b_bits_data),
.io_deq_bits_corrupt (nodeIn_1_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d128s2k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_1_c_ready),
.io_enq_valid (nodeIn_1_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_1_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_1_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_1_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_1_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_1_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_1_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (x1_nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (x1_nodeOut_c_valid),
.io_deq_bits_opcode (x1_nodeOut_c_bits_opcode),
.io_deq_bits_param (x1_nodeOut_c_bits_param),
.io_deq_bits_size (x1_nodeOut_c_bits_size),
.io_deq_bits_source (x1_nodeOut_c_bits_source),
.io_deq_bits_address (x1_nodeOut_c_bits_address),
.io_deq_bits_data (x1_nodeOut_c_bits_data),
.io_deq_bits_corrupt (x1_nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d128s2k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_1_e_ready),
.io_enq_valid (nodeIn_1_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_1_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_valid (x1_nodeOut_e_valid),
.io_deq_bits_sink (x1_nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_valid = auto_in_1_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_opcode = auto_in_1_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_param = auto_in_1_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_size = auto_in_1_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_source = auto_in_1_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_address = auto_in_1_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_mask = auto_in_1_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_data = auto_in_1_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_1_b_bits_corrupt = auto_in_1_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_1_c_ready = auto_in_1_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_param = auto_in_1_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_sink = auto_in_1_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_1_e_ready = auto_in_1_e_ready_0; // @[Buffer.scala:40:9]
assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_param = auto_in_0_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_sink = auto_in_0_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_1_b_ready = auto_out_1_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_valid = auto_out_1_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_opcode = auto_out_1_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_param = auto_out_1_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_size = auto_out_1_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_source = auto_out_1_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_address = auto_out_1_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_data = auto_out_1_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_1_c_bits_corrupt = auto_out_1_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_1_e_valid = auto_out_1_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_1_e_bits_sink = auto_out_1_e_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Nodes.scala:
package constellation.channel
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy._
case class EmptyParams()
case class ChannelEdgeParams(cp: ChannelParams, p: Parameters)
object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] {
def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
ChannelEdgeParams(pu, p)
}
def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p)
def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString)
}
override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = {
val monitor = Module(new NoCMonitor(edge.cp)(edge.p))
monitor.io.in := bundle
}
// TODO: Add nodepath stuff? override def mixO, override def mixI
}
case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams()))
case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams))
case class ChannelAdapterNode(
slaveFn: ChannelParams => ChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn)
case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)()
case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)()
case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters)
case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters)
object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] {
def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
IngressChannelEdgeParams(pu, p)
}
def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p)
def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString)
}
}
object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] {
def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = {
EgressChannelEdgeParams(pu, p)
}
def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p)
def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) {
RenderedEdge(colour = "ffffff", label = "X")
} else {
RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString)
}
}
case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams()))
case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams))
case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams()))
case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams))
case class IngressChannelAdapterNode(
slaveFn: IngressChannelParams => IngressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn)
case class EgressChannelAdapterNode(
slaveFn: EgressChannelParams => EgressChannelParams = { d => d })(
implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn)
case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)()
case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)()
case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)()
case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)()
File Router.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{RoutingRelation}
import constellation.noc.{HasNoCParams}
case class UserRouterParams(
// Payload width. Must match payload width on all channels attached to this routing node
payloadBits: Int = 64,
// Combines SA and ST stages (removes pipeline register)
combineSAST: Boolean = false,
// Combines RC and VA stages (removes pipeline register)
combineRCVA: Boolean = false,
// Adds combinational path from SA to VA
coupleSAVA: Boolean = false,
vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p)
)
case class RouterParams(
nodeId: Int,
nIngress: Int,
nEgress: Int,
user: UserRouterParams
)
trait HasRouterOutputParams {
def outParams: Seq[ChannelParams]
def egressParams: Seq[EgressChannelParams]
def allOutParams = outParams ++ egressParams
def nOutputs = outParams.size
def nEgress = egressParams.size
def nAllOutputs = allOutParams.size
}
trait HasRouterInputParams {
def inParams: Seq[ChannelParams]
def ingressParams: Seq[IngressChannelParams]
def allInParams = inParams ++ ingressParams
def nInputs = inParams.size
def nIngress = ingressParams.size
def nAllInputs = allInParams.size
}
trait HasRouterParams
{
def routerParams: RouterParams
def nodeId = routerParams.nodeId
def payloadBits = routerParams.user.payloadBits
}
class DebugBundle(val nIn: Int) extends Bundle {
val va_stall = Vec(nIn, UInt())
val sa_stall = Vec(nIn, UInt())
}
class Router(
val routerParams: RouterParams,
preDiplomaticInParams: Seq[ChannelParams],
preDiplomaticIngressParams: Seq[IngressChannelParams],
outDests: Seq[Int],
egressIds: Seq[Int]
)(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams {
val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams
val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u))
val sourceNodes = outDests.map(u => ChannelSourceNode(u))
val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u))
val egressNodes = egressIds.map(u => EgressChannelSourceNode(u))
val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size))
val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None
def inParams = module.inParams
def outParams = module.outParams
def ingressParams = module.ingressParams
def egressParams = module.egressParams
lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams {
val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip
val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip
val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip
val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip
val io_debug = debugNode.out(0)._1
val inParams = edgesIn.map(_.cp)
val outParams = edgesOut.map(_.cp)
val ingressParams = edgesIngress.map(_.cp)
val egressParams = edgesEgress.map(_.cp)
allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits))
allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits))
require(nIngress == routerParams.nIngress)
require(nEgress == routerParams.nEgress)
require(nAllInputs >= 1)
require(nAllOutputs >= 1)
require(nodeId < (1 << nodeIdBits))
val input_units = inParams.zipWithIndex.map { case (u,i) =>
Module(new InputUnit(u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"input_unit_${i}_from_${u.srcId}") }
val ingress_units = ingressParams.zipWithIndex.map { case (u,i) =>
Module(new IngressUnit(i, u, outParams, egressParams,
routerParams.user.combineRCVA, routerParams.user.combineSAST))
.suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") }
val all_input_units = input_units ++ ingress_units
val output_units = outParams.zipWithIndex.map { case (u,i) =>
Module(new OutputUnit(inParams, ingressParams, u))
.suggestName(s"output_unit_${i}_to_${u.destId}")}
val egress_units = egressParams.zipWithIndex.map { case (u,i) =>
Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1,
routerParams.user.combineSAST,
inParams, ingressParams, u))
.suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")}
val all_output_units = output_units ++ egress_units
val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams))
val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams))
val vc_allocator = Module(routerParams.user.vcAllocator(
VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams)
)(p))
val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams))
val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire)))
dontTouch(fires_count)
(io_in zip input_units ).foreach { case (i,u) => u.io.in <> i }
(io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit }
(output_units zip io_out ).foreach { case (u,o) => o <> u.io.out }
(egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out }
(route_computer.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.router_req }
(all_input_units zip route_computer.io.resp).foreach {
case (u,o) => u.io.router_resp <> o }
(vc_allocator.io.req zip all_input_units).foreach {
case (i,u) => i <> u.io.vcalloc_req }
(all_input_units zip vc_allocator.io.resp).foreach {
case (u,o) => u.io.vcalloc_resp <> o }
(all_output_units zip vc_allocator.io.out_allocs).foreach {
case (u,a) => u.io.allocs <> a }
(vc_allocator.io.channel_status zip all_output_units).foreach {
case (a,u) => a := u.io.channel_status }
all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) =>
in.io.out_credit_available(outIdx) := out.io.credit_available
})
(all_input_units zip switch_allocator.io.req).foreach {
case (u,r) => r <> u.io.salloc_req }
(all_output_units zip switch_allocator.io.credit_alloc).foreach {
case (u,a) => u.io.credit_alloc := a }
(switch.io.in zip all_input_units).foreach {
case (i,u) => i <> u.io.out }
(all_output_units zip switch.io.out).foreach {
case (u,o) => u.io.in <> o }
switch.io.sel := (if (routerParams.user.combineSAST) {
switch_allocator.io.switch_sel
} else {
RegNext(switch_allocator.io.switch_sel)
})
if (hasCtrl) {
val io_ctrl = ctrlNode.get.out(0)._1
val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams))
io_ctrl <> ctrl.io.ctrl
(all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r }
(all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) }
} else {
input_units.foreach(_.io.block := false.B)
ingress_units.foreach(_.io.block := false.B)
}
(io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r }
(io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r }
val debug_tsc = RegInit(0.U(64.W))
debug_tsc := debug_tsc + 1.U
val debug_sample = RegInit(0.U(64.W))
debug_sample := debug_sample + 1.U
val sample_rate = PlusArg("noc_util_sample_rate", width=20)
when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U }
def sample(fire: Bool, s: String) = {
val util_ctr = RegInit(0.U(64.W))
val fired = RegInit(false.B)
util_ctr := util_ctr + fire
fired := fired || fire
when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) {
val fmtStr = s"nocsample %d $s %d\n"
printf(fmtStr, debug_tsc, util_ctr);
fired := fire
}
}
destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f =>
sample(f.fire, s"${edge.cp.srcId} $nodeId")
} }
ingressNodes.map(_.in(0)).foreach { case (in, edge) =>
sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId")
}
egressNodes.map(_.out(0)).foreach { case (out, edge) =>
sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}")
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module Router( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_5, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_va_stall_6, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_5, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_debug_out_sa_stall_6, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_3_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_3_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_3_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_egress_nodes_out_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_4_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_4_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_4_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_4_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_ingress_nodes_in_4_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_ingress_nodes_in_4_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_3_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_3_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_3_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_3_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_ingress_nodes_in_3_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_3_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [144:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [144:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_6_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_6_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_6_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_6_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_6_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_6_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_4_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_1_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32]
wire _vc_allocator_io_req_6_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_5_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_6_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_5_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_5_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_4_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_5_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_4_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_6_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_5_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_5_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_5_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_4_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_4_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_6_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_5_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_6_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_6_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_6_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_6_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_6_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_5_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_io_out_5_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_5_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_5_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_5_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_4_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [144:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_5_to_14_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_5_to_14_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_5_to_14_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_4_to_13_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_4_to_13_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_4_to_13_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_3_to_1_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_1_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_1_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_2_to_0_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_0_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_0_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_1_to_4_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_1_to_4_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire [3:0] _ingress_unit_6_from_26_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_6_from_26_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [144:0] _ingress_unit_6_from_26_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_6_from_26_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_6_from_26_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_6_from_26_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_6_from_26_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_6_from_26_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_6_from_26_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_6_from_26_io_in_ready; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [144:0] _ingress_unit_5_from_3_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_5_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_5_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_5_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_5_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_5_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_5_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_5_from_3_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_2_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_2_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [144:0] _ingress_unit_4_from_2_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_4_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_4_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_4_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_4_from_2_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_0_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_0_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [144:0] _ingress_unit_2_from_0_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_0_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_0_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_0_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_0_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_0_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_0_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_0_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_1_from_4_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_4_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [144:0] _input_unit_1_from_4_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_4_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_4_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_4_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_1_from_4_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_4_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_5_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_5_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_1_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [144:0] _input_unit_0_from_1_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_1_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_1_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_4_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_0_io_vcalloc_req_valid}} + {2'h0, _vc_allocator_io_req_4_ready & _ingress_unit_4_from_2_io_vcalloc_req_valid} + {1'h0, {1'h0, _vc_allocator_io_req_5_ready & _ingress_unit_5_from_3_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_6_ready & _ingress_unit_6_from_26_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_6; // @[Router.scala:203:29]
reg fired_6; // @[Router.scala:204:26]
wire _GEN_6 = _GEN_0 & fired_6; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_7; // @[Router.scala:203:29]
reg fired_7; // @[Router.scala:204:26]
wire _GEN_7 = _GEN_0 & fired_7; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_8; // @[Router.scala:203:29]
reg fired_8; // @[Router.scala:204:26]
wire _GEN_8 = _GEN_0 & fired_8; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_9; // @[Router.scala:203:29]
reg fired_9; // @[Router.scala:204:26]
wire _GEN_9 = _GEN_0 & fired_9; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_10; // @[Router.scala:203:29]
reg fired_10; // @[Router.scala:204:26]
wire _GEN_10 = _GEN_0 & fired_10; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_50 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_101 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1326 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1326; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1326; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1399 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1399; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1399; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1399; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1252 = _T_1326 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1252 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1252 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1252 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1252 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1252 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1298 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1298 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1267 = _T_1399 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1267 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1267 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1267 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1370 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1370 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1352 = _T_1399 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1352 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1352 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1352 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
| module IssueSlot_67( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_503( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_247 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Periphery.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.experimental.{noPrefix, IntParam}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters}
import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource}
import freechips.rocketchip.jtag.JTAGIO
import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget}
import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
/** Protocols used for communicating with external debugging tools */
sealed trait DebugExportProtocol
case object DMI extends DebugExportProtocol
case object JTAG extends DebugExportProtocol
case object CJTAG extends DebugExportProtocol
case object APB extends DebugExportProtocol
/** Options for possible debug interfaces */
case class DebugAttachParams(
protocols: Set[DebugExportProtocol] = Set(DMI),
externalDisable: Boolean = false,
masterWhere: TLBusWrapperLocation = FBUS,
slaveWhere: TLBusWrapperLocation = CBUS
) {
def dmi = protocols.contains(DMI)
def jtag = protocols.contains(JTAG)
def cjtag = protocols.contains(CJTAG)
def apb = protocols.contains(APB)
}
case object ExportDebug extends Field(DebugAttachParams())
class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) {
val clock = Clock()
val reset = Reset()
}
class DebugIO(implicit val p: Parameters) extends Bundle {
val clock = Input(Clock())
val reset = Input(Reset())
val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO()))
val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO)
val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32))))
//------------------------------
val ndreset = Output(Bool())
val dmactive = Output(Bool())
val dmactiveAck = Input(Bool())
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool()))
}
class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO {
}
class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle {
val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool())))
val hartIsInReset = Input(Vec(nComponents, Bool()))
}
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), or exports and hooks up APB,
* based on a global parameter.
*/
trait HasPeripheryDebug { this: BaseSubsystem =>
private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere)
lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
val debugTLDomainOpt = p(DebugModuleKey).map { _ =>
val domain = ClockSinkNode(Seq(ClockSinkParameters()))
domain := tlbus.fixedClockNode
domain
}
lazy val debugOpt = p(DebugModuleKey).map { params =>
val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ }
tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
(apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) =>
slave := master
}
tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") {
_ := TLWidthWidget(1) := sb2tl.node
}
}
tlDM
}
val debugNode = debugOpt.map(_.intnode)
val psd = InModuleBody {
val psd = IO(new PSDIO)
psd
}
val resetctrl = InModuleBody {
debugOpt.map { debug =>
debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset
debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock
val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size))
debug.module.io.hartIsInReset := resetctrl.hartIsInReset
resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}
resetctrl
}
}
// noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603
val debug = InModuleBody { noPrefix(debugOpt.map { debugmod =>
val debug = IO(new DebugIO)
require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined),
"You cannot have both DMI and JTAG interface in HasPeripheryDebug")
require(!(debug.clockeddmi.isDefined && debug.apb.isDefined),
"You cannot have both DMI and APB interface in HasPeripheryDebug")
require(!(debug.systemjtag.isDefined && debug.apb.isDefined),
"You cannot have both APB and JTAG interface in HasPeripheryDebug")
debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg }
(debug.apb
zip apbDebugNodeOpt
zip debugmod.module.io.apb_clock
zip debugmod.module.io.apb_reset).foreach {
case (((io, apb), c ), r) =>
apb.out(0)._1 <> io
c:= io.clock
r:= io.reset
}
debugmod.module.io.debug_reset := debug.reset
debugmod.module.io.debug_clock := debug.clock
debug.ndreset := debugmod.module.io.ctrl.ndreset
debug.dmactive := debugmod.module.io.ctrl.dmactive
debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck
debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}}
// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B }
debug
})}
val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) }
def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag
debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }) // force TMS high when debug is disabled
dtm.io.jtag_clock := sj.jtag.TCK
dtm.io.jtag_reset := sj.reset
dtm.io.jtag_mfr_id := sj.mfr_id
dtm.io.jtag_part_number := sj.part_number
dtm.io.jtag_version := sj.version
dtm.rf_reset := sj.reset
debugOpt.map { outerdebug =>
outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi
outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK
outerdebug.module.io.dmi.get.dmiReset := sj.reset
}
dtm
}
}
/** BlackBox to export DMI interface */
class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Clock())
val reset = Input(Bool())
val debug = new DMIIO
val exit = Output(UInt(32.W))
})
def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
io.clk := tbclk
io.reset := tbreset
dutio.dmi <> io.debug
dutio.dmiClock := tbclk
dutio.dmiReset := tbreset
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimDTM.v")
addResource("/csrc/SimDTM.cc")
}
/** BlackBox to export JTAG interface */
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay)))
with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val jtag = new JTAGIO(hasTRSTn = true)
val enable = Input(Bool())
val init_done = Input(Bool())
val exit = Output(UInt(32.W))
})
def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
dutio.TCK := io.jtag.TCK
dutio.TMS := io.jtag.TMS
dutio.TDI := io.jtag.TDI
io.jtag.TDO := dutio.TDO
io.clock := tbclock
io.reset := tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := init_done
// Success is determined by the gdbserver
// which is controlling this simulation.
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimJTAG.v")
addResource("/csrc/SimJTAG.cc")
addResource("/csrc/remote_bitbang.h")
addResource("/csrc/remote_bitbang.cc")
}
object Debug {
def connectDebug(
debugOpt: Option[DebugIO],
resetctrlOpt: Option[ResetCtrlIO],
psdio: PSDIO,
c: Clock,
r: Bool,
out: Bool,
tckHalfPeriod: Int = 2,
cmdDelay: Int = 2,
psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode()))
(implicit p: Parameters): Unit = {
connectDebugClockAndReset(debugOpt, c)
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }}
debugOpt.map { debug =>
debug.clockeddmi.foreach { d =>
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
debug.systemjtag.foreach { sj =>
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
sj.reset := r.asAsyncReset
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
sj.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
debug.apb.foreach { apb =>
require(false, "No support for connectDebug for an APB debug connection.")
}
psdio.psd.foreach { _ <> psd }
debug.disableDebug.foreach { x => x := false.B }
}
}
def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
debugOpt.foreach { debug =>
val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) |
debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) |
debug.apb.map(_.reset.asBool).getOrElse(false.B)
connectDebugClockHelper(debug, dmi_reset, c, sync)
}
}
def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
val debug_reset = Wire(Bool())
withClockAndReset(c, dmi_reset) {
val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset
debug_reset := debug_reset_syncd
}
// Need to clock DM during debug_reset because of synchronous reset, so keep
// the clock alive for one cycle after debug_reset asserts to action this behavior.
// The unit should also be clocked when dmactive is high.
withClockAndReset(c, debug_reset.asAsyncReset) {
val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive
val clock_en = RegNext(next=dmactiveAck, init=true.B)
val gated_clock =
if (!p(DebugModuleKey).get.clockGate) c
else ClockGate(c, clock_en, "debug_clock_gate")
debug.clock := gated_clock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset)
debug.dmactiveAck := dmactiveAck
}
}
def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = {
psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } )
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }}
debugOpt.map { debug =>
debug.clock := true.B.asClock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset)
debug.systemjtag.foreach { sj =>
sj.jtag.TCK := true.B.asClock
sj.jtag.TMS := true.B
sj.jtag.TDI := true.B
sj.jtag.TRSTn.foreach { r => r := true.B }
sj.reset := true.B.asAsyncReset
sj.mfr_id := 0.U
sj.part_number := 0.U
sj.version := 0.U
}
debug.clockeddmi.foreach { d =>
d.dmi.req.valid := false.B
d.dmi.req.bits.addr := 0.U
d.dmi.req.bits.data := 0.U
d.dmi.req.bits.op := 0.U
d.dmi.resp.ready := true.B
d.dmiClock := false.B.asClock
d.dmiReset := true.B.asAsyncReset
}
debug.apb.foreach { apb =>
apb.clock := false.B.asClock
apb.reset := true.B.asAsyncReset
apb.pready := false.B
apb.pslverr := false.B
apb.prdata := 0.U
apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser))
apb.psel := false.B
apb.penable := false.B
}
debug.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
debug.disableDebug.foreach { x => x := false.B }
debug.dmactiveAck := false.B
debug.ndreset
}.getOrElse(false.B)
}
}
File ResetCatchAndSync.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.{withClockAndReset, withReset}
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = IO(new Bundle {
val sync_reset = Output(Bool())
val psd = Input(new PSDTestMode())
})
// Bypass both the resets to the flops themselves (to prevent DFT holes on
// those flops) and on the output of the synchronizer circuit (to control
// reset to any flops this circuit drives).
val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool)
withReset(post_psd_reset) {
io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(true.B, sync))
}
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode())))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, name = Some(name), psd = Some(psd))
}
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File IOCell.scala:
// See LICENSE for license details
package chipyard.iocell
import chisel3._
import chisel3.util.{Cat, HasBlackBoxInline}
import chisel3.reflect.DataMirror
import chisel3.experimental.{Analog, BaseModule}
// The following four IO cell bundle types are bare-minimum functional connections
// for modeling 4 different IO cell scenarios. The intention is that the user
// would create wrapper modules that extend these interfaces with additional
// control signals. These are loosely similar to the sifive-blocks PinCtrl bundles
// (https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/pinctrl/PinCtrl.scala),
// but we want to avoid a dependency on an external libraries.
/** The base IO bundle for an analog signal (typically something with no digital buffers inside)
* pad: off-chip (external) connection
* core: internal connection
*/
class AnalogIOCellBundle extends Bundle {
val pad = Analog(1.W) // Pad/bump signal (off-chip)
val core = Analog(1.W) // core signal (on-chip)
}
/** The base IO bundle for a signal with runtime-controllable direction
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalGPIOCellBundle extends Bundle {
val pad = Analog(1.W)
val i = Output(Bool())
val ie = Input(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital output signal
* pad: off-chip (external) connection
* o: output from chip logic (input to IO cell)
* oe: enable signal for o
*/
class DigitalOutIOCellBundle extends Bundle {
val pad = Output(Bool())
val o = Input(Bool())
val oe = Input(Bool())
}
/** The base IO bundle for a digital input signal
* pad: off-chip (external) connection
* i: input to chip logic (output from IO cell)
* ie: enable signal for i
*/
class DigitalInIOCellBundle extends Bundle {
val pad = Input(Bool())
val i = Output(Bool())
val ie = Input(Bool())
}
trait IOCell extends BaseModule {
var iocell_name: Option[String] = None
/** Set IOCell name
* @param s Proposed name for the IOCell
*
* @return An inherited IOCell with given the proposed name
*/
def suggestName(s: String): this.type = {
iocell_name = Some(s)
super.suggestName(s)
}
}
trait AnalogIOCell extends IOCell {
val io: AnalogIOCellBundle
}
trait DigitalGPIOCell extends IOCell {
val io: DigitalGPIOCellBundle
}
trait DigitalInIOCell extends IOCell {
val io: DigitalInIOCellBundle
}
trait DigitalOutIOCell extends IOCell {
val io: DigitalOutIOCellBundle
}
// The following Generic IO cell black boxes have verilog models that mimic a very simple
// implementation of an IO cell. For building a real chip, it is important to implement
// and use similar classes which wrap the foundry-specific IO cells.
abstract class GenericIOCell extends BlackBox with HasBlackBoxInline {
val impl: String
val moduleName = this.getClass.getSimpleName
setInline(s"$moduleName.v", impl);
}
class GenericAnalogIOCell extends GenericIOCell with AnalogIOCell {
val io = IO(new AnalogIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericAnalogIOCell(
inout pad,
inout core
);
assign core = 1'bz;
assign pad = core;
endmodule"""
}
class GenericDigitalGPIOCell extends GenericIOCell with DigitalGPIOCell {
val io = IO(new DigitalGPIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalGPIOCell(
inout pad,
output i,
input ie,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalInIOCell extends GenericIOCell with DigitalInIOCell {
val io = IO(new DigitalInIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalInIOCell(
input pad,
output i,
input ie
);
assign i = ie ? pad : 1'b0;
endmodule"""
}
class GenericDigitalOutIOCell extends GenericIOCell with DigitalOutIOCell {
val io = IO(new DigitalOutIOCellBundle)
lazy val impl = s"""
`timescale 1ns/1ps
module GenericDigitalOutIOCell(
output pad,
input o,
input oe
);
assign pad = oe ? o : 1'bz;
endmodule"""
}
trait IOCellTypeParams {
def analog(): AnalogIOCell
def gpio(): DigitalGPIOCell
def input(): DigitalInIOCell
def output(): DigitalOutIOCell
}
case class GenericIOCellParams() extends IOCellTypeParams {
def analog() = Module(new GenericAnalogIOCell)
def gpio() = Module(new GenericDigitalGPIOCell)
def input() = Module(new GenericDigitalInIOCell)
def output() = Module(new GenericDigitalOutIOCell)
}
object IOCell {
/** From within a RawModule or MultiIOModule context, generate new module IOs from a given
* signal and return the new IO and a Seq containing all generated IO cells.
* @param coreSignal The signal onto which to add IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @param abstractResetAsAsync When set, will coerce abstract resets to
* AsyncReset, and otherwise to Bool (sync reset)
* @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances)
*/
def generateIOFromSignal[T <: Data](
coreSignal: T,
name: String,
typeParams: IOCellTypeParams = GenericIOCellParams(),
abstractResetAsAsync: Boolean = false
): (T, Seq[IOCell]) = {
val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name)
val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset
val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn)
(padSignal, iocells)
}
/** Connect two identical signals together by adding IO cells between them and return a Seq
* containing all generated IO cells.
* @param coreSignal The core-side (internal) signal onto which to connect/add IO cells
* @param padSignal The pad-side (external) signal onto which to connect IO cells
* @param name An optional name or name prefix to use for naming IO cells
* @return A Seq of all generated IO cell instances
*/
val toSyncReset: (Reset) => Bool = _.asBool
val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset
def generateFromSignal[T <: Data, R <: Reset](
coreSignal: T,
padSignal: T,
name: Option[String] = None,
typeParams: IOCellTypeParams = GenericIOCellParams(),
concretizeResetFn: (Reset) => R = toSyncReset
): Seq[IOCell] = {
def genCell[T <: Data](
castToBool: (T) => Bool,
castFromBool: (Bool) => T
)(coreSignal: T,
padSignal: T
): Seq[IOCell] = {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocell = typeParams.input()
name.foreach(n => {
iocell.suggestName(n)
})
coreSignal := castFromBool(iocell.io.i)
iocell.io.ie := true.B
iocell.io.pad := castToBool(padSignal)
Seq(iocell)
}
case ActualDirection.Output => {
val iocell = typeParams.output()
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := castToBool(coreSignal)
iocell.io.oe := true.B
padSignal := castFromBool(iocell.io.pad)
Seq(iocell)
}
case _ => throw new Exception(s"Signal does not have a direction and cannot be matched to an IOCell")
}
}
def genCellForClock = genCell[Clock](_.asUInt.asBool, _.asClock) _
def genCellForAsyncReset = genCell[AsyncReset](_.asBool, _.asAsyncReset) _
def genCellForAbstractReset = genCell[Reset](_.asBool, concretizeResetFn) _
(coreSignal, padSignal) match {
case (coreSignal: Analog, padSignal: Analog) => {
if (coreSignal.getWidth == 0) {
Seq()
} else {
require(
coreSignal.getWidth == 1,
"Analogs wider than 1 bit are not supported because we can't bit-select Analogs (https://github.com/freechipsproject/chisel3/issues/536)"
)
val iocell = typeParams.analog()
name.foreach(n => iocell.suggestName(n))
iocell.io.core <> coreSignal
padSignal <> iocell.io.pad
Seq(iocell)
}
}
case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal)
case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal)
case (coreSignal: Bits, padSignal: Bits) => {
require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
if (padSignal.getWidth == 0) {
// This dummy assignment will prevent invalid firrtl from being emitted
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => coreSignal := 0.U
case _ => {}
}
Seq()
} else {
DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => {
val iocells = padSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.input()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.pad := sig
iocell.io.ie := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
coreSignal := Cat(iocells.map(_.io.i).reverse)
iocells
}
case ActualDirection.Output => {
val iocells = coreSignal.asBools.zipWithIndex.map { case (sig, i) =>
val iocell = typeParams.output()
// Note that we are relying on chisel deterministically naming this in the index order (which it does)
// This has the side-effect of naming index 0 with no _0 suffix, which is how chisel names other signals
// An alternative solution would be to suggestName(n + "_" + i)
name.foreach(n => {
iocell.suggestName(n)
})
iocell.io.o := sig
iocell.io.oe := true.B
iocell
}
// Note that the reverse here is because Cat(Seq(a,b,c,d)) yields abcd, but a is index 0 of the Seq
padSignal := Cat(iocells.map(_.io.pad).reverse)
iocells
}
case _ => throw new Exception("Bits signal does not have a direction and cannot be matched to IOCell(s)")
}
}
}
case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal)
case (coreSignal: Vec[_], padSignal: Vec[_]) => {
require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), typeParams)
total ++ ios
}
}
case (coreSignal: Record, padSignal: Record) => {
coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) =>
val pad = padSignal.elements(eltName)
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), typeParams)
total ++ ios
}
}
case _ => { throw new Exception("Oops, I don't know how to handle this signal.") }
}
}
}
File ChipTop.scala:
package chipyard
import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{DontTouch}
import chipyard.iobinders._
import chipyard.iocell._
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))
/**
* The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
* named "system", which is an instance of DigitalTop by default. The diplomatic clocks of System, as well as its implicit clock,
* is aggregated into the clockGroupNode. The parameterized functions controlled by ClockingSchemeKey and GlobalResetSchemeKey
* drive clock and reset generation
*/
class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
with HasIOBinders {
// The system module specified by BuildSystem
lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
// NOTE: Making this a LazyRawModule is moderately dangerous, as anonymous children
// of ChipTop (ex: ClockGroup) do not receive clock or reset.
// However. anonymous children of ChipTop should not need an implicit Clock or Reset
// anyways, they probably need to be explicitly clocked.
lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch { }
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File ClockGate.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath}
import org.chipsalliance.cde.config.{Field, Parameters}
import java.nio.file.{Files, Paths}
case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper)
case object ClockGateModelFile extends Field[Option[String]](None)
abstract class ClockGate extends BlackBox
with HasBlackBoxResource with HasBlackBoxPath {
val io = IO(new Bundle{
val in = Input(Clock())
val test_en = Input(Bool())
val en = Input(Bool())
val out = Output(Clock())
})
def addVerilogResource(vsrc: String): Unit = {
if (Files.exists(Paths.get(vsrc)))
addPath(vsrc)
else
addResource(vsrc)
}
}
object ClockGate {
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: Option[String] = None)(implicit p: Parameters): Clock = {
val cg = Module(p(ClockGateImpl)())
name.foreach(cg.suggestName(_))
p(ClockGateModelFile).map(cg.addVerilogResource(_))
cg.io.in := in
cg.io.test_en := false.B
cg.io.en := en
cg.io.out
}
def apply[T <: ClockGate](
in: Clock,
en: Bool,
name: String)(implicit p: Parameters): Clock =
apply(in, en, Some(name))
}
// behavioral model of Integrated Clock Gating cell
class EICG_wrapper extends ClockGate
File IOBinders.scala:
package chipyard.iobinders
import chisel3._
import chisel3.reflect.DataMirror
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import org.chipsalliance.diplomacy.aop._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress, RegionType}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import tracegen.{TraceGenSystemModuleImp}
import chipyard.iocell._
import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
import testchipip.spi.{SPIChipIO}
import testchipip.boot.{CanHavePeripheryCustomBootPin}
import testchipip.soc.{CanHavePeripheryChipIdPin}
import testchipip.util.{ClockedIO}
import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
import chipyard.example.{CanHavePeripheryGCD}
import scala.reflect.{ClassTag}
object IOBinderTypes {
type IOBinderTuple = (Seq[Port[_]], Seq[IOCell])
type IOBinderFunction = (Boolean, => Any) => ModuleValue[IOBinderTuple]
}
import IOBinderTypes._
// System for instantiating binders based
// on the scala type of the Target (_not_ its IO). This avoids needing to
// duplicate harnesses (essentially test harnesses) for each target.
// IOBinders is map between string representations of traits to the desired
// IO connection behavior for tops matching that trait. We use strings to enable
// composition and overriding of IOBinders, much like how normal Keys in the config
// system are used/ At elaboration, the testharness traverses this set of functions,
// and functions which match the type of the DigitalTop are evaluated.
// You can add your own binder by adding a new (key, fn) pair, typically by using
// the OverrideIOBinder or ComposeIOBinder macros
case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](
Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)
)
abstract trait HasIOBinders extends HasChipyardPorts { this: LazyModule =>
val lazySystem: LazyModule
private val iobinders = p(IOBinders)
// Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the
// context of a LazyRawModuleImp
private val lzy = iobinders.map({ case (s,fns) => s -> fns.map(f => f(true, lazySystem)) })
private val imp = iobinders.map({ case (s,fns) => s -> fns.map(f => f(false, lazySystem.module)) })
private lazy val lzyFlattened: Map[String, IOBinderTuple] = lzy.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
private lazy val impFlattened: Map[String, IOBinderTuple] = imp.map({
case (s,ms) => s -> (ms.map(_._1).flatten, ms.map(_._2).flatten)
})
// A publicly accessible list of IO cells (useful for a floorplanning tool, for example)
val iocells = InModuleBody { (lzyFlattened.values ++ impFlattened.values).unzip._2.flatten.toBuffer }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop ports
val portMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._1 ++ impFlattened(k)._1)).toMap }
// A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells
val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap }
def ports = portMap.getWrappedValue.values.flatten.toSeq
InModuleBody {
println("IOCells generated by IOBinders:")
for ((k, v) <- iocellMap) {
if (!v.isEmpty) {
val cells = v.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" IOBinder for $k generated:")
for ((t, c) <- cells) { println(s" $c X $t") }
}
}
println()
val totals = iocells.map(_.getClass.getSimpleName).groupBy(identity).mapValues(_.size)
println(s" Total generated ${iocells.size} IOCells:")
for ((t, c) <- totals) { println(s" $c X $t") }
}
}
// Note: The parameters instance is accessible only through LazyModule
// or LazyModuleImpLike. The self-type requirement in traits like
// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder
// As a result, IOBinders only work on Modules which inherit LazyModule or
// or LazyModuleImpLike
object GetSystemParameters {
def apply(s: Any): Parameters = {
s match {
case s: LazyModule => s.p
case s: LazyModuleImpLike => s.p
case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
}
}
}
class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
case IOBinders => {
val upMap = up(IOBinders)
upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
}
})
class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((_, t) => { InModuleBody {
t match {
case system: T => fn(system)
case _ => (Nil, Nil)
}
}}): IOBinderFunction)
)
class LazyIOBinder[T](composes: Boolean, fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends IOBinder[T](
up => (if (composes) up else Nil) ++ Seq(((isLazy, t) => {
val empty = new ModuleValue[IOBinderTuple] {
def getWrappedValue: IOBinderTuple = (Nil, Nil)
}
if (isLazy) {
t match {
case system: T => fn(system)
case _ => empty
}
} else {
empty
}
}): IOBinderFunction)
)
// The "Override" binders override any previous IOBinders (lazy or concrete) defined on the same trait.
// The "Compose" binders do not override previously defined IOBinders on the same trait
// The default IOBinders evaluate only in the concrete "ModuleImp" phase of elaboration
// The "Lazy" IOBinders evaluate in the LazyModule phase, but can also generate hardware through InModuleBody
class OverrideIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](false, fn)
class ComposeIOBinder[T](fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends ConcreteIOBinder[T](true, fn)
class OverrideLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](false, fn)
class ComposeLazyIOBinder[T](fn: T => ModuleValue[IOBinderTuple])(implicit tag: ClassTag[T]) extends LazyIOBinder[T](true, fn)
case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams())
class WithGPIOCells extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) =>
gpio.pins.zipWithIndex.map({ case (pin, j) =>
val p = system.asInstanceOf[BaseSubsystem].p
val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}")
val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}")
iocell.io.o := pin.o.oval
iocell.io.oe := pin.o.oe
iocell.io.ie := pin.o.ie
pin.i.ival := iocell.io.i
pin.i.po.foreach(_ := DontCare)
iocell.io.pad <> g
(GPIOPort(() => g, i, j), iocell)
}).unzip
}).unzip
(ports2d.flatten, cells2d.flatten)
}
})
class WithGPIOPunchthrough extends OverrideIOBinder({
(system: HasPeripheryGPIO) => {
val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
io_gpio <> gpio
GPIOPinsPort(() => io_gpio, i)
}
(ports, Nil)
}
})
class WithI2CPunchthrough extends OverrideIOBinder({
(system: HasPeripheryI2C) => {
val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
io_i2c <> i2c
I2CPort(() => i2c)
}
(ports, Nil)
}
})
// DOC include start: WithUARTIOCells
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUART) => {
val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true)
val where = PBUS // TODO fix
val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
val freqMHz = bus.dtsFrequency.get / 1000000
(UARTPort(() => port, i, freqMHz.toInt), ios)
}).unzip
(ports, cells2d.flatten)
}
})
// DOC include end: WithUARTIOCells
class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
(system: HasPeripherySPI) => {
// attach resource to 1st SPI
if (system.tlSpiNodes.size > 0) ResourceBinding {
Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0))
}
InModuleBody {
val spi = system.spi
val ports = spi.zipWithIndex.map({ case (s, i) =>
val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
io_spi <> s
SPIPort(() => io_spi)
})
(ports, Nil)
}
}
})
class WithSPIFlashIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlash) => {
val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
val p = system.asInstanceOf[BaseSubsystem].p
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset)
val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset)
// DQ are bidirectional, so then need special treatment
val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>
val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")
iocell.io.o := pin.o
iocell.io.oe := pin.oe
iocell.io.ie := true.B
pin.i := iocell.io.i
iocell.io.pad <> ana
iocell
}
(SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
}).unzip
(ports, cells2d.flatten)
}
})
class WithExtInterruptIOCells extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp) => {
if (system.outer.nExtInterrupts > 0) {
val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ExtIntPort(() => port)), cells)
} else {
system.interrupts := DontCare // why do I have to drive this 0-wide wire???
(Nil, Nil)
}
}
})
// Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip
class JTAGChipIO extends Bundle {
val TCK = Input(Clock())
val TMS = Input(Bool())
val TDI = Input(Bool())
val TDO = Output(Bool())
}
// WARNING: Don't disable syncReset unless you are trying to
// get around bugs in RTL simulators
class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
(system: HasPeripheryDebug) => {
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
val clockSinkNode = system.debugOpt.map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := tlbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody { system.asInstanceOf[BaseSubsystem] match { case system: HasPeripheryDebug => {
system.debug.map({ debug =>
// We never use the PSDIO, so tie it off on-chip
system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := clockBundle.reset.asBool } }
system.debug.map { d =>
// Tie off extTrigger
d.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
// Tie off disableDebug
d.disableDebug.foreach { d => d := false.B }
// Drive JTAG on-chip IOs
d.systemjtag.map { j =>
j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool)
j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
}
Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock)
// Add IOCells for the DMI/JTAG/APB ports
val dmiTuple = debug.clockeddmi.map { d =>
val (port, cells) = IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true)
(DMIPort(() => port), cells)
}
val jtagTuple = debug.systemjtag.map { j =>
val jtag_wire = Wire(new JTAGChipIO)
j.jtag.TCK := jtag_wire.TCK
j.jtag.TMS := jtag_wire.TMS
j.jtag.TDI := jtag_wire.TDI
jtag_wire.TDO := j.jtag.TDO.data
val (port, cells) = IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
(JTAGPort(() => port), cells)
}
require(!debug.apb.isDefined)
val allTuples = (dmiTuple ++ jtagTuple).toSeq
(allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
}).getOrElse((Nil, Nil))
}}}
}
})
class WithSerialTLIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true)
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithChipIdIOCells extends OverrideIOBinder({
(system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(ChipIdPort(() => port)), cells)
}).getOrElse(Nil, Nil)
})
class WithSerialTLPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => {
val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) =>
val sys = system.asInstanceOf[BaseSubsystem]
val port = IO(chiselTypeOf(s.getWrappedValue))
port <> s.getWrappedValue
(SerialTLPort(() => port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil)
}).unzip
(ports.toSeq, cells.flatten.toSeq)
}
})
class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MemPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtMem).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MemPort] = system.mem_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MemPort(() => port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt)
}).toSeq
(ports, Nil)
}
}
})
class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveMasterAXI4MMIOPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(SBUS).fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4MMIOPort] = system.mmio_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
port.bits <> m
port.clock := clockBundle.clock
AXI4MMIOPort(() => port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i))
}).toSeq
(ports, Nil)
}
}
})
class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
(system: CanHaveSlaveAXI4Port) => {
implicit val p: Parameters = GetSystemParameters(system)
val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters())))
val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS)
clockSinkNode.map(_ := fbus.fixedClockNode)
def clockBundle = clockSinkNode.get.in.head._1
InModuleBody {
val ports: Seq[AXI4InPort] = system.l2_frontend_bus_axi4.zipWithIndex.map({ case (m, i) =>
val port = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
m <> port.bits
port.clock := clockBundle.clock
AXI4InPort(() => port, p(ExtIn).get)
}).toSeq
(ports, Nil)
}
}
})
class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryBlockDevice) => {
val ports: Seq[BlockDevicePort] = system.bdev.map({ bdev =>
val p = GetSystemParameters(system)
val bdParams = p(BlockDeviceKey).get
val port = IO(new ClockedIO(new BlockDeviceIO(bdParams))).suggestName("blockdev")
port <> bdev
BlockDevicePort(() => port, bdParams)
}).toSeq
(ports, Nil)
}
})
class WithNICIOPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryIceNIC) => {
val ports: Seq[NICPort] = system.icenicOpt.map({ n =>
val p = GetSystemParameters(system)
val port = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
port <> n
NICPort(() => port, p(NICKey).get)
}).toSeq
(ports, Nil)
}
})
class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
(system: TraceGenSystemModuleImp) => {
val success: Bool = IO(Output(Bool())).suggestName("success")
success := system.success
(Seq(SuccessPort(() => success)), Nil)
}
})
class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
(system: CanHaveTraceIO) => InModuleBody {
val ports: Option[TracePort] = system.traceIO.map { t =>
val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
trace <> t
val p = GetSystemParameters(system)
val chipyardSystem = system.asInstanceOf[ChipyardSystem]
val tiles = chipyardSystem.totalTiles.values
val viewpointBus = system.asInstanceOf[HasConfigurableTLNetworkTopology].viewpointBus
val mems = viewpointBus.unifyManagers.filter { m =>
val regionTypes = Seq(RegionType.CACHED, RegionType.TRACKED, RegionType.UNCACHED, RegionType.IDEMPOTENT)
val ignoreAddresses = Seq(
0x10000 // bootrom is handled specially
)
regionTypes.contains(m.regionType) && !ignoreAddresses.contains(m.address.map(_.base).min)
}.map { m =>
val base = m.address.map(_.base).min
val size = m.address.map(_.max).max - base + 1
(base, size)
}
val useSimDTM = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
val cfg = SpikeCosimConfig(
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0),
pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
nharts = tiles.size,
bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
has_dtm = useSimDTM,
mems = mems,
// Connect using the legacy API for firesim only
mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
)
TracePort(() => trace, cfg)
}
(ports.toSeq, Nil)
}
})
class WithCustomBootPin extends OverrideIOBinder({
(system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true)
(Seq(CustomBootPort(() => port)), cells)
}).getOrElse((Nil, Nil))
})
class WithUARTTSIPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p =>
val sys = system.asInstanceOf[BaseSubsystem]
val uart_tsi = IO(new UARTTSIIO(p.uartParams))
uart_tsi <> p
(Seq(UARTTSIPort(() => uart_tsi)), Nil)
}).getOrElse((Nil, Nil))
})
class WithTLMemPunchthrough extends OverrideIOBinder({
(system: CanHaveMasterTLMemPort) => {
val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
io_tl_mem_pins_temp <> system.mem_tl
(Seq(TLMemPort(() => io_tl_mem_pins_temp)), Nil)
}
})
class WithDontTouchPorts extends OverrideIOBinder({
(system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
})
class WithNMITiedOff extends ComposeIOBinder({
(system: HasHierarchicalElementsRootContextModuleImp) => {
system.nmi.foreach { nmi =>
nmi.rnmi := false.B
nmi.rnmi_interrupt_vector := 0.U
nmi.rnmi_exception_vector := 0.U
}
(Nil, Nil)
}
})
class WithGCDBusyPunchthrough extends OverrideIOBinder({
(system: CanHavePeripheryGCD) => system.gcd_busy.map { busy =>
val io_gcd_busy = IO(Output(Bool()))
io_gcd_busy := busy
(Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
}.getOrElse((Nil, Nil))
})
File ClockBinders.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chipyard.iobinders._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import chipyard.iocell._
// This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate
// the requested clocks. This also adds TileLink ClockDivider and ClockSelector
// blocks, which allow memory-mapped control of clock division, and clock muxing
// between the FakePLL and the slow off-chip clock
// Note: This will not simulate properly with firesim
// Unsetting enable will prevent the divider/selector from actually modifying the clock,
// while preserving the address map. Unsetting enable should only be done for RTL
// simulators (Verilator) which do not model reset properly
class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) }
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
// The order of the connections to clockSelector.clockNode configures the inputs
// of the clockSelector's clockMux. Default to using the slowClockSource,
// software should enable the PLL, then switch to the pllClockSource
clockSelector.clockNode := slowClockSource
clockSelector.clockNode := pllClockSource
val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]()
pllCtrlSink := pllCtrl.ctrlNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
slowClockSource.out.unzip._1.map { o =>
o.clock := clock_wire
o.reset := reset_wire
}
// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
// with a blackbox of whatever PLL is being integrated
val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
fake_pll.io.power := pllCtrlSink.in(0)._1.power
fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
pllClockSource.out.unzip._1.map { o =>
o.clock := fake_pll.io.clk
o.reset := reset_wire
}
(Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
// This passes all clocks through to the TestHarness
class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
// This aggregate node should do nothing
val clockGroupAggNode = ClockGroupAggregateNode("fake")
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
InModuleBody {
val reset_io = IO(Input(AsyncReset()))
require(clockGroupAggNode.out.size == 1)
val (bundle, edge) = clockGroupAggNode.out(0)
val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) =>
require(m.take.isDefined, s"""Clock ${m.name.get} has no requested frequency
|Clocks: ${edge.sink.members.map(_.name.get)}""".stripMargin)
val freq = m.take.get.freqMHz
val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
b.clock := clock_io
b.reset := reset_io
ClockPort(() => clock_io, freq)
}.toSeq
((clock_ios :+ ResetPort(() => reset_io)), Nil)
}
}
})
// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies
class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
implicit val p = GetSystemParameters(system)
val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock"))
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
clockGroupsSourceNode.out.foreach { case (bundle, edge) =>
bundle.member.data.foreach { b =>
b.clock := clock_io
b.reset := reset_io
}
}
(Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
}
}
})
class WithClockTapIOCells extends OverrideIOBinder({
(system: CanHaveClockTap) => {
system.clockTapIO.map { tap =>
val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
(Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
}.getOrElse((Nil, Nil))
}
})
| module ChipTop( // @[ChipTop.scala:33:44]
output uart_0_txd, // @[IOCell.scala:196:23]
input uart_0_rxd, // @[IOCell.scala:196:23]
input custom_boot, // @[IOCell.scala:196:23]
input jtag_TCK, // @[IOCell.scala:196:23]
input jtag_TMS, // @[IOCell.scala:196:23]
input jtag_TDI, // @[IOCell.scala:196:23]
output jtag_TDO, // @[IOCell.scala:196:23]
input reset_io, // @[ClockBinders.scala:87:24]
input clock_uncore, // @[ClockBinders.scala:95:26]
output clock_tap, // @[IOCell.scala:196:23]
output serial_tl_0_in_ready, // @[IOCell.scala:196:23]
input serial_tl_0_in_valid, // @[IOCell.scala:196:23]
input [31:0] serial_tl_0_in_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_out_ready, // @[IOCell.scala:196:23]
output serial_tl_0_out_valid, // @[IOCell.scala:196:23]
output [31:0] serial_tl_0_out_bits_phit, // @[IOCell.scala:196:23]
input serial_tl_0_clock_in // @[IOCell.scala:196:23]
);
wire _iocell_serial_tl_0_in_valid_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_31_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_30_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_29_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_28_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_27_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_26_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_25_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_24_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_23_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_22_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_21_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_20_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_19_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_18_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_17_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_16_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_15_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_14_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_13_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_12_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_11_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_10_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_9_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_8_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_7_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_6_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_5_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_4_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_3_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_2_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_1_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_in_bits_phit_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_ready_i; // @[IOCell.scala:176:23]
wire _iocell_serial_tl_0_out_bits_phit_31_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_30_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_29_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_28_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_27_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_26_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_25_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_24_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_23_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_22_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_21_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_20_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_19_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_18_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_17_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_16_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_15_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_14_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_13_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_12_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_11_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_10_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_9_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_8_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_7_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_6_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_5_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_4_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_3_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_2_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_1_pad; // @[IOCell.scala:177:24]
wire _iocell_serial_tl_0_out_bits_phit_pad; // @[IOCell.scala:177:24]
wire _gated_clock_debug_clock_gate_out; // @[ClockGate.scala:36:20]
wire _system_debug_systemjtag_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28]
wire _iocell_custom_boot_i; // @[IOCell.scala:176:23]
wire _iocell_uart_0_rxd_i; // @[IOCell.scala:176:23]
wire _system_debug_dmactive; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_in_ready; // @[ChipTop.scala:27:35]
wire _system_serial_tl_0_out_valid; // @[ChipTop.scala:27:35]
wire [31:0] _system_serial_tl_0_out_bits_phit; // @[ChipTop.scala:27:35]
wire _system_uart_0_txd; // @[ChipTop.scala:27:35]
wire uart_0_rxd_0 = uart_0_rxd; // @[ChipTop.scala:33:44]
wire jtag_TCK_0 = jtag_TCK; // @[ChipTop.scala:33:44]
wire jtag_TMS_0 = jtag_TMS; // @[ChipTop.scala:33:44]
wire jtag_TDI_0 = jtag_TDI; // @[ChipTop.scala:33:44]
wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[ChipTop.scala:33:44]
wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[ChipTop.scala:33:44]
wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[ChipTop.scala:33:44]
wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[ChipTop.scala:33:44]
wire clockGroupAggNodeOut_member_allClocks_uncore_clock = clock_uncore; // @[MixedNode.scala:542:17]
wire clockGroupAggNodeOut_member_allClocks_uncore_reset = reset_io; // @[MixedNode.scala:542:17]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroupAggNodeIn_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:551:17]
wire clockGroupAggNodeIn_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:551:17]
wire clockGroupsSourceNodeOut_member_fake_uncore_clock = 1'h0; // @[MixedNode.scala:542:17]
wire clockGroupsSourceNodeOut_member_fake_uncore_reset = 1'h0; // @[MixedNode.scala:542:17]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _system_debug_systemjtag_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _clock_tap_T; // @[IOCell.scala:248:61]
wire _iocell_jtag_TCK_io_pad_T = jtag_TCK_0; // @[IOCell.scala:248:44]
wire [31:0] _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31]
wire _iocell_serial_tl_0_clock_in_io_pad_T = serial_tl_0_clock_in_0; // @[IOCell.scala:248:44]
wire uart_0_txd_0; // @[ChipTop.scala:33:44]
wire jtag_TDO_0; // @[ChipTop.scala:33:44]
wire _clock_tap_output; // @[ChipTop.scala:33:44]
wire serial_tl_0_in_ready_0; // @[ChipTop.scala:33:44]
wire [31:0] serial_tl_0_out_bits_phit_0; // @[ChipTop.scala:33:44]
wire serial_tl_0_out_valid_0; // @[ChipTop.scala:33:44]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire _system_resetctrl_hartIsInReset_0_T = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire _system_debug_systemjtag_reset_T = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire _dmi_reset_T; // @[Periphery.scala:281:38]
wire _dmi_reset_T_1 = _dmi_reset_T; // @[Periphery.scala:280:82, :281:38]
wire dmi_reset = _dmi_reset_T_1; // @[Periphery.scala:280:82, :281:65]
wire debug_reset_syncd; // @[Periphery.scala:290:40]
wire debug_reset; // @[Periphery.scala:288:27]
wire _debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24]
assign debug_reset_syncd = ~_debug_reset_syncd_WIRE; // @[ShiftReg.scala:48:24]
assign debug_reset = debug_reset_syncd; // @[Periphery.scala:288:27, :290:40]
wire dmactiveAck; // @[ShiftReg.scala:48:24]
reg clock_en; // @[Periphery.scala:298:29]
wire _jtag_wire_TCK_T; // @[IOCell.scala:248:61]
wire jtag_wire_TCK; // @[IOBinders.scala:339:31]
wire jtag_wire_TMS; // @[IOBinders.scala:339:31]
wire jtag_wire_TDI; // @[IOBinders.scala:339:31]
wire jtag_wire_TDO; // @[IOBinders.scala:339:31]
assign jtag_wire_TCK = _jtag_wire_TCK_T; // @[IOCell.scala:248:61]
wire _iocell_jtag_TCK_io_pad_T_1 = _iocell_jtag_TCK_io_pad_T; // @[IOCell.scala:248:{44,51}]
wire _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:44]
wire _iocell_clock_tap_io_o_T_1 = _iocell_clock_tap_io_o_T; // @[IOCell.scala:248:{44,51}]
assign _clock_tap_output = _clock_tap_T; // @[IOCell.scala:248:61]
wire _iocell_serial_tl_0_clock_in_io_pad_T_1 = _iocell_serial_tl_0_clock_in_io_pad_T; // @[IOCell.scala:248:{44,51}]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_1_pad, _iocell_serial_tl_0_out_bits_phit_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_3_pad, _iocell_serial_tl_0_out_bits_phit_2_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_5_pad, _iocell_serial_tl_0_out_bits_phit_4_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_7_pad, _iocell_serial_tl_0_out_bits_phit_6_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_lo_hi = {serial_tl_0_out_bits_phit_lo_lo_hi_hi, serial_tl_0_out_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_lo_lo = {serial_tl_0_out_bits_phit_lo_lo_hi, serial_tl_0_out_bits_phit_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_9_pad, _iocell_serial_tl_0_out_bits_phit_8_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_11_pad, _iocell_serial_tl_0_out_bits_phit_10_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_hi_lo = {serial_tl_0_out_bits_phit_lo_hi_lo_hi, serial_tl_0_out_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_13_pad, _iocell_serial_tl_0_out_bits_phit_12_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_15_pad, _iocell_serial_tl_0_out_bits_phit_14_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_lo_hi_hi = {serial_tl_0_out_bits_phit_lo_hi_hi_hi, serial_tl_0_out_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_lo_hi = {serial_tl_0_out_bits_phit_lo_hi_hi, serial_tl_0_out_bits_phit_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [15:0] serial_tl_0_out_bits_phit_lo = {serial_tl_0_out_bits_phit_lo_hi, serial_tl_0_out_bits_phit_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_out_bits_phit_17_pad, _iocell_serial_tl_0_out_bits_phit_16_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_out_bits_phit_19_pad, _iocell_serial_tl_0_out_bits_phit_18_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_lo_lo = {serial_tl_0_out_bits_phit_hi_lo_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_out_bits_phit_21_pad, _iocell_serial_tl_0_out_bits_phit_20_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_out_bits_phit_23_pad, _iocell_serial_tl_0_out_bits_phit_22_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_lo_hi = {serial_tl_0_out_bits_phit_hi_lo_hi_hi, serial_tl_0_out_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_hi_lo = {serial_tl_0_out_bits_phit_hi_lo_hi, serial_tl_0_out_bits_phit_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_out_bits_phit_25_pad, _iocell_serial_tl_0_out_bits_phit_24_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_out_bits_phit_27_pad, _iocell_serial_tl_0_out_bits_phit_26_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_hi_lo = {serial_tl_0_out_bits_phit_hi_hi_lo_hi, serial_tl_0_out_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_out_bits_phit_29_pad, _iocell_serial_tl_0_out_bits_phit_28_pad}; // @[IOCell.scala:177:24, :312:31]
wire [1:0] serial_tl_0_out_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_out_bits_phit_31_pad, _iocell_serial_tl_0_out_bits_phit_30_pad}; // @[IOCell.scala:177:24, :312:31]
wire [3:0] serial_tl_0_out_bits_phit_hi_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [7:0] serial_tl_0_out_bits_phit_hi_hi = {serial_tl_0_out_bits_phit_hi_hi_hi, serial_tl_0_out_bits_phit_hi_hi_lo}; // @[IOCell.scala:312:31]
wire [15:0] serial_tl_0_out_bits_phit_hi = {serial_tl_0_out_bits_phit_hi_hi, serial_tl_0_out_bits_phit_hi_lo}; // @[IOCell.scala:312:31]
assign _serial_tl_0_out_bits_phit_T = {serial_tl_0_out_bits_phit_hi, serial_tl_0_out_bits_phit_lo}; // @[IOCell.scala:312:31]
assign serial_tl_0_out_bits_phit_0 = _serial_tl_0_out_bits_phit_T; // @[IOCell.scala:312:31]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_1_i, _iocell_serial_tl_0_in_bits_phit_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_3_i, _iocell_serial_tl_0_in_bits_phit_2_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_5_i, _iocell_serial_tl_0_in_bits_phit_4_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_7_i, _iocell_serial_tl_0_in_bits_phit_6_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_lo_hi = {system_serial_tl_0_in_bits_phit_lo_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_lo_lo = {system_serial_tl_0_in_bits_phit_lo_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_9_i, _iocell_serial_tl_0_in_bits_phit_8_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_11_i, _iocell_serial_tl_0_in_bits_phit_10_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_lo = {system_serial_tl_0_in_bits_phit_lo_hi_lo_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_13_i, _iocell_serial_tl_0_in_bits_phit_12_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_lo_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_15_i, _iocell_serial_tl_0_in_bits_phit_14_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_lo_hi_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_lo_hi = {system_serial_tl_0_in_bits_phit_lo_hi_hi, system_serial_tl_0_in_bits_phit_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [15:0] system_serial_tl_0_in_bits_phit_lo = {system_serial_tl_0_in_bits_phit_lo_hi, system_serial_tl_0_in_bits_phit_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_lo = {_iocell_serial_tl_0_in_bits_phit_17_i, _iocell_serial_tl_0_in_bits_phit_16_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_lo_hi = {_iocell_serial_tl_0_in_bits_phit_19_i, _iocell_serial_tl_0_in_bits_phit_18_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_lo = {system_serial_tl_0_in_bits_phit_hi_lo_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_lo = {_iocell_serial_tl_0_in_bits_phit_21_i, _iocell_serial_tl_0_in_bits_phit_20_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_lo_hi_hi = {_iocell_serial_tl_0_in_bits_phit_23_i, _iocell_serial_tl_0_in_bits_phit_22_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_lo_hi = {system_serial_tl_0_in_bits_phit_hi_lo_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_hi_lo = {system_serial_tl_0_in_bits_phit_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_lo = {_iocell_serial_tl_0_in_bits_phit_25_i, _iocell_serial_tl_0_in_bits_phit_24_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_lo_hi = {_iocell_serial_tl_0_in_bits_phit_27_i, _iocell_serial_tl_0_in_bits_phit_26_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_lo = {system_serial_tl_0_in_bits_phit_hi_hi_lo_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo_lo}; // @[IOCell.scala:295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_lo = {_iocell_serial_tl_0_in_bits_phit_29_i, _iocell_serial_tl_0_in_bits_phit_28_i}; // @[IOCell.scala:176:23, :295:32]
wire [1:0] system_serial_tl_0_in_bits_phit_hi_hi_hi_hi = {_iocell_serial_tl_0_in_bits_phit_31_i, _iocell_serial_tl_0_in_bits_phit_30_i}; // @[IOCell.scala:176:23, :295:32]
wire [3:0] system_serial_tl_0_in_bits_phit_hi_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [7:0] system_serial_tl_0_in_bits_phit_hi_hi = {system_serial_tl_0_in_bits_phit_hi_hi_hi, system_serial_tl_0_in_bits_phit_hi_hi_lo}; // @[IOCell.scala:295:32]
wire [15:0] system_serial_tl_0_in_bits_phit_hi = {system_serial_tl_0_in_bits_phit_hi_hi, system_serial_tl_0_in_bits_phit_hi_lo}; // @[IOCell.scala:295:32]
wire [31:0] _system_serial_tl_0_in_bits_phit_T = {system_serial_tl_0_in_bits_phit_hi, system_serial_tl_0_in_bits_phit_lo}; // @[IOCell.scala:295:32]
always @(posedge clockSinkNodeIn_clock or posedge debug_reset) begin // @[Periphery.scala:288:27]
if (debug_reset) // @[Periphery.scala:288:27]
clock_en <= 1'h1; // @[Periphery.scala:298:29]
else // @[MixedNode.scala:551:17]
clock_en <= dmactiveAck; // @[ShiftReg.scala:48:24]
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_86( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_86 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_96( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
| module BranchKillableQueue_25( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [33:0] io_enq_bits_addr, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_enq_bits_tag_match, // @[util.scala:463:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14]
input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14]
input [1:0] io_enq_bits_way_en, // @[util.scala:463:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [33:0] io_deq_bits_addr, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
output io_deq_bits_tag_match, // @[util.scala:463:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14]
output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14]
output [1:0] io_deq_bits_way_en, // @[util.scala:463:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14]
output io_empty // @[util.scala:463:14]
);
wire _out_valid_T_12; // @[util.scala:496:38]
wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22]
wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22]
wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22]
wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22]
wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22]
wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22]
wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22]
wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22]
wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22]
wire _main_io_deq_bits_is_hella; // @[util.scala:476:22]
wire _main_io_deq_bits_tag_match; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22]
wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22]
wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22]
wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22]
wire _main_io_empty; // @[util.scala:476:22]
wire [3:0] _main_io_count; // @[util.scala:476:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7]
wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7]
wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}]
wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27]
wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27]
wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7]
wire io_flush = 1'h0; // @[util.scala:458:7]
wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94]
wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59]
wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61]
wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22]
wire _io_empty_T_1; // @[util.scala:484:31]
wire [3:0] _io_count_T_1; // @[util.scala:485:31]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_bits_tag_match_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty_0; // @[util.scala:458:7]
wire [3:0] io_count; // @[util.scala:458:7]
reg [31:0] out_reg_uop_inst; // @[util.scala:477:22]
reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22]
reg out_reg_uop_is_rvc; // @[util.scala:477:22]
reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22]
reg out_reg_uop_iq_type_0; // @[util.scala:477:22]
reg out_reg_uop_iq_type_1; // @[util.scala:477:22]
reg out_reg_uop_iq_type_2; // @[util.scala:477:22]
reg out_reg_uop_iq_type_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_0; // @[util.scala:477:22]
reg out_reg_uop_fu_code_1; // @[util.scala:477:22]
reg out_reg_uop_fu_code_2; // @[util.scala:477:22]
reg out_reg_uop_fu_code_3; // @[util.scala:477:22]
reg out_reg_uop_fu_code_4; // @[util.scala:477:22]
reg out_reg_uop_fu_code_5; // @[util.scala:477:22]
reg out_reg_uop_fu_code_6; // @[util.scala:477:22]
reg out_reg_uop_fu_code_7; // @[util.scala:477:22]
reg out_reg_uop_fu_code_8; // @[util.scala:477:22]
reg out_reg_uop_fu_code_9; // @[util.scala:477:22]
reg out_reg_uop_iw_issued; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22]
reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22]
reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22]
reg out_reg_uop_dis_col_sel; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22]
reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22]
reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22]
reg out_reg_uop_is_sfb; // @[util.scala:477:22]
reg out_reg_uop_is_fence; // @[util.scala:477:22]
reg out_reg_uop_is_fencei; // @[util.scala:477:22]
reg out_reg_uop_is_sfence; // @[util.scala:477:22]
reg out_reg_uop_is_amo; // @[util.scala:477:22]
reg out_reg_uop_is_eret; // @[util.scala:477:22]
reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22]
reg out_reg_uop_is_rocc; // @[util.scala:477:22]
reg out_reg_uop_is_mov; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22]
reg out_reg_uop_edge_inst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22]
reg out_reg_uop_taken; // @[util.scala:477:22]
reg out_reg_uop_imm_rename; // @[util.scala:477:22]
reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22]
reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22]
reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22]
reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22]
reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22]
reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22]
reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22]
reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22]
reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22]
reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22]
reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22]
reg out_reg_uop_prs1_busy; // @[util.scala:477:22]
reg out_reg_uop_prs2_busy; // @[util.scala:477:22]
reg out_reg_uop_prs3_busy; // @[util.scala:477:22]
reg out_reg_uop_ppred_busy; // @[util.scala:477:22]
reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22]
reg out_reg_uop_exception; // @[util.scala:477:22]
reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22]
reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22]
reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22]
reg out_reg_uop_mem_signed; // @[util.scala:477:22]
reg out_reg_uop_uses_ldq; // @[util.scala:477:22]
reg out_reg_uop_uses_stq; // @[util.scala:477:22]
reg out_reg_uop_is_unique; // @[util.scala:477:22]
reg out_reg_uop_flush_on_commit; // @[util.scala:477:22]
reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22]
reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22]
reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22]
reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22]
reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22]
reg out_reg_uop_frs3_en; // @[util.scala:477:22]
reg out_reg_uop_fcn_dw; // @[util.scala:477:22]
reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22]
reg out_reg_uop_fp_val; // @[util.scala:477:22]
reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22]
reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22]
reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22]
reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22]
reg out_reg_uop_bp_debug_if; // @[util.scala:477:22]
reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22]
reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22]
reg [33:0] out_reg_addr; // @[util.scala:477:22]
assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22]
reg [63:0] out_reg_data; // @[util.scala:477:22]
assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22]
reg out_reg_is_hella; // @[util.scala:477:22]
assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22]
reg out_reg_tag_match; // @[util.scala:477:22]
assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22]
assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22]
reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22]
assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22]
reg [1:0] out_reg_way_en; // @[util.scala:477:22]
assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22]
reg [4:0] out_reg_sdq_id; // @[util.scala:477:22]
assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22]
reg out_valid; // @[util.scala:478:28]
assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28]
wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28]
reg [31:0] out_uop_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22]
reg [31:0] out_uop_debug_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22]
wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22]
reg out_uop_is_rvc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22]
reg [33:0] out_uop_debug_pc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22]
wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_0; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_1; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_2; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22]
reg out_uop_iq_type_3; // @[util.scala:479:22]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_0; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_1; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_2; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_3; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_4; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_5; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_6; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_7; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_8; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22]
reg out_uop_fu_code_9; // @[util.scala:479:22]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22]
wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22]
wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22]
reg out_uop_dis_col_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22]
wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_mask; // @[util.scala:479:22]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22]
wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22]
reg [1:0] out_uop_br_tag; // @[util.scala:479:22]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_br_type; // @[util.scala:479:22]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfb; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22]
reg out_uop_is_fence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22]
reg out_uop_is_fencei; // @[util.scala:479:22]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22]
reg out_uop_is_sfence; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22]
reg out_uop_is_amo; // @[util.scala:479:22]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22]
reg out_uop_is_eret; // @[util.scala:479:22]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22]
reg out_uop_is_sys_pc2epc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22]
reg out_uop_is_rocc; // @[util.scala:479:22]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22]
reg out_uop_is_mov; // @[util.scala:479:22]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22]
reg out_uop_edge_inst; // @[util.scala:479:22]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22]
wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pc_lob; // @[util.scala:479:22]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22]
reg out_uop_taken; // @[util.scala:479:22]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22]
wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22]
reg out_uop_imm_rename; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22]
wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_imm_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_pimm; // @[util.scala:479:22]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22]
reg [19:0] out_uop_imm_packed; // @[util.scala:479:22]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22]
wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_op1_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_op2_sel; // @[util.scala:479:22]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wen; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_toint; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_fma; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_div; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22]
reg out_uop_fp_ctrl_vec; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_rob_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_stq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs1; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs2; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_prs3; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22]
reg [3:0] out_uop_ppred; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22]
wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22]
reg out_uop_prs1_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs2_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22]
reg out_uop_prs3_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22]
reg out_uop_ppred_busy; // @[util.scala:479:22]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22]
wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22]
reg out_uop_exception; // @[util.scala:479:22]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22]
wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22]
reg [63:0] out_uop_exc_cause; // @[util.scala:479:22]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22]
wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_mem_size; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22]
reg out_uop_mem_signed; // @[util.scala:479:22]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22]
wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22]
reg out_uop_uses_ldq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22]
reg out_uop_uses_stq; // @[util.scala:479:22]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22]
wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22]
reg out_uop_is_unique; // @[util.scala:479:22]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22]
wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22]
reg out_uop_flush_on_commit; // @[util.scala:479:22]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22]
wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22]
reg out_uop_ldst_is_rs1; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22]
wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_ldst; // @[util.scala:479:22]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs1; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs2; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22]
reg [5:0] out_uop_lrs3; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22]
wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22]
reg out_uop_frs3_en; // @[util.scala:479:22]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22]
wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22]
reg out_uop_fcn_dw; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22]
wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22]
reg [4:0] out_uop_fcn_op; // @[util.scala:479:22]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22]
wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22]
reg out_uop_fp_val; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22]
wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_fp_rm; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22]
reg [1:0] out_uop_fp_typ; // @[util.scala:479:22]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22]
wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_pf_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ae_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22]
reg out_uop_xcpt_ma_if; // @[util.scala:479:22]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_debug_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22]
reg out_uop_bp_xcpt_if; // @[util.scala:479:22]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22]
wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22]
reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22]
wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22]
wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34]
assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31]
wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31]
assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31]
assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31]
wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23]
assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}]
wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35]
wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}]
wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25]
wire out_uop_out_1_iq_type_0; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_1; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_2; // @[util.scala:104:23]
wire out_uop_out_1_iq_type_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_0; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_1; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_2; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_3; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_4; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_5; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_6; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_7; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_8; // @[util.scala:104:23]
wire out_uop_out_1_fu_code_9; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23]
wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23]
wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23]
wire out_uop_out_1_is_rvc; // @[util.scala:104:23]
wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23]
wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23]
wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23]
wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23]
wire out_uop_out_1_is_sfb; // @[util.scala:104:23]
wire out_uop_out_1_is_fence; // @[util.scala:104:23]
wire out_uop_out_1_is_fencei; // @[util.scala:104:23]
wire out_uop_out_1_is_sfence; // @[util.scala:104:23]
wire out_uop_out_1_is_amo; // @[util.scala:104:23]
wire out_uop_out_1_is_eret; // @[util.scala:104:23]
wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23]
wire out_uop_out_1_is_rocc; // @[util.scala:104:23]
wire out_uop_out_1_is_mov; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23]
wire out_uop_out_1_edge_inst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23]
wire out_uop_out_1_taken; // @[util.scala:104:23]
wire out_uop_out_1_imm_rename; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23]
wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23]
wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23]
wire out_uop_out_1_prs1_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs2_busy; // @[util.scala:104:23]
wire out_uop_out_1_prs3_busy; // @[util.scala:104:23]
wire out_uop_out_1_ppred_busy; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23]
wire out_uop_out_1_exception; // @[util.scala:104:23]
wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23]
wire out_uop_out_1_mem_signed; // @[util.scala:104:23]
wire out_uop_out_1_uses_ldq; // @[util.scala:104:23]
wire out_uop_out_1_uses_stq; // @[util.scala:104:23]
wire out_uop_out_1_is_unique; // @[util.scala:104:23]
wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23]
wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23]
wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23]
wire out_uop_out_1_frs3_en; // @[util.scala:104:23]
wire out_uop_out_1_fcn_dw; // @[util.scala:104:23]
wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23]
wire out_uop_out_1_fp_val; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23]
wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23]
wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23]
wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23]
wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23]
assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
always @(posedge clock) begin // @[util.scala:458:7]
if (main_io_deq_ready) begin // @[util.scala:495:23]
out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22]
out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22]
out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22]
out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22]
out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22]
out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22]
out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22]
out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22]
out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22]
out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22]
out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22]
out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22]
out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22]
out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22]
out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22]
out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22]
out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22]
out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22]
out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22]
out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22]
out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22]
out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22]
out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22]
out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22]
out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22]
out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22]
out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22]
out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22]
out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22]
out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22]
out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22]
out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22]
out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22]
out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22]
out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22]
out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22]
out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22]
out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22]
out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22]
out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22]
out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22]
out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22]
end
out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15]
if (reset) // @[util.scala:458:7]
out_valid <= 1'h0; // @[util.scala:478:28]
else // @[util.scala:458:7]
out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}]
always @(posedge)
BranchKillableQueue_24 main ( // @[util.scala:476:22]
.clock (clock),
.reset (reset),
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[util.scala:458:7]
.io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7]
.io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7]
.io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7]
.io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7]
.io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7]
.io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7]
.io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7]
.io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7]
.io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7]
.io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7]
.io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7]
.io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7]
.io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7]
.io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7]
.io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7]
.io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7]
.io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7]
.io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7]
.io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7]
.io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7]
.io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7]
.io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7]
.io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7]
.io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7]
.io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7]
.io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7]
.io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7]
.io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7]
.io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7]
.io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7]
.io_deq_ready (main_io_deq_ready), // @[util.scala:495:23]
.io_deq_valid (_out_valid_T_12),
.io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst),
.io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst),
.io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc),
.io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc),
.io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0),
.io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1),
.io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2),
.io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3),
.io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0),
.io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1),
.io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2),
.io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3),
.io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4),
.io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5),
.io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6),
.io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7),
.io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8),
.io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9),
.io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued),
.io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen),
.io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen),
.io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child),
.io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child),
.io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint),
.io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint),
.io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint),
.io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel),
.io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask),
.io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag),
.io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type),
.io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb),
.io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence),
.io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei),
.io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence),
.io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo),
.io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret),
.io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc),
.io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc),
.io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov),
.io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx),
.io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst),
.io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob),
.io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken),
.io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename),
.io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel),
.io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm),
.io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed),
.io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel),
.io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel),
.io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst),
.io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen),
.io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1),
.io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2),
.io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3),
.io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12),
.io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23),
.io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn),
.io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut),
.io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint),
.io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint),
.io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe),
.io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma),
.io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div),
.io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt),
.io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags),
.io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec),
.io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx),
.io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx),
.io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx),
.io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx),
.io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst),
.io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1),
.io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2),
.io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3),
.io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred),
.io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy),
.io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy),
.io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy),
.io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy),
.io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst),
.io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception),
.io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause),
.io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd),
.io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size),
.io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed),
.io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq),
.io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq),
.io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique),
.io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit),
.io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd),
.io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1),
.io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst),
.io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1),
.io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2),
.io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3),
.io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype),
.io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype),
.io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype),
.io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en),
.io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw),
.io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op),
.io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val),
.io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm),
.io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ),
.io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if),
.io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if),
.io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if),
.io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if),
.io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if),
.io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc),
.io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc),
.io_deq_bits_addr (_main_io_deq_bits_addr),
.io_deq_bits_data (_main_io_deq_bits_data),
.io_deq_bits_is_hella (_main_io_deq_bits_is_hella),
.io_deq_bits_tag_match (_main_io_deq_bits_tag_match),
.io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state),
.io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag),
.io_deq_bits_way_en (_main_io_deq_bits_way_en),
.io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id),
.io_empty (_main_io_empty),
.io_count (_main_io_count)
); // @[util.scala:476:22]
assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22]
assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22]
assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7]
assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7]
assign io_empty = io_empty_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_28( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File BootROM.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resources.{Resource, SimpleDevice}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
import java.nio.ByteBuffer
import java.nio.file.{Files, Paths}
/** Size, location and contents of the boot rom. */
case class BootROMParams(
address: BigInt = 0x10000,
size: Int = 0x10000,
hang: BigInt = 0x10040, // The hang parameter is used as the power-on reset vector
contentFileName: String)
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = List(AddressSet(base, size-1)),
resources = resources,
regionType = RegionType.UNCACHED,
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
fifoId = Some(0))),
beatBytes = beatBytes)))
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val contents = contentsDelayed
val wrapSize = 1 << log2Ceil(contents.size)
require (wrapSize <= size)
val (in, edge) = node.in(0)
val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
val rom = VecInit(bigs.map(_.U((8*beatBytes).W)))
in.d.valid := in.a.valid
in.a.ready := in.d.ready
val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
val high = if (wrapSize == size) 0.U else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, 0.U, rom(index)))
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
case class BootROMLocated(loc: HierarchicalLocation) extends Field[Option[BootROMParams]](None)
object BootROM {
/** BootROM.attach not only instantiates a TLROM and attaches it to the tilelink interconnect
* at a configurable location, but also drives the tiles' reset vectors to point
* at its 'hang' address parameter value.
*/
def attach(params: BootROMParams, subsystem: BaseSubsystem with HasHierarchicalElements with HasTileInputConstants, where: TLBusWrapperLocation)
(implicit p: Parameters): TLROM = {
val tlbus = subsystem.locateTLBusWrapper(where)
val bootROMDomainWrapper = tlbus.generateSynchronousDomain("BootROM").suggestName("bootrom_domain")
val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
lazy val contents = {
val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
val rom = ByteBuffer.wrap(romdata)
rom.array() ++ subsystem.dtb.contents
}
val bootrom = bootROMDomainWrapper {
LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
}
bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus, Some("BootROM")) := _ }
// Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
InModuleBody {
val reset_vector_source = bootROMResetVectorSourceNode.bundle
require(reset_vector_source.getWidth >= params.hang.bitLength,
s"BootROM defined with a reset vector (${params.hang})too large for physical address space (${reset_vector_source.getWidth})")
bootROMResetVectorSourceNode.bundle := params.hang.U
}
bootrom
}
}
| module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire [511:0][63:0] _GEN =
'{64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
64'h0,
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64'h100000002000000,
64'h300000099010000,
64'h400000003000000,
64'h64656C62,
64'h6173696462010000,
64'h900000003000000,
64'h10000000008,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h3066697468,
64'h2C6263751B000000,
64'hA00000003000000,
64'h66697468,
64'h100000002000000,
64'h200000002000000,
64'h400000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h30000000074656B,
64'h636F72785F73627A,
64'h5F62627A5F61627A,
64'h5F68667A5F6D7068,
64'h697A5F6965636E65,
64'h66697A5F72736369,
64'h7A62636466616D69,
64'h3436767232010000,
64'h3800000003000000,
64'h2E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h800000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'h1000000B2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h200000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h80000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369,
64'h72003074656B636F,
64'h722C657669666973,
64'h1B00000015000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'h380C000060020000,
64'h10000000,
64'h1100000028000000,
64'h700C000038000000,
64'hD00E0000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5350300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
TLMonitor_50 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_in_d_ready),
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (auto_in_a_valid),
.io_in_d_bits_size (auto_in_a_bits_size),
.io_in_d_bits_source (auto_in_a_bits_source)
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_d_ready; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_a_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_a_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_a_bits_source; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = (|(auto_in_a_bits_address[15:12])) ? 64'h0 : _GEN[auto_in_a_bits_address[11:3]]; // @[BootROM.scala:41:9, :55:34, :56:64, :57:{47,53}]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_231( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File TilelinkAdapters.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val flit = Decoupled(new IngressFlit(flitWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
def requestOH: Seq[Bool]
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.flit.valid := protocol.valid
protocol.ready := io.flit.ready && (is_body || !has_body)
io.flit.bits.head := head && !is_body
io.flit.bits.tail := tail && (is_body || !has_body)
io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) =>
r -> idToEgress(i).U
})
io.flit.bits.payload := Mux(is_body, body, const)
when (io.flit.fire && io.flit.bits.head) { is_body := true.B }
when (io.flit.fire && io.flit.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper {
val flitWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val flit = Flipped(Decoupled(new EgressFlit(flitWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg)
io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.flit.bits.payload, body_fields)
when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload }
when (io.flit.fire && io.flit.bits.tail) { is_const := true.B }
}
trait HasAddressDecoder {
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
val edgeIn: TLEdge
val edgesOut: Seq[TLEdge]
lazy val reacheableIO = edgesOut.map { mp =>
edgeIn.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
}.toVector
lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) =>
reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector
def outputPortFn(connectIO: Seq[Boolean]) = {
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectIO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_))
}
}
class TLAToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToAEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val connectAIO = reacheableIO
lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) =>
connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) {
io.protocol <> protocol
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToBIngress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
}
class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToCEgress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder {
has_body := edgeIn.hasData(protocol.bits)
lazy val connectCIO = releaseIO
lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map {
case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address))
}
q.io.enq <> io.protocol
q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U
}
class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) {
io.protocol <> protocol
}
class TLDToNoC(
edgeOut: TLEdge,
edgesIn: Seq[TLEdge],
bundle: TLBundleParameters,
masterToDIngress: Int => Int,
sourceStart: Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) {
has_body := edgeOut.hasData(protocol.bits)
lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) }
q.io.enq <> io.protocol
q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U
}
class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p)
{
io.protocol <> protocol
io.protocol.bits.source := trim(protocol.bits.source, sourceSize)
}
class TLEToNoC(
val edgeIn: TLEdge,
val edgesOut: Seq[TLEdge],
bundle: TLBundleParameters,
slaveToEEgress: Int => Int
)(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) {
has_body := edgeIn.hasData(protocol.bits)
lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) }
q.io.enq <> io.protocol
}
class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) {
io.protocol <> protocol
io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize)
}
| module TLBFromNoC_1( // @[TilelinkAdapters.scala:145:7]
input clock, // @[TilelinkAdapters.scala:145:7]
input reset, // @[TilelinkAdapters.scala:145:7]
input io_protocol_ready, // @[TilelinkAdapters.scala:56:14]
output io_protocol_valid, // @[TilelinkAdapters.scala:56:14]
output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14]
output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14]
output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14]
output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14]
output [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:56:14]
output [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:56:14]
output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14]
output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14]
output io_flit_ready, // @[TilelinkAdapters.scala:56:14]
input io_flit_valid, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14]
input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14]
input [72:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14]
);
reg is_const; // @[TilelinkAdapters.scala:68:25]
reg [46:0] const_reg; // @[TilelinkAdapters.scala:69:22]
wire [46:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[46:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18]
wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}]
wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35]
wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:145:7]
if (reset) // @[TilelinkAdapters.scala:145:7]
is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :145:7]
else // @[TilelinkAdapters.scala:145:7]
is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35]
if (_GEN_0) // @[TilelinkAdapters.scala:84:22]
const_reg <= io_flit_bits_payload[46:0]; // @[TilelinkAdapters.scala:56:14, :69:22]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File tracegen.scala:
package boom.v4.lsu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, BundleBridgeSource}
import freechips.rocketchip.prci.{SynchronousCrossing, ClockCrossingType}
import freechips.rocketchip.groundtest._
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.subsystem._
import boom.v4.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
import boom.v4.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
import freechips.rocketchip.prci.ClockSinkParameters
class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
with MemoryOpConstants {
val io = IO(new Bundle {
val lsu = Flipped(new LSUCoreIO)
val tracegen = Flipped(new HellaCacheIO)
})
io.lsu := DontCare
io.lsu.tsc_reg := 0.U(1.W)
val rob_sz = numRobEntries
val rob = Reg(Vec(rob_sz, new HellaCacheReq))
val rob_respd = RegInit(VecInit((~(0.U(rob_sz.W))).asBools))
val rob_uop = Reg(Vec(rob_sz, new MicroOp))
val rob_bsy = RegInit(VecInit(0.U(rob_sz.W).asBools))
val rob_head = RegInit(0.U(log2Up(rob_sz).W))
val rob_tail = RegInit(0.U(log2Up(rob_sz).W))
val rob_wait_till_empty = RegInit(false.B)
val ready_for_amo = rob_tail === rob_head && io.lsu.fencei_rdy
when (ready_for_amo) {
rob_wait_till_empty := false.B
}
def WrapInc(idx: UInt, max: Int): UInt = {
Mux(idx === (max-1).U, 0.U, idx + 1.U)
}
io.tracegen := DontCare
io.tracegen.req.ready := (!rob_bsy(rob_tail) &&
!rob_wait_till_empty &&
(ready_for_amo || !(isAMO(io.tracegen.req.bits.cmd) || io.tracegen.req.bits.cmd === M_XLR || io.tracegen.req.bits.cmd === M_XSC)) &&
(WrapInc(rob_tail, rob_sz) =/= rob_head) &&
!(io.lsu.ldq_full(0) && isRead(io.tracegen.req.bits.cmd)) &&
!(io.lsu.stq_full(0) && isWrite(io.tracegen.req.bits.cmd))
)
val tracegen_uop = WireInit((0.U).asTypeOf(new MicroOp))
tracegen_uop.uses_ldq := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd)
tracegen_uop.uses_stq := isWrite(io.tracegen.req.bits.cmd)
tracegen_uop.rob_idx := rob_tail
tracegen_uop.debug_inst := io.tracegen.req.bits.tag
tracegen_uop.mem_size := io.tracegen.req.bits.size
tracegen_uop.mem_cmd := io.tracegen.req.bits.cmd
tracegen_uop.mem_signed := io.tracegen.req.bits.signed
tracegen_uop.ldq_idx := io.lsu.dis_ldq_idx(0)
tracegen_uop.stq_idx := io.lsu.dis_stq_idx(0)
tracegen_uop.is_amo := isAMO(io.tracegen.req.bits.cmd) || io.tracegen.req.bits.cmd === M_XSC
tracegen_uop.uses_ldq := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd)
tracegen_uop.uses_stq := isWrite(io.tracegen.req.bits.cmd)
io.lsu.dis_uops(0).valid := io.tracegen.req.fire
io.lsu.dis_uops(0).bits := tracegen_uop
when (io.tracegen.req.fire) {
rob_tail := WrapInc(rob_tail, rob_sz)
rob_bsy(rob_tail) := true.B
rob_uop(rob_tail) := tracegen_uop
rob_respd(rob_tail) := false.B
rob(rob_tail) := io.tracegen.req.bits
when (
isAMO(io.tracegen.req.bits.cmd) ||
io.tracegen.req.bits.cmd === M_XLR ||
io.tracegen.req.bits.cmd === M_XSC
) {
rob_wait_till_empty := true.B
}
}
io.lsu.dgen(1).valid := false.B
io.lsu.dgen(1).bits := DontCare
io.lsu.commit.valids(0) := (!rob_bsy(rob_head) && rob_head =/= rob_tail && rob_respd(rob_head))
io.lsu.commit.uops(0) := rob_uop(rob_head)
io.lsu.commit.fflags := DontCare
when (io.lsu.commit.valids(0)) {
rob_head := WrapInc(rob_head, rob_sz)
}
when (io.lsu.clr_bsy(0).valid) {
rob_bsy(io.lsu.clr_bsy(0).bits) := false.B
}
when (io.lsu.clr_unsafe(0).valid && rob(io.lsu.clr_unsafe(0).bits).cmd =/= M_XLR) {
rob_bsy(io.lsu.clr_unsafe(0).bits) := false.B
}
when (io.lsu.iresp(0).valid) {
rob_bsy(io.lsu.iresp(0).bits.uop.rob_idx) := false.B
}
assert(!io.lsu.lxcpt.valid)
io.lsu.agen(0).valid := ShiftRegister(io.tracegen.req.fire, 2)
io.lsu.agen(0).bits := DontCare
io.lsu.agen(0).bits.uop := ShiftRegister(tracegen_uop, 2)
io.lsu.agen(0).bits.data := ShiftRegister(io.tracegen.req.bits.addr, 2)
io.lsu.dgen(0).valid := ShiftRegister(io.tracegen.req.fire && tracegen_uop.uses_stq, 2)
io.lsu.dgen(0).bits := DontCare
io.lsu.dgen(0).bits.uop := ShiftRegister(tracegen_uop, 2)
io.lsu.dgen(0).bits.data := ShiftRegister(io.tracegen.req.bits.data, 2)
io.tracegen.resp.valid := io.lsu.iresp(0).valid
io.tracegen.resp.bits := DontCare
io.tracegen.resp.bits.tag := io.lsu.iresp(0).bits.uop.debug_inst
io.tracegen.resp.bits.size := io.lsu.iresp(0).bits.uop.mem_size
io.tracegen.resp.bits.data := io.lsu.iresp(0).bits.data
val store_resp_idx = PriorityEncoder((0 until rob_sz) map {i =>
!rob_respd(i) && isWrite(rob(i).cmd)
})
val can_do_store_resp = ~rob_respd(store_resp_idx) && isWrite(rob(store_resp_idx).cmd) && !isRead(rob(store_resp_idx).cmd)
when (can_do_store_resp && !io.lsu.iresp(0).valid) {
rob_respd(store_resp_idx) := true.B
io.tracegen.resp.valid := true.B
io.tracegen.resp.bits.tag := rob(store_resp_idx).tag
}
when (io.lsu.iresp(0).valid) {
rob_respd(io.lsu.iresp(0).bits.uop.rob_idx) := true.B
}
io.lsu.exception := false.B
io.lsu.fence_dmem := false.B
io.lsu.rob_pnr_idx := rob_tail
io.lsu.commit_load_at_rob_head := false.B
io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.v4.exu.BrUpdateMasks)
io.lsu.brupdate.b2.uop := DontCare
io.lsu.brupdate.b2.mispredict := false.B
io.lsu.brupdate.b2.taken := false.B
io.lsu.brupdate.b2.cfi_type := 0.U
io.lsu.brupdate.b2.pc_sel := 0.U
io.lsu.brupdate.b2.jalr_target := 0.U
io.lsu.brupdate.b2.target_offset := 0.S(2.W)
io.lsu.rob_head_idx := rob_head
io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy
io.lsu.mcontext := 0.U(1.W)
io.lsu.scontext := 0.U(1.W)
}
case class BoomTraceGenTileAttachParams(
tileParams: BoomTraceGenParams,
crossingParams: HierarchicalElementCrossingParamsLike
) extends CanAttachTile {
type TileType = BoomTraceGenTile
val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams)
}
case class BoomTraceGenParams(
wordBits: Int,
addrBits: Int,
addrBag: List[BigInt],
maxRequests: Int,
memStart: BigInt,
numGens: Int,
dcache: Option[DCacheParams] = Some(DCacheParams()),
tileId: Int = 0
) extends InstantiableTileParams[BoomTraceGenTile]
{
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = {
new BoomTraceGenTile(this, crossing, lookup)
}
val core = RocketCoreParams(nPMPs = 0) //TODO remove this
val btb = None
val icache = Some(ICacheParams())
val beuAddr = None
val blockerCtrlAddr = None
val name = None
val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, tileId)
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
val baseName = "boom_l1_tracegen"
val uniqueName = s"${baseName}_$tileId"
}
class BoomTraceGenTile private(
val params: BoomTraceGenParams,
crossing: ClockCrossingType,
lookup: LookupByHartIdImpl,
q: Parameters) extends BaseTile(params, crossing, lookup, q)
with SinksExternalInterrupts
with SourcesExternalNotifications
{
def this(params: BoomTraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil)
val intOutwardNode = None
val slaveNode: TLInwardNode = TLIdentityNode()
val statusNode = BundleBridgeSource(() => new GroundTestStatus)
val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
dcache=params.dcache,
core=BoomCoreParams(nPMPs=0, numLdqEntries=16, numStqEntries=16, useVM=false))))
val dcache = LazyModule(new BoomNonBlockingDCache(tileId)(boom_params))
val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node
override lazy val module = new BoomTraceGenTileModuleImp(this)
}
class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
extends BaseTileModuleImp(outer){
val status = outer.statusNode.bundle
val halt_and_catch_fire = None
val tracegen = Module(new TraceGenerator(outer.params.traceParams))
tracegen.io.hartid := outer.hartIdSinkNode.bundle
val ptw = Module(new DummyPTW(1))
val lsu = Module(new LSU()(outer.boom_params, outer.dcache.module.edge))
val boom_shim = Module(new BoomLSUShim()(outer.boom_params))
ptw.io.requestors.head <> lsu.io.ptw
outer.dcache.module.io.lsu <> lsu.io.dmem
boom_shim.io.tracegen <> tracegen.io.mem
tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered
boom_shim.io.lsu <> lsu.io.core
// Normally the PTW would use this port
lsu.io.hellacache := DontCare
lsu.io.hellacache.req.valid := false.B
outer.reportCease(Some(tracegen.io.finished))
outer.reportHalt(Some(tracegen.io.timeout))
outer.reportWFI(None)
status.timeout.valid := tracegen.io.timeout
status.timeout.bits := 0.U
status.error.valid := false.B
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.tileId}: request timed out")
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
| module BoomLSUShim_1( // @[tracegen.scala:19:7]
input clock, // @[tracegen.scala:19:7]
input reset, // @[tracegen.scala:19:7]
output io_lsu_agen_0_valid, // @[tracegen.scala:21:14]
output [31:0] io_lsu_agen_0_bits_uop_debug_inst, // @[tracegen.scala:21:14]
output io_lsu_agen_0_bits_uop_is_amo, // @[tracegen.scala:21:14]
output [4:0] io_lsu_agen_0_bits_uop_rob_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_agen_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_agen_0_bits_uop_stq_idx, // @[tracegen.scala:21:14]
output [4:0] io_lsu_agen_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14]
output io_lsu_agen_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14]
output io_lsu_agen_0_bits_uop_uses_stq, // @[tracegen.scala:21:14]
output [63:0] io_lsu_agen_0_bits_data, // @[tracegen.scala:21:14]
output io_lsu_dgen_0_valid, // @[tracegen.scala:21:14]
output [31:0] io_lsu_dgen_0_bits_uop_debug_inst, // @[tracegen.scala:21:14]
output io_lsu_dgen_0_bits_uop_is_amo, // @[tracegen.scala:21:14]
output [4:0] io_lsu_dgen_0_bits_uop_rob_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_dgen_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_dgen_0_bits_uop_stq_idx, // @[tracegen.scala:21:14]
output [4:0] io_lsu_dgen_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14]
output io_lsu_dgen_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14]
output io_lsu_dgen_0_bits_uop_uses_stq, // @[tracegen.scala:21:14]
output [63:0] io_lsu_dgen_0_bits_data, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_valid, // @[tracegen.scala:21:14]
input [31:0] io_lsu_iwakeups_0_bits_uop_inst, // @[tracegen.scala:21:14]
input [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_rvc, // @[tracegen.scala:21:14]
input [33:0] io_lsu_iwakeups_0_bits_uop_debug_pc, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_issued, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iwakeups_0_bits_uop_br_mask, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_br_tag, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iwakeups_0_bits_uop_br_type, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_sfb, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_fence, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_fencei, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_sfence, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_amo, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_eret, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_rocc, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_mov, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iwakeups_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_edge_inst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_taken, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_imm_rename, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iwakeups_0_bits_uop_pimm, // @[tracegen.scala:21:14]
input [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iwakeups_0_bits_uop_rob_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_pdst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_prs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_prs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_prs3, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iwakeups_0_bits_uop_ppred, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_exception, // @[tracegen.scala:21:14]
input [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_mem_size, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_mem_signed, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_uses_stq, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_is_unique, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_ldst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_lrs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_lrs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iwakeups_0_bits_uop_lrs3, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_frs3_en, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_fp_val, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_bypassable, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_speculative_mask, // @[tracegen.scala:21:14]
input io_lsu_iwakeups_0_bits_rebusy, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_valid, // @[tracegen.scala:21:14]
input [31:0] io_lsu_iresp_0_bits_uop_inst, // @[tracegen.scala:21:14]
input [31:0] io_lsu_iresp_0_bits_uop_debug_inst, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_rvc, // @[tracegen.scala:21:14]
input [33:0] io_lsu_iresp_0_bits_uop_debug_pc, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_issued, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iresp_0_bits_uop_br_mask, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_br_tag, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iresp_0_bits_uop_br_type, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_sfb, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_fence, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_fencei, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_sfence, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_amo, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_eret, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_rocc, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_mov, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iresp_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_edge_inst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_pc_lob, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_taken, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_imm_rename, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iresp_0_bits_uop_imm_sel, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iresp_0_bits_uop_pimm, // @[tracegen.scala:21:14]
input [19:0] io_lsu_iresp_0_bits_uop_imm_packed, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_op1_sel, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iresp_0_bits_uop_op2_sel, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iresp_0_bits_uop_rob_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iresp_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iresp_0_bits_uop_stq_idx, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_pdst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_prs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_prs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_prs3, // @[tracegen.scala:21:14]
input [3:0] io_lsu_iresp_0_bits_uop_ppred, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_exception, // @[tracegen.scala:21:14]
input [63:0] io_lsu_iresp_0_bits_uop_exc_cause, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iresp_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_mem_size, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_mem_signed, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_uses_stq, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_is_unique, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iresp_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_ldst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_lrs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_lrs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_iresp_0_bits_uop_lrs3, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_frs3_en, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14]
input [4:0] io_lsu_iresp_0_bits_uop_fcn_op, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_fp_val, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iresp_0_bits_uop_fp_rm, // @[tracegen.scala:21:14]
input [1:0] io_lsu_iresp_0_bits_uop_fp_typ, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14]
input io_lsu_iresp_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14]
input [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14]
input [63:0] io_lsu_iresp_0_bits_data, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_valid, // @[tracegen.scala:21:14]
input [31:0] io_lsu_fresp_0_bits_uop_inst, // @[tracegen.scala:21:14]
input [31:0] io_lsu_fresp_0_bits_uop_debug_inst, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_rvc, // @[tracegen.scala:21:14]
input [33:0] io_lsu_fresp_0_bits_uop_debug_pc, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_issued, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14]
input [3:0] io_lsu_fresp_0_bits_uop_br_mask, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_br_tag, // @[tracegen.scala:21:14]
input [3:0] io_lsu_fresp_0_bits_uop_br_type, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_sfb, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_fence, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_fencei, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_sfence, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_amo, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_eret, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_rocc, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_mov, // @[tracegen.scala:21:14]
input [3:0] io_lsu_fresp_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_edge_inst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_pc_lob, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_taken, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_imm_rename, // @[tracegen.scala:21:14]
input [2:0] io_lsu_fresp_0_bits_uop_imm_sel, // @[tracegen.scala:21:14]
input [4:0] io_lsu_fresp_0_bits_uop_pimm, // @[tracegen.scala:21:14]
input [19:0] io_lsu_fresp_0_bits_uop_imm_packed, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_op1_sel, // @[tracegen.scala:21:14]
input [2:0] io_lsu_fresp_0_bits_uop_op2_sel, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14]
input [4:0] io_lsu_fresp_0_bits_uop_rob_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_fresp_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_fresp_0_bits_uop_stq_idx, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_pdst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_prs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_prs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_prs3, // @[tracegen.scala:21:14]
input [3:0] io_lsu_fresp_0_bits_uop_ppred, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_exception, // @[tracegen.scala:21:14]
input [63:0] io_lsu_fresp_0_bits_uop_exc_cause, // @[tracegen.scala:21:14]
input [4:0] io_lsu_fresp_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_mem_size, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_mem_signed, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_uses_stq, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_is_unique, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14]
input [2:0] io_lsu_fresp_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_ldst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_lrs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_lrs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_fresp_0_bits_uop_lrs3, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_frs3_en, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14]
input [4:0] io_lsu_fresp_0_bits_uop_fcn_op, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_fp_val, // @[tracegen.scala:21:14]
input [2:0] io_lsu_fresp_0_bits_uop_fp_rm, // @[tracegen.scala:21:14]
input [1:0] io_lsu_fresp_0_bits_uop_fp_typ, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14]
input io_lsu_fresp_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14]
input [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14]
input [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14]
input [63:0] io_lsu_fresp_0_bits_data, // @[tracegen.scala:21:14]
output io_lsu_dis_uops_0_valid, // @[tracegen.scala:21:14]
output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[tracegen.scala:21:14]
output io_lsu_dis_uops_0_bits_is_amo, // @[tracegen.scala:21:14]
output [4:0] io_lsu_dis_uops_0_bits_rob_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_dis_uops_0_bits_stq_idx, // @[tracegen.scala:21:14]
output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[tracegen.scala:21:14]
output io_lsu_dis_uops_0_bits_uses_ldq, // @[tracegen.scala:21:14]
output io_lsu_dis_uops_0_bits_uses_stq, // @[tracegen.scala:21:14]
input [3:0] io_lsu_dis_ldq_idx_0, // @[tracegen.scala:21:14]
input [3:0] io_lsu_dis_stq_idx_0, // @[tracegen.scala:21:14]
input io_lsu_ldq_full_0, // @[tracegen.scala:21:14]
input io_lsu_stq_full_0, // @[tracegen.scala:21:14]
output io_lsu_commit_valids_0, // @[tracegen.scala:21:14]
output [31:0] io_lsu_commit_uops_0_inst, // @[tracegen.scala:21:14]
output [31:0] io_lsu_commit_uops_0_debug_inst, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_rvc, // @[tracegen.scala:21:14]
output [33:0] io_lsu_commit_uops_0_debug_pc, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iq_type_0, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iq_type_1, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iq_type_2, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iq_type_3, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_0, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_1, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_2, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_3, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_4, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_5, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_6, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_7, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_8, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fu_code_9, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_issued, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_issued_partial_agen, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_issued_partial_dgen, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_p1_speculative_child, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_p2_speculative_child, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_p1_bypass_hint, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_p2_bypass_hint, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_iw_p3_bypass_hint, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_dis_col_sel, // @[tracegen.scala:21:14]
output [3:0] io_lsu_commit_uops_0_br_mask, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_br_tag, // @[tracegen.scala:21:14]
output [3:0] io_lsu_commit_uops_0_br_type, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_sfb, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_fence, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_fencei, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_sfence, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_amo, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_eret, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_sys_pc2epc, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_rocc, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_mov, // @[tracegen.scala:21:14]
output [3:0] io_lsu_commit_uops_0_ftq_idx, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_edge_inst, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_pc_lob, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_taken, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_imm_rename, // @[tracegen.scala:21:14]
output [2:0] io_lsu_commit_uops_0_imm_sel, // @[tracegen.scala:21:14]
output [4:0] io_lsu_commit_uops_0_pimm, // @[tracegen.scala:21:14]
output [19:0] io_lsu_commit_uops_0_imm_packed, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_op1_sel, // @[tracegen.scala:21:14]
output [2:0] io_lsu_commit_uops_0_op2_sel, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_ldst, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_wen, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_ren1, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_ren2, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_ren3, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_swap12, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_swap23, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_fromint, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_toint, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_fastpipe, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_fma, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_div, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_sqrt, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_wflags, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_ctrl_vec, // @[tracegen.scala:21:14]
output [4:0] io_lsu_commit_uops_0_rob_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_commit_uops_0_ldq_idx, // @[tracegen.scala:21:14]
output [3:0] io_lsu_commit_uops_0_stq_idx, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_pdst, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_prs1, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_prs2, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_prs3, // @[tracegen.scala:21:14]
output [3:0] io_lsu_commit_uops_0_ppred, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_prs1_busy, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_prs2_busy, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_prs3_busy, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_ppred_busy, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_stale_pdst, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_exception, // @[tracegen.scala:21:14]
output [63:0] io_lsu_commit_uops_0_exc_cause, // @[tracegen.scala:21:14]
output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_mem_size, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_mem_signed, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_uses_ldq, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_uses_stq, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_is_unique, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_flush_on_commit, // @[tracegen.scala:21:14]
output [2:0] io_lsu_commit_uops_0_csr_cmd, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_ldst_is_rs1, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_ldst, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_lrs1, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_lrs2, // @[tracegen.scala:21:14]
output [5:0] io_lsu_commit_uops_0_lrs3, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_frs3_en, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fcn_dw, // @[tracegen.scala:21:14]
output [4:0] io_lsu_commit_uops_0_fcn_op, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_fp_val, // @[tracegen.scala:21:14]
output [2:0] io_lsu_commit_uops_0_fp_rm, // @[tracegen.scala:21:14]
output [1:0] io_lsu_commit_uops_0_fp_typ, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_xcpt_pf_if, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_xcpt_ae_if, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_xcpt_ma_if, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_bp_debug_if, // @[tracegen.scala:21:14]
output io_lsu_commit_uops_0_bp_xcpt_if, // @[tracegen.scala:21:14]
output [2:0] io_lsu_commit_uops_0_debug_fsrc, // @[tracegen.scala:21:14]
output [2:0] io_lsu_commit_uops_0_debug_tsrc, // @[tracegen.scala:21:14]
input io_lsu_clr_bsy_0_valid, // @[tracegen.scala:21:14]
input [4:0] io_lsu_clr_bsy_0_bits, // @[tracegen.scala:21:14]
input io_lsu_clr_unsafe_0_valid, // @[tracegen.scala:21:14]
input [4:0] io_lsu_clr_unsafe_0_bits, // @[tracegen.scala:21:14]
output [4:0] io_lsu_rob_pnr_idx, // @[tracegen.scala:21:14]
output [4:0] io_lsu_rob_head_idx, // @[tracegen.scala:21:14]
input io_lsu_fencei_rdy, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_valid, // @[tracegen.scala:21:14]
input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[tracegen.scala:21:14]
input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_rvc, // @[tracegen.scala:21:14]
input [33:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iq_type_0, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iq_type_1, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iq_type_2, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iq_type_3, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_0, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_1, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_2, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_3, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_4, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_5, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_6, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_7, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_8, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fu_code_9, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_issued, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_dis_col_sel, // @[tracegen.scala:21:14]
input [3:0] io_lsu_lxcpt_bits_uop_br_mask, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_br_tag, // @[tracegen.scala:21:14]
input [3:0] io_lsu_lxcpt_bits_uop_br_type, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_sfb, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_fence, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_fencei, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_sfence, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_amo, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_eret, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_rocc, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_mov, // @[tracegen.scala:21:14]
input [3:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_edge_inst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_taken, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_imm_rename, // @[tracegen.scala:21:14]
input [2:0] io_lsu_lxcpt_bits_uop_imm_sel, // @[tracegen.scala:21:14]
input [4:0] io_lsu_lxcpt_bits_uop_pimm, // @[tracegen.scala:21:14]
input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_op1_sel, // @[tracegen.scala:21:14]
input [2:0] io_lsu_lxcpt_bits_uop_op2_sel, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14]
input [4:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[tracegen.scala:21:14]
input [3:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_pdst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_prs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_prs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_prs3, // @[tracegen.scala:21:14]
input [3:0] io_lsu_lxcpt_bits_uop_ppred, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_prs1_busy, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_prs2_busy, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_prs3_busy, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_ppred_busy, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_exception, // @[tracegen.scala:21:14]
input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[tracegen.scala:21:14]
input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_mem_signed, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_uses_ldq, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_uses_stq, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_is_unique, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[tracegen.scala:21:14]
input [2:0] io_lsu_lxcpt_bits_uop_csr_cmd, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[tracegen.scala:21:14]
input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_frs3_en, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fcn_dw, // @[tracegen.scala:21:14]
input [4:0] io_lsu_lxcpt_bits_uop_fcn_op, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_fp_val, // @[tracegen.scala:21:14]
input [2:0] io_lsu_lxcpt_bits_uop_fp_rm, // @[tracegen.scala:21:14]
input [1:0] io_lsu_lxcpt_bits_uop_fp_typ, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[tracegen.scala:21:14]
input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14]
input [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[tracegen.scala:21:14]
input [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[tracegen.scala:21:14]
input [4:0] io_lsu_lxcpt_bits_cause, // @[tracegen.scala:21:14]
input [33:0] io_lsu_lxcpt_bits_badvaddr, // @[tracegen.scala:21:14]
input io_lsu_perf_acquire, // @[tracegen.scala:21:14]
input io_lsu_perf_release, // @[tracegen.scala:21:14]
output io_tracegen_req_ready, // @[tracegen.scala:21:14]
input io_tracegen_req_valid, // @[tracegen.scala:21:14]
input [33:0] io_tracegen_req_bits_addr, // @[tracegen.scala:21:14]
input [5:0] io_tracegen_req_bits_tag, // @[tracegen.scala:21:14]
input [4:0] io_tracegen_req_bits_cmd, // @[tracegen.scala:21:14]
input [63:0] io_tracegen_req_bits_data, // @[tracegen.scala:21:14]
input [63:0] io_tracegen_s1_data_data, // @[tracegen.scala:21:14]
output io_tracegen_resp_valid, // @[tracegen.scala:21:14]
output [5:0] io_tracegen_resp_bits_tag, // @[tracegen.scala:21:14]
output [1:0] io_tracegen_resp_bits_size, // @[tracegen.scala:21:14]
output [63:0] io_tracegen_resp_bits_data, // @[tracegen.scala:21:14]
output io_tracegen_ordered // @[tracegen.scala:21:14]
);
wire io_lsu_iwakeups_0_valid_0 = io_lsu_iwakeups_0_valid; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_iwakeups_0_bits_uop_inst_0 = io_lsu_iwakeups_0_bits_uop_inst; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst_0 = io_lsu_iwakeups_0_bits_uop_debug_inst; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_rvc_0 = io_lsu_iwakeups_0_bits_uop_is_rvc; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_iwakeups_0_bits_uop_debug_pc_0 = io_lsu_iwakeups_0_bits_uop_debug_pc; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iq_type_0_0 = io_lsu_iwakeups_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iq_type_1_0 = io_lsu_iwakeups_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iq_type_2_0 = io_lsu_iwakeups_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iq_type_3_0 = io_lsu_iwakeups_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_0_0 = io_lsu_iwakeups_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_1_0 = io_lsu_iwakeups_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_2_0 = io_lsu_iwakeups_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_3_0 = io_lsu_iwakeups_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_4_0 = io_lsu_iwakeups_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_5_0 = io_lsu_iwakeups_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_6_0 = io_lsu_iwakeups_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_7_0 = io_lsu_iwakeups_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_8_0 = io_lsu_iwakeups_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fu_code_9_0 = io_lsu_iwakeups_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_issued_0 = io_lsu_iwakeups_0_bits_uop_iw_issued; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_dis_col_sel_0 = io_lsu_iwakeups_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iwakeups_0_bits_uop_br_mask_0 = io_lsu_iwakeups_0_bits_uop_br_mask; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_br_tag_0 = io_lsu_iwakeups_0_bits_uop_br_tag; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iwakeups_0_bits_uop_br_type_0 = io_lsu_iwakeups_0_bits_uop_br_type; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_sfb_0 = io_lsu_iwakeups_0_bits_uop_is_sfb; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_fence_0 = io_lsu_iwakeups_0_bits_uop_is_fence; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_fencei_0 = io_lsu_iwakeups_0_bits_uop_is_fencei; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_sfence_0 = io_lsu_iwakeups_0_bits_uop_is_sfence; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_amo_0 = io_lsu_iwakeups_0_bits_uop_is_amo; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_eret_0 = io_lsu_iwakeups_0_bits_uop_is_eret; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_rocc_0 = io_lsu_iwakeups_0_bits_uop_is_rocc; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_mov_0 = io_lsu_iwakeups_0_bits_uop_is_mov; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iwakeups_0_bits_uop_ftq_idx_0 = io_lsu_iwakeups_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_edge_inst_0 = io_lsu_iwakeups_0_bits_uop_edge_inst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob_0 = io_lsu_iwakeups_0_bits_uop_pc_lob; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_taken_0 = io_lsu_iwakeups_0_bits_uop_taken; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_imm_rename_0 = io_lsu_iwakeups_0_bits_uop_imm_rename; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel_0 = io_lsu_iwakeups_0_bits_uop_imm_sel; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iwakeups_0_bits_uop_pimm_0 = io_lsu_iwakeups_0_bits_uop_pimm; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed_0 = io_lsu_iwakeups_0_bits_uop_imm_packed; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel_0 = io_lsu_iwakeups_0_bits_uop_op1_sel; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel_0 = io_lsu_iwakeups_0_bits_uop_op2_sel; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_div_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iwakeups_0_bits_uop_rob_idx_0 = io_lsu_iwakeups_0_bits_uop_rob_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx_0 = io_lsu_iwakeups_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx_0 = io_lsu_iwakeups_0_bits_uop_stq_idx; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx_0 = io_lsu_iwakeups_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_pdst_0 = io_lsu_iwakeups_0_bits_uop_pdst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_prs1_0 = io_lsu_iwakeups_0_bits_uop_prs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_prs2_0 = io_lsu_iwakeups_0_bits_uop_prs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_prs3_0 = io_lsu_iwakeups_0_bits_uop_prs3; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iwakeups_0_bits_uop_ppred_0 = io_lsu_iwakeups_0_bits_uop_ppred; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_prs1_busy_0 = io_lsu_iwakeups_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_prs2_busy_0 = io_lsu_iwakeups_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_prs3_busy_0 = io_lsu_iwakeups_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_ppred_busy_0 = io_lsu_iwakeups_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_stale_pdst_0 = io_lsu_iwakeups_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_exception_0 = io_lsu_iwakeups_0_bits_uop_exception; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause_0 = io_lsu_iwakeups_0_bits_uop_exc_cause; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd_0 = io_lsu_iwakeups_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_mem_size_0 = io_lsu_iwakeups_0_bits_uop_mem_size; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_mem_signed_0 = io_lsu_iwakeups_0_bits_uop_mem_signed; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_uses_ldq_0 = io_lsu_iwakeups_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_uses_stq_0 = io_lsu_iwakeups_0_bits_uop_uses_stq; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_is_unique_0 = io_lsu_iwakeups_0_bits_uop_is_unique; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_flush_on_commit_0 = io_lsu_iwakeups_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd_0 = io_lsu_iwakeups_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_ldst_is_rs1_0 = io_lsu_iwakeups_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_ldst_0 = io_lsu_iwakeups_0_bits_uop_ldst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs1_0 = io_lsu_iwakeups_0_bits_uop_lrs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs2_0 = io_lsu_iwakeups_0_bits_uop_lrs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs3_0 = io_lsu_iwakeups_0_bits_uop_lrs3; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype_0 = io_lsu_iwakeups_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_frs3_en_0 = io_lsu_iwakeups_0_bits_uop_frs3_en; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fcn_dw_0 = io_lsu_iwakeups_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op_0 = io_lsu_iwakeups_0_bits_uop_fcn_op; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_fp_val_0 = io_lsu_iwakeups_0_bits_uop_fp_val; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm_0 = io_lsu_iwakeups_0_bits_uop_fp_rm; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ_0 = io_lsu_iwakeups_0_bits_uop_fp_typ; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_xcpt_pf_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_xcpt_ae_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_xcpt_ma_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_bp_debug_if_0 = io_lsu_iwakeups_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_uop_bp_xcpt_if_0 = io_lsu_iwakeups_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_bypassable_0 = io_lsu_iwakeups_0_bits_bypassable; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_speculative_mask_0 = io_lsu_iwakeups_0_bits_speculative_mask; // @[tracegen.scala:19:7]
wire io_lsu_iwakeups_0_bits_rebusy_0 = io_lsu_iwakeups_0_bits_rebusy; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_valid_0 = io_lsu_iresp_0_valid; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_iresp_0_bits_uop_inst_0 = io_lsu_iresp_0_bits_uop_inst; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_iresp_0_bits_uop_debug_inst_0 = io_lsu_iresp_0_bits_uop_debug_inst; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_rvc_0 = io_lsu_iresp_0_bits_uop_is_rvc; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_iresp_0_bits_uop_debug_pc_0 = io_lsu_iresp_0_bits_uop_debug_pc; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iq_type_0_0 = io_lsu_iresp_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iq_type_1_0 = io_lsu_iresp_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iq_type_2_0 = io_lsu_iresp_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iq_type_3_0 = io_lsu_iresp_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_0_0 = io_lsu_iresp_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_1_0 = io_lsu_iresp_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_2_0 = io_lsu_iresp_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_3_0 = io_lsu_iresp_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_4_0 = io_lsu_iresp_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_5_0 = io_lsu_iresp_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_6_0 = io_lsu_iresp_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_7_0 = io_lsu_iresp_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_8_0 = io_lsu_iresp_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fu_code_9_0 = io_lsu_iresp_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_issued_0 = io_lsu_iresp_0_bits_uop_iw_issued; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_dis_col_sel_0 = io_lsu_iresp_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iresp_0_bits_uop_br_mask_0 = io_lsu_iresp_0_bits_uop_br_mask; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_br_tag_0 = io_lsu_iresp_0_bits_uop_br_tag; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iresp_0_bits_uop_br_type_0 = io_lsu_iresp_0_bits_uop_br_type; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_sfb_0 = io_lsu_iresp_0_bits_uop_is_sfb; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_fence_0 = io_lsu_iresp_0_bits_uop_is_fence; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_fencei_0 = io_lsu_iresp_0_bits_uop_is_fencei; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_sfence_0 = io_lsu_iresp_0_bits_uop_is_sfence; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_amo_0 = io_lsu_iresp_0_bits_uop_is_amo; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_eret_0 = io_lsu_iresp_0_bits_uop_is_eret; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iresp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_rocc_0 = io_lsu_iresp_0_bits_uop_is_rocc; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_mov_0 = io_lsu_iresp_0_bits_uop_is_mov; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iresp_0_bits_uop_ftq_idx_0 = io_lsu_iresp_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_edge_inst_0 = io_lsu_iresp_0_bits_uop_edge_inst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_pc_lob_0 = io_lsu_iresp_0_bits_uop_pc_lob; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_taken_0 = io_lsu_iresp_0_bits_uop_taken; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_imm_rename_0 = io_lsu_iresp_0_bits_uop_imm_rename; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iresp_0_bits_uop_imm_sel_0 = io_lsu_iresp_0_bits_uop_imm_sel; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iresp_0_bits_uop_pimm_0 = io_lsu_iresp_0_bits_uop_pimm; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_iresp_0_bits_uop_imm_packed_0 = io_lsu_iresp_0_bits_uop_imm_packed; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_op1_sel_0 = io_lsu_iresp_0_bits_uop_op1_sel; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iresp_0_bits_uop_op2_sel_0 = io_lsu_iresp_0_bits_uop_op2_sel; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iresp_0_bits_uop_rob_idx_0 = io_lsu_iresp_0_bits_uop_rob_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iresp_0_bits_uop_ldq_idx_0 = io_lsu_iresp_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iresp_0_bits_uop_stq_idx_0 = io_lsu_iresp_0_bits_uop_stq_idx; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_rxq_idx_0 = io_lsu_iresp_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_pdst_0 = io_lsu_iresp_0_bits_uop_pdst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_prs1_0 = io_lsu_iresp_0_bits_uop_prs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_prs2_0 = io_lsu_iresp_0_bits_uop_prs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_prs3_0 = io_lsu_iresp_0_bits_uop_prs3; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_iresp_0_bits_uop_ppred_0 = io_lsu_iresp_0_bits_uop_ppred; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_prs1_busy_0 = io_lsu_iresp_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_prs2_busy_0 = io_lsu_iresp_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_prs3_busy_0 = io_lsu_iresp_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_ppred_busy_0 = io_lsu_iresp_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_stale_pdst_0 = io_lsu_iresp_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_exception_0 = io_lsu_iresp_0_bits_uop_exception; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_iresp_0_bits_uop_exc_cause_0 = io_lsu_iresp_0_bits_uop_exc_cause; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iresp_0_bits_uop_mem_cmd_0 = io_lsu_iresp_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_mem_size_0 = io_lsu_iresp_0_bits_uop_mem_size; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_mem_signed_0 = io_lsu_iresp_0_bits_uop_mem_signed; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_uses_ldq_0 = io_lsu_iresp_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_uses_stq_0 = io_lsu_iresp_0_bits_uop_uses_stq; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_is_unique_0 = io_lsu_iresp_0_bits_uop_is_unique; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_flush_on_commit_0 = io_lsu_iresp_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iresp_0_bits_uop_csr_cmd_0 = io_lsu_iresp_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_iresp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_ldst_0 = io_lsu_iresp_0_bits_uop_ldst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_lrs1_0 = io_lsu_iresp_0_bits_uop_lrs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_lrs2_0 = io_lsu_iresp_0_bits_uop_lrs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_iresp_0_bits_uop_lrs3_0 = io_lsu_iresp_0_bits_uop_lrs3; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_dst_rtype_0 = io_lsu_iresp_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype_0 = io_lsu_iresp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype_0 = io_lsu_iresp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_frs3_en_0 = io_lsu_iresp_0_bits_uop_frs3_en; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fcn_dw_0 = io_lsu_iresp_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iresp_0_bits_uop_fcn_op_0 = io_lsu_iresp_0_bits_uop_fcn_op; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_fp_val_0 = io_lsu_iresp_0_bits_uop_fp_val; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iresp_0_bits_uop_fp_rm_0 = io_lsu_iresp_0_bits_uop_fp_rm; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_iresp_0_bits_uop_fp_typ_0 = io_lsu_iresp_0_bits_uop_fp_typ; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_iresp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_bp_debug_if_0 = io_lsu_iresp_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_iresp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc_0 = io_lsu_iresp_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc_0 = io_lsu_iresp_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_iresp_0_bits_data_0 = io_lsu_iresp_0_bits_data; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_valid_0 = io_lsu_fresp_0_valid; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_fresp_0_bits_uop_inst_0 = io_lsu_fresp_0_bits_uop_inst; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_fresp_0_bits_uop_debug_inst_0 = io_lsu_fresp_0_bits_uop_debug_inst; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_rvc_0 = io_lsu_fresp_0_bits_uop_is_rvc; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_fresp_0_bits_uop_debug_pc_0 = io_lsu_fresp_0_bits_uop_debug_pc; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iq_type_0_0 = io_lsu_fresp_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iq_type_1_0 = io_lsu_fresp_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iq_type_2_0 = io_lsu_fresp_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iq_type_3_0 = io_lsu_fresp_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_0_0 = io_lsu_fresp_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_1_0 = io_lsu_fresp_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_2_0 = io_lsu_fresp_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_3_0 = io_lsu_fresp_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_4_0 = io_lsu_fresp_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_5_0 = io_lsu_fresp_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_6_0 = io_lsu_fresp_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_7_0 = io_lsu_fresp_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_8_0 = io_lsu_fresp_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fu_code_9_0 = io_lsu_fresp_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_issued_0 = io_lsu_fresp_0_bits_uop_iw_issued; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_dis_col_sel_0 = io_lsu_fresp_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_fresp_0_bits_uop_br_mask_0 = io_lsu_fresp_0_bits_uop_br_mask; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_br_tag_0 = io_lsu_fresp_0_bits_uop_br_tag; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_fresp_0_bits_uop_br_type_0 = io_lsu_fresp_0_bits_uop_br_type; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_sfb_0 = io_lsu_fresp_0_bits_uop_is_sfb; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_fence_0 = io_lsu_fresp_0_bits_uop_is_fence; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_fencei_0 = io_lsu_fresp_0_bits_uop_is_fencei; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_sfence_0 = io_lsu_fresp_0_bits_uop_is_sfence; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_amo_0 = io_lsu_fresp_0_bits_uop_is_amo; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_eret_0 = io_lsu_fresp_0_bits_uop_is_eret; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_fresp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_rocc_0 = io_lsu_fresp_0_bits_uop_is_rocc; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_mov_0 = io_lsu_fresp_0_bits_uop_is_mov; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_fresp_0_bits_uop_ftq_idx_0 = io_lsu_fresp_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_edge_inst_0 = io_lsu_fresp_0_bits_uop_edge_inst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_pc_lob_0 = io_lsu_fresp_0_bits_uop_pc_lob; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_taken_0 = io_lsu_fresp_0_bits_uop_taken; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_imm_rename_0 = io_lsu_fresp_0_bits_uop_imm_rename; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_fresp_0_bits_uop_imm_sel_0 = io_lsu_fresp_0_bits_uop_imm_sel; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_fresp_0_bits_uop_pimm_0 = io_lsu_fresp_0_bits_uop_pimm; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_fresp_0_bits_uop_imm_packed_0 = io_lsu_fresp_0_bits_uop_imm_packed; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_op1_sel_0 = io_lsu_fresp_0_bits_uop_op1_sel; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_fresp_0_bits_uop_op2_sel_0 = io_lsu_fresp_0_bits_uop_op2_sel; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_fresp_0_bits_uop_rob_idx_0 = io_lsu_fresp_0_bits_uop_rob_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_fresp_0_bits_uop_ldq_idx_0 = io_lsu_fresp_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_fresp_0_bits_uop_stq_idx_0 = io_lsu_fresp_0_bits_uop_stq_idx; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_rxq_idx_0 = io_lsu_fresp_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_pdst_0 = io_lsu_fresp_0_bits_uop_pdst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_prs1_0 = io_lsu_fresp_0_bits_uop_prs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_prs2_0 = io_lsu_fresp_0_bits_uop_prs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_prs3_0 = io_lsu_fresp_0_bits_uop_prs3; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_fresp_0_bits_uop_ppred_0 = io_lsu_fresp_0_bits_uop_ppred; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_prs1_busy_0 = io_lsu_fresp_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_prs2_busy_0 = io_lsu_fresp_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_prs3_busy_0 = io_lsu_fresp_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_ppred_busy_0 = io_lsu_fresp_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_stale_pdst_0 = io_lsu_fresp_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_exception_0 = io_lsu_fresp_0_bits_uop_exception; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_fresp_0_bits_uop_exc_cause_0 = io_lsu_fresp_0_bits_uop_exc_cause; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_fresp_0_bits_uop_mem_cmd_0 = io_lsu_fresp_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_mem_size_0 = io_lsu_fresp_0_bits_uop_mem_size; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_mem_signed_0 = io_lsu_fresp_0_bits_uop_mem_signed; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_uses_ldq_0 = io_lsu_fresp_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_uses_stq_0 = io_lsu_fresp_0_bits_uop_uses_stq; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_is_unique_0 = io_lsu_fresp_0_bits_uop_is_unique; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_flush_on_commit_0 = io_lsu_fresp_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_fresp_0_bits_uop_csr_cmd_0 = io_lsu_fresp_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_fresp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_ldst_0 = io_lsu_fresp_0_bits_uop_ldst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_lrs1_0 = io_lsu_fresp_0_bits_uop_lrs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_lrs2_0 = io_lsu_fresp_0_bits_uop_lrs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_fresp_0_bits_uop_lrs3_0 = io_lsu_fresp_0_bits_uop_lrs3; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_dst_rtype_0 = io_lsu_fresp_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype_0 = io_lsu_fresp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype_0 = io_lsu_fresp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_frs3_en_0 = io_lsu_fresp_0_bits_uop_frs3_en; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fcn_dw_0 = io_lsu_fresp_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_fresp_0_bits_uop_fcn_op_0 = io_lsu_fresp_0_bits_uop_fcn_op; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_fp_val_0 = io_lsu_fresp_0_bits_uop_fp_val; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_fresp_0_bits_uop_fp_rm_0 = io_lsu_fresp_0_bits_uop_fp_rm; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_fresp_0_bits_uop_fp_typ_0 = io_lsu_fresp_0_bits_uop_fp_typ; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_fresp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_bp_debug_if_0 = io_lsu_fresp_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_fresp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc_0 = io_lsu_fresp_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc_0 = io_lsu_fresp_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_fresp_0_bits_data_0 = io_lsu_fresp_0_bits_data; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[tracegen.scala:19:7]
wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[tracegen.scala:19:7]
wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[tracegen.scala:19:7]
wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[tracegen.scala:19:7]
wire io_lsu_clr_unsafe_0_valid_0 = io_lsu_clr_unsafe_0_valid; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[tracegen.scala:19:7]
wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iq_type_0_0 = io_lsu_lxcpt_bits_uop_iq_type_0; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iq_type_1_0 = io_lsu_lxcpt_bits_uop_iq_type_1; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iq_type_2_0 = io_lsu_lxcpt_bits_uop_iq_type_2; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iq_type_3_0 = io_lsu_lxcpt_bits_uop_iq_type_3; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_0_0 = io_lsu_lxcpt_bits_uop_fu_code_0; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_1_0 = io_lsu_lxcpt_bits_uop_fu_code_1; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_2_0 = io_lsu_lxcpt_bits_uop_fu_code_2; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_3_0 = io_lsu_lxcpt_bits_uop_fu_code_3; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_4_0 = io_lsu_lxcpt_bits_uop_fu_code_4; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_5_0 = io_lsu_lxcpt_bits_uop_fu_code_5; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_6_0 = io_lsu_lxcpt_bits_uop_fu_code_6; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_7_0 = io_lsu_lxcpt_bits_uop_fu_code_7; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_8_0 = io_lsu_lxcpt_bits_uop_fu_code_8; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fu_code_9_0 = io_lsu_lxcpt_bits_uop_fu_code_9; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_issued_0 = io_lsu_lxcpt_bits_uop_iw_issued; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_issued_partial_agen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_p1_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_p2_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_dis_col_sel_0 = io_lsu_lxcpt_bits_uop_dis_col_sel; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_lxcpt_bits_uop_br_type_0 = io_lsu_lxcpt_bits_uop_br_type; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_sfence_0 = io_lsu_lxcpt_bits_uop_is_sfence; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_eret_0 = io_lsu_lxcpt_bits_uop_is_eret; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_rocc_0 = io_lsu_lxcpt_bits_uop_is_rocc; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_mov_0 = io_lsu_lxcpt_bits_uop_is_mov; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_imm_rename_0 = io_lsu_lxcpt_bits_uop_imm_rename; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_lxcpt_bits_uop_imm_sel_0 = io_lsu_lxcpt_bits_uop_imm_sel; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_lxcpt_bits_uop_pimm_0 = io_lsu_lxcpt_bits_uop_pimm; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_op1_sel_0 = io_lsu_lxcpt_bits_uop_op1_sel; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_lxcpt_bits_uop_op2_sel_0 = io_lsu_lxcpt_bits_uop_op2_sel; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_ldst_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_wen_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren1_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren2_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren3_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap12_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap23_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_fromint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_toint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_fma_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_div_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_wflags_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_ctrl_vec_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_lxcpt_bits_uop_csr_cmd_0 = io_lsu_lxcpt_bits_uop_csr_cmd; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fcn_dw_0 = io_lsu_lxcpt_bits_uop_fcn_dw; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_lxcpt_bits_uop_fcn_op_0 = io_lsu_lxcpt_bits_uop_fcn_op; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_lxcpt_bits_uop_fp_rm_0 = io_lsu_lxcpt_bits_uop_fp_rm; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_lxcpt_bits_uop_fp_typ_0 = io_lsu_lxcpt_bits_uop_fp_typ; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:19:7]
wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[tracegen.scala:19:7]
wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[tracegen.scala:19:7]
wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[tracegen.scala:19:7]
wire io_tracegen_req_valid_0 = io_tracegen_req_valid; // @[tracegen.scala:19:7]
wire [33:0] io_tracegen_req_bits_addr_0 = io_tracegen_req_bits_addr; // @[tracegen.scala:19:7]
wire [5:0] io_tracegen_req_bits_tag_0 = io_tracegen_req_bits_tag; // @[tracegen.scala:19:7]
wire [4:0] io_tracegen_req_bits_cmd_0 = io_tracegen_req_bits_cmd; // @[tracegen.scala:19:7]
wire [63:0] io_tracegen_req_bits_data_0 = io_tracegen_req_bits_data; // @[tracegen.scala:19:7]
wire [63:0] io_tracegen_s1_data_data_0 = io_tracegen_s1_data_data; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_agen_0_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dgen_0_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dgen_1_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dgen_1_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dgen_2_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dgen_2_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dis_uops_0_bits_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_commit_uops_0_inst_0 = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_commit_debug_insts_0 = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_status_isa = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] io_tracegen_s2_paddr = 32'h0; // @[tracegen.scala:19:7]
wire [31:0] _tracegen_uop_WIRE_inst = 32'h0; // @[tracegen.scala:55:45]
wire [31:0] _tracegen_uop_WIRE_debug_inst = 32'h0; // @[tracegen.scala:55:45]
wire [31:0] tracegen_uop_inst = 32'h0; // @[tracegen.scala:55:30]
wire io_lsu_agen_0_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_valid = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_amo = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_1_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_valid = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_amo = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_2_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_predicated = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_iresp_0_bits_fflags_valid = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_predicated = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_fresp_0_bits_fflags_valid = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_sfence_valid = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_sfence_bits_rs1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_sfence_bits_rs2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_sfence_bits_asid = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_sfence_bits_hv = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_sfence_bits_hg = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_rvc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iq_type_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iq_type_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iq_type_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iq_type_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_4 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_5 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_6 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_7 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_8 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fu_code_9 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_issued = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_dis_col_sel = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_sfb = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_fence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_fencei = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_sfence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_eret = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_rocc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_mov = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_edge_inst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_taken = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_imm_rename = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_prs1_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_prs2_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_prs3_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_exception = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_mem_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_unique = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_flush_on_commit = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_frs3_en = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fcn_dw = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_fp_val = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_bp_debug_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_arch_valids_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_rvc_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iq_type_0_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iq_type_1_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iq_type_2_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iq_type_3_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_0_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_1_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_2_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_3_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_4_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_5_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_6_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_7_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_8_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fu_code_9_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_issued_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_issued_partial_agen_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_issued_partial_dgen_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_p1_speculative_child_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_p2_speculative_child_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_p1_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_p2_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_iw_p3_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_dis_col_sel_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_sfb_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_fence_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_fencei_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_sfence_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_eret_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_sys_pc2epc_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_rocc_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_mov_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_edge_inst_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_taken_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_imm_rename_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_ldst_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_wen_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_ren1_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_ren2_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_ren3_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_swap12_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_swap23_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_fromint_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_toint_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_fastpipe_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_fma_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_div_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_sqrt_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_wflags_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_ctrl_vec_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_prs1_busy_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_prs2_busy_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_prs3_busy_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_ppred_busy_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_exception_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_mem_signed_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_unique_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_flush_on_commit_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_ldst_is_rs1_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_frs3_en_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fcn_dw_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_fp_val_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_xcpt_pf_if_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_xcpt_ae_if_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_xcpt_ma_if_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_bp_debug_if_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_bp_xcpt_if_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_fflags_valid = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_commit_load_at_rob_head = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_fence_dmem = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_fence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_amo = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_eret = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_mov = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_taken = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_exception = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_is_unique = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_fp_val = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_mispredict = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_brupdate_b2_taken = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_exception = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_tsc_reg = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_debug = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_cease = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_wfi = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_dv = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_v = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_sd = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_mpv = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_gva = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_mbe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_sbe = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_sd_rv32 = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_tsr = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_tw = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_tvm = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_mxr = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_sum = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_mprv = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_spp = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_mpie = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_ube = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_spie = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_upie = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_mie = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_hie = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_sie = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_status_uie = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_mcontext = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_scontext = 1'h0; // @[tracegen.scala:19:7]
wire io_lsu_perf_tlbMiss = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_req_bits_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_req_bits_dv = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_req_bits_phys = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_req_bits_no_resp = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_req_bits_no_alloc = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_req_bits_no_xcpt = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s1_kill = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_nack = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_nack_cause_raw = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_kill = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_uncached = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_resp_bits_signed = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_resp_bits_dv = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_resp_bits_replay = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_resp_bits_has_data = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_replay_next = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_ma_ld = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_ma_st = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_pf_ld = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_pf_st = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_gf_ld = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_gf_st = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_ae_ld = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_xcpt_ae_st = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_s2_gpa_is_pte = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_store_pending = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_acquire = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_release = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_grant = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_tlbMiss = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_blocked = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_canAcceptStoreThenLoad = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_canAcceptStoreThenRMW = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_canAcceptLoadThenLoad = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_storeBufferEmptyAfterLoad = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_perf_storeBufferEmptyAfterStore = 1'h0; // @[tracegen.scala:19:7]
wire io_tracegen_clock_enabled = 1'h0; // @[tracegen.scala:19:7]
wire _rob_bsy_WIRE_0 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_1 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_2 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_3 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_4 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_5 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_6 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_7 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_8 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_9 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_10 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_11 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_12 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_13 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_14 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_15 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_16 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_17 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_18 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_19 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_20 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_21 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_22 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_23 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_24 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_25 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_26 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_27 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_28 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_29 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_30 = 1'h0; // @[tracegen.scala:33:33]
wire _rob_bsy_WIRE_31 = 1'h0; // @[tracegen.scala:33:33]
wire _tracegen_uop_WIRE_is_rvc = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iq_type_0 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iq_type_1 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iq_type_2 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iq_type_3 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_0 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_1 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_2 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_3 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_4 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_5 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_6 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_7 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_8 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fu_code_9 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_issued = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_dis_col_sel = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_sfb = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_fence = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_fencei = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_sfence = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_amo = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_eret = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_sys_pc2epc = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_rocc = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_mov = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_edge_inst = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_taken = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_imm_rename = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_wen = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_toint = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_fma = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_div = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_ctrl_vec = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_prs1_busy = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_prs2_busy = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_prs3_busy = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_ppred_busy = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_exception = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_mem_signed = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_uses_ldq = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_uses_stq = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_is_unique = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_flush_on_commit = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_ldst_is_rs1 = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_frs3_en = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fcn_dw = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_fp_val = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_xcpt_pf_if = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_xcpt_ae_if = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_xcpt_ma_if = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_bp_debug_if = 1'h0; // @[tracegen.scala:55:45]
wire _tracegen_uop_WIRE_bp_xcpt_if = 1'h0; // @[tracegen.scala:55:45]
wire tracegen_uop_is_rvc = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iq_type_0 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iq_type_1 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iq_type_2 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iq_type_3 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_0 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_1 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_2 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_3 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_4 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_5 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_6 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_7 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_8 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fu_code_9 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_issued = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_dis_col_sel = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_sfb = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_fence = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_fencei = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_sfence = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_eret = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_rocc = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_mov = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_edge_inst = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_taken = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_imm_rename = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_prs1_busy = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_prs2_busy = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_prs3_busy = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_ppred_busy = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_exception = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_mem_signed = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_is_unique = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_flush_on_commit = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_frs3_en = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fcn_dw = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_fp_val = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_bp_debug_if = 1'h0; // @[tracegen.scala:55:30]
wire tracegen_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:55:30]
wire [33:0] io_lsu_agen_0_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_dgen_0_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_dgen_1_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_dgen_2_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_dis_uops_0_bits_debug_pc = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_commit_uops_0_debug_pc_0 = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_tracegen_resp_bits_addr = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] io_tracegen_s2_gpa = 34'h0; // @[tracegen.scala:19:7]
wire [33:0] _tracegen_uop_WIRE_debug_pc = 34'h0; // @[tracegen.scala:55:45]
wire [33:0] tracegen_uop_debug_pc = 34'h0; // @[tracegen.scala:55:30]
wire [3:0] io_lsu_agen_0_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_agen_0_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_agen_0_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_agen_0_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_0_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_0_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_0_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_0_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_1_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_1_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_1_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_1_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_1_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_1_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_2_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_2_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_2_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_2_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_2_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_2_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_uops_0_bits_br_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_uops_0_bits_br_type = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_uops_0_bits_ftq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_uops_0_bits_ppred = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_commit_uops_0_br_mask_0 = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_commit_uops_0_br_type_0 = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_commit_uops_0_ftq_idx_0 = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_commit_uops_0_ppred_0 = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b2_uop_br_type = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0; // @[tracegen.scala:19:7]
wire [3:0] _tracegen_uop_WIRE_br_mask = 4'h0; // @[tracegen.scala:55:45]
wire [3:0] _tracegen_uop_WIRE_br_type = 4'h0; // @[tracegen.scala:55:45]
wire [3:0] _tracegen_uop_WIRE_ftq_idx = 4'h0; // @[tracegen.scala:55:45]
wire [3:0] _tracegen_uop_WIRE_ldq_idx = 4'h0; // @[tracegen.scala:55:45]
wire [3:0] _tracegen_uop_WIRE_stq_idx = 4'h0; // @[tracegen.scala:55:45]
wire [3:0] _tracegen_uop_WIRE_ppred = 4'h0; // @[tracegen.scala:55:45]
wire [3:0] tracegen_uop_br_mask = 4'h0; // @[tracegen.scala:55:30]
wire [3:0] tracegen_uop_br_type = 4'h0; // @[tracegen.scala:55:30]
wire [3:0] tracegen_uop_ftq_idx = 4'h0; // @[tracegen.scala:55:30]
wire [3:0] tracegen_uop_ppred = 4'h0; // @[tracegen.scala:55:30]
wire [3:0] _io_lsu_brupdate_b1_WIRE_resolve_mask = 4'h0; // @[tracegen.scala:151:39]
wire [3:0] _io_lsu_brupdate_b1_WIRE_mispredict_mask = 4'h0; // @[tracegen.scala:151:39]
wire [1:0] io_lsu_agen_0_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_agen_0_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_mem_size = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_1_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_mem_size = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_2_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_br_tag = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_op1_sel = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_fp_typ = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_br_tag_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_op1_sel_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_rxq_idx_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_dst_rtype_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_fp_typ_0 = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_dprv = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_prv = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_sxl = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_uxl = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_xs = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_fs = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_mpp = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_status_vs = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] io_tracegen_resp_bits_dprv = 2'h0; // @[tracegen.scala:19:7]
wire [1:0] _tracegen_uop_WIRE_br_tag = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_op1_sel = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_rxq_idx = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_mem_size = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_dst_rtype = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_lrs1_rtype = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_lrs2_rtype = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] _tracegen_uop_WIRE_fp_typ = 2'h0; // @[tracegen.scala:55:45]
wire [1:0] tracegen_uop_br_tag = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_op1_sel = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_rxq_idx = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_dst_rtype = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:55:30]
wire [1:0] tracegen_uop_fp_typ = 2'h0; // @[tracegen.scala:55:30]
wire [5:0] io_lsu_agen_0_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_agen_0_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_0_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_1_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dgen_2_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_pc_lob = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_prs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_prs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_prs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_stale_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_ldst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_dis_uops_0_bits_lrs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_pc_lob_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_pdst_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_prs1_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_prs2_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_prs3_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_stale_pdst_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_ldst_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_lrs1_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_lrs2_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_commit_uops_0_lrs3_0 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_prs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7]
wire [5:0] _tracegen_uop_WIRE_pc_lob = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_pdst = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_prs1 = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_prs2 = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_prs3 = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_stale_pdst = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_ldst = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_lrs1 = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_lrs2 = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] _tracegen_uop_WIRE_lrs3 = 6'h0; // @[tracegen.scala:55:45]
wire [5:0] tracegen_uop_pc_lob = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_pdst = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_prs1 = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_prs2 = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_prs3 = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_stale_pdst = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_ldst = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_lrs1 = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_lrs2 = 6'h0; // @[tracegen.scala:55:30]
wire [5:0] tracegen_uop_lrs3 = 6'h0; // @[tracegen.scala:55:30]
wire [2:0] io_lsu_agen_0_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_agen_0_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_agen_0_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_agen_0_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_agen_0_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_agen_0_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_0_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_0_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_0_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_0_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_0_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_0_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_1_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_1_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_1_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_1_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_1_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_1_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_2_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_2_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_2_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_2_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_2_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dgen_2_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dis_uops_0_bits_imm_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dis_uops_0_bits_op2_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dis_uops_0_bits_csr_cmd = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dis_uops_0_bits_fp_rm = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dis_uops_0_bits_debug_fsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_dis_uops_0_bits_debug_tsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_commit_uops_0_imm_sel_0 = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_commit_uops_0_op2_sel_0 = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_commit_uops_0_csr_cmd_0 = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_commit_uops_0_fp_rm_0 = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_commit_uops_0_debug_fsrc_0 = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_commit_uops_0_debug_tsrc_0 = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_brupdate_b2_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_brupdate_b2_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_brupdate_b2_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_brupdate_b2_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_brupdate_b2_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_brupdate_b2_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0; // @[tracegen.scala:19:7]
wire [2:0] _tracegen_uop_WIRE_imm_sel = 3'h0; // @[tracegen.scala:55:45]
wire [2:0] _tracegen_uop_WIRE_op2_sel = 3'h0; // @[tracegen.scala:55:45]
wire [2:0] _tracegen_uop_WIRE_csr_cmd = 3'h0; // @[tracegen.scala:55:45]
wire [2:0] _tracegen_uop_WIRE_fp_rm = 3'h0; // @[tracegen.scala:55:45]
wire [2:0] _tracegen_uop_WIRE_debug_fsrc = 3'h0; // @[tracegen.scala:55:45]
wire [2:0] _tracegen_uop_WIRE_debug_tsrc = 3'h0; // @[tracegen.scala:55:45]
wire [2:0] tracegen_uop_imm_sel = 3'h0; // @[tracegen.scala:55:30]
wire [2:0] tracegen_uop_op2_sel = 3'h0; // @[tracegen.scala:55:30]
wire [2:0] tracegen_uop_csr_cmd = 3'h0; // @[tracegen.scala:55:30]
wire [2:0] tracegen_uop_fp_rm = 3'h0; // @[tracegen.scala:55:30]
wire [2:0] tracegen_uop_debug_fsrc = 3'h0; // @[tracegen.scala:55:30]
wire [2:0] tracegen_uop_debug_tsrc = 3'h0; // @[tracegen.scala:55:30]
wire [4:0] io_lsu_agen_0_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_agen_0_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_0_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_0_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_1_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_1_bits_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_1_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_1_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_2_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_2_bits_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_2_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_2_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_iresp_0_bits_fflags_bits = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_fresp_0_bits_fflags_bits = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dis_uops_0_bits_pimm = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dis_uops_0_bits_fcn_op = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_commit_uops_0_pimm_0 = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_commit_uops_0_fcn_op_0 = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_commit_fflags_bits = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_brupdate_b2_uop_pimm = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_brupdate_b2_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_brupdate_b2_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] io_tracegen_resp_bits_cmd = 5'h0; // @[tracegen.scala:19:7]
wire [4:0] _tracegen_uop_WIRE_pimm = 5'h0; // @[tracegen.scala:55:45]
wire [4:0] _tracegen_uop_WIRE_rob_idx = 5'h0; // @[tracegen.scala:55:45]
wire [4:0] _tracegen_uop_WIRE_mem_cmd = 5'h0; // @[tracegen.scala:55:45]
wire [4:0] _tracegen_uop_WIRE_fcn_op = 5'h0; // @[tracegen.scala:55:45]
wire [4:0] tracegen_uop_pimm = 5'h0; // @[tracegen.scala:55:30]
wire [4:0] tracegen_uop_fcn_op = 5'h0; // @[tracegen.scala:55:30]
wire [19:0] io_lsu_agen_0_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_dgen_0_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_dgen_1_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_dgen_2_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_dis_uops_0_bits_imm_packed = 20'h0; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_commit_uops_0_imm_packed_0 = 20'h0; // @[tracegen.scala:19:7]
wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7]
wire [19:0] _tracegen_uop_WIRE_imm_packed = 20'h0; // @[tracegen.scala:55:45]
wire [19:0] tracegen_uop_imm_packed = 20'h0; // @[tracegen.scala:55:30]
wire [63:0] io_lsu_agen_0_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_dgen_0_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_dgen_1_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_dgen_1_bits_data = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_dgen_2_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_dgen_2_bits_data = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_dis_uops_0_bits_exc_cause = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_commit_uops_0_exc_cause_0 = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_commit_debug_wdata_0 = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_tracegen_resp_bits_data_word_bypass = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_tracegen_resp_bits_data_raw = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] io_tracegen_resp_bits_store_data = 64'h0; // @[tracegen.scala:19:7]
wire [63:0] _tracegen_uop_WIRE_exc_cause = 64'h0; // @[tracegen.scala:55:45]
wire [63:0] tracegen_uop_exc_cause = 64'h0; // @[tracegen.scala:55:30]
wire [1:0] io_lsu_agen_0_bits_uop_mem_size = 2'h3; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dgen_0_bits_uop_mem_size = 2'h3; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_dis_uops_0_bits_mem_size = 2'h3; // @[tracegen.scala:19:7]
wire [1:0] io_lsu_commit_uops_0_mem_size_0 = 2'h3; // @[tracegen.scala:19:7]
wire [1:0] io_tracegen_req_bits_size = 2'h3; // @[tracegen.scala:19:7]
wire [1:0] io_tracegen_req_bits_dprv = 2'h3; // @[tracegen.scala:19:7]
wire [1:0] tracegen_uop_mem_size = 2'h3; // @[tracegen.scala:55:30]
wire [7:0] io_tracegen_req_bits_mask = 8'hFF; // @[tracegen.scala:19:7]
wire [7:0] io_tracegen_s1_data_mask = 8'hFF; // @[tracegen.scala:19:7]
wire [32:0] io_lsu_sfence_bits_addr = 33'h0; // @[tracegen.scala:19:7]
wire [20:0] io_lsu_brupdate_b2_target_offset = 21'h0; // @[tracegen.scala:19:7]
wire [22:0] io_lsu_status_zero2 = 23'h0; // @[tracegen.scala:19:7]
wire [7:0] io_lsu_status_zero1 = 8'h0; // @[tracegen.scala:19:7]
wire [7:0] io_tracegen_resp_bits_mask = 8'h0; // @[tracegen.scala:19:7]
wire io_tracegen_keep_clock_enabled = 1'h1; // @[tracegen.scala:19:7]
wire _rob_respd_T_1 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_2 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_3 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_4 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_5 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_6 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_7 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_8 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_9 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_10 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_11 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_12 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_13 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_14 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_15 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_16 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_17 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_18 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_19 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_20 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_21 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_22 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_23 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_24 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_25 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_26 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_27 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_28 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_29 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_30 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_31 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_T_32 = 1'h1; // @[tracegen.scala:31:54]
wire _rob_respd_WIRE_0 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_1 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_2 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_3 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_4 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_5 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_6 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_7 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_8 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_9 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_10 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_11 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_12 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_13 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_14 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_15 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_16 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_17 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_18 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_19 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_20 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_21 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_22 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_23 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_24 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_25 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_26 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_27 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_28 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_29 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_30 = 1'h1; // @[tracegen.scala:31:34]
wire _rob_respd_WIRE_31 = 1'h1; // @[tracegen.scala:31:34]
wire [31:0] _rob_respd_T = 32'hFFFFFFFF; // @[tracegen.scala:31:36]
wire [1:0] io_tracegen_resp_bits_size_0 = io_lsu_iresp_0_bits_uop_mem_size_0; // @[tracegen.scala:19:7]
wire [63:0] io_tracegen_resp_bits_data_0 = io_lsu_iresp_0_bits_data_0; // @[tracegen.scala:19:7]
wire _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35]
wire [31:0] tracegen_uop_debug_inst; // @[tracegen.scala:55:30]
wire tracegen_uop_is_amo; // @[tracegen.scala:55:30]
wire [4:0] tracegen_uop_rob_idx; // @[tracegen.scala:55:30]
wire [3:0] tracegen_uop_ldq_idx; // @[tracegen.scala:55:30]
wire [3:0] tracegen_uop_stq_idx; // @[tracegen.scala:55:30]
wire [4:0] tracegen_uop_mem_cmd; // @[tracegen.scala:55:30]
wire tracegen_uop_uses_ldq; // @[tracegen.scala:55:30]
wire tracegen_uop_uses_stq; // @[tracegen.scala:55:30]
assign tracegen_uop_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[tracegen.scala:19:7, :55:30]
assign tracegen_uop_stq_idx = io_lsu_dis_stq_idx_0_0; // @[tracegen.scala:19:7, :55:30]
wire _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:92:75]
wire _io_tracegen_req_ready_T_86; // @[tracegen.scala:51:63]
assign tracegen_uop_mem_cmd = io_tracegen_req_bits_cmd_0; // @[tracegen.scala:19:7, :55:30]
wire _io_tracegen_ordered_T; // @[tracegen.scala:162:40]
wire [31:0] io_lsu_agen_0_bits_uop_debug_inst_0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_is_amo_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_agen_0_bits_uop_rob_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_agen_0_bits_uop_ldq_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_agen_0_bits_uop_stq_idx_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_agen_0_bits_uop_mem_cmd_0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_uses_ldq_0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_bits_uop_uses_stq_0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_agen_0_bits_data_0; // @[tracegen.scala:19:7]
wire io_lsu_agen_0_valid_0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dgen_0_bits_uop_debug_inst_0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_is_amo_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_0_bits_uop_rob_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_0_bits_uop_ldq_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dgen_0_bits_uop_stq_idx_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dgen_0_bits_uop_mem_cmd_0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_uses_ldq_0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_bits_uop_uses_stq_0; // @[tracegen.scala:19:7]
wire [63:0] io_lsu_dgen_0_bits_data_0; // @[tracegen.scala:19:7]
wire io_lsu_dgen_0_valid_0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_is_amo_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[tracegen.scala:19:7]
wire io_lsu_dis_uops_0_valid_0; // @[tracegen.scala:19:7]
wire io_lsu_commit_valids_0_0; // @[tracegen.scala:19:7]
wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_is_amo_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_commit_uops_0_rob_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_commit_uops_0_ldq_idx_0; // @[tracegen.scala:19:7]
wire [3:0] io_lsu_commit_uops_0_stq_idx_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_uses_ldq_0; // @[tracegen.scala:19:7]
wire io_lsu_commit_uops_0_uses_stq_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_rob_pnr_idx_0; // @[tracegen.scala:19:7]
wire [4:0] io_lsu_rob_head_idx_0; // @[tracegen.scala:19:7]
wire io_tracegen_req_ready_0; // @[tracegen.scala:19:7]
wire [5:0] io_tracegen_resp_bits_tag_0; // @[tracegen.scala:19:7]
wire io_tracegen_resp_valid_0; // @[tracegen.scala:19:7]
wire io_tracegen_ordered_0; // @[tracegen.scala:19:7]
reg [33:0] rob_0_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_0_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_0_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_0_data; // @[tracegen.scala:30:16]
reg [33:0] rob_1_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_1_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_1_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_1_data; // @[tracegen.scala:30:16]
reg [33:0] rob_2_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_2_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_2_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_2_data; // @[tracegen.scala:30:16]
reg [33:0] rob_3_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_3_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_3_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_3_data; // @[tracegen.scala:30:16]
reg [33:0] rob_4_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_4_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_4_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_4_data; // @[tracegen.scala:30:16]
reg [33:0] rob_5_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_5_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_5_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_5_data; // @[tracegen.scala:30:16]
reg [33:0] rob_6_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_6_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_6_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_6_data; // @[tracegen.scala:30:16]
reg [33:0] rob_7_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_7_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_7_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_7_data; // @[tracegen.scala:30:16]
reg [33:0] rob_8_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_8_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_8_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_8_data; // @[tracegen.scala:30:16]
reg [33:0] rob_9_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_9_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_9_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_9_data; // @[tracegen.scala:30:16]
reg [33:0] rob_10_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_10_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_10_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_10_data; // @[tracegen.scala:30:16]
reg [33:0] rob_11_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_11_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_11_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_11_data; // @[tracegen.scala:30:16]
reg [33:0] rob_12_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_12_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_12_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_12_data; // @[tracegen.scala:30:16]
reg [33:0] rob_13_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_13_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_13_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_13_data; // @[tracegen.scala:30:16]
reg [33:0] rob_14_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_14_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_14_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_14_data; // @[tracegen.scala:30:16]
reg [33:0] rob_15_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_15_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_15_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_15_data; // @[tracegen.scala:30:16]
reg [33:0] rob_16_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_16_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_16_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_16_data; // @[tracegen.scala:30:16]
reg [33:0] rob_17_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_17_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_17_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_17_data; // @[tracegen.scala:30:16]
reg [33:0] rob_18_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_18_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_18_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_18_data; // @[tracegen.scala:30:16]
reg [33:0] rob_19_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_19_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_19_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_19_data; // @[tracegen.scala:30:16]
reg [33:0] rob_20_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_20_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_20_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_20_data; // @[tracegen.scala:30:16]
reg [33:0] rob_21_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_21_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_21_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_21_data; // @[tracegen.scala:30:16]
reg [33:0] rob_22_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_22_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_22_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_22_data; // @[tracegen.scala:30:16]
reg [33:0] rob_23_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_23_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_23_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_23_data; // @[tracegen.scala:30:16]
reg [33:0] rob_24_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_24_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_24_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_24_data; // @[tracegen.scala:30:16]
reg [33:0] rob_25_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_25_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_25_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_25_data; // @[tracegen.scala:30:16]
reg [33:0] rob_26_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_26_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_26_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_26_data; // @[tracegen.scala:30:16]
reg [33:0] rob_27_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_27_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_27_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_27_data; // @[tracegen.scala:30:16]
reg [33:0] rob_28_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_28_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_28_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_28_data; // @[tracegen.scala:30:16]
reg [33:0] rob_29_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_29_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_29_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_29_data; // @[tracegen.scala:30:16]
reg [33:0] rob_30_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_30_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_30_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_30_data; // @[tracegen.scala:30:16]
reg [33:0] rob_31_addr; // @[tracegen.scala:30:16]
reg [5:0] rob_31_tag; // @[tracegen.scala:30:16]
reg [4:0] rob_31_cmd; // @[tracegen.scala:30:16]
reg [63:0] rob_31_data; // @[tracegen.scala:30:16]
reg rob_respd_0; // @[tracegen.scala:31:26]
reg rob_respd_1; // @[tracegen.scala:31:26]
reg rob_respd_2; // @[tracegen.scala:31:26]
reg rob_respd_3; // @[tracegen.scala:31:26]
reg rob_respd_4; // @[tracegen.scala:31:26]
reg rob_respd_5; // @[tracegen.scala:31:26]
reg rob_respd_6; // @[tracegen.scala:31:26]
reg rob_respd_7; // @[tracegen.scala:31:26]
reg rob_respd_8; // @[tracegen.scala:31:26]
reg rob_respd_9; // @[tracegen.scala:31:26]
reg rob_respd_10; // @[tracegen.scala:31:26]
reg rob_respd_11; // @[tracegen.scala:31:26]
reg rob_respd_12; // @[tracegen.scala:31:26]
reg rob_respd_13; // @[tracegen.scala:31:26]
reg rob_respd_14; // @[tracegen.scala:31:26]
reg rob_respd_15; // @[tracegen.scala:31:26]
reg rob_respd_16; // @[tracegen.scala:31:26]
reg rob_respd_17; // @[tracegen.scala:31:26]
reg rob_respd_18; // @[tracegen.scala:31:26]
reg rob_respd_19; // @[tracegen.scala:31:26]
reg rob_respd_20; // @[tracegen.scala:31:26]
reg rob_respd_21; // @[tracegen.scala:31:26]
reg rob_respd_22; // @[tracegen.scala:31:26]
reg rob_respd_23; // @[tracegen.scala:31:26]
reg rob_respd_24; // @[tracegen.scala:31:26]
reg rob_respd_25; // @[tracegen.scala:31:26]
reg rob_respd_26; // @[tracegen.scala:31:26]
reg rob_respd_27; // @[tracegen.scala:31:26]
reg rob_respd_28; // @[tracegen.scala:31:26]
reg rob_respd_29; // @[tracegen.scala:31:26]
reg rob_respd_30; // @[tracegen.scala:31:26]
reg rob_respd_31; // @[tracegen.scala:31:26]
reg [31:0] rob_uop_0_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_0_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_0_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_0_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_0_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_0_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_0_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_0_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_1_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_1_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_1_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_1_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_1_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_1_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_1_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_1_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_2_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_2_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_2_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_2_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_2_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_2_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_2_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_2_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_3_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_3_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_3_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_3_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_3_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_3_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_3_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_3_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_4_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_4_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_4_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_4_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_4_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_4_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_4_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_4_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_5_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_5_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_5_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_5_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_5_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_5_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_5_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_5_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_6_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_6_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_6_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_6_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_6_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_6_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_6_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_6_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_7_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_7_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_7_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_7_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_7_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_7_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_7_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_7_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_8_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_8_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_8_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_8_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_8_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_8_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_8_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_8_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_9_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_9_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_9_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_9_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_9_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_9_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_9_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_9_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_10_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_10_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_10_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_10_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_10_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_10_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_10_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_10_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_11_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_11_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_11_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_11_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_11_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_11_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_11_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_11_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_12_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_12_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_12_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_12_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_12_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_12_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_12_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_12_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_13_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_13_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_13_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_13_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_13_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_13_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_13_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_13_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_14_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_14_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_14_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_14_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_14_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_14_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_14_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_14_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_15_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_15_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_15_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_15_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_15_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_15_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_15_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_15_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_16_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_16_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_16_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_16_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_16_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_16_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_16_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_16_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_17_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_17_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_17_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_17_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_17_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_17_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_17_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_17_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_18_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_18_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_18_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_18_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_18_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_18_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_18_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_18_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_19_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_19_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_19_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_19_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_19_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_19_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_19_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_19_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_20_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_20_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_20_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_20_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_20_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_20_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_20_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_20_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_21_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_21_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_21_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_21_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_21_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_21_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_21_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_21_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_22_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_22_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_22_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_22_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_22_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_22_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_22_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_22_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_23_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_23_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_23_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_23_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_23_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_23_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_23_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_23_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_24_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_24_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_24_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_24_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_24_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_24_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_24_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_24_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_25_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_25_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_25_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_25_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_25_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_25_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_25_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_25_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_26_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_26_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_26_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_26_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_26_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_26_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_26_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_26_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_27_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_27_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_27_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_27_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_27_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_27_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_27_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_27_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_28_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_28_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_28_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_28_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_28_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_28_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_28_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_28_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_29_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_29_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_29_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_29_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_29_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_29_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_29_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_29_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_30_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_30_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_30_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_30_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_30_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_30_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_30_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_30_uses_stq; // @[tracegen.scala:32:20]
reg [31:0] rob_uop_31_debug_inst; // @[tracegen.scala:32:20]
reg rob_uop_31_is_amo; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_31_rob_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_31_ldq_idx; // @[tracegen.scala:32:20]
reg [3:0] rob_uop_31_stq_idx; // @[tracegen.scala:32:20]
reg [4:0] rob_uop_31_mem_cmd; // @[tracegen.scala:32:20]
reg rob_uop_31_uses_ldq; // @[tracegen.scala:32:20]
reg rob_uop_31_uses_stq; // @[tracegen.scala:32:20]
reg rob_bsy_0; // @[tracegen.scala:33:25]
reg rob_bsy_1; // @[tracegen.scala:33:25]
reg rob_bsy_2; // @[tracegen.scala:33:25]
reg rob_bsy_3; // @[tracegen.scala:33:25]
reg rob_bsy_4; // @[tracegen.scala:33:25]
reg rob_bsy_5; // @[tracegen.scala:33:25]
reg rob_bsy_6; // @[tracegen.scala:33:25]
reg rob_bsy_7; // @[tracegen.scala:33:25]
reg rob_bsy_8; // @[tracegen.scala:33:25]
reg rob_bsy_9; // @[tracegen.scala:33:25]
reg rob_bsy_10; // @[tracegen.scala:33:25]
reg rob_bsy_11; // @[tracegen.scala:33:25]
reg rob_bsy_12; // @[tracegen.scala:33:25]
reg rob_bsy_13; // @[tracegen.scala:33:25]
reg rob_bsy_14; // @[tracegen.scala:33:25]
reg rob_bsy_15; // @[tracegen.scala:33:25]
reg rob_bsy_16; // @[tracegen.scala:33:25]
reg rob_bsy_17; // @[tracegen.scala:33:25]
reg rob_bsy_18; // @[tracegen.scala:33:25]
reg rob_bsy_19; // @[tracegen.scala:33:25]
reg rob_bsy_20; // @[tracegen.scala:33:25]
reg rob_bsy_21; // @[tracegen.scala:33:25]
reg rob_bsy_22; // @[tracegen.scala:33:25]
reg rob_bsy_23; // @[tracegen.scala:33:25]
reg rob_bsy_24; // @[tracegen.scala:33:25]
reg rob_bsy_25; // @[tracegen.scala:33:25]
reg rob_bsy_26; // @[tracegen.scala:33:25]
reg rob_bsy_27; // @[tracegen.scala:33:25]
reg rob_bsy_28; // @[tracegen.scala:33:25]
reg rob_bsy_29; // @[tracegen.scala:33:25]
reg rob_bsy_30; // @[tracegen.scala:33:25]
reg rob_bsy_31; // @[tracegen.scala:33:25]
reg [4:0] rob_head; // @[tracegen.scala:34:25]
assign io_lsu_rob_head_idx_0 = rob_head; // @[tracegen.scala:19:7, :34:25]
reg [4:0] rob_tail; // @[tracegen.scala:35:25]
assign io_lsu_rob_pnr_idx_0 = rob_tail; // @[tracegen.scala:19:7, :35:25]
assign tracegen_uop_rob_idx = rob_tail; // @[tracegen.scala:35:25, :55:30]
reg rob_wait_till_empty; // @[tracegen.scala:36:36]
wire _ready_for_amo_T = rob_tail == rob_head; // @[tracegen.scala:34:25, :35:25, :37:32]
wire ready_for_amo = _ready_for_amo_T & io_lsu_fencei_rdy_0; // @[tracegen.scala:19:7, :37:{32,45}]
wire [31:0] _GEN = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[tracegen.scala:33:25, :47:29]
wire _io_tracegen_req_ready_T = ~_GEN[rob_tail]; // @[tracegen.scala:35:25, :47:29]
wire _io_tracegen_req_ready_T_1 = ~rob_wait_till_empty; // @[tracegen.scala:36:36, :48:5]
wire _io_tracegen_req_ready_T_2 = _io_tracegen_req_ready_T & _io_tracegen_req_ready_T_1; // @[tracegen.scala:47:{29,48}, :48:5]
wire _T_1 = io_tracegen_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_3; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_3 = _T_1; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_40; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_40 = _T_1; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_66; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_66 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_7; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_7 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_30; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_30 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_5; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_5 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_57; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_57 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_80; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_80 = _T_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_28; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_28 = _T_1; // @[package.scala:16:47]
wire _T_2 = io_tracegen_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_4; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_4 = _T_2; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_41; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_41 = _T_2; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_67; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_67 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_8 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_31 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_6 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_1; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_1 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_58; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_58 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_81; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_81 = _T_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_29; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_29 = _T_2; // @[package.scala:16:47]
wire _T_3 = io_tracegen_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_5; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_5 = _T_3; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_42; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_42 = _T_3; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_68; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_68 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_9 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_32 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_7 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_2; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_2 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_59; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_59 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_82; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_82 = _T_3; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_30; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_30 = _T_3; // @[package.scala:16:47]
wire _T_4 = io_tracegen_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_6; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_6 = _T_4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_43; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_43 = _T_4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_69; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_69 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_10 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_33 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_8 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_3; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_3 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_60; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_60 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_83; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_83 = _T_4; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_31; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_31 = _T_4; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_7 = _io_tracegen_req_ready_T_3 | _io_tracegen_req_ready_T_4; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_8 = _io_tracegen_req_ready_T_7 | _io_tracegen_req_ready_T_5; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_9 = _io_tracegen_req_ready_T_8 | _io_tracegen_req_ready_T_6; // @[package.scala:16:47, :81:59]
wire _T_8 = io_tracegen_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_10; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_10 = _T_8; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_47; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_47 = _T_8; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_73; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_73 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_14; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_14 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_37; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_37 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_12; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_12 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_7; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_7 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_64; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_64 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_87; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_87 = _T_8; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_35; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_35 = _T_8; // @[package.scala:16:47]
wire _T_9 = io_tracegen_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_11; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_11 = _T_9; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_48; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_48 = _T_9; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_74; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_74 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_15 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_38 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_13 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_8; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_8 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_65; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_65 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_88; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_88 = _T_9; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_36; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_36 = _T_9; // @[package.scala:16:47]
wire _T_10 = io_tracegen_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_12; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_12 = _T_10; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_49; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_49 = _T_10; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_75; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_75 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_16 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_39 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_14 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_9; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_9 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_66; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_66 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_89; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_89 = _T_10; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_37; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_37 = _T_10; // @[package.scala:16:47]
wire _T_11 = io_tracegen_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_13; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_13 = _T_11; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_50; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_50 = _T_11; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_76; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_76 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_17 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_40 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_15 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_10; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_10 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_67; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_67 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_90; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_90 = _T_11; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_38; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_38 = _T_11; // @[package.scala:16:47]
wire _T_12 = io_tracegen_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_14; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_14 = _T_12; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_51; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_51 = _T_12; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_77; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_77 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_18 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_41 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_16 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_is_amo_T_11; // @[package.scala:16:47]
assign _tracegen_uop_is_amo_T_11 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_68; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_68 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_91; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_91 = _T_12; // @[package.scala:16:47]
wire _tracegen_uop_uses_stq_T_39; // @[package.scala:16:47]
assign _tracegen_uop_uses_stq_T_39 = _T_12; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_15 = _io_tracegen_req_ready_T_10 | _io_tracegen_req_ready_T_11; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_16 = _io_tracegen_req_ready_T_15 | _io_tracegen_req_ready_T_12; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_17 = _io_tracegen_req_ready_T_16 | _io_tracegen_req_ready_T_13; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_18 = _io_tracegen_req_ready_T_17 | _io_tracegen_req_ready_T_14; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_19 = _io_tracegen_req_ready_T_9 | _io_tracegen_req_ready_T_18; // @[package.scala:81:59]
wire _T_18 = io_tracegen_req_bits_cmd_0 == 5'h6; // @[tracegen.scala:19:7, :49:85]
wire _io_tracegen_req_ready_T_20; // @[tracegen.scala:49:85]
assign _io_tracegen_req_ready_T_20 = _T_18; // @[tracegen.scala:49:85]
wire _io_tracegen_req_ready_T_35; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_35 = _T_18; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_2 = _T_18; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_52; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_52 = _T_18; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_21 = _io_tracegen_req_ready_T_19 | _io_tracegen_req_ready_T_20; // @[Consts.scala:87:44]
wire _T_20 = io_tracegen_req_bits_cmd_0 == 5'h7; // @[tracegen.scala:19:7, :49:123]
wire _io_tracegen_req_ready_T_22; // @[tracegen.scala:49:123]
assign _io_tracegen_req_ready_T_22 = _T_20; // @[tracegen.scala:49:123]
wire _io_tracegen_req_ready_T_36; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_36 = _T_20; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_64; // @[Consts.scala:90:66]
assign _io_tracegen_req_ready_T_64 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_3 = _T_20; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:66]
assign _tracegen_uop_uses_ldq_T_28 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:66]
assign _tracegen_uop_uses_stq_T_3 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_is_amo_T_17; // @[tracegen.scala:65:92]
assign _tracegen_uop_is_amo_T_17 = _T_20; // @[tracegen.scala:49:123, :65:92]
wire _tracegen_uop_uses_ldq_T_53; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_53 = _T_20; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_78; // @[Consts.scala:90:66]
assign _tracegen_uop_uses_ldq_T_78 = _T_20; // @[Consts.scala:90:66]
wire _tracegen_uop_uses_stq_T_26; // @[Consts.scala:90:66]
assign _tracegen_uop_uses_stq_T_26 = _T_20; // @[Consts.scala:90:66]
wire _io_tracegen_req_ready_T_23 = _io_tracegen_req_ready_T_21 | _io_tracegen_req_ready_T_22; // @[tracegen.scala:49:{57,95,123}]
wire _io_tracegen_req_ready_T_24 = ~_io_tracegen_req_ready_T_23; // @[tracegen.scala:49:{23,95}]
wire _io_tracegen_req_ready_T_25 = ready_for_amo | _io_tracegen_req_ready_T_24; // @[tracegen.scala:37:45, :49:{20,23}]
wire _io_tracegen_req_ready_T_26 = _io_tracegen_req_ready_T_2 & _io_tracegen_req_ready_T_25; // @[tracegen.scala:47:48, :48:26, :49:20]
wire _io_tracegen_req_ready_T_27 = &rob_tail; // @[tracegen.scala:35:25, :43:13]
wire [5:0] _GEN_0 = {1'h0, rob_tail} + 6'h1; // @[tracegen.scala:35:25, :43:37]
wire [5:0] _io_tracegen_req_ready_T_28; // @[tracegen.scala:43:37]
assign _io_tracegen_req_ready_T_28 = _GEN_0; // @[tracegen.scala:43:37]
wire [5:0] _rob_tail_T_1; // @[tracegen.scala:43:37]
assign _rob_tail_T_1 = _GEN_0; // @[tracegen.scala:43:37]
wire [4:0] _io_tracegen_req_ready_T_29 = _io_tracegen_req_ready_T_28[4:0]; // @[tracegen.scala:43:37]
wire [4:0] _io_tracegen_req_ready_T_30 = _io_tracegen_req_ready_T_27 ? 5'h0 : _io_tracegen_req_ready_T_29; // @[tracegen.scala:43:{8,13,37}]
wire _io_tracegen_req_ready_T_31 = _io_tracegen_req_ready_T_30 != rob_head; // @[tracegen.scala:34:25, :43:8, :50:32]
wire _io_tracegen_req_ready_T_32 = _io_tracegen_req_ready_T_26 & _io_tracegen_req_ready_T_31; // @[tracegen.scala:48:26, :49:135, :50:32]
wire _GEN_1 = io_tracegen_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_33; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_33 = _GEN_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T = _GEN_1; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_50; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_50 = _GEN_1; // @[package.scala:16:47]
wire _GEN_2 = io_tracegen_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_34; // @[package.scala:16:47]
assign _io_tracegen_req_ready_T_34 = _GEN_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_1 = _GEN_2; // @[package.scala:16:47]
wire _tracegen_uop_uses_ldq_T_51; // @[package.scala:16:47]
assign _tracegen_uop_uses_ldq_T_51 = _GEN_2; // @[package.scala:16:47]
wire _io_tracegen_req_ready_T_37 = _io_tracegen_req_ready_T_33 | _io_tracegen_req_ready_T_34; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_38 = _io_tracegen_req_ready_T_37 | _io_tracegen_req_ready_T_35; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_39 = _io_tracegen_req_ready_T_38 | _io_tracegen_req_ready_T_36; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_44 = _io_tracegen_req_ready_T_40 | _io_tracegen_req_ready_T_41; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_45 = _io_tracegen_req_ready_T_44 | _io_tracegen_req_ready_T_42; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_46 = _io_tracegen_req_ready_T_45 | _io_tracegen_req_ready_T_43; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_52 = _io_tracegen_req_ready_T_47 | _io_tracegen_req_ready_T_48; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_53 = _io_tracegen_req_ready_T_52 | _io_tracegen_req_ready_T_49; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_54 = _io_tracegen_req_ready_T_53 | _io_tracegen_req_ready_T_50; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_55 = _io_tracegen_req_ready_T_54 | _io_tracegen_req_ready_T_51; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_56 = _io_tracegen_req_ready_T_46 | _io_tracegen_req_ready_T_55; // @[package.scala:81:59]
wire _io_tracegen_req_ready_T_57 = _io_tracegen_req_ready_T_39 | _io_tracegen_req_ready_T_56; // @[package.scala:81:59]
wire _io_tracegen_req_ready_T_58 = io_lsu_ldq_full_0_0 & _io_tracegen_req_ready_T_57; // @[Consts.scala:89:68]
wire _io_tracegen_req_ready_T_59 = ~_io_tracegen_req_ready_T_58; // @[tracegen.scala:51:{5,26}]
wire _io_tracegen_req_ready_T_60 = _io_tracegen_req_ready_T_32 & _io_tracegen_req_ready_T_59; // @[tracegen.scala:49:135, :50:46, :51:5]
wire _GEN_3 = io_tracegen_req_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _io_tracegen_req_ready_T_61; // @[Consts.scala:90:32]
assign _io_tracegen_req_ready_T_61 = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_uses_ldq_T_25; // @[Consts.scala:90:32]
assign _tracegen_uop_uses_ldq_T_25 = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_uses_stq_T; // @[Consts.scala:90:32]
assign _tracegen_uop_uses_stq_T = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_uses_ldq_T_75; // @[Consts.scala:90:32]
assign _tracegen_uop_uses_ldq_T_75 = _GEN_3; // @[Consts.scala:90:32]
wire _tracegen_uop_uses_stq_T_23; // @[Consts.scala:90:32]
assign _tracegen_uop_uses_stq_T_23 = _GEN_3; // @[Consts.scala:90:32]
wire _GEN_4 = io_tracegen_req_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _io_tracegen_req_ready_T_62; // @[Consts.scala:90:49]
assign _io_tracegen_req_ready_T_62 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:49]
assign _tracegen_uop_uses_ldq_T_26 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:49]
assign _tracegen_uop_uses_stq_T_1 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_uses_ldq_T_76; // @[Consts.scala:90:49]
assign _tracegen_uop_uses_ldq_T_76 = _GEN_4; // @[Consts.scala:90:49]
wire _tracegen_uop_uses_stq_T_24; // @[Consts.scala:90:49]
assign _tracegen_uop_uses_stq_T_24 = _GEN_4; // @[Consts.scala:90:49]
wire _io_tracegen_req_ready_T_63 = _io_tracegen_req_ready_T_61 | _io_tracegen_req_ready_T_62; // @[Consts.scala:90:{32,42,49}]
wire _io_tracegen_req_ready_T_65 = _io_tracegen_req_ready_T_63 | _io_tracegen_req_ready_T_64; // @[Consts.scala:90:{42,59,66}]
wire _io_tracegen_req_ready_T_70 = _io_tracegen_req_ready_T_66 | _io_tracegen_req_ready_T_67; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_71 = _io_tracegen_req_ready_T_70 | _io_tracegen_req_ready_T_68; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_72 = _io_tracegen_req_ready_T_71 | _io_tracegen_req_ready_T_69; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_78 = _io_tracegen_req_ready_T_73 | _io_tracegen_req_ready_T_74; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_79 = _io_tracegen_req_ready_T_78 | _io_tracegen_req_ready_T_75; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_80 = _io_tracegen_req_ready_T_79 | _io_tracegen_req_ready_T_76; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_81 = _io_tracegen_req_ready_T_80 | _io_tracegen_req_ready_T_77; // @[package.scala:16:47, :81:59]
wire _io_tracegen_req_ready_T_82 = _io_tracegen_req_ready_T_72 | _io_tracegen_req_ready_T_81; // @[package.scala:81:59]
wire _io_tracegen_req_ready_T_83 = _io_tracegen_req_ready_T_65 | _io_tracegen_req_ready_T_82; // @[Consts.scala:87:44, :90:{59,76}]
wire _io_tracegen_req_ready_T_84 = io_lsu_stq_full_0_0 & _io_tracegen_req_ready_T_83; // @[Consts.scala:90:76]
wire _io_tracegen_req_ready_T_85 = ~_io_tracegen_req_ready_T_84; // @[tracegen.scala:52:{5,26}]
assign _io_tracegen_req_ready_T_86 = _io_tracegen_req_ready_T_60 & _io_tracegen_req_ready_T_85; // @[tracegen.scala:50:46, :51:63, :52:5]
assign io_tracegen_req_ready_0 = _io_tracegen_req_ready_T_86; // @[tracegen.scala:19:7, :51:63]
assign io_lsu_dis_uops_0_bits_debug_inst_0 = tracegen_uop_debug_inst; // @[tracegen.scala:19:7, :55:30]
wire _tracegen_uop_is_amo_T_18; // @[tracegen.scala:65:64]
assign io_lsu_dis_uops_0_bits_is_amo_0 = tracegen_uop_is_amo; // @[tracegen.scala:19:7, :55:30]
assign io_lsu_dis_uops_0_bits_rob_idx_0 = tracegen_uop_rob_idx; // @[tracegen.scala:19:7, :55:30]
assign io_lsu_dis_uops_0_bits_ldq_idx_0 = tracegen_uop_ldq_idx; // @[tracegen.scala:19:7, :55:30]
assign io_lsu_dis_uops_0_bits_stq_idx_0 = tracegen_uop_stq_idx; // @[tracegen.scala:19:7, :55:30]
assign io_lsu_dis_uops_0_bits_mem_cmd_0 = tracegen_uop_mem_cmd; // @[tracegen.scala:19:7, :55:30]
wire _tracegen_uop_uses_ldq_T_99; // @[tracegen.scala:66:65]
assign io_lsu_dis_uops_0_bits_uses_ldq_0 = tracegen_uop_uses_ldq; // @[tracegen.scala:19:7, :55:30]
wire _tracegen_uop_uses_stq_T_45; // @[Consts.scala:90:76]
assign io_lsu_dis_uops_0_bits_uses_stq_0 = tracegen_uop_uses_stq; // @[tracegen.scala:19:7, :55:30]
wire _tracegen_uop_uses_ldq_T_4 = _tracegen_uop_uses_ldq_T | _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_5 = _tracegen_uop_uses_ldq_T_4 | _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_6 = _tracegen_uop_uses_ldq_T_5 | _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_11 = _tracegen_uop_uses_ldq_T_7 | _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_12 = _tracegen_uop_uses_ldq_T_11 | _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_13 = _tracegen_uop_uses_ldq_T_12 | _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_19 = _tracegen_uop_uses_ldq_T_14 | _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_20 = _tracegen_uop_uses_ldq_T_19 | _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_21 = _tracegen_uop_uses_ldq_T_20 | _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_22 = _tracegen_uop_uses_ldq_T_21 | _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_23 = _tracegen_uop_uses_ldq_T_13 | _tracegen_uop_uses_ldq_T_22; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_24 = _tracegen_uop_uses_ldq_T_6 | _tracegen_uop_uses_ldq_T_23; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_27 = _tracegen_uop_uses_ldq_T_25 | _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_uses_ldq_T_29 = _tracegen_uop_uses_ldq_T_27 | _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_uses_ldq_T_34 = _tracegen_uop_uses_ldq_T_30 | _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_35 = _tracegen_uop_uses_ldq_T_34 | _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_36 = _tracegen_uop_uses_ldq_T_35 | _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_42 = _tracegen_uop_uses_ldq_T_37 | _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_43 = _tracegen_uop_uses_ldq_T_42 | _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_44 = _tracegen_uop_uses_ldq_T_43 | _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_45 = _tracegen_uop_uses_ldq_T_44 | _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_46 = _tracegen_uop_uses_ldq_T_36 | _tracegen_uop_uses_ldq_T_45; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_47 = _tracegen_uop_uses_ldq_T_29 | _tracegen_uop_uses_ldq_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _tracegen_uop_uses_ldq_T_48 = ~_tracegen_uop_uses_ldq_T_47; // @[Consts.scala:90:76]
wire _tracegen_uop_uses_ldq_T_49 = _tracegen_uop_uses_ldq_T_24 & _tracegen_uop_uses_ldq_T_48; // @[Consts.scala:89:68]
wire _tracegen_uop_uses_stq_T_2 = _tracegen_uop_uses_stq_T | _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_uses_stq_T_4 = _tracegen_uop_uses_stq_T_2 | _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_uses_stq_T_9 = _tracegen_uop_uses_stq_T_5 | _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_10 = _tracegen_uop_uses_stq_T_9 | _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_11 = _tracegen_uop_uses_stq_T_10 | _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_17 = _tracegen_uop_uses_stq_T_12 | _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_18 = _tracegen_uop_uses_stq_T_17 | _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_19 = _tracegen_uop_uses_stq_T_18 | _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_20 = _tracegen_uop_uses_stq_T_19 | _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_21 = _tracegen_uop_uses_stq_T_11 | _tracegen_uop_uses_stq_T_20; // @[package.scala:81:59]
wire _tracegen_uop_uses_stq_T_22 = _tracegen_uop_uses_stq_T_4 | _tracegen_uop_uses_stq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
assign tracegen_uop_debug_inst = {26'h0, io_tracegen_req_bits_tag_0}; // @[tracegen.scala:19:7, :55:30, :59:29]
wire _tracegen_uop_is_amo_T_4 = _tracegen_uop_is_amo_T | _tracegen_uop_is_amo_T_1; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_5 = _tracegen_uop_is_amo_T_4 | _tracegen_uop_is_amo_T_2; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_6 = _tracegen_uop_is_amo_T_5 | _tracegen_uop_is_amo_T_3; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_12 = _tracegen_uop_is_amo_T_7 | _tracegen_uop_is_amo_T_8; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_13 = _tracegen_uop_is_amo_T_12 | _tracegen_uop_is_amo_T_9; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_14 = _tracegen_uop_is_amo_T_13 | _tracegen_uop_is_amo_T_10; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_15 = _tracegen_uop_is_amo_T_14 | _tracegen_uop_is_amo_T_11; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_is_amo_T_16 = _tracegen_uop_is_amo_T_6 | _tracegen_uop_is_amo_T_15; // @[package.scala:81:59]
assign _tracegen_uop_is_amo_T_18 = _tracegen_uop_is_amo_T_16 | _tracegen_uop_is_amo_T_17; // @[Consts.scala:87:44]
assign tracegen_uop_is_amo = _tracegen_uop_is_amo_T_18; // @[tracegen.scala:55:30, :65:64]
wire _tracegen_uop_uses_ldq_T_54 = _tracegen_uop_uses_ldq_T_50 | _tracegen_uop_uses_ldq_T_51; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_55 = _tracegen_uop_uses_ldq_T_54 | _tracegen_uop_uses_ldq_T_52; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_56 = _tracegen_uop_uses_ldq_T_55 | _tracegen_uop_uses_ldq_T_53; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_61 = _tracegen_uop_uses_ldq_T_57 | _tracegen_uop_uses_ldq_T_58; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_62 = _tracegen_uop_uses_ldq_T_61 | _tracegen_uop_uses_ldq_T_59; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_63 = _tracegen_uop_uses_ldq_T_62 | _tracegen_uop_uses_ldq_T_60; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_69 = _tracegen_uop_uses_ldq_T_64 | _tracegen_uop_uses_ldq_T_65; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_70 = _tracegen_uop_uses_ldq_T_69 | _tracegen_uop_uses_ldq_T_66; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_71 = _tracegen_uop_uses_ldq_T_70 | _tracegen_uop_uses_ldq_T_67; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_72 = _tracegen_uop_uses_ldq_T_71 | _tracegen_uop_uses_ldq_T_68; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_73 = _tracegen_uop_uses_ldq_T_63 | _tracegen_uop_uses_ldq_T_72; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_74 = _tracegen_uop_uses_ldq_T_56 | _tracegen_uop_uses_ldq_T_73; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_77 = _tracegen_uop_uses_ldq_T_75 | _tracegen_uop_uses_ldq_T_76; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_uses_ldq_T_79 = _tracegen_uop_uses_ldq_T_77 | _tracegen_uop_uses_ldq_T_78; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_uses_ldq_T_84 = _tracegen_uop_uses_ldq_T_80 | _tracegen_uop_uses_ldq_T_81; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_85 = _tracegen_uop_uses_ldq_T_84 | _tracegen_uop_uses_ldq_T_82; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_86 = _tracegen_uop_uses_ldq_T_85 | _tracegen_uop_uses_ldq_T_83; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_92 = _tracegen_uop_uses_ldq_T_87 | _tracegen_uop_uses_ldq_T_88; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_93 = _tracegen_uop_uses_ldq_T_92 | _tracegen_uop_uses_ldq_T_89; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_94 = _tracegen_uop_uses_ldq_T_93 | _tracegen_uop_uses_ldq_T_90; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_95 = _tracegen_uop_uses_ldq_T_94 | _tracegen_uop_uses_ldq_T_91; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_ldq_T_96 = _tracegen_uop_uses_ldq_T_86 | _tracegen_uop_uses_ldq_T_95; // @[package.scala:81:59]
wire _tracegen_uop_uses_ldq_T_97 = _tracegen_uop_uses_ldq_T_79 | _tracegen_uop_uses_ldq_T_96; // @[Consts.scala:87:44, :90:{59,76}]
wire _tracegen_uop_uses_ldq_T_98 = ~_tracegen_uop_uses_ldq_T_97; // @[Consts.scala:90:76]
assign _tracegen_uop_uses_ldq_T_99 = _tracegen_uop_uses_ldq_T_74 & _tracegen_uop_uses_ldq_T_98; // @[Consts.scala:89:68]
assign tracegen_uop_uses_ldq = _tracegen_uop_uses_ldq_T_99; // @[tracegen.scala:55:30, :66:65]
wire _tracegen_uop_uses_stq_T_25 = _tracegen_uop_uses_stq_T_23 | _tracegen_uop_uses_stq_T_24; // @[Consts.scala:90:{32,42,49}]
wire _tracegen_uop_uses_stq_T_27 = _tracegen_uop_uses_stq_T_25 | _tracegen_uop_uses_stq_T_26; // @[Consts.scala:90:{42,59,66}]
wire _tracegen_uop_uses_stq_T_32 = _tracegen_uop_uses_stq_T_28 | _tracegen_uop_uses_stq_T_29; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_33 = _tracegen_uop_uses_stq_T_32 | _tracegen_uop_uses_stq_T_30; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_34 = _tracegen_uop_uses_stq_T_33 | _tracegen_uop_uses_stq_T_31; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_40 = _tracegen_uop_uses_stq_T_35 | _tracegen_uop_uses_stq_T_36; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_41 = _tracegen_uop_uses_stq_T_40 | _tracegen_uop_uses_stq_T_37; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_42 = _tracegen_uop_uses_stq_T_41 | _tracegen_uop_uses_stq_T_38; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_43 = _tracegen_uop_uses_stq_T_42 | _tracegen_uop_uses_stq_T_39; // @[package.scala:16:47, :81:59]
wire _tracegen_uop_uses_stq_T_44 = _tracegen_uop_uses_stq_T_34 | _tracegen_uop_uses_stq_T_43; // @[package.scala:81:59]
assign _tracegen_uop_uses_stq_T_45 = _tracegen_uop_uses_stq_T_27 | _tracegen_uop_uses_stq_T_44; // @[Consts.scala:87:44, :90:{59,76}]
assign tracegen_uop_uses_stq = _tracegen_uop_uses_stq_T_45; // @[Consts.scala:90:76]
wire _T = io_tracegen_req_ready_0 & io_tracegen_req_valid_0; // @[Decoupled.scala:51:35]
assign _io_lsu_dis_uops_0_valid_T = _T; // @[Decoupled.scala:51:35]
wire _io_lsu_agen_0_valid_T; // @[Decoupled.scala:51:35]
assign _io_lsu_agen_0_valid_T = _T; // @[Decoupled.scala:51:35]
wire _io_lsu_dgen_0_valid_T; // @[Decoupled.scala:51:35]
assign _io_lsu_dgen_0_valid_T = _T; // @[Decoupled.scala:51:35]
assign io_lsu_dis_uops_0_valid_0 = _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35]
wire _rob_tail_T = &rob_tail; // @[tracegen.scala:35:25, :43:13]
wire [4:0] _rob_tail_T_2 = _rob_tail_T_1[4:0]; // @[tracegen.scala:43:37]
wire [4:0] _rob_tail_T_3 = _rob_tail_T ? 5'h0 : _rob_tail_T_2; // @[tracegen.scala:43:{8,13,37}]
wire _io_lsu_commit_valids_0_T = ~_GEN[rob_head]; // @[tracegen.scala:34:25, :47:29, :92:31]
wire _io_lsu_commit_valids_0_T_1 = rob_head != rob_tail; // @[tracegen.scala:34:25, :35:25, :92:62]
wire _io_lsu_commit_valids_0_T_2 = _io_lsu_commit_valids_0_T & _io_lsu_commit_valids_0_T_1; // @[tracegen.scala:92:{31,50,62}]
wire [31:0] _GEN_5 = {{rob_respd_31}, {rob_respd_30}, {rob_respd_29}, {rob_respd_28}, {rob_respd_27}, {rob_respd_26}, {rob_respd_25}, {rob_respd_24}, {rob_respd_23}, {rob_respd_22}, {rob_respd_21}, {rob_respd_20}, {rob_respd_19}, {rob_respd_18}, {rob_respd_17}, {rob_respd_16}, {rob_respd_15}, {rob_respd_14}, {rob_respd_13}, {rob_respd_12}, {rob_respd_11}, {rob_respd_10}, {rob_respd_9}, {rob_respd_8}, {rob_respd_7}, {rob_respd_6}, {rob_respd_5}, {rob_respd_4}, {rob_respd_3}, {rob_respd_2}, {rob_respd_1}, {rob_respd_0}}; // @[tracegen.scala:31:26, :92:75]
assign _io_lsu_commit_valids_0_T_3 = _io_lsu_commit_valids_0_T_2 & _GEN_5[rob_head]; // @[tracegen.scala:34:25, :92:{50,75}]
assign io_lsu_commit_valids_0_0 = _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:19:7, :92:75]
wire [31:0][31:0] _GEN_6 = {{rob_uop_31_debug_inst}, {rob_uop_30_debug_inst}, {rob_uop_29_debug_inst}, {rob_uop_28_debug_inst}, {rob_uop_27_debug_inst}, {rob_uop_26_debug_inst}, {rob_uop_25_debug_inst}, {rob_uop_24_debug_inst}, {rob_uop_23_debug_inst}, {rob_uop_22_debug_inst}, {rob_uop_21_debug_inst}, {rob_uop_20_debug_inst}, {rob_uop_19_debug_inst}, {rob_uop_18_debug_inst}, {rob_uop_17_debug_inst}, {rob_uop_16_debug_inst}, {rob_uop_15_debug_inst}, {rob_uop_14_debug_inst}, {rob_uop_13_debug_inst}, {rob_uop_12_debug_inst}, {rob_uop_11_debug_inst}, {rob_uop_10_debug_inst}, {rob_uop_9_debug_inst}, {rob_uop_8_debug_inst}, {rob_uop_7_debug_inst}, {rob_uop_6_debug_inst}, {rob_uop_5_debug_inst}, {rob_uop_4_debug_inst}, {rob_uop_3_debug_inst}, {rob_uop_2_debug_inst}, {rob_uop_1_debug_inst}, {rob_uop_0_debug_inst}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_debug_inst_0 = _GEN_6[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire [31:0] _GEN_7 = {{rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_is_amo_0 = _GEN_7[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire [31:0][4:0] _GEN_8 = {{rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_rob_idx_0 = _GEN_8[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire [31:0][3:0] _GEN_9 = {{rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_ldq_idx_0 = _GEN_9[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire [31:0][3:0] _GEN_10 = {{rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_stq_idx_0 = _GEN_10[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire [31:0][4:0] _GEN_11 = {{rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_mem_cmd_0 = _GEN_11[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire [31:0] _GEN_12 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_uses_ldq_0 = _GEN_12[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire [31:0] _GEN_13 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[tracegen.scala:32:20, :93:27]
assign io_lsu_commit_uops_0_uses_stq_0 = _GEN_13[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27]
wire _rob_head_T = &rob_head; // @[tracegen.scala:34:25, :43:13]
wire [5:0] _rob_head_T_1 = {1'h0, rob_head} + 6'h1; // @[tracegen.scala:34:25, :43:37]
wire [4:0] _rob_head_T_2 = _rob_head_T_1[4:0]; // @[tracegen.scala:43:37]
wire [4:0] _rob_head_T_3 = _rob_head_T ? 5'h0 : _rob_head_T_2; // @[tracegen.scala:43:{8,13,37}]
wire [31:0][4:0] _GEN_14 = {{rob_31_cmd}, {rob_30_cmd}, {rob_29_cmd}, {rob_28_cmd}, {rob_27_cmd}, {rob_26_cmd}, {rob_25_cmd}, {rob_24_cmd}, {rob_23_cmd}, {rob_22_cmd}, {rob_21_cmd}, {rob_20_cmd}, {rob_19_cmd}, {rob_18_cmd}, {rob_17_cmd}, {rob_16_cmd}, {rob_15_cmd}, {rob_14_cmd}, {rob_13_cmd}, {rob_12_cmd}, {rob_11_cmd}, {rob_10_cmd}, {rob_9_cmd}, {rob_8_cmd}, {rob_7_cmd}, {rob_6_cmd}, {rob_5_cmd}, {rob_4_cmd}, {rob_3_cmd}, {rob_2_cmd}, {rob_1_cmd}, {rob_0_cmd}}; // @[tracegen.scala:30:16, :102:74] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_26( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34]
wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34]
wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34]
wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1492 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1492; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1492; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1565 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1565; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1565; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1565; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [16:0] a_set; // @[Monitor.scala:626:34]
wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [135:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1418 = _T_1492 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1418 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1418 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1418 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1418 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1418 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [16:0] d_clr; // @[Monitor.scala:664:34]
wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1464 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1464 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1433 = _T_1565 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1433 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1433 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1433 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [16:0] d_clr_1; // @[Monitor.scala:774:34]
wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1536 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1536 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire _T_1518 = _T_1565 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1518 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1518 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1518 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ReservationStation.scala:
package gemmini
import chisel3._
import chisel3.util._
import freechips.rocketchip.tile.RoCCCommand
import freechips.rocketchip.util.PlusArg
import GemminiISA._
import Util._
import midas.targetutils.PerfCounter
import midas.targetutils.SynthesizePrintf
// TODO unify this class with GemminiCmdWithDeps
class ReservationStationIssue[T <: Data](cmd_t: T, id_width: Int) extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
val cmd = Output(cmd_t.cloneType)
val rob_id = Output(UInt(id_width.W))
def fire = valid && ready
}
// TODO we don't need to store the full command in here. We should be able to release the command directly into the relevant controller and only store the associated metadata in the ROB. This would reduce the size considerably
class ReservationStation[T <: Data : Arithmetic, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V],
cmd_t: GemminiCmd) extends Module {
import config._
val block_rows = tileRows * meshRows
val block_cols = tileColumns * meshColumns
val max_instructions_completed_per_type_per_cycle = 2 // Every cycle, at most two instructions of a single "type" (ld/st/ex) can be completed: one through the io.completed port, and the other if it is a "complete-on-issue" instruction
val io = IO(new Bundle {
val alloc = Flipped(Decoupled(cmd_t.cloneType))
val completed = Flipped(Valid(UInt(ROB_ID_WIDTH.W)))
val issue = new Bundle {
val ld = new ReservationStationIssue(cmd_t, ROB_ID_WIDTH)
val st = new ReservationStationIssue(cmd_t, ROB_ID_WIDTH)
val ex = new ReservationStationIssue(cmd_t, ROB_ID_WIDTH)
}
val conv_ld_completed = Output(UInt(log2Up(max_instructions_completed_per_type_per_cycle+1).W))
val conv_ex_completed = Output(UInt(log2Up(max_instructions_completed_per_type_per_cycle+1).W))
val conv_st_completed = Output(UInt(log2Up(max_instructions_completed_per_type_per_cycle+1).W))
val matmul_ld_completed = Output(UInt(log2Up(max_instructions_completed_per_type_per_cycle+1).W))
val matmul_ex_completed = Output(UInt(log2Up(max_instructions_completed_per_type_per_cycle+1).W))
val matmul_st_completed = Output(UInt(log2Up(max_instructions_completed_per_type_per_cycle+1).W))
val busy = Output(Bool())
val counter = new CounterEventIO()
})
// TODO make this a ChiselEnum
val ldq :: exq :: stq :: Nil = Enum(3)
val q_t = ldq.cloneType
class OpT extends Bundle {
val start = local_addr_t.cloneType
val end = local_addr_t.cloneType
val wraps_around = Bool()
def overlaps(other: OpT): Bool = {
((other.start <= start && (start < other.end || other.wraps_around)) ||
(start <= other.start && (other.start < end || wraps_around))) &&
!(start.is_garbage() || other.start.is_garbage()) // TODO the "is_garbage" check might not really be necessary
}
}
val instructions_allocated = RegInit(0.U(32.W))
when (io.alloc.fire) {
instructions_allocated := instructions_allocated + 1.U
}
dontTouch(instructions_allocated)
class Entry extends Bundle {
val q = q_t.cloneType
val is_config = Bool()
val opa = UDValid(new OpT)
val opa_is_dst = Bool()
val opb = UDValid(new OpT)
// val op1 = UDValid(new OpT)
// val op1 = UDValid(new OpT)
// val op2 = UDValid(new OpT)
// val dst = UDValid(new OpT)
val issued = Bool()
val complete_on_issue = Bool()
val cmd = cmd_t.cloneType
// instead of one large deps vector, we need 3 separate ones if we want
// easy indexing, small area while allowing them to be different sizes
val deps_ld = Vec(reservation_station_entries_ld, Bool())
val deps_ex = Vec(reservation_station_entries_ex, Bool())
val deps_st = Vec(reservation_station_entries_st, Bool())
def ready(dummy: Int = 0): Bool = !(deps_ld.reduce(_ || _) || deps_ex.reduce(_ || _) || deps_st.reduce(_ || _))
// Debugging signals
val allocated_at = UInt(instructions_allocated.getWidth.W)
}
assert(isPow2(reservation_station_entries_ld))
assert(isPow2(reservation_station_entries_ex))
assert(isPow2(reservation_station_entries_st))
val entries_ld = Reg(Vec(reservation_station_entries_ld, UDValid(new Entry)))
val entries_ex = Reg(Vec(reservation_station_entries_ex, UDValid(new Entry)))
val entries_st = Reg(Vec(reservation_station_entries_st, UDValid(new Entry)))
val entries = entries_ld ++ entries_ex ++ entries_st
val empty_ld = !entries_ld.map(_.valid).reduce(_ || _)
val empty_ex = !entries_ex.map(_.valid).reduce(_ || _)
val empty_st = !entries_st.map(_.valid).reduce(_ || _)
val full_ld = entries_ld.map(_.valid).reduce(_ && _)
val full_ex = entries_ex.map(_.valid).reduce(_ && _)
val full_st = entries_st.map(_.valid).reduce(_ && _)
val empty = !entries.map(_.valid).reduce(_ || _)
val full = entries.map(_.valid).reduce(_ && _)
val utilization = PopCount(entries.map(e => e.valid)) // TODO it may be cheaper to count the utilization in a register, rather than performing a PopCount
val solitary_preload = RegInit(false.B) // This checks whether or not the reservation station received a "preload" instruction, but hasn't yet received the following "compute" instruction
io.busy := !empty && !(utilization === 1.U && solitary_preload)
// Tell the conv and matmul FSMs if any of their issued instructions completed
val conv_ld_issue_completed = WireInit(false.B)
val conv_st_issue_completed = WireInit(false.B)
val conv_ex_issue_completed = WireInit(false.B)
val conv_ld_completed = WireInit(false.B)
val conv_st_completed = WireInit(false.B)
val conv_ex_completed = WireInit(false.B)
val matmul_ld_issue_completed = WireInit(false.B)
val matmul_st_issue_completed = WireInit(false.B)
val matmul_ex_issue_completed = WireInit(false.B)
val matmul_ld_completed = WireInit(false.B)
val matmul_st_completed = WireInit(false.B)
val matmul_ex_completed = WireInit(false.B)
io.conv_ld_completed := conv_ld_issue_completed +& conv_ld_completed
io.conv_st_completed := conv_st_issue_completed +& conv_st_completed
io.conv_ex_completed := conv_ex_issue_completed +& conv_ex_completed
io.matmul_ld_completed := matmul_ld_issue_completed +& matmul_ld_completed
io.matmul_st_completed := matmul_st_issue_completed +& matmul_st_completed
io.matmul_ex_completed := matmul_ex_issue_completed +& matmul_ex_completed
// Config values set by programmer
val a_stride = Reg(UInt(a_stride_bits.W))
val c_stride = Reg(UInt(c_stride_bits.W))
val a_transpose = Reg(Bool())
val ld_block_strides = Reg(Vec(load_states, UInt(block_stride_bits.W)))
val st_block_stride = block_rows.U
val pooling_is_enabled = Reg(Bool())
val ld_pixel_repeats = Reg(Vec(load_states, UInt(pixel_repeats_bits.W))) // This is the ld_pixel_repeat MINUS ONE
val new_entry = Wire(new Entry)
new_entry := DontCare
val new_allocs_oh_ld = Wire(Vec(reservation_station_entries_ld, Bool()))
val new_allocs_oh_ex = Wire(Vec(reservation_station_entries_ex, Bool()))
val new_allocs_oh_st = Wire(Vec(reservation_station_entries_st, Bool()))
val new_entry_oh = new_allocs_oh_ld ++ new_allocs_oh_ex ++ new_allocs_oh_st
new_entry_oh.foreach(_ := false.B)
val alloc_fire = io.alloc.fire
io.alloc.ready := false.B
when (io.alloc.valid) {
val spAddrBits = 32
val cmd = io.alloc.bits.cmd
val funct = cmd.inst.funct
val funct_is_compute = funct === COMPUTE_AND_STAY_CMD || funct === COMPUTE_AND_FLIP_CMD
val config_cmd_type = cmd.rs1(1,0) // TODO magic numbers
new_entry.issued := false.B
new_entry.cmd := io.alloc.bits
new_entry.is_config := funct === CONFIG_CMD
val op1 = Wire(UDValid(new OpT))
op1.valid := false.B
op1.bits := DontCare
val op2 = Wire(UDValid(new OpT))
op2.valid := false.B
op2.bits := DontCare
val dst = Wire(UDValid(new OpT))
dst.valid := false.B
dst.bits := DontCare
assert(!(op1.valid && op2.valid && dst.valid))
new_entry.opa_is_dst := dst.valid
when (dst.valid) {
new_entry.opa := dst
new_entry.opb := Mux(op1.valid, op1, op2)
} .otherwise {
new_entry.opa := Mux(op1.valid, op1, op2)
new_entry.opb := op2
}
op1.valid := funct === PRELOAD_CMD || funct_is_compute
op1.bits.start := cmd.rs1.asTypeOf(local_addr_t)
when (funct === PRELOAD_CMD) {
// TODO check b_transpose here iff WS mode is enabled
val preload_rows = cmd.rs1(48 + log2Up(block_rows + 1) - 1, 48)
op1.bits.end := op1.bits.start + preload_rows
op1.bits.wraps_around := op1.bits.start.add_with_overflow(preload_rows)._2
}.otherwise {
val rows = cmd.rs1(48 + log2Up(block_rows + 1) - 1, 48)
val cols = cmd.rs1(32 + log2Up(block_cols + 1) - 1, 32)
val compute_rows = Mux(a_transpose, cols, rows) * a_stride
op1.bits.end := op1.bits.start + compute_rows
op1.bits.wraps_around := op1.bits.start.add_with_overflow(compute_rows)._2
}
op2.valid := funct_is_compute || funct === STORE_CMD
op2.bits.start := cmd.rs2.asTypeOf(local_addr_t)
when (funct_is_compute) {
val compute_rows = cmd.rs2(48 + log2Up(block_rows + 1) - 1, 48)
op2.bits.end := op2.bits.start + compute_rows
op2.bits.wraps_around := op2.bits.start.add_with_overflow(compute_rows)._2
}.elsewhen (pooling_is_enabled) {
// If pooling is enabled, then we assume that this command simply mvouts everything in this accumulator bank from
// start to the end of the bank // TODO this won't work when acc_banks =/= 2
val acc_bank = op2.bits.start.acc_bank()
val next_bank_addr = WireInit(0.U.asTypeOf(local_addr_t))
next_bank_addr.is_acc_addr := true.B
next_bank_addr.data := (acc_bank + 1.U) << local_addr_t.accBankRowBits
op2.bits.end := next_bank_addr
op2.bits.wraps_around := next_bank_addr.acc_bank() === 0.U
}.otherwise {
val block_stride = st_block_stride
val mvout_cols = cmd.rs2(32 + mvout_cols_bits - 1, 32)
val mvout_rows = cmd.rs2(48 + mvout_rows_bits - 1, 48)
val mvout_mats = mvout_cols / block_cols.U(mvout_cols_bits.W) + (mvout_cols % block_cols.U =/= 0.U)
val total_mvout_rows = ((mvout_mats - 1.U) * block_stride) + mvout_rows
op2.bits.end := op2.bits.start + total_mvout_rows
op2.bits.wraps_around := pooling_is_enabled || op2.bits.start.add_with_overflow(total_mvout_rows)._2
}
dst.valid := funct === PRELOAD_CMD || funct === LOAD_CMD || funct === LOAD2_CMD || funct === LOAD3_CMD
dst.bits.start := cmd.rs2(31, 0).asTypeOf(local_addr_t)
when (funct === PRELOAD_CMD) {
val preload_rows = cmd.rs2(48 + log2Up(block_rows + 1) - 1, 48) * c_stride
dst.bits.end := dst.bits.start + preload_rows
dst.bits.wraps_around := dst.bits.start.add_with_overflow(preload_rows)._2
}.otherwise {
val id = MuxCase(0.U, Seq((new_entry.cmd.cmd.inst.funct === LOAD2_CMD) -> 1.U,
(new_entry.cmd.cmd.inst.funct === LOAD3_CMD) -> 2.U))
val block_stride = ld_block_strides(id)
val pixel_repeats = ld_pixel_repeats(id)
val mvin_cols = cmd.rs2(32 + mvin_cols_bits - 1, 32)
val mvin_rows = cmd.rs2(48 + mvin_rows_bits - 1, 48)
val mvin_mats = mvin_cols / block_cols.U(mvin_cols_bits.W) + (mvin_cols % block_cols.U =/= 0.U)
val total_mvin_rows = ((mvin_mats - 1.U) * block_stride) + mvin_rows
// TODO We have to know how the LoopConv's internals work here. Our abstractions are leaking
if (has_first_layer_optimizations) {
val start = cmd.rs2(31, 0).asTypeOf(local_addr_t)
// TODO instead of using a floor-sub that's hardcoded to the Scratchpad bank boundaries, we should find some way of letting the programmer specify the start address
dst.bits.start := Mux(start.is_acc_addr, start,
Mux(start.full_sp_addr() > (local_addr_t.spRows / 2).U,
start.floorSub(pixel_repeats, (local_addr_t.spRows / 2).U)._1,
start.floorSub(pixel_repeats, 0.U)._1,
)
)
}
dst.bits.end := dst.bits.start + total_mvin_rows
dst.bits.wraps_around := dst.bits.start.add_with_overflow(total_mvin_rows)._2
}
val is_load = funct === LOAD_CMD || funct === LOAD2_CMD || funct === LOAD3_CMD || (funct === CONFIG_CMD && config_cmd_type === CONFIG_LOAD)
val is_ex = funct === PRELOAD_CMD || funct_is_compute || (funct === CONFIG_CMD && config_cmd_type === CONFIG_EX)
val is_store = funct === STORE_CMD || (funct === CONFIG_CMD && (config_cmd_type === CONFIG_STORE || config_cmd_type === CONFIG_NORM))
val is_norm = funct === CONFIG_CMD && config_cmd_type === CONFIG_NORM // normalization commands are a subset of store commands, so they still go in the store queue
new_entry.q := Mux1H(Seq(
is_load -> ldq,
is_store -> stq,
is_ex -> exq
))
assert(is_load || is_store || is_ex)
assert(ldq < exq && exq < stq)
val not_config = !new_entry.is_config
when (is_load) {
// war (after ex/st) | waw (after ex)
new_entry.deps_ld := VecInit(entries_ld.map { e => e.valid && !e.bits.issued }) // same q
new_entry.deps_ex := VecInit(entries_ex.map { e => e.valid && !new_entry.is_config && (
(new_entry.opa.bits.overlaps(e.bits.opa.bits) && e.bits.opa.valid) || // waw if preload, war if compute
(new_entry.opa.bits.overlaps(e.bits.opb.bits) && e.bits.opb.valid))}) // war
new_entry.deps_st := VecInit(entries_st.map { e => e.valid && e.bits.opa.valid && not_config &&
new_entry.opa.bits.overlaps(e.bits.opa.bits)}) // war
}.elsewhen (is_ex) {
// raw (after ld) | war (after st) | waw (after ld)
new_entry.deps_ld := VecInit(entries_ld.map { e => e.valid && e.bits.opa.valid && not_config && (
new_entry.opa.bits.overlaps(e.bits.opa.bits) || // waw if preload, raw if compute
new_entry.opb.bits.overlaps(e.bits.opa.bits))}) // raw
new_entry.deps_ex := VecInit(entries_ex.map { e => e.valid && !e.bits.issued }) // same q
new_entry.deps_st := VecInit(entries_st.map { e => e.valid && e.bits.opa.valid && not_config && new_entry.opa_is_dst &&
new_entry.opa.bits.overlaps(e.bits.opa.bits)}) // war
}.otherwise {
// raw (after ld/ex)
new_entry.deps_ld := VecInit(entries_ld.map { e => e.valid && e.bits.opa.valid && not_config &&
new_entry.opa.bits.overlaps(e.bits.opa.bits)}) // raw
new_entry.deps_ex := VecInit(entries_ex.map { e => e.valid && e.bits.opa.valid && not_config &&
e.bits.opa_is_dst && new_entry.opa.bits.overlaps(e.bits.opa.bits)}) // raw only if ex is preload
new_entry.deps_st := VecInit(entries_st.map { e => e.valid && !e.bits.issued }) // same q
}
new_entry.allocated_at := instructions_allocated
new_entry.complete_on_issue := new_entry.is_config && new_entry.q =/= exq
Seq(
(ldq, entries_ld, new_allocs_oh_ld, reservation_station_entries_ld),
(exq, entries_ex, new_allocs_oh_ex, reservation_station_entries_ex),
(stq, entries_st, new_allocs_oh_st, reservation_station_entries_st))
.foreach { case (q, entries_type, new_allocs_type, entries_count) =>
when (new_entry.q === q) {
val is_full = PopCount(Seq(dst.valid, op1.valid, op2.valid)) > 1.U
when (q =/= exq) { assert(!is_full) }
// looking for the first invalid entry
val alloc_id = MuxCase((entries_count - 1).U, entries_type.zipWithIndex.map { case (e, i) => !e.valid -> i.U })
when (!entries_type(alloc_id).valid) {
io.alloc.ready := true.B
entries_type(alloc_id).valid := true.B
entries_type(alloc_id).bits := new_entry
new_allocs_type(alloc_id) := true.B
}
}
}
when (io.alloc.fire) {
when (new_entry.is_config && new_entry.q === exq) {
a_stride := new_entry.cmd.cmd.rs1(31, 16) // TODO magic numbers // TODO this needs to be kept in sync with ExecuteController.scala
c_stride := new_entry.cmd.cmd.rs2(63, 48) // TODO magic numbers // TODO this needs to be kept in sync with ExecuteController.scala
val set_only_strides = new_entry.cmd.cmd.rs1(7) // TODO magic numbers
when (!set_only_strides) {
a_transpose := new_entry.cmd.cmd.rs1(8) // TODO magic numbers
}
}.elsewhen(new_entry.is_config && new_entry.q === ldq) {
val id = new_entry.cmd.cmd.rs1(4,3) // TODO magic numbers
val block_stride = new_entry.cmd.cmd.rs1(31, 16) // TODO magic numbers
val repeat_pixels = maxOf(new_entry.cmd.cmd.rs1(8 + pixel_repeats_bits - 1, 8), 1.U) // TODO we use a default value of pixel repeats here, for backwards compatibility. However, we should deprecate and remove this default value eventually
ld_block_strides(id) := block_stride
ld_pixel_repeats(id) := repeat_pixels - 1.U
}.elsewhen(new_entry.is_config && new_entry.q === stq && !is_norm) {
val pool_stride = new_entry.cmd.cmd.rs1(5, 4) // TODO magic numbers
pooling_is_enabled := pool_stride =/= 0.U
}.elsewhen(funct === PRELOAD_CMD) {
solitary_preload := true.B
}.elsewhen(funct_is_compute) {
solitary_preload := false.B
}
}
}
// Issue commands which are ready to be issued
Seq((ldq, io.issue.ld, entries_ld), (exq, io.issue.ex, entries_ex), (stq, io.issue.st, entries_st))
.foreach { case (q, io, entries_type) =>
val issue_valids = entries_type.map(e => e.valid && e.bits.ready() && !e.bits.issued)
val issue_sel = PriorityEncoderOH(issue_valids)
val issue_id = OHToUInt(issue_sel)
val global_issue_id = Cat(q.asUInt, issue_id.pad(log2Up(res_max_per_type)))
assert(q.getWidth == 2)
assert(global_issue_id.getWidth == 2 + log2Up(res_max_per_type))
val issue_entry = Mux1H(issue_sel, entries_type)
io.valid := issue_valids.reduce(_||_)
io.cmd := issue_entry.bits.cmd
// use the most significant 2 bits to indicate instruction type
io.rob_id := global_issue_id
val complete_on_issue = entries_type(issue_id).bits.complete_on_issue
val from_conv_fsm = entries_type(issue_id).bits.cmd.from_conv_fsm
val from_matmul_fsm = entries_type(issue_id).bits.cmd.from_matmul_fsm
when (io.fire) {
entries_type.zipWithIndex.foreach { case (e, i) =>
when (issue_sel(i)) {
e.bits.issued := true.B
e.valid := !e.bits.complete_on_issue
}
}
// Update the "deps" vectors of all instructions which depend on the one that is being issued
Seq((ldq, entries_ld), (exq, entries_ex), (stq, entries_st))
.foreach { case (q_, entries_type_) =>
entries_type_.zipWithIndex.foreach { case (e, i) =>
val deps_type = if (q == ldq) e.bits.deps_ld
else if (q == exq) e.bits.deps_ex else e.bits.deps_st
when (q === q_) {
deps_type(issue_id) := false.B
}.otherwise {
when (issue_entry.bits.complete_on_issue) {
deps_type(issue_id) := false.B
}
}
}
}
// If the instruction completed on issue, then notify the conv/matmul FSMs that another one of their commands
// completed
when (q === ldq) { conv_ld_issue_completed := complete_on_issue && from_conv_fsm }
when (q === stq) { conv_st_issue_completed := complete_on_issue && from_conv_fsm }
when (q === exq) { conv_ex_issue_completed := complete_on_issue && from_conv_fsm }
when (q === ldq) { matmul_ld_issue_completed := complete_on_issue && from_matmul_fsm }
when (q === stq) { matmul_st_issue_completed := complete_on_issue && from_matmul_fsm }
when (q === exq) { matmul_ex_issue_completed := complete_on_issue && from_matmul_fsm }
}
}
// Mark entries as completed once they've returned
when (io.completed.fire) {
val type_width = log2Up(res_max_per_type)
val queue_type = io.completed.bits(type_width + 1, type_width)
val issue_id = io.completed.bits(type_width - 1, 0)
when (queue_type === ldq) {
entries.foreach(_.bits.deps_ld(issue_id) := false.B)
entries_ld(issue_id).valid := false.B
conv_ld_completed := entries_ld(issue_id).bits.cmd.from_conv_fsm
matmul_ld_completed := entries_ld(issue_id).bits.cmd.from_matmul_fsm
assert(entries_ld(issue_id).valid)
}.elsewhen (queue_type === exq) {
entries.foreach(_.bits.deps_ex(issue_id) := false.B)
entries_ex(issue_id).valid := false.B
conv_ex_completed := entries_ex(issue_id).bits.cmd.from_conv_fsm
matmul_ex_completed := entries_ex(issue_id).bits.cmd.from_matmul_fsm
assert(entries_ex(issue_id).valid)
}.elsewhen (queue_type === stq) {
entries.foreach(_.bits.deps_st(issue_id) := false.B)
entries_st(issue_id).valid := false.B
conv_st_completed := entries_st(issue_id).bits.cmd.from_conv_fsm
matmul_st_completed := entries_st(issue_id).bits.cmd.from_matmul_fsm
assert(entries_st(issue_id).valid)
}.otherwise {
assert(queue_type =/= 3.U)
}
}
// Explicitly mark "opb" in all ld/st queues entries as being invalid.
// This helps us to reduce the total reservation table area
Seq(entries_ld, entries_st).foreach { entries_type =>
entries_type.foreach { e =>
e.bits.opb.valid := false.B
e.bits.opb.bits := DontCare
}
}
// val utilization = PopCount(entries.map(e => e.valid))
val utilization_ld_q_unissued = PopCount(entries.map(e => e.valid && !e.bits.issued && e.bits.q === ldq))
val utilization_st_q_unissued = PopCount(entries.map(e => e.valid && !e.bits.issued && e.bits.q === stq))
val utilization_ex_q_unissued = PopCount(entries.map(e => e.valid && !e.bits.issued && e.bits.q === exq))
val utilization_ld_q = PopCount(entries_ld.map(e => e.valid))
val utilization_st_q = PopCount(entries_st.map(e => e.valid))
val utilization_ex_q = PopCount(entries_ex.map(e => e.valid))
val valids = VecInit(entries.map(_.valid))
val functs = VecInit(entries.map(_.bits.cmd.cmd.inst.funct))
val issueds = VecInit(entries.map(_.bits.issued))
val packed_deps = VecInit(entries.map(e =>
Cat(Cat(e.bits.deps_ld.reverse), Cat(e.bits.deps_ex.reverse), Cat(e.bits.deps_st.reverse))))
dontTouch(valids)
dontTouch(functs)
dontTouch(issueds)
dontTouch(packed_deps)
val pop_count_packed_deps = VecInit(entries.map(e => Mux(e.valid,
PopCount(e.bits.deps_ld) + PopCount(e.bits.deps_ex) + PopCount(e.bits.deps_st), 0.U)))
val min_pop_count = pop_count_packed_deps.reduce((acc, d) => minOf(acc, d))
// assert(min_pop_count < 2.U)
dontTouch(pop_count_packed_deps)
dontTouch(min_pop_count)
val cycles_since_issue = RegInit(0.U(16.W))
when (io.issue.ld.fire || io.issue.st.fire || io.issue.ex.fire || !io.busy || io.completed.fire) {
cycles_since_issue := 0.U
}.elsewhen(io.busy) {
cycles_since_issue := cycles_since_issue + 1.U
}
assert(cycles_since_issue < PlusArg("gemmini_timeout", 10000), "pipeline stall")
for (e <- entries) {
dontTouch(e.bits.allocated_at)
}
val cntr = Counter(2000000)
when (cntr.inc()) {
printf(p"Utilization: $utilization\n")
printf(p"Utilization ld q (incomplete): $utilization_ld_q_unissued\n")
printf(p"Utilization st q (incomplete): $utilization_st_q_unissued\n")
printf(p"Utilization ex q (incomplete): $utilization_ex_q_unissued\n")
printf(p"Utilization ld q: $utilization_ld_q\n")
printf(p"Utilization st q: $utilization_st_q\n")
printf(p"Utilization ex q: $utilization_ex_q\n")
if (use_firesim_simulation_counters) {
printf(SynthesizePrintf("Utilization: %d\n", utilization))
printf(SynthesizePrintf("Utilization ld q (incomplete): %d\n", utilization_ld_q_unissued))
printf(SynthesizePrintf("Utilization st q (incomplete): %d\n", utilization_st_q_unissued))
printf(SynthesizePrintf("Utilization ex q (incomplete): %d\n", utilization_ex_q_unissued))
printf(SynthesizePrintf("Utilization ld q: %d\n", utilization_ld_q))
printf(SynthesizePrintf("Utilization st q: %d\n", utilization_st_q))
printf(SynthesizePrintf("Utilization ex q: %d\n", utilization_ex_q))
}
printf(p"Packed deps: $packed_deps\n")
}
if (use_firesim_simulation_counters) {
PerfCounter(io.busy, "reservation_station_busy", "cycles where reservation station has entries")
PerfCounter(!io.alloc.ready, "reservation_station_full", "cycles where reservation station is full")
}
when (reset.asBool) {
entries.foreach(_.valid := false.B)
}
CounterEventIO.init(io.counter)
io.counter.connectExternalCounter(CounterExternal.RESERVATION_STATION_LD_COUNT, utilization_ld_q)
io.counter.connectExternalCounter(CounterExternal.RESERVATION_STATION_ST_COUNT, utilization_st_q)
io.counter.connectExternalCounter(CounterExternal.RESERVATION_STATION_EX_COUNT, utilization_ex_q)
io.counter.connectEventSignal(CounterEvent.RESERVATION_STATION_ACTIVE_CYCLES, io.busy)
io.counter.connectEventSignal(CounterEvent.RESERVATION_STATION_FULL_CYCLES, !io.alloc.ready)
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File LocalAddr.scala:
package gemmini
import chisel3._
import chisel3.util._
class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle {
private val localAddrBits = 32 // TODO magic number
private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries)
private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries)
private val maxAddrBits = spAddrBits max accAddrBits
private val spBankBits = log2Up(sp_banks)
private val spBankRowBits = log2Up(sp_bank_entries)
private val accBankBits = log2Up(acc_banks)
val accBankRowBits = log2Up(acc_bank_entries)
val spRows = sp_banks * sp_bank_entries
val is_acc_addr = Bool()
val accumulate = Bool()
val read_full_acc_row = Bool()
val norm_cmd = NormCmd()
private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth + norm_cmd.getWidth
assert(maxAddrBits + metadata_w < 32)
val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W)
val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W)
val data = UInt(maxAddrBits.W)
def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits)
def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0)
def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits)
def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0)
def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0)
def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0)
def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data
def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this))
def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR &&
(if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B)
def +(other: UInt) = {
require(isPow2(sp_bank_entries)) // TODO remove this requirement
require(isPow2(acc_bank_entries)) // TODO remove this requirement
val result = WireInit(this)
result.data := data + other
result
}
def <=(other: LocalAddr) =
is_acc_addr === other.is_acc_addr &&
Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr())
def <(other: LocalAddr) =
is_acc_addr === other.is_acc_addr &&
Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr())
def >(other: LocalAddr) =
is_acc_addr === other.is_acc_addr &&
Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr())
def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = {
require(isPow2(sp_bank_entries)) // TODO remove this requirement
require(isPow2(acc_bank_entries)) // TODO remove this requirement
val sum = data +& other
val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits))
val result = WireInit(this)
result.data := sum(maxAddrBits - 1, 0)
(result, overflow)
}
// This function can only be used with non-accumulator addresses. Returns both new address and underflow
def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = {
require(isPow2(sp_bank_entries)) // TODO remove this requirement
require(isPow2(acc_bank_entries)) // TODO remove this requirement
val underflow = data < (floor +& other)
val result = WireInit(this)
result.data := Mux(underflow, floor, data - other)
(result, underflow)
}
def make_this_garbage(dummy: Int = 0): Unit = {
is_acc_addr := true.B
accumulate := true.B
read_full_acc_row := true.B
garbage_bit := 1.U
data := ~(0.U(maxAddrBits.W))
}
}
object LocalAddr {
def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = {
// This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience
// function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths
val result = WireInit(t.asTypeOf(local_addr_t))
if (result.garbage_bit.getWidth > 0) result.garbage := 0.U
result
}
def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = {
// This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage
// address
val result = WireInit(cast_to_local_addr(local_addr_t, t))
result.is_acc_addr := false.B
result.accumulate := false.B
result.read_full_acc_row := false.B
// assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses")
result
}
def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = {
// This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage
// address
val result = WireInit(cast_to_local_addr(local_addr_t, t))
result.is_acc_addr := true.B
result.accumulate := accumulate
result.read_full_acc_row := read_full
// assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses")
result
}
def garbage_addr(local_addr_t: LocalAddr): LocalAddr = {
val result = Wire(chiselTypeOf(local_addr_t))
result := DontCare
result.make_this_garbage()
result
}
}
| module ReservationStation( // @[ReservationStation.scala:26:7]
input clock, // @[ReservationStation.scala:26:7]
input reset, // @[ReservationStation.scala:26:7]
output io_alloc_ready, // @[ReservationStation.scala:35:14]
input io_alloc_valid, // @[ReservationStation.scala:35:14]
input [6:0] io_alloc_bits_cmd_inst_funct, // @[ReservationStation.scala:35:14]
input [4:0] io_alloc_bits_cmd_inst_rs2, // @[ReservationStation.scala:35:14]
input [4:0] io_alloc_bits_cmd_inst_rs1, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_inst_xd, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_inst_xs1, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_inst_xs2, // @[ReservationStation.scala:35:14]
input [4:0] io_alloc_bits_cmd_inst_rd, // @[ReservationStation.scala:35:14]
input [6:0] io_alloc_bits_cmd_inst_opcode, // @[ReservationStation.scala:35:14]
input [63:0] io_alloc_bits_cmd_rs1, // @[ReservationStation.scala:35:14]
input [63:0] io_alloc_bits_cmd_rs2, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_debug, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_cease, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_wfi, // @[ReservationStation.scala:35:14]
input [31:0] io_alloc_bits_cmd_status_isa, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_dprv, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_dv, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_prv, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_v, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_sd, // @[ReservationStation.scala:35:14]
input [22:0] io_alloc_bits_cmd_status_zero2, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_mpv, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_gva, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_mbe, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_sbe, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_sxl, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_uxl, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14]
input [7:0] io_alloc_bits_cmd_status_zero1, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_tsr, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_tw, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_tvm, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_mxr, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_sum, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_mprv, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_xs, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_fs, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_mpp, // @[ReservationStation.scala:35:14]
input [1:0] io_alloc_bits_cmd_status_vs, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_spp, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_mpie, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_ube, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_spie, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_upie, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_mie, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_hie, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_sie, // @[ReservationStation.scala:35:14]
input io_alloc_bits_cmd_status_uie, // @[ReservationStation.scala:35:14]
input io_alloc_bits_rob_id_valid, // @[ReservationStation.scala:35:14]
input [5:0] io_alloc_bits_rob_id_bits, // @[ReservationStation.scala:35:14]
input io_alloc_bits_from_matmul_fsm, // @[ReservationStation.scala:35:14]
input io_alloc_bits_from_conv_fsm, // @[ReservationStation.scala:35:14]
input io_completed_valid, // @[ReservationStation.scala:35:14]
input [5:0] io_completed_bits, // @[ReservationStation.scala:35:14]
output io_issue_ld_valid, // @[ReservationStation.scala:35:14]
input io_issue_ld_ready, // @[ReservationStation.scala:35:14]
output [6:0] io_issue_ld_cmd_cmd_inst_funct, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_ld_cmd_cmd_inst_rs2, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_ld_cmd_cmd_inst_rs1, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_inst_xd, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_inst_xs1, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_inst_xs2, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_ld_cmd_cmd_inst_rd, // @[ReservationStation.scala:35:14]
output [6:0] io_issue_ld_cmd_cmd_inst_opcode, // @[ReservationStation.scala:35:14]
output [63:0] io_issue_ld_cmd_cmd_rs1, // @[ReservationStation.scala:35:14]
output [63:0] io_issue_ld_cmd_cmd_rs2, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_debug, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_cease, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_wfi, // @[ReservationStation.scala:35:14]
output [31:0] io_issue_ld_cmd_cmd_status_isa, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_dprv, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_dv, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_prv, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_v, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_sd, // @[ReservationStation.scala:35:14]
output [22:0] io_issue_ld_cmd_cmd_status_zero2, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_mpv, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_gva, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_mbe, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_sbe, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_sxl, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_uxl, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14]
output [7:0] io_issue_ld_cmd_cmd_status_zero1, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_tsr, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_tw, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_tvm, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_mxr, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_sum, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_mprv, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_xs, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_fs, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_mpp, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ld_cmd_cmd_status_vs, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_spp, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_mpie, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_ube, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_spie, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_upie, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_mie, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_hie, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_sie, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_cmd_status_uie, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_from_matmul_fsm, // @[ReservationStation.scala:35:14]
output io_issue_ld_cmd_from_conv_fsm, // @[ReservationStation.scala:35:14]
output [5:0] io_issue_ld_rob_id, // @[ReservationStation.scala:35:14]
output io_issue_st_valid, // @[ReservationStation.scala:35:14]
input io_issue_st_ready, // @[ReservationStation.scala:35:14]
output [6:0] io_issue_st_cmd_cmd_inst_funct, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_st_cmd_cmd_inst_rs2, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_st_cmd_cmd_inst_rs1, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_inst_xd, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_inst_xs1, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_inst_xs2, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_st_cmd_cmd_inst_rd, // @[ReservationStation.scala:35:14]
output [6:0] io_issue_st_cmd_cmd_inst_opcode, // @[ReservationStation.scala:35:14]
output [63:0] io_issue_st_cmd_cmd_rs1, // @[ReservationStation.scala:35:14]
output [63:0] io_issue_st_cmd_cmd_rs2, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_debug, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_cease, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_wfi, // @[ReservationStation.scala:35:14]
output [31:0] io_issue_st_cmd_cmd_status_isa, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_dprv, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_dv, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_prv, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_v, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_sd, // @[ReservationStation.scala:35:14]
output [22:0] io_issue_st_cmd_cmd_status_zero2, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_mpv, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_gva, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_mbe, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_sbe, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_sxl, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_uxl, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14]
output [7:0] io_issue_st_cmd_cmd_status_zero1, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_tsr, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_tw, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_tvm, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_mxr, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_sum, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_mprv, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_xs, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_fs, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_mpp, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_st_cmd_cmd_status_vs, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_spp, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_mpie, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_ube, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_spie, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_upie, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_mie, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_hie, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_sie, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_cmd_status_uie, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_from_matmul_fsm, // @[ReservationStation.scala:35:14]
output io_issue_st_cmd_from_conv_fsm, // @[ReservationStation.scala:35:14]
output [5:0] io_issue_st_rob_id, // @[ReservationStation.scala:35:14]
output io_issue_ex_valid, // @[ReservationStation.scala:35:14]
input io_issue_ex_ready, // @[ReservationStation.scala:35:14]
output [6:0] io_issue_ex_cmd_cmd_inst_funct, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_ex_cmd_cmd_inst_rs2, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_ex_cmd_cmd_inst_rs1, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_inst_xd, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_inst_xs1, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_inst_xs2, // @[ReservationStation.scala:35:14]
output [4:0] io_issue_ex_cmd_cmd_inst_rd, // @[ReservationStation.scala:35:14]
output [6:0] io_issue_ex_cmd_cmd_inst_opcode, // @[ReservationStation.scala:35:14]
output [63:0] io_issue_ex_cmd_cmd_rs1, // @[ReservationStation.scala:35:14]
output [63:0] io_issue_ex_cmd_cmd_rs2, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_debug, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_cease, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_wfi, // @[ReservationStation.scala:35:14]
output [31:0] io_issue_ex_cmd_cmd_status_isa, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_dprv, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_dv, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_prv, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_v, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_sd, // @[ReservationStation.scala:35:14]
output [22:0] io_issue_ex_cmd_cmd_status_zero2, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_mpv, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_gva, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_mbe, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_sbe, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_sxl, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_uxl, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_sd_rv32, // @[ReservationStation.scala:35:14]
output [7:0] io_issue_ex_cmd_cmd_status_zero1, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_tsr, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_tw, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_tvm, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_mxr, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_sum, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_mprv, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_xs, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_fs, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_mpp, // @[ReservationStation.scala:35:14]
output [1:0] io_issue_ex_cmd_cmd_status_vs, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_spp, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_mpie, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_ube, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_spie, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_upie, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_mie, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_hie, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_sie, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_cmd_status_uie, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_from_matmul_fsm, // @[ReservationStation.scala:35:14]
output io_issue_ex_cmd_from_conv_fsm, // @[ReservationStation.scala:35:14]
output [5:0] io_issue_ex_rob_id, // @[ReservationStation.scala:35:14]
output [1:0] io_conv_ld_completed, // @[ReservationStation.scala:35:14]
output [1:0] io_conv_ex_completed, // @[ReservationStation.scala:35:14]
output [1:0] io_conv_st_completed, // @[ReservationStation.scala:35:14]
output [1:0] io_matmul_ld_completed, // @[ReservationStation.scala:35:14]
output [1:0] io_matmul_ex_completed, // @[ReservationStation.scala:35:14]
output [1:0] io_matmul_st_completed, // @[ReservationStation.scala:35:14]
output io_busy, // @[ReservationStation.scala:35:14]
output io_counter_event_signal_41, // @[ReservationStation.scala:35:14]
output io_counter_event_signal_42, // @[ReservationStation.scala:35:14]
output [31:0] io_counter_external_values_1, // @[ReservationStation.scala:35:14]
output [31:0] io_counter_external_values_2, // @[ReservationStation.scala:35:14]
output [31:0] io_counter_external_values_3, // @[ReservationStation.scala:35:14]
input io_counter_external_reset // @[ReservationStation.scala:35:14]
);
wire start_garbage_bit; // @[ReservationStation.scala:281:44]
wire [10:0] start_garbage; // @[ReservationStation.scala:281:44]
wire [2:0] start_norm_cmd; // @[ReservationStation.scala:281:44]
wire start_read_full_acc_row; // @[ReservationStation.scala:281:44]
wire start_accumulate; // @[ReservationStation.scala:281:44]
wire start_is_acc_addr; // @[ReservationStation.scala:281:44]
wire dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19]
wire [10:0] dst_bits_start_garbage; // @[ReservationStation.scala:202:19]
wire [2:0] dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19]
wire dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19]
wire dst_bits_start_accumulate; // @[ReservationStation.scala:202:19]
wire dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19]
wire op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19]
wire [10:0] op2_bits_start_garbage; // @[ReservationStation.scala:199:19]
wire [2:0] op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19]
wire op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19]
wire op2_bits_start_accumulate; // @[ReservationStation.scala:199:19]
wire op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19]
wire op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19]
wire [10:0] op1_bits_start_garbage; // @[ReservationStation.scala:196:19]
wire [2:0] op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19]
wire op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19]
wire op1_bits_start_accumulate; // @[ReservationStation.scala:196:19]
wire op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19]
wire io_busy_0; // @[ReservationStation.scala:26:7]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_alloc_valid_0 = io_alloc_valid; // @[ReservationStation.scala:26:7]
wire [6:0] io_alloc_bits_cmd_inst_funct_0 = io_alloc_bits_cmd_inst_funct; // @[ReservationStation.scala:26:7]
wire [4:0] io_alloc_bits_cmd_inst_rs2_0 = io_alloc_bits_cmd_inst_rs2; // @[ReservationStation.scala:26:7]
wire [4:0] io_alloc_bits_cmd_inst_rs1_0 = io_alloc_bits_cmd_inst_rs1; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_inst_xd_0 = io_alloc_bits_cmd_inst_xd; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_inst_xs1_0 = io_alloc_bits_cmd_inst_xs1; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_inst_xs2_0 = io_alloc_bits_cmd_inst_xs2; // @[ReservationStation.scala:26:7]
wire [4:0] io_alloc_bits_cmd_inst_rd_0 = io_alloc_bits_cmd_inst_rd; // @[ReservationStation.scala:26:7]
wire [6:0] io_alloc_bits_cmd_inst_opcode_0 = io_alloc_bits_cmd_inst_opcode; // @[ReservationStation.scala:26:7]
wire [63:0] io_alloc_bits_cmd_rs1_0 = io_alloc_bits_cmd_rs1; // @[ReservationStation.scala:26:7]
wire [63:0] io_alloc_bits_cmd_rs2_0 = io_alloc_bits_cmd_rs2; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_debug_0 = io_alloc_bits_cmd_status_debug; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_cease_0 = io_alloc_bits_cmd_status_cease; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_wfi_0 = io_alloc_bits_cmd_status_wfi; // @[ReservationStation.scala:26:7]
wire [31:0] io_alloc_bits_cmd_status_isa_0 = io_alloc_bits_cmd_status_isa; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_dprv_0 = io_alloc_bits_cmd_status_dprv; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_dv_0 = io_alloc_bits_cmd_status_dv; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_prv_0 = io_alloc_bits_cmd_status_prv; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_v_0 = io_alloc_bits_cmd_status_v; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_sd_0 = io_alloc_bits_cmd_status_sd; // @[ReservationStation.scala:26:7]
wire [22:0] io_alloc_bits_cmd_status_zero2_0 = io_alloc_bits_cmd_status_zero2; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_mpv_0 = io_alloc_bits_cmd_status_mpv; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_gva_0 = io_alloc_bits_cmd_status_gva; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_mbe_0 = io_alloc_bits_cmd_status_mbe; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_sbe_0 = io_alloc_bits_cmd_status_sbe; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_sxl_0 = io_alloc_bits_cmd_status_sxl; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_uxl_0 = io_alloc_bits_cmd_status_uxl; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_sd_rv32_0 = io_alloc_bits_cmd_status_sd_rv32; // @[ReservationStation.scala:26:7]
wire [7:0] io_alloc_bits_cmd_status_zero1_0 = io_alloc_bits_cmd_status_zero1; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_tsr_0 = io_alloc_bits_cmd_status_tsr; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_tw_0 = io_alloc_bits_cmd_status_tw; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_tvm_0 = io_alloc_bits_cmd_status_tvm; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_mxr_0 = io_alloc_bits_cmd_status_mxr; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_sum_0 = io_alloc_bits_cmd_status_sum; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_mprv_0 = io_alloc_bits_cmd_status_mprv; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_xs_0 = io_alloc_bits_cmd_status_xs; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_fs_0 = io_alloc_bits_cmd_status_fs; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_mpp_0 = io_alloc_bits_cmd_status_mpp; // @[ReservationStation.scala:26:7]
wire [1:0] io_alloc_bits_cmd_status_vs_0 = io_alloc_bits_cmd_status_vs; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_spp_0 = io_alloc_bits_cmd_status_spp; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_mpie_0 = io_alloc_bits_cmd_status_mpie; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_ube_0 = io_alloc_bits_cmd_status_ube; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_spie_0 = io_alloc_bits_cmd_status_spie; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_upie_0 = io_alloc_bits_cmd_status_upie; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_mie_0 = io_alloc_bits_cmd_status_mie; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_hie_0 = io_alloc_bits_cmd_status_hie; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_sie_0 = io_alloc_bits_cmd_status_sie; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_cmd_status_uie_0 = io_alloc_bits_cmd_status_uie; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_rob_id_valid_0 = io_alloc_bits_rob_id_valid; // @[ReservationStation.scala:26:7]
wire [5:0] io_alloc_bits_rob_id_bits_0 = io_alloc_bits_rob_id_bits; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_from_matmul_fsm_0 = io_alloc_bits_from_matmul_fsm; // @[ReservationStation.scala:26:7]
wire io_alloc_bits_from_conv_fsm_0 = io_alloc_bits_from_conv_fsm; // @[ReservationStation.scala:26:7]
wire io_completed_valid_0 = io_completed_valid; // @[ReservationStation.scala:26:7]
wire [5:0] io_completed_bits_0 = io_completed_bits; // @[ReservationStation.scala:26:7]
wire io_issue_ld_ready_0 = io_issue_ld_ready; // @[ReservationStation.scala:26:7]
wire io_issue_st_ready_0 = io_issue_st_ready; // @[ReservationStation.scala:26:7]
wire io_issue_ex_ready_0 = io_issue_ex_ready; // @[ReservationStation.scala:26:7]
wire io_counter_external_reset_0 = io_counter_external_reset; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_0 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_1 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_2 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_3 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_4 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_5 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_6 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_7 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_8 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_9 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_10 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_11 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_12 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_13 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_14 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_15 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_16 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_17 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_18 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_19 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_20 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_21 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_22 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_23 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_24 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_25 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_26 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_27 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_28 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_29 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_30 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_31 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_32 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_33 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_34 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_35 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_36 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_37 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_38 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_39 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_40 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_43 = 1'h0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_44 = 1'h0; // @[ReservationStation.scala:26:7]
wire new_entry_issued = 1'h0; // @[ReservationStation.scala:171:23]
wire _next_bank_addr_WIRE_is_acc_addr = 1'h0; // @[ReservationStation.scala:242:49]
wire _next_bank_addr_WIRE_accumulate = 1'h0; // @[ReservationStation.scala:242:49]
wire _next_bank_addr_WIRE_read_full_acc_row = 1'h0; // @[ReservationStation.scala:242:49]
wire _next_bank_addr_WIRE_garbage_bit = 1'h0; // @[ReservationStation.scala:242:49]
wire next_bank_addr_accumulate = 1'h0; // @[ReservationStation.scala:242:36]
wire next_bank_addr_read_full_acc_row = 1'h0; // @[ReservationStation.scala:242:36]
wire next_bank_addr_garbage_bit = 1'h0; // @[ReservationStation.scala:242:36]
wire issue_entry_bits_opb_valid = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_bits_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_valid = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_valid = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_91_bits_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_92_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1230 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1231 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1232 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1233 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1234 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1235 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1236 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1237 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1238 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1239 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1240 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1241 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1242 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1243 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1244 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_93 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_94_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_94_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_94_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_94_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1260 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1261 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1262 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1263 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1264 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1265 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1266 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1267 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1268 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1269 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1270 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1271 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1272 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1273 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1274 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_96 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1313 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1314 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1315 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1316 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1317 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1318 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1319 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1320 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1321 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1322 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1323 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1324 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1325 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1326 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1327 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_101 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1328 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1329 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1330 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1331 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1332 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1333 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1334 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1335 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1336 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1337 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1338 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1339 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1340 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1341 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1342 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_102 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1343 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1344 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1345 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1346 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1347 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1348 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1349 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1350 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1351 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1352 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1353 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1354 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1355 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1356 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1357 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_103 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_104_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_104_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_104_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_104_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1373 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1374 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1375 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1376 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1377 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1378 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1379 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1380 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1381 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1382 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1383 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1384 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1385 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1386 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1387 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_106 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1426 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1427 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1428 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1429 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1430 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1431 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1432 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1433 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1434 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1435 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1436 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1437 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1438 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1439 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1440 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_111 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1441 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1442 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1443 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1444 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1445 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1446 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1447 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1448 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1449 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1450 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1451 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1452 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1453 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1454 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1455 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_112 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1456 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1457 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1458 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1459 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1460 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1461 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1462 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1463 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1464 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1465 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1466 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1467 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1468 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1469 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1470 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_113 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1471 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1472 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1473 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1474 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1475 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1476 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1477 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1478 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1479 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1480 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1481 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1482 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1483 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1484 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_1485 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_114 = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_valid = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_valid = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opb_bits_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_valid = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_377_bits_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_start_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_start_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_start_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_start_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_end_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_end_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_end_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_end_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_378_wraps_around = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6098 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6099 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6100 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6101 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6102 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6103 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6104 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_379 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_380_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_380_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_380_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_380_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6112 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6113 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6114 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6115 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6116 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6117 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6118 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_382 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6137 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6138 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6139 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6140 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6141 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6142 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6143 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_387 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6144 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6145 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6146 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6147 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6148 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6149 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6150 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_388 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6151 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6152 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6153 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6154 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6155 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6156 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6157 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_389 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_390_is_acc_addr = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_390_accumulate = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_390_read_full_acc_row = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_390_garbage_bit = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6165 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6166 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6167 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6168 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6169 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6170 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6171 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_392 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6190 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6191 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6192 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6193 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6194 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6195 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6196 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_397 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6197 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6198 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6199 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6200 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6201 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6202 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6203 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_398 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6204 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6205 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6206 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6207 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6208 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6209 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6210 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_399 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6211 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6212 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6213 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6214 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6215 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6216 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_T_6217 = 1'h0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_400 = 1'h0; // @[Mux.scala:30:73]
wire [2:0] _next_bank_addr_WIRE_norm_cmd = 3'h0; // @[ReservationStation.scala:242:49]
wire [2:0] next_bank_addr_norm_cmd = 3'h0; // @[ReservationStation.scala:242:36]
wire [2:0] issue_entry_bits_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] issue_entry_bits_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_91_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_91_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_92_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_92_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_94_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1290 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1291 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1292 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1293 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1294 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1295 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1296 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1297 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1298 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1299 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1300 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1301 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1302 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1303 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1304 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1305 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1306 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1307 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1308 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1309 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1310 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1311 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1312 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_98 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_99 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_100 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_104_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1403 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1404 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1405 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1406 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1407 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1408 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1409 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1410 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1411 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1412 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1413 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1414 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1415 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1416 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1417 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1418 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1419 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1420 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1421 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1422 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1423 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1424 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1425 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_108 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_109 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_110 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] issue_entry_2_bits_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] issue_entry_2_bits_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_286_opb_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_286_opb_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_377_bits_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_377_bits_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_378_start_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_378_end_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_380_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6126 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6127 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6128 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6129 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6130 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6131 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6132 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6133 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6134 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6135 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6136 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_384 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_385 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_386 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_390_norm_cmd = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6179 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6180 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6181 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6182 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6183 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6184 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6185 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6186 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6187 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6188 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6189 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_394 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_395 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_396 = 3'h0; // @[Mux.scala:30:73]
wire [10:0] _next_bank_addr_WIRE_garbage = 11'h0; // @[ReservationStation.scala:242:49]
wire [10:0] next_bank_addr_garbage = 11'h0; // @[ReservationStation.scala:242:36]
wire [10:0] issue_entry_bits_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] issue_entry_bits_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_91_bits_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_91_bits_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_92_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_92_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_94_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1275 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1276 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1277 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1278 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1279 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1280 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1281 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1282 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1283 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1284 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1285 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1286 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1287 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1288 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1289 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_97 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_104_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1388 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1389 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1390 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1391 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1392 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1393 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1394 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1395 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1396 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1397 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1398 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1399 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1400 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1401 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1402 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_107 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] issue_entry_2_bits_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] issue_entry_2_bits_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_286_opb_bits_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_286_opb_bits_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_377_bits_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_377_bits_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_378_start_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_378_end_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_380_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6119 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6120 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6121 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6122 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6123 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6124 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6125 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_383 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_390_garbage = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6172 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6173 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6174 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6175 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6176 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6177 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6178 = 11'h0; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_393 = 11'h0; // @[Mux.scala:30:73]
wire [13:0] _next_bank_addr_WIRE_data = 14'h0; // @[ReservationStation.scala:242:49]
wire [13:0] issue_entry_bits_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] issue_entry_bits_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_91_bits_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_91_bits_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_92_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_92_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_94_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1245 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1246 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1247 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1248 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1249 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1250 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1251 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1252 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1253 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1254 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1255 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1256 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1257 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1258 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1259 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_95 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_104_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1358 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1359 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1360 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1361 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1362 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1363 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1364 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1365 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1366 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1367 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1368 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1369 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1370 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1371 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1372 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_105 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] issue_entry_2_bits_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] issue_entry_2_bits_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_286_opb_bits_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_286_opb_bits_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_377_bits_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_377_bits_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_378_start_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_378_end_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_380_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6105 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6106 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6107 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6108 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6109 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6110 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6111 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_381 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_390_data = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6158 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6159 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6160 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6161 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6162 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6163 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6164 = 14'h0; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_391 = 14'h0; // @[Mux.scala:30:73]
wire [31:0] io_counter_external_values_0 = 32'h0; // @[ReservationStation.scala:26:7]
wire [31:0] io_counter_external_values_4 = 32'h0; // @[ReservationStation.scala:26:7]
wire [31:0] io_counter_external_values_5 = 32'h0; // @[ReservationStation.scala:26:7]
wire [31:0] io_counter_external_values_6 = 32'h0; // @[ReservationStation.scala:26:7]
wire [31:0] io_counter_external_values_7 = 32'h0; // @[ReservationStation.scala:26:7]
wire [1:0] _alloc_id_T_50 = 2'h3; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_31 = 4'hF; // @[Mux.scala:126:16]
wire [2:0] _alloc_id_T_8 = 3'h7; // @[Mux.scala:126:16]
wire [1:0] _new_entry_q_T = 2'h0; // @[Mux.scala:30:73]
wire next_bank_addr_is_acc_addr = 1'h1; // @[ReservationStation.scala:242:36]
wire [6:0] new_entry_cmd_cmd_inst_funct = io_alloc_bits_cmd_inst_funct_0; // @[ReservationStation.scala:26:7, :171:23]
wire [4:0] new_entry_cmd_cmd_inst_rs2 = io_alloc_bits_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7, :171:23]
wire [4:0] new_entry_cmd_cmd_inst_rs1 = io_alloc_bits_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_inst_xd = io_alloc_bits_cmd_inst_xd_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_inst_xs1 = io_alloc_bits_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_inst_xs2 = io_alloc_bits_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7, :171:23]
wire [4:0] new_entry_cmd_cmd_inst_rd = io_alloc_bits_cmd_inst_rd_0; // @[ReservationStation.scala:26:7, :171:23]
wire [6:0] new_entry_cmd_cmd_inst_opcode = io_alloc_bits_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7, :171:23]
wire [63:0] new_entry_cmd_cmd_rs1 = io_alloc_bits_cmd_rs1_0; // @[ReservationStation.scala:26:7, :171:23]
wire [63:0] new_entry_cmd_cmd_rs2 = io_alloc_bits_cmd_rs2_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_debug = io_alloc_bits_cmd_status_debug_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_cease = io_alloc_bits_cmd_status_cease_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_wfi = io_alloc_bits_cmd_status_wfi_0; // @[ReservationStation.scala:26:7, :171:23]
wire [31:0] new_entry_cmd_cmd_status_isa = io_alloc_bits_cmd_status_isa_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_dprv = io_alloc_bits_cmd_status_dprv_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_dv = io_alloc_bits_cmd_status_dv_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_prv = io_alloc_bits_cmd_status_prv_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_v = io_alloc_bits_cmd_status_v_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_sd = io_alloc_bits_cmd_status_sd_0; // @[ReservationStation.scala:26:7, :171:23]
wire [22:0] new_entry_cmd_cmd_status_zero2 = io_alloc_bits_cmd_status_zero2_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_mpv = io_alloc_bits_cmd_status_mpv_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_gva = io_alloc_bits_cmd_status_gva_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_mbe = io_alloc_bits_cmd_status_mbe_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_sbe = io_alloc_bits_cmd_status_sbe_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_sxl = io_alloc_bits_cmd_status_sxl_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_uxl = io_alloc_bits_cmd_status_uxl_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_sd_rv32 = io_alloc_bits_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7, :171:23]
wire [7:0] new_entry_cmd_cmd_status_zero1 = io_alloc_bits_cmd_status_zero1_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_tsr = io_alloc_bits_cmd_status_tsr_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_tw = io_alloc_bits_cmd_status_tw_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_tvm = io_alloc_bits_cmd_status_tvm_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_mxr = io_alloc_bits_cmd_status_mxr_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_sum = io_alloc_bits_cmd_status_sum_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_mprv = io_alloc_bits_cmd_status_mprv_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_xs = io_alloc_bits_cmd_status_xs_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_fs = io_alloc_bits_cmd_status_fs_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_mpp = io_alloc_bits_cmd_status_mpp_0; // @[ReservationStation.scala:26:7, :171:23]
wire [1:0] new_entry_cmd_cmd_status_vs = io_alloc_bits_cmd_status_vs_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_spp = io_alloc_bits_cmd_status_spp_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_mpie = io_alloc_bits_cmd_status_mpie_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_ube = io_alloc_bits_cmd_status_ube_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_spie = io_alloc_bits_cmd_status_spie_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_upie = io_alloc_bits_cmd_status_upie_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_mie = io_alloc_bits_cmd_status_mie_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_hie = io_alloc_bits_cmd_status_hie_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_sie = io_alloc_bits_cmd_status_sie_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_cmd_status_uie = io_alloc_bits_cmd_status_uie_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_rob_id_valid = io_alloc_bits_rob_id_valid_0; // @[ReservationStation.scala:26:7, :171:23]
wire [5:0] new_entry_cmd_rob_id_bits = io_alloc_bits_rob_id_bits_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_from_matmul_fsm = io_alloc_bits_from_matmul_fsm_0; // @[ReservationStation.scala:26:7, :171:23]
wire new_entry_cmd_from_conv_fsm = io_alloc_bits_from_conv_fsm_0; // @[ReservationStation.scala:26:7, :171:23]
wire _io_issue_ld_valid_T_6; // @[ReservationStation.scala:404:38]
wire [6:0] issue_entry_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] issue_entry_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] issue_entry_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] issue_entry_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] issue_entry_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] issue_entry_bits_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] issue_entry_bits_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] issue_entry_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] issue_entry_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] issue_entry_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] issue_entry_bits_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire issue_entry_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire [5:0] global_issue_id; // @[ReservationStation.scala:398:30]
wire _io_issue_st_valid_T_2; // @[ReservationStation.scala:404:38]
wire [6:0] issue_entry_2_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] issue_entry_2_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] issue_entry_2_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] issue_entry_2_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] issue_entry_2_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] issue_entry_2_bits_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] issue_entry_2_bits_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] issue_entry_2_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] issue_entry_2_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] issue_entry_2_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] issue_entry_2_bits_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire issue_entry_2_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire [5:0] global_issue_id_2; // @[ReservationStation.scala:398:30]
wire _io_issue_ex_valid_T_14; // @[ReservationStation.scala:404:38]
wire [6:0] issue_entry_1_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] issue_entry_1_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] issue_entry_1_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] issue_entry_1_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] issue_entry_1_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] issue_entry_1_bits_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] issue_entry_1_bits_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] issue_entry_1_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] issue_entry_1_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] issue_entry_1_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] issue_entry_1_bits_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire issue_entry_1_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire [5:0] global_issue_id_1; // @[ReservationStation.scala:398:30]
wire [1:0] _io_conv_ld_completed_T; // @[ReservationStation.scala:154:51]
wire [1:0] _io_conv_ex_completed_T; // @[ReservationStation.scala:156:51]
wire [1:0] _io_conv_st_completed_T; // @[ReservationStation.scala:155:51]
wire [1:0] _io_matmul_ld_completed_T; // @[ReservationStation.scala:158:55]
wire [1:0] _io_matmul_ex_completed_T; // @[ReservationStation.scala:160:55]
wire [1:0] _io_matmul_st_completed_T; // @[ReservationStation.scala:159:55]
wire _io_busy_T_4; // @[ReservationStation.scala:135:21]
wire io_counter_event_signal_42_0 = io_busy_0; // @[ReservationStation.scala:26:7]
wire io_alloc_ready_0; // @[ReservationStation.scala:26:7]
wire [6:0] io_issue_ld_cmd_cmd_inst_funct_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_ld_cmd_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_ld_cmd_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_inst_xd_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_ld_cmd_cmd_inst_rd_0; // @[ReservationStation.scala:26:7]
wire [6:0] io_issue_ld_cmd_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_debug_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_cease_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_wfi_0; // @[ReservationStation.scala:26:7]
wire [31:0] io_issue_ld_cmd_cmd_status_isa_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_dprv_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_dv_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_prv_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_v_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_sd_0; // @[ReservationStation.scala:26:7]
wire [22:0] io_issue_ld_cmd_cmd_status_zero2_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_mpv_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_gva_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_mbe_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_sbe_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_sxl_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_uxl_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7]
wire [7:0] io_issue_ld_cmd_cmd_status_zero1_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_tsr_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_tw_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_tvm_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_mxr_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_sum_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_mprv_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_xs_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_fs_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_mpp_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ld_cmd_cmd_status_vs_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_spp_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_mpie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_ube_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_spie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_upie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_mie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_hie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_sie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_cmd_status_uie_0; // @[ReservationStation.scala:26:7]
wire [63:0] io_issue_ld_cmd_cmd_rs1_0; // @[ReservationStation.scala:26:7]
wire [63:0] io_issue_ld_cmd_cmd_rs2_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_rob_id_valid; // @[ReservationStation.scala:26:7]
wire [5:0] io_issue_ld_cmd_rob_id_bits; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_from_matmul_fsm_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_cmd_from_conv_fsm_0; // @[ReservationStation.scala:26:7]
wire io_issue_ld_valid_0; // @[ReservationStation.scala:26:7]
wire [5:0] io_issue_ld_rob_id_0; // @[ReservationStation.scala:26:7]
wire [6:0] io_issue_st_cmd_cmd_inst_funct_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_st_cmd_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_st_cmd_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_inst_xd_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_st_cmd_cmd_inst_rd_0; // @[ReservationStation.scala:26:7]
wire [6:0] io_issue_st_cmd_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_debug_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_cease_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_wfi_0; // @[ReservationStation.scala:26:7]
wire [31:0] io_issue_st_cmd_cmd_status_isa_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_dprv_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_dv_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_prv_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_v_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_sd_0; // @[ReservationStation.scala:26:7]
wire [22:0] io_issue_st_cmd_cmd_status_zero2_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_mpv_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_gva_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_mbe_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_sbe_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_sxl_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_uxl_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7]
wire [7:0] io_issue_st_cmd_cmd_status_zero1_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_tsr_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_tw_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_tvm_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_mxr_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_sum_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_mprv_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_xs_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_fs_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_mpp_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_st_cmd_cmd_status_vs_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_spp_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_mpie_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_ube_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_spie_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_upie_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_mie_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_hie_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_sie_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_cmd_status_uie_0; // @[ReservationStation.scala:26:7]
wire [63:0] io_issue_st_cmd_cmd_rs1_0; // @[ReservationStation.scala:26:7]
wire [63:0] io_issue_st_cmd_cmd_rs2_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_rob_id_valid; // @[ReservationStation.scala:26:7]
wire [5:0] io_issue_st_cmd_rob_id_bits; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_from_matmul_fsm_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_cmd_from_conv_fsm_0; // @[ReservationStation.scala:26:7]
wire io_issue_st_valid_0; // @[ReservationStation.scala:26:7]
wire [5:0] io_issue_st_rob_id_0; // @[ReservationStation.scala:26:7]
wire [6:0] io_issue_ex_cmd_cmd_inst_funct_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_ex_cmd_cmd_inst_rs2_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_ex_cmd_cmd_inst_rs1_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_inst_xd_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_inst_xs1_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_inst_xs2_0; // @[ReservationStation.scala:26:7]
wire [4:0] io_issue_ex_cmd_cmd_inst_rd_0; // @[ReservationStation.scala:26:7]
wire [6:0] io_issue_ex_cmd_cmd_inst_opcode_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_debug_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_cease_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_wfi_0; // @[ReservationStation.scala:26:7]
wire [31:0] io_issue_ex_cmd_cmd_status_isa_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_dprv_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_dv_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_prv_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_v_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_sd_0; // @[ReservationStation.scala:26:7]
wire [22:0] io_issue_ex_cmd_cmd_status_zero2_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_mpv_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_gva_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_mbe_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_sbe_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_sxl_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_uxl_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_sd_rv32_0; // @[ReservationStation.scala:26:7]
wire [7:0] io_issue_ex_cmd_cmd_status_zero1_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_tsr_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_tw_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_tvm_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_mxr_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_sum_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_mprv_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_xs_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_fs_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_mpp_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_issue_ex_cmd_cmd_status_vs_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_spp_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_mpie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_ube_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_spie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_upie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_mie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_hie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_sie_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_cmd_status_uie_0; // @[ReservationStation.scala:26:7]
wire [63:0] io_issue_ex_cmd_cmd_rs1_0; // @[ReservationStation.scala:26:7]
wire [63:0] io_issue_ex_cmd_cmd_rs2_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_rob_id_valid; // @[ReservationStation.scala:26:7]
wire [5:0] io_issue_ex_cmd_rob_id_bits; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_from_matmul_fsm_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_cmd_from_conv_fsm_0; // @[ReservationStation.scala:26:7]
wire io_issue_ex_valid_0; // @[ReservationStation.scala:26:7]
wire [5:0] io_issue_ex_rob_id_0; // @[ReservationStation.scala:26:7]
wire io_counter_event_signal_41_0; // @[ReservationStation.scala:26:7]
wire [31:0] io_counter_external_values_1_0; // @[ReservationStation.scala:26:7]
wire [31:0] io_counter_external_values_2_0; // @[ReservationStation.scala:26:7]
wire [31:0] io_counter_external_values_3_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_conv_ld_completed_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_conv_ex_completed_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_conv_st_completed_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_matmul_ld_completed_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_matmul_ex_completed_0; // @[ReservationStation.scala:26:7]
wire [1:0] io_matmul_st_completed_0; // @[ReservationStation.scala:26:7]
reg [31:0] instructions_allocated; // @[ReservationStation.scala:75:39]
wire [31:0] new_entry_allocated_at = instructions_allocated; // @[ReservationStation.scala:75:39, :171:23]
wire alloc_fire = io_alloc_ready_0 & io_alloc_valid_0; // @[Decoupled.scala:51:35]
wire [32:0] _instructions_allocated_T = {1'h0, instructions_allocated} + 33'h1; // @[ReservationStation.scala:75:39, :77:54]
wire [31:0] _instructions_allocated_T_1 = _instructions_allocated_T[31:0]; // @[ReservationStation.scala:77:54]
reg entries_ld_0_valid; // @[ReservationStation.scala:117:23]
wire valids_0 = entries_ld_0_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_0_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_0_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1674 = entries_ld_0_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_0_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_0_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_0_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1561 = entries_ld_0_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_0_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_0_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_0 = entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_0_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_0 = entries_ld_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_0_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_0_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_0_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_0_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_0_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_0_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_0_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_0_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_0_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_0_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_0_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_0_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_0_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ld_1_valid; // @[ReservationStation.scala:117:23]
wire valids_1 = entries_ld_1_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_1_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_1_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1676 = entries_ld_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_1_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_1_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_1_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1563 = entries_ld_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_1_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_1_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_1 = entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_1_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_1 = entries_ld_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_1_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_1_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_1_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_1_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_1_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_1_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_1_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_1_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_1_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_1_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_1_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_1_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_1_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ld_2_valid; // @[ReservationStation.scala:117:23]
wire valids_2 = entries_ld_2_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_2_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_2_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1678 = entries_ld_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_2_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_2_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_2_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1565 = entries_ld_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_2_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_2_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_2 = entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_2_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_2 = entries_ld_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_2_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_2_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_2_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_2_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_2_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_2_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_2_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_2_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_2_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_2_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_2_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_2_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_2_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ld_3_valid; // @[ReservationStation.scala:117:23]
wire valids_3 = entries_ld_3_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_3_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_3_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1680 = entries_ld_3_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_3_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_3_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_3_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1567 = entries_ld_3_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_3_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_3_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_3 = entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_3_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_3 = entries_ld_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_3_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_3_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_3_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_3_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_3_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_3_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_3_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_3_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_3_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_3_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_3_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_3_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_3_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ld_4_valid; // @[ReservationStation.scala:117:23]
wire valids_4 = entries_ld_4_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_4_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_4_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1682 = entries_ld_4_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_4_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_4_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_4_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1569 = entries_ld_4_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_4_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_4_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_4 = entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_4_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_4 = entries_ld_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_4_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_4_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_4_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_4_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_4_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_4_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_4_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_4_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_4_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_4_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_4_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_4_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_4_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ld_5_valid; // @[ReservationStation.scala:117:23]
wire valids_5 = entries_ld_5_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_5_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_5_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1684 = entries_ld_5_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_5_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_5_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_5_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1571 = entries_ld_5_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_5_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_5_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_5 = entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_5_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_5 = entries_ld_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_5_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_5_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_5_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_5_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_5_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_5_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_5_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_5_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_5_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_5_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_5_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_5_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_5_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ld_6_valid; // @[ReservationStation.scala:117:23]
wire valids_6 = entries_ld_6_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_6_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_6_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1686 = entries_ld_6_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_6_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_6_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_6_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1573 = entries_ld_6_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_6_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_6_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_6 = entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_6_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_6 = entries_ld_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_6_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_6_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_6_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_6_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_6_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_6_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_6_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_6_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_6_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_6_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_6_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_6_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_6_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ld_7_valid; // @[ReservationStation.scala:117:23]
wire valids_7 = entries_ld_7_valid; // @[ReservationStation.scala:117:23, :502:23]
reg [1:0] entries_ld_7_bits_q; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_is_config; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_valid; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_7_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1688 = entries_ld_7_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_7_bits_opa_bits_start_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_7_bits_opa_bits_start_data; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:117:23]
reg [2:0] entries_ld_7_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:117:23]
wire [2:0] _issue_entry_T_1575 = entries_ld_7_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ld_7_bits_opa_bits_end_garbage; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:117:23]
reg [13:0] entries_ld_7_bits_opa_bits_end_data; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_bits_wraps_around; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_opa_is_dst; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23]
wire issueds_7 = entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :504:24]
reg entries_ld_7_bits_complete_on_issue; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23]
wire [6:0] functs_7 = entries_ld_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:117:23, :503:23]
reg [4:0] entries_ld_7_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_7_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:117:23]
reg [4:0] entries_ld_7_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:117:23]
reg [6:0] entries_ld_7_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_7_bits_cmd_cmd_rs1; // @[ReservationStation.scala:117:23]
reg [63:0] entries_ld_7_bits_cmd_cmd_rs2; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_7_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_v; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:117:23]
reg [22:0] entries_ld_7_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:117:23]
reg [7:0] entries_ld_7_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:117:23]
reg [1:0] entries_ld_7_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_rob_id_valid; // @[ReservationStation.scala:117:23]
reg [5:0] entries_ld_7_bits_cmd_rob_id_bits; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_0; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_1; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_2; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_3; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_4; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_5; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_6; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ld_7; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_0; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_1; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_2; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_3; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_4; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_5; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_6; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_7; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_8; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_9; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_10; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_11; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_12; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_13; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_14; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_ex_15; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_st_0; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_st_1; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_st_2; // @[ReservationStation.scala:117:23]
reg entries_ld_7_bits_deps_st_3; // @[ReservationStation.scala:117:23]
reg [31:0] entries_ld_7_bits_allocated_at; // @[ReservationStation.scala:117:23]
reg entries_ex_0_valid; // @[ReservationStation.scala:118:23]
wire valids_8 = entries_ex_0_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_0_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_0_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5260 = entries_ex_0_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_0_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_0_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_0_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5027 = entries_ex_0_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_0_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_0_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_0_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4701 = entries_ex_0_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_0_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_0_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_0_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4468 = entries_ex_0_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_0_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_0_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_8 = entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_0_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_8 = entries_ex_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_0_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_0_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_0_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_0_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_0_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_0_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_0_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_0_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_0_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_0_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_0_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_0_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_0_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_1_valid; // @[ReservationStation.scala:118:23]
wire valids_9 = entries_ex_1_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_1_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_1_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5262 = entries_ex_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_1_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_1_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_1_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5029 = entries_ex_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_1_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_1_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_1_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4703 = entries_ex_1_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_1_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_1_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_1_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4470 = entries_ex_1_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_1_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_1_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_9 = entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_1_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_9 = entries_ex_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_1_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_1_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_1_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_1_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_1_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_1_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_1_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_1_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_1_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_1_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_1_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_1_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_1_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_2_valid; // @[ReservationStation.scala:118:23]
wire valids_10 = entries_ex_2_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_2_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_2_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5264 = entries_ex_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_2_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_2_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_2_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5031 = entries_ex_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_2_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_2_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_2_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4705 = entries_ex_2_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_2_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_2_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_2_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4472 = entries_ex_2_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_2_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_2_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_10 = entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_2_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_10 = entries_ex_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_2_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_2_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_2_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_2_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_2_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_2_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_2_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_2_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_2_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_2_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_2_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_2_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_2_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_3_valid; // @[ReservationStation.scala:118:23]
wire valids_11 = entries_ex_3_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_3_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_3_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5266 = entries_ex_3_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_3_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_3_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_3_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5033 = entries_ex_3_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_3_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_3_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_3_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4707 = entries_ex_3_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_3_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_3_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_3_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4474 = entries_ex_3_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_3_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_3_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_11 = entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_3_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_11 = entries_ex_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_3_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_3_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_3_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_3_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_3_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_3_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_3_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_3_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_3_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_3_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_3_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_3_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_3_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_4_valid; // @[ReservationStation.scala:118:23]
wire valids_12 = entries_ex_4_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_4_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_4_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5268 = entries_ex_4_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_4_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_4_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_4_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5035 = entries_ex_4_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_4_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_4_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_4_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4709 = entries_ex_4_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_4_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_4_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_4_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4476 = entries_ex_4_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_4_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_4_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_12 = entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_4_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_12 = entries_ex_4_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_4_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_4_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_4_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_4_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_4_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_4_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_4_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_4_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_4_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_4_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_4_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_4_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_4_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_5_valid; // @[ReservationStation.scala:118:23]
wire valids_13 = entries_ex_5_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_5_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_5_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5270 = entries_ex_5_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_5_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_5_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_5_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5037 = entries_ex_5_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_5_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_5_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_5_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4711 = entries_ex_5_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_5_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_5_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_5_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4478 = entries_ex_5_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_5_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_5_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_13 = entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_5_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_13 = entries_ex_5_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_5_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_5_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_5_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_5_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_5_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_5_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_5_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_5_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_5_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_5_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_5_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_5_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_5_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_6_valid; // @[ReservationStation.scala:118:23]
wire valids_14 = entries_ex_6_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_6_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_6_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5272 = entries_ex_6_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_6_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_6_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_6_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5039 = entries_ex_6_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_6_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_6_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_6_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4713 = entries_ex_6_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_6_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_6_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_6_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4480 = entries_ex_6_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_6_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_6_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_14 = entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_6_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_14 = entries_ex_6_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_6_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_6_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_6_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_6_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_6_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_6_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_6_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_6_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_6_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_6_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_6_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_6_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_6_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_7_valid; // @[ReservationStation.scala:118:23]
wire valids_15 = entries_ex_7_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_7_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_7_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5274 = entries_ex_7_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_7_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_7_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_7_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5041 = entries_ex_7_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_7_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_7_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_7_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4715 = entries_ex_7_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_7_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_7_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_7_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4482 = entries_ex_7_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_7_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_7_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_15 = entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_7_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_15 = entries_ex_7_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_7_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_7_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_7_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_7_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_7_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_7_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_7_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_7_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_7_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_7_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_7_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_7_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_7_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_8_valid; // @[ReservationStation.scala:118:23]
wire valids_16 = entries_ex_8_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_8_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_8_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5276 = entries_ex_8_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_8_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_8_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_8_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5043 = entries_ex_8_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_8_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_8_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_8_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4717 = entries_ex_8_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_8_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_8_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_8_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4484 = entries_ex_8_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_8_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_8_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_16 = entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_8_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_8_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_16 = entries_ex_8_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_8_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_8_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_8_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_8_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_8_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_8_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_8_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_8_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_8_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_8_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_8_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_8_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_8_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_9_valid; // @[ReservationStation.scala:118:23]
wire valids_17 = entries_ex_9_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_9_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_9_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5278 = entries_ex_9_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_9_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_9_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_9_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5045 = entries_ex_9_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_9_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_9_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_9_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4719 = entries_ex_9_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_9_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_9_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_9_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4486 = entries_ex_9_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_9_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_9_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_17 = entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_9_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_9_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_17 = entries_ex_9_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_9_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_9_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_9_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_9_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_9_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_9_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_9_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_9_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_9_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_9_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_9_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_9_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_9_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_10_valid; // @[ReservationStation.scala:118:23]
wire valids_18 = entries_ex_10_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_10_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_10_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5280 = entries_ex_10_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_10_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_10_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_10_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5047 = entries_ex_10_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_10_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_10_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_10_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4721 = entries_ex_10_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_10_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_10_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_10_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4488 = entries_ex_10_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_10_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_10_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_18 = entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_10_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_10_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_18 = entries_ex_10_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_10_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_10_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_10_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_10_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_10_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_10_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_10_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_10_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_10_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_10_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_10_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_10_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_10_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_11_valid; // @[ReservationStation.scala:118:23]
wire valids_19 = entries_ex_11_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_11_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_11_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5282 = entries_ex_11_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_11_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_11_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_11_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5049 = entries_ex_11_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_11_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_11_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_11_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4723 = entries_ex_11_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_11_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_11_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_11_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4490 = entries_ex_11_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_11_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_11_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_19 = entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_11_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_11_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_19 = entries_ex_11_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_11_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_11_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_11_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_11_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_11_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_11_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_11_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_11_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_11_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_11_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_11_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_11_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_11_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_12_valid; // @[ReservationStation.scala:118:23]
wire valids_20 = entries_ex_12_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_12_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_12_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5284 = entries_ex_12_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_12_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_12_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_12_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5051 = entries_ex_12_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_12_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_12_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_12_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4725 = entries_ex_12_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_12_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_12_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_12_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4492 = entries_ex_12_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_12_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_12_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_20 = entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_12_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_12_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_20 = entries_ex_12_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_12_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_12_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_12_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_12_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_12_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_12_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_12_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_12_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_12_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_12_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_12_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_12_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_12_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_13_valid; // @[ReservationStation.scala:118:23]
wire valids_21 = entries_ex_13_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_13_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_13_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5286 = entries_ex_13_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_13_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_13_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_13_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5053 = entries_ex_13_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_13_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_13_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_13_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4727 = entries_ex_13_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_13_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_13_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_13_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4494 = entries_ex_13_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_13_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_13_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_21 = entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_13_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_13_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_21 = entries_ex_13_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_13_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_13_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_13_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_13_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_13_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_13_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_13_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_13_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_13_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_13_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_13_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_13_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_13_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_14_valid; // @[ReservationStation.scala:118:23]
wire valids_22 = entries_ex_14_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_14_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_14_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5288 = entries_ex_14_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_14_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_14_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_14_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5055 = entries_ex_14_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_14_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_14_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_14_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4729 = entries_ex_14_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_14_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_14_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_14_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4496 = entries_ex_14_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_14_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_14_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_22 = entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_14_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_14_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_22 = entries_ex_14_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_14_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_14_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_14_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_14_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_14_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_14_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_14_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_14_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_14_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_14_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_14_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_14_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_14_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_ex_15_valid; // @[ReservationStation.scala:118:23]
wire valids_23 = entries_ex_15_valid; // @[ReservationStation.scala:118:23, :502:23]
reg [1:0] entries_ex_15_bits_q; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_is_config; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_15_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5290 = entries_ex_15_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_15_bits_opa_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_15_bits_opa_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_15_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_5057 = entries_ex_15_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_15_bits_opa_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_15_bits_opa_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opa_is_dst; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_valid; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_start_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_15_bits_opb_bits_start_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4731 = entries_ex_15_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_15_bits_opb_bits_start_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_start_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_15_bits_opb_bits_start_data; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_end_accumulate; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:118:23]
reg [2:0] entries_ex_15_bits_opb_bits_end_norm_cmd; // @[ReservationStation.scala:118:23]
wire [2:0] _issue_entry_T_4498 = entries_ex_15_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_ex_15_bits_opb_bits_end_garbage; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_end_garbage_bit; // @[ReservationStation.scala:118:23]
reg [13:0] entries_ex_15_bits_opb_bits_end_data; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_opb_bits_wraps_around; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23]
wire issueds_23 = entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :504:24]
reg entries_ex_15_bits_complete_on_issue; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_15_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23]
wire [6:0] functs_23 = entries_ex_15_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:118:23, :503:23]
reg [4:0] entries_ex_15_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_15_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:118:23]
reg [4:0] entries_ex_15_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:118:23]
reg [6:0] entries_ex_15_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_15_bits_cmd_cmd_rs1; // @[ReservationStation.scala:118:23]
reg [63:0] entries_ex_15_bits_cmd_cmd_rs2; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_15_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_v; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:118:23]
reg [22:0] entries_ex_15_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:118:23]
reg [7:0] entries_ex_15_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:118:23]
reg [1:0] entries_ex_15_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_rob_id_valid; // @[ReservationStation.scala:118:23]
reg [5:0] entries_ex_15_bits_cmd_rob_id_bits; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_0; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_1; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_2; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_3; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_4; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_5; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_6; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ld_7; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_0; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_1; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_2; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_3; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_4; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_5; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_6; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_7; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_8; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_9; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_10; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_11; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_12; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_13; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_14; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_ex_15; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_st_0; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_st_1; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_st_2; // @[ReservationStation.scala:118:23]
reg entries_ex_15_bits_deps_st_3; // @[ReservationStation.scala:118:23]
reg [31:0] entries_ex_15_bits_allocated_at; // @[ReservationStation.scala:118:23]
reg entries_st_0_valid; // @[ReservationStation.scala:119:23]
wire valids_24 = entries_st_0_valid; // @[ReservationStation.scala:119:23, :502:23]
reg [1:0] entries_st_0_bits_q; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_is_config; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_valid; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_0_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6306 = entries_st_0_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_0_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_0_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_0_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6253 = entries_st_0_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_0_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_0_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_opa_is_dst; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_issued; // @[ReservationStation.scala:119:23]
wire issueds_24 = entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :504:24]
reg entries_st_0_bits_complete_on_issue; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23]
wire [6:0] functs_24 = entries_st_0_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23]
reg [4:0] entries_st_0_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_0_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_0_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_0_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_0_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_0_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_0_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23]
reg [22:0] entries_st_0_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23]
reg [7:0] entries_st_0_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_0_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23]
reg [5:0] entries_st_0_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_0; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_1; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_2; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_3; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_4; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_5; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_6; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ld_7; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_0; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_1; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_2; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_3; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_4; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_5; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_6; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_7; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_8; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_9; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_10; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_11; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_12; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_13; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_14; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_ex_15; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_st_0; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_st_1; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_st_2; // @[ReservationStation.scala:119:23]
reg entries_st_0_bits_deps_st_3; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_0_bits_allocated_at; // @[ReservationStation.scala:119:23]
reg entries_st_1_valid; // @[ReservationStation.scala:119:23]
wire valids_25 = entries_st_1_valid; // @[ReservationStation.scala:119:23, :502:23]
reg [1:0] entries_st_1_bits_q; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_is_config; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_valid; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_1_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6308 = entries_st_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_1_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_1_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_1_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6255 = entries_st_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_1_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_1_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_opa_is_dst; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_issued; // @[ReservationStation.scala:119:23]
wire issueds_25 = entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :504:24]
reg entries_st_1_bits_complete_on_issue; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23]
wire [6:0] functs_25 = entries_st_1_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23]
reg [4:0] entries_st_1_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_1_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_1_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_1_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_1_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_1_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_1_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23]
reg [22:0] entries_st_1_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23]
reg [7:0] entries_st_1_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_1_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23]
reg [5:0] entries_st_1_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_0; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_1; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_2; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_3; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_4; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_5; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_6; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ld_7; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_0; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_1; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_2; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_3; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_4; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_5; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_6; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_7; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_8; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_9; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_10; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_11; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_12; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_13; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_14; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_ex_15; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_st_0; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_st_1; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_st_2; // @[ReservationStation.scala:119:23]
reg entries_st_1_bits_deps_st_3; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_1_bits_allocated_at; // @[ReservationStation.scala:119:23]
reg entries_st_2_valid; // @[ReservationStation.scala:119:23]
wire valids_26 = entries_st_2_valid; // @[ReservationStation.scala:119:23, :502:23]
reg [1:0] entries_st_2_bits_q; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_is_config; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_valid; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_2_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6310 = entries_st_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_2_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_2_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_2_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6257 = entries_st_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_2_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_2_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_opa_is_dst; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_issued; // @[ReservationStation.scala:119:23]
wire issueds_26 = entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :504:24]
reg entries_st_2_bits_complete_on_issue; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23]
wire [6:0] functs_26 = entries_st_2_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23]
reg [4:0] entries_st_2_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_2_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_2_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_2_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_2_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_2_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_2_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23]
reg [22:0] entries_st_2_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23]
reg [7:0] entries_st_2_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_2_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23]
reg [5:0] entries_st_2_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_0; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_1; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_2; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_3; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_4; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_5; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_6; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ld_7; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_0; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_1; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_2; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_3; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_4; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_5; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_6; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_7; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_8; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_9; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_10; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_11; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_12; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_13; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_14; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_ex_15; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_st_0; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_st_1; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_st_2; // @[ReservationStation.scala:119:23]
reg entries_st_2_bits_deps_st_3; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_2_bits_allocated_at; // @[ReservationStation.scala:119:23]
reg entries_st_3_valid; // @[ReservationStation.scala:119:23]
wire valids_27 = entries_st_3_valid; // @[ReservationStation.scala:119:23, :502:23]
reg [1:0] entries_st_3_bits_q; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_is_config; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_valid; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_3_bits_opa_bits_start_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6312 = entries_st_3_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_3_bits_opa_bits_start_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_start_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_3_bits_opa_bits_start_data; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_end_accumulate; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:119:23]
reg [2:0] entries_st_3_bits_opa_bits_end_norm_cmd; // @[ReservationStation.scala:119:23]
wire [2:0] _issue_entry_T_6259 = entries_st_3_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
reg [10:0] entries_st_3_bits_opa_bits_end_garbage; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_end_garbage_bit; // @[ReservationStation.scala:119:23]
reg [13:0] entries_st_3_bits_opa_bits_end_data; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_bits_wraps_around; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_opa_is_dst; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_issued; // @[ReservationStation.scala:119:23]
wire issueds_27 = entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :504:24]
reg entries_st_3_bits_complete_on_issue; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23]
wire [6:0] functs_27 = entries_st_3_bits_cmd_cmd_inst_funct; // @[ReservationStation.scala:119:23, :503:23]
reg [4:0] entries_st_3_bits_cmd_cmd_inst_rs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_3_bits_cmd_cmd_inst_rs1; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_inst_xd; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_inst_xs1; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_inst_xs2; // @[ReservationStation.scala:119:23]
reg [4:0] entries_st_3_bits_cmd_cmd_inst_rd; // @[ReservationStation.scala:119:23]
reg [6:0] entries_st_3_bits_cmd_cmd_inst_opcode; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_3_bits_cmd_cmd_rs1; // @[ReservationStation.scala:119:23]
reg [63:0] entries_st_3_bits_cmd_cmd_rs2; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_debug; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_cease; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_wfi; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_3_bits_cmd_cmd_status_isa; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_dprv; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_dv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_prv; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_v; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_sd; // @[ReservationStation.scala:119:23]
reg [22:0] entries_st_3_bits_cmd_cmd_status_zero2; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_mpv; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_gva; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_mbe; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_sbe; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_sxl; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_uxl; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_sd_rv32; // @[ReservationStation.scala:119:23]
reg [7:0] entries_st_3_bits_cmd_cmd_status_zero1; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_tsr; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_tw; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_tvm; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_mxr; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_sum; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_mprv; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_xs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_fs; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_mpp; // @[ReservationStation.scala:119:23]
reg [1:0] entries_st_3_bits_cmd_cmd_status_vs; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_spp; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_mpie; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_ube; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_spie; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_upie; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_mie; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_hie; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_sie; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_cmd_status_uie; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_rob_id_valid; // @[ReservationStation.scala:119:23]
reg [5:0] entries_st_3_bits_cmd_rob_id_bits; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_from_matmul_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_cmd_from_conv_fsm; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_0; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_1; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_2; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_3; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_4; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_5; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_6; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ld_7; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_0; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_1; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_2; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_3; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_4; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_5; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_6; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_7; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_8; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_9; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_10; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_11; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_12; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_13; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_14; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_ex_15; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_st_0; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_st_1; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_st_2; // @[ReservationStation.scala:119:23]
reg entries_st_3_bits_deps_st_3; // @[ReservationStation.scala:119:23]
reg [31:0] entries_st_3_bits_allocated_at; // @[ReservationStation.scala:119:23]
wire _GEN = entries_ld_0_valid | entries_ld_1_valid; // @[ReservationStation.scala:117:23, :123:52]
wire _empty_ld_T; // @[ReservationStation.scala:123:52]
assign _empty_ld_T = _GEN; // @[ReservationStation.scala:123:52]
wire _empty_T; // @[ReservationStation.scala:130:46]
assign _empty_T = _GEN; // @[ReservationStation.scala:123:52, :130:46]
wire _empty_ld_T_1 = _empty_ld_T | entries_ld_2_valid; // @[ReservationStation.scala:117:23, :123:52]
wire _empty_ld_T_2 = _empty_ld_T_1 | entries_ld_3_valid; // @[ReservationStation.scala:117:23, :123:52]
wire _empty_ld_T_3 = _empty_ld_T_2 | entries_ld_4_valid; // @[ReservationStation.scala:117:23, :123:52]
wire _empty_ld_T_4 = _empty_ld_T_3 | entries_ld_5_valid; // @[ReservationStation.scala:117:23, :123:52]
wire _empty_ld_T_5 = _empty_ld_T_4 | entries_ld_6_valid; // @[ReservationStation.scala:117:23, :123:52]
wire _empty_ld_T_6 = _empty_ld_T_5 | entries_ld_7_valid; // @[ReservationStation.scala:117:23, :123:52]
wire empty_ld = ~_empty_ld_T_6; // @[ReservationStation.scala:123:{18,52}]
wire _empty_ex_T = entries_ex_0_valid | entries_ex_1_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_1 = _empty_ex_T | entries_ex_2_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_2 = _empty_ex_T_1 | entries_ex_3_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_3 = _empty_ex_T_2 | entries_ex_4_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_4 = _empty_ex_T_3 | entries_ex_5_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_5 = _empty_ex_T_4 | entries_ex_6_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_6 = _empty_ex_T_5 | entries_ex_7_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_7 = _empty_ex_T_6 | entries_ex_8_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_8 = _empty_ex_T_7 | entries_ex_9_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_9 = _empty_ex_T_8 | entries_ex_10_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_10 = _empty_ex_T_9 | entries_ex_11_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_11 = _empty_ex_T_10 | entries_ex_12_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_12 = _empty_ex_T_11 | entries_ex_13_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_13 = _empty_ex_T_12 | entries_ex_14_valid; // @[ReservationStation.scala:118:23, :124:52]
wire _empty_ex_T_14 = _empty_ex_T_13 | entries_ex_15_valid; // @[ReservationStation.scala:118:23, :124:52]
wire empty_ex = ~_empty_ex_T_14; // @[ReservationStation.scala:124:{18,52}]
wire _empty_st_T = entries_st_0_valid | entries_st_1_valid; // @[ReservationStation.scala:119:23, :125:52]
wire _empty_st_T_1 = _empty_st_T | entries_st_2_valid; // @[ReservationStation.scala:119:23, :125:52]
wire _empty_st_T_2 = _empty_st_T_1 | entries_st_3_valid; // @[ReservationStation.scala:119:23, :125:52]
wire empty_st = ~_empty_st_T_2; // @[ReservationStation.scala:125:{18,52}]
wire _GEN_0 = entries_ld_0_valid & entries_ld_1_valid; // @[ReservationStation.scala:117:23, :126:50]
wire _full_ld_T; // @[ReservationStation.scala:126:50]
assign _full_ld_T = _GEN_0; // @[ReservationStation.scala:126:50]
wire _full_T; // @[ReservationStation.scala:131:44]
assign _full_T = _GEN_0; // @[ReservationStation.scala:126:50, :131:44]
wire _full_ld_T_1 = _full_ld_T & entries_ld_2_valid; // @[ReservationStation.scala:117:23, :126:50]
wire _full_ld_T_2 = _full_ld_T_1 & entries_ld_3_valid; // @[ReservationStation.scala:117:23, :126:50]
wire _full_ld_T_3 = _full_ld_T_2 & entries_ld_4_valid; // @[ReservationStation.scala:117:23, :126:50]
wire _full_ld_T_4 = _full_ld_T_3 & entries_ld_5_valid; // @[ReservationStation.scala:117:23, :126:50]
wire _full_ld_T_5 = _full_ld_T_4 & entries_ld_6_valid; // @[ReservationStation.scala:117:23, :126:50]
wire full_ld = _full_ld_T_5 & entries_ld_7_valid; // @[ReservationStation.scala:117:23, :126:50]
wire _full_ex_T = entries_ex_0_valid & entries_ex_1_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_1 = _full_ex_T & entries_ex_2_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_2 = _full_ex_T_1 & entries_ex_3_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_3 = _full_ex_T_2 & entries_ex_4_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_4 = _full_ex_T_3 & entries_ex_5_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_5 = _full_ex_T_4 & entries_ex_6_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_6 = _full_ex_T_5 & entries_ex_7_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_7 = _full_ex_T_6 & entries_ex_8_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_8 = _full_ex_T_7 & entries_ex_9_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_9 = _full_ex_T_8 & entries_ex_10_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_10 = _full_ex_T_9 & entries_ex_11_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_11 = _full_ex_T_10 & entries_ex_12_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_12 = _full_ex_T_11 & entries_ex_13_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_ex_T_13 = _full_ex_T_12 & entries_ex_14_valid; // @[ReservationStation.scala:118:23, :127:50]
wire full_ex = _full_ex_T_13 & entries_ex_15_valid; // @[ReservationStation.scala:118:23, :127:50]
wire _full_st_T = entries_st_0_valid & entries_st_1_valid; // @[ReservationStation.scala:119:23, :128:50]
wire _full_st_T_1 = _full_st_T & entries_st_2_valid; // @[ReservationStation.scala:119:23, :128:50]
wire full_st = _full_st_T_1 & entries_st_3_valid; // @[ReservationStation.scala:119:23, :128:50]
wire _empty_T_1 = _empty_T | entries_ld_2_valid; // @[ReservationStation.scala:117:23, :130:46]
wire _empty_T_2 = _empty_T_1 | entries_ld_3_valid; // @[ReservationStation.scala:117:23, :130:46]
wire _empty_T_3 = _empty_T_2 | entries_ld_4_valid; // @[ReservationStation.scala:117:23, :130:46]
wire _empty_T_4 = _empty_T_3 | entries_ld_5_valid; // @[ReservationStation.scala:117:23, :130:46]
wire _empty_T_5 = _empty_T_4 | entries_ld_6_valid; // @[ReservationStation.scala:117:23, :130:46]
wire _empty_T_6 = _empty_T_5 | entries_ld_7_valid; // @[ReservationStation.scala:117:23, :130:46]
wire _empty_T_7 = _empty_T_6 | entries_ex_0_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_8 = _empty_T_7 | entries_ex_1_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_9 = _empty_T_8 | entries_ex_2_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_10 = _empty_T_9 | entries_ex_3_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_11 = _empty_T_10 | entries_ex_4_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_12 = _empty_T_11 | entries_ex_5_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_13 = _empty_T_12 | entries_ex_6_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_14 = _empty_T_13 | entries_ex_7_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_15 = _empty_T_14 | entries_ex_8_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_16 = _empty_T_15 | entries_ex_9_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_17 = _empty_T_16 | entries_ex_10_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_18 = _empty_T_17 | entries_ex_11_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_19 = _empty_T_18 | entries_ex_12_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_20 = _empty_T_19 | entries_ex_13_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_21 = _empty_T_20 | entries_ex_14_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_22 = _empty_T_21 | entries_ex_15_valid; // @[ReservationStation.scala:118:23, :130:46]
wire _empty_T_23 = _empty_T_22 | entries_st_0_valid; // @[ReservationStation.scala:119:23, :130:46]
wire _empty_T_24 = _empty_T_23 | entries_st_1_valid; // @[ReservationStation.scala:119:23, :130:46]
wire _empty_T_25 = _empty_T_24 | entries_st_2_valid; // @[ReservationStation.scala:119:23, :130:46]
wire _empty_T_26 = _empty_T_25 | entries_st_3_valid; // @[ReservationStation.scala:119:23, :130:46]
wire empty = ~_empty_T_26; // @[ReservationStation.scala:130:{15,46}]
wire _full_T_1 = _full_T & entries_ld_2_valid; // @[ReservationStation.scala:117:23, :131:44]
wire _full_T_2 = _full_T_1 & entries_ld_3_valid; // @[ReservationStation.scala:117:23, :131:44]
wire _full_T_3 = _full_T_2 & entries_ld_4_valid; // @[ReservationStation.scala:117:23, :131:44]
wire _full_T_4 = _full_T_3 & entries_ld_5_valid; // @[ReservationStation.scala:117:23, :131:44]
wire _full_T_5 = _full_T_4 & entries_ld_6_valid; // @[ReservationStation.scala:117:23, :131:44]
wire _full_T_6 = _full_T_5 & entries_ld_7_valid; // @[ReservationStation.scala:117:23, :131:44]
wire _full_T_7 = _full_T_6 & entries_ex_0_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_8 = _full_T_7 & entries_ex_1_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_9 = _full_T_8 & entries_ex_2_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_10 = _full_T_9 & entries_ex_3_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_11 = _full_T_10 & entries_ex_4_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_12 = _full_T_11 & entries_ex_5_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_13 = _full_T_12 & entries_ex_6_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_14 = _full_T_13 & entries_ex_7_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_15 = _full_T_14 & entries_ex_8_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_16 = _full_T_15 & entries_ex_9_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_17 = _full_T_16 & entries_ex_10_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_18 = _full_T_17 & entries_ex_11_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_19 = _full_T_18 & entries_ex_12_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_20 = _full_T_19 & entries_ex_13_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_21 = _full_T_20 & entries_ex_14_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_22 = _full_T_21 & entries_ex_15_valid; // @[ReservationStation.scala:118:23, :131:44]
wire _full_T_23 = _full_T_22 & entries_st_0_valid; // @[ReservationStation.scala:119:23, :131:44]
wire _full_T_24 = _full_T_23 & entries_st_1_valid; // @[ReservationStation.scala:119:23, :131:44]
wire _full_T_25 = _full_T_24 & entries_st_2_valid; // @[ReservationStation.scala:119:23, :131:44]
wire full = _full_T_25 & entries_st_3_valid; // @[ReservationStation.scala:119:23, :131:44]
wire [1:0] _GEN_1 = {1'h0, entries_ld_1_valid}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _GEN_2 = {1'h0, entries_ld_2_valid}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _utilization_T = _GEN_1 + _GEN_2; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_T_1 = _utilization_T; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_2 = {2'h0, entries_ld_0_valid} + {1'h0, _utilization_T_1}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _utilization_T_3 = _utilization_T_2[1:0]; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_3 = {1'h0, entries_ld_3_valid}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _GEN_4 = {1'h0, entries_ld_4_valid}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _utilization_T_4 = _GEN_3 + _GEN_4; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_T_5 = _utilization_T_4; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_5 = {1'h0, entries_ld_5_valid}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _GEN_6 = {1'h0, entries_ld_6_valid}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _utilization_T_6 = _GEN_5 + _GEN_6; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_T_7 = _utilization_T_6; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_8 = {1'h0, _utilization_T_5} + {1'h0, _utilization_T_7}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_9 = _utilization_T_8; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_10 = {2'h0, _utilization_T_3} + {1'h0, _utilization_T_9}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_11 = _utilization_T_10[2:0]; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_7 = {1'h0, entries_ex_0_valid} + {1'h0, entries_ex_1_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_12; // @[ReservationStation.scala:133:29]
assign _utilization_T_12 = _GEN_7; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_ex_q_T; // @[ReservationStation.scala:500:34]
assign _utilization_ex_q_T = _GEN_7; // @[ReservationStation.scala:133:29, :500:34]
wire [1:0] _utilization_T_13 = _utilization_T_12; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_14 = {2'h0, entries_ld_7_valid} + {1'h0, _utilization_T_13}; // @[ReservationStation.scala:117:23, :133:29]
wire [1:0] _utilization_T_15 = _utilization_T_14[1:0]; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_8 = {1'h0, entries_ex_2_valid} + {1'h0, entries_ex_3_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_16; // @[ReservationStation.scala:133:29]
assign _utilization_T_16 = _GEN_8; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_ex_q_T_2; // @[ReservationStation.scala:500:34]
assign _utilization_ex_q_T_2 = _GEN_8; // @[ReservationStation.scala:133:29, :500:34]
wire [1:0] _utilization_T_17 = _utilization_T_16; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_9 = {1'h0, entries_ex_4_valid} + {1'h0, entries_ex_5_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_18; // @[ReservationStation.scala:133:29]
assign _utilization_T_18 = _GEN_9; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_ex_q_T_6; // @[ReservationStation.scala:500:34]
assign _utilization_ex_q_T_6 = _GEN_9; // @[ReservationStation.scala:133:29, :500:34]
wire [1:0] _utilization_T_19 = _utilization_T_18; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_20 = {1'h0, _utilization_T_17} + {1'h0, _utilization_T_19}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_21 = _utilization_T_20; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_22 = {2'h0, _utilization_T_15} + {1'h0, _utilization_T_21}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_23 = _utilization_T_22[2:0]; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_24 = {1'h0, _utilization_T_11} + {1'h0, _utilization_T_23}; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_25 = _utilization_T_24; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_10 = {1'h0, entries_ex_7_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _GEN_11 = {1'h0, entries_ex_8_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_26 = _GEN_10 + _GEN_11; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_T_27 = _utilization_T_26; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_28 = {2'h0, entries_ex_6_valid} + {1'h0, _utilization_T_27}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_29 = _utilization_T_28[1:0]; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_12 = {1'h0, entries_ex_9_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _GEN_13 = {1'h0, entries_ex_10_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_30 = _GEN_12 + _GEN_13; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_T_31 = _utilization_T_30; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_14 = {1'h0, entries_ex_11_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _GEN_15 = {1'h0, entries_ex_12_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_32 = _GEN_14 + _GEN_15; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_T_33 = _utilization_T_32; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_34 = {1'h0, _utilization_T_31} + {1'h0, _utilization_T_33}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_35 = _utilization_T_34; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_36 = {2'h0, _utilization_T_29} + {1'h0, _utilization_T_35}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_37 = _utilization_T_36[2:0]; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_16 = {1'h0, entries_ex_14_valid} + {1'h0, entries_ex_15_valid}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_38; // @[ReservationStation.scala:133:29]
assign _utilization_T_38 = _GEN_16; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_ex_q_T_22; // @[ReservationStation.scala:500:34]
assign _utilization_ex_q_T_22 = _GEN_16; // @[ReservationStation.scala:133:29, :500:34]
wire [1:0] _utilization_T_39 = _utilization_T_38; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_40 = {2'h0, entries_ex_13_valid} + {1'h0, _utilization_T_39}; // @[ReservationStation.scala:118:23, :133:29]
wire [1:0] _utilization_T_41 = _utilization_T_40[1:0]; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_17 = {1'h0, entries_st_0_valid} + {1'h0, entries_st_1_valid}; // @[ReservationStation.scala:119:23, :133:29]
wire [1:0] _utilization_T_42; // @[ReservationStation.scala:133:29]
assign _utilization_T_42 = _GEN_17; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_st_q_T; // @[ReservationStation.scala:499:34]
assign _utilization_st_q_T = _GEN_17; // @[ReservationStation.scala:133:29, :499:34]
wire [1:0] _utilization_T_43 = _utilization_T_42; // @[ReservationStation.scala:133:29]
wire [1:0] _GEN_18 = {1'h0, entries_st_2_valid} + {1'h0, entries_st_3_valid}; // @[ReservationStation.scala:119:23, :133:29]
wire [1:0] _utilization_T_44; // @[ReservationStation.scala:133:29]
assign _utilization_T_44 = _GEN_18; // @[ReservationStation.scala:133:29]
wire [1:0] _utilization_st_q_T_2; // @[ReservationStation.scala:499:34]
assign _utilization_st_q_T_2 = _GEN_18; // @[ReservationStation.scala:133:29, :499:34]
wire [1:0] _utilization_T_45 = _utilization_T_44; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_46 = {1'h0, _utilization_T_43} + {1'h0, _utilization_T_45}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_47 = _utilization_T_46; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_48 = {2'h0, _utilization_T_41} + {1'h0, _utilization_T_47}; // @[ReservationStation.scala:133:29]
wire [2:0] _utilization_T_49 = _utilization_T_48[2:0]; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_50 = {1'h0, _utilization_T_37} + {1'h0, _utilization_T_49}; // @[ReservationStation.scala:133:29]
wire [3:0] _utilization_T_51 = _utilization_T_50; // @[ReservationStation.scala:133:29]
wire [4:0] _utilization_T_52 = {1'h0, _utilization_T_25} + {1'h0, _utilization_T_51}; // @[ReservationStation.scala:133:29]
wire [4:0] utilization = _utilization_T_52; // @[ReservationStation.scala:133:29]
reg solitary_preload; // @[ReservationStation.scala:134:33]
wire _io_busy_T = ~empty; // @[ReservationStation.scala:130:15, :135:14]
wire _io_busy_T_1 = utilization == 5'h1; // @[ReservationStation.scala:133:29, :135:38]
wire _io_busy_T_2 = _io_busy_T_1 & solitary_preload; // @[ReservationStation.scala:134:33, :135:{38,46}]
wire _io_busy_T_3 = ~_io_busy_T_2; // @[ReservationStation.scala:135:{24,46}]
assign _io_busy_T_4 = _io_busy_T & _io_busy_T_3; // @[ReservationStation.scala:135:{14,21,24}]
assign io_busy_0 = _io_busy_T_4; // @[ReservationStation.scala:26:7, :135:21]
wire conv_ld_issue_completed; // @[ReservationStation.scala:138:41]
wire conv_st_issue_completed; // @[ReservationStation.scala:139:41]
wire conv_ex_issue_completed; // @[ReservationStation.scala:140:41]
wire conv_ld_completed; // @[ReservationStation.scala:142:35]
wire conv_st_completed; // @[ReservationStation.scala:143:35]
wire conv_ex_completed; // @[ReservationStation.scala:144:35]
wire matmul_ld_issue_completed; // @[ReservationStation.scala:146:43]
wire matmul_st_issue_completed; // @[ReservationStation.scala:147:43]
wire matmul_ex_issue_completed; // @[ReservationStation.scala:148:43]
wire matmul_ld_completed; // @[ReservationStation.scala:150:37]
wire matmul_st_completed; // @[ReservationStation.scala:151:37]
wire matmul_ex_completed; // @[ReservationStation.scala:152:37]
assign _io_conv_ld_completed_T = {1'h0, conv_ld_issue_completed} + {1'h0, conv_ld_completed}; // @[ReservationStation.scala:138:41, :142:35, :154:51]
assign io_conv_ld_completed_0 = _io_conv_ld_completed_T; // @[ReservationStation.scala:26:7, :154:51]
assign _io_conv_st_completed_T = {1'h0, conv_st_issue_completed} + {1'h0, conv_st_completed}; // @[ReservationStation.scala:139:41, :143:35, :155:51]
assign io_conv_st_completed_0 = _io_conv_st_completed_T; // @[ReservationStation.scala:26:7, :155:51]
assign _io_conv_ex_completed_T = {1'h0, conv_ex_issue_completed} + {1'h0, conv_ex_completed}; // @[ReservationStation.scala:140:41, :144:35, :156:51]
assign io_conv_ex_completed_0 = _io_conv_ex_completed_T; // @[ReservationStation.scala:26:7, :156:51]
assign _io_matmul_ld_completed_T = {1'h0, matmul_ld_issue_completed} + {1'h0, matmul_ld_completed}; // @[ReservationStation.scala:146:43, :150:37, :158:55]
assign io_matmul_ld_completed_0 = _io_matmul_ld_completed_T; // @[ReservationStation.scala:26:7, :158:55]
assign _io_matmul_st_completed_T = {1'h0, matmul_st_issue_completed} + {1'h0, matmul_st_completed}; // @[ReservationStation.scala:147:43, :151:37, :159:55]
assign io_matmul_st_completed_0 = _io_matmul_st_completed_T; // @[ReservationStation.scala:26:7, :159:55]
assign _io_matmul_ex_completed_T = {1'h0, matmul_ex_issue_completed} + {1'h0, matmul_ex_completed}; // @[ReservationStation.scala:148:43, :152:37, :160:55]
assign io_matmul_ex_completed_0 = _io_matmul_ex_completed_T; // @[ReservationStation.scala:26:7, :160:55]
reg [13:0] a_stride; // @[ReservationStation.scala:163:21]
reg [13:0] c_stride; // @[ReservationStation.scala:164:21]
reg a_transpose; // @[ReservationStation.scala:165:24]
reg [13:0] ld_block_strides_0; // @[ReservationStation.scala:166:29]
reg [13:0] ld_block_strides_1; // @[ReservationStation.scala:166:29]
reg [13:0] ld_block_strides_2; // @[ReservationStation.scala:166:29]
reg pooling_is_enabled; // @[ReservationStation.scala:168:31]
reg [4:0] ld_pixel_repeats_0; // @[ReservationStation.scala:169:29]
reg [4:0] ld_pixel_repeats_1; // @[ReservationStation.scala:169:29]
reg [4:0] ld_pixel_repeats_2; // @[ReservationStation.scala:169:29]
wire [1:0] _new_entry_q_WIRE; // @[Mux.scala:30:73]
wire _new_entry_is_config_T; // @[ReservationStation.scala:194:34]
wire dst_valid; // @[ReservationStation.scala:202:19]
wire _new_entry_complete_on_issue_T_1; // @[ReservationStation.scala:343:56]
wire new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23]
wire [2:0] new_entry_opa_bits_start_norm_cmd; // @[ReservationStation.scala:171:23]
wire [10:0] new_entry_opa_bits_start_garbage; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_start_garbage_bit; // @[ReservationStation.scala:171:23]
wire [13:0] new_entry_opa_bits_start_data; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_end_accumulate; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23]
wire [2:0] new_entry_opa_bits_end_norm_cmd; // @[ReservationStation.scala:171:23]
wire [10:0] new_entry_opa_bits_end_garbage; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_end_garbage_bit; // @[ReservationStation.scala:171:23]
wire [13:0] new_entry_opa_bits_end_data; // @[ReservationStation.scala:171:23]
wire new_entry_opa_bits_wraps_around; // @[ReservationStation.scala:171:23]
wire new_entry_opa_valid; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_start_accumulate; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23]
wire [2:0] new_entry_opb_bits_start_norm_cmd; // @[ReservationStation.scala:171:23]
wire [10:0] new_entry_opb_bits_start_garbage; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_start_garbage_bit; // @[ReservationStation.scala:171:23]
wire [13:0] new_entry_opb_bits_start_data; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_end_accumulate; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23]
wire [2:0] new_entry_opb_bits_end_norm_cmd; // @[ReservationStation.scala:171:23]
wire [10:0] new_entry_opb_bits_end_garbage; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_end_garbage_bit; // @[ReservationStation.scala:171:23]
wire [13:0] new_entry_opb_bits_end_data; // @[ReservationStation.scala:171:23]
wire new_entry_opb_bits_wraps_around; // @[ReservationStation.scala:171:23]
wire new_entry_opb_valid; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_0; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_1; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_2; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_3; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_4; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_5; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_6; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ld_7; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_0; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_1; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_2; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_3; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_4; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_5; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_6; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_7; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_8; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_9; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_10; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_11; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_12; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_13; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_14; // @[ReservationStation.scala:171:23]
wire new_entry_deps_ex_15; // @[ReservationStation.scala:171:23]
wire new_entry_deps_st_0; // @[ReservationStation.scala:171:23]
wire new_entry_deps_st_1; // @[ReservationStation.scala:171:23]
wire new_entry_deps_st_2; // @[ReservationStation.scala:171:23]
wire new_entry_deps_st_3; // @[ReservationStation.scala:171:23]
wire [1:0] new_entry_q; // @[ReservationStation.scala:171:23]
wire new_entry_is_config; // @[ReservationStation.scala:171:23]
wire new_entry_opa_is_dst; // @[ReservationStation.scala:171:23]
wire new_entry_complete_on_issue; // @[ReservationStation.scala:171:23]
wire new_allocs_oh_ld_0; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ld_1; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ld_2; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ld_3; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ld_4; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ld_5; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ld_6; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ld_7; // @[ReservationStation.scala:174:30]
wire new_allocs_oh_ex_0; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_1; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_2; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_3; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_4; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_5; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_6; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_7; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_8; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_9; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_10; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_11; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_12; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_13; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_14; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_ex_15; // @[ReservationStation.scala:175:30]
wire new_allocs_oh_st_0; // @[ReservationStation.scala:176:30]
wire new_allocs_oh_st_1; // @[ReservationStation.scala:176:30]
wire new_allocs_oh_st_2; // @[ReservationStation.scala:176:30]
wire new_allocs_oh_st_3; // @[ReservationStation.scala:176:30]
wire _funct_is_compute_T = io_alloc_bits_cmd_inst_funct_0 == 7'h5; // @[ReservationStation.scala:26:7, :188:34]
wire _funct_is_compute_T_1 = io_alloc_bits_cmd_inst_funct_0 == 7'h4; // @[ReservationStation.scala:26:7, :188:68]
wire funct_is_compute = _funct_is_compute_T | _funct_is_compute_T_1; // @[ReservationStation.scala:188:{34,59,68}]
wire [1:0] config_cmd_type = io_alloc_bits_cmd_rs1_0[1:0]; // @[ReservationStation.scala:26:7, :189:34]
wire _GEN_19 = io_alloc_bits_cmd_inst_funct_0 == 7'h0; // @[ReservationStation.scala:26:7, :194:34]
assign _new_entry_is_config_T = _GEN_19; // @[ReservationStation.scala:194:34]
wire _is_load_T_5; // @[ReservationStation.scala:295:94]
assign _is_load_T_5 = _GEN_19; // @[ReservationStation.scala:194:34, :295:94]
wire _is_ex_T_2; // @[ReservationStation.scala:296:69]
assign _is_ex_T_2 = _GEN_19; // @[ReservationStation.scala:194:34, :296:69]
wire _is_store_T_1; // @[ReservationStation.scala:297:50]
assign _is_store_T_1 = _GEN_19; // @[ReservationStation.scala:194:34, :297:50]
wire _is_norm_T; // @[ReservationStation.scala:298:25]
assign _is_norm_T = _GEN_19; // @[ReservationStation.scala:194:34, :298:25]
assign new_entry_is_config = _new_entry_is_config_T; // @[ReservationStation.scala:171:23, :194:34]
wire _op1_valid_T_1; // @[ReservationStation.scala:216:40]
wire _op1_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:217:39]
wire _op1_bits_start_WIRE_accumulate; // @[ReservationStation.scala:217:39]
wire op1_bits_end_result_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19]
wire op1_bits_end_result_1_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_1_is_acc_addr = op1_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19]
wire _op1_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:217:39]
wire op1_bits_end_result_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19]
wire op1_bits_end_result_1_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_1_accumulate = op1_bits_start_accumulate; // @[ReservationStation.scala:196:19]
wire [2:0] _op1_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:217:39]
wire op1_bits_end_result_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19]
wire op1_bits_end_result_1_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_1_read_full_acc_row = op1_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19]
wire [10:0] _op1_bits_start_WIRE_garbage; // @[ReservationStation.scala:217:39]
wire [2:0] op1_bits_end_result_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19]
wire [2:0] op1_bits_wraps_around_result_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19]
wire [2:0] op1_bits_end_result_1_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19]
wire [2:0] op1_bits_wraps_around_result_1_norm_cmd = op1_bits_start_norm_cmd; // @[ReservationStation.scala:196:19]
wire _op1_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:217:39]
wire [10:0] op1_bits_end_result_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19]
wire [10:0] op1_bits_wraps_around_result_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19]
wire [10:0] op1_bits_end_result_1_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19]
wire [10:0] op1_bits_wraps_around_result_1_garbage = op1_bits_start_garbage; // @[ReservationStation.scala:196:19]
wire [13:0] _op1_bits_start_WIRE_data; // @[ReservationStation.scala:217:39]
wire op1_bits_end_result_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19]
wire op1_bits_end_result_1_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around_result_1_garbage_bit = op1_bits_start_garbage_bit; // @[ReservationStation.scala:196:19]
wire [13:0] op1_bits_start_data; // @[ReservationStation.scala:196:19]
wire op1_bits_end_is_acc_addr; // @[ReservationStation.scala:196:19]
wire op1_bits_end_accumulate; // @[ReservationStation.scala:196:19]
wire op1_bits_end_read_full_acc_row; // @[ReservationStation.scala:196:19]
wire [2:0] op1_bits_end_norm_cmd; // @[ReservationStation.scala:196:19]
wire [10:0] op1_bits_end_garbage; // @[ReservationStation.scala:196:19]
wire op1_bits_end_garbage_bit; // @[ReservationStation.scala:196:19]
wire [13:0] op1_bits_end_data; // @[ReservationStation.scala:196:19]
wire op1_bits_wraps_around; // @[ReservationStation.scala:196:19]
wire op1_valid; // @[ReservationStation.scala:196:19]
wire _op2_valid_T_1; // @[ReservationStation.scala:231:35]
wire _op2_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:232:39]
wire _op2_bits_start_WIRE_accumulate; // @[ReservationStation.scala:232:39]
wire op2_bits_end_result_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19]
wire op2_bits_end_result_1_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_1_is_acc_addr = op2_bits_start_is_acc_addr; // @[ReservationStation.scala:199:19]
wire _op2_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:232:39]
wire op2_bits_end_result_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19]
wire op2_bits_end_result_1_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_1_accumulate = op2_bits_start_accumulate; // @[ReservationStation.scala:199:19]
wire [2:0] _op2_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:232:39]
wire op2_bits_end_result_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19]
wire op2_bits_end_result_1_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_1_read_full_acc_row = op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:199:19]
wire [10:0] _op2_bits_start_WIRE_garbage; // @[ReservationStation.scala:232:39]
wire [2:0] op2_bits_end_result_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19]
wire [2:0] op2_bits_wraps_around_result_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19]
wire [2:0] op2_bits_end_result_1_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19]
wire [2:0] op2_bits_wraps_around_result_1_norm_cmd = op2_bits_start_norm_cmd; // @[ReservationStation.scala:199:19]
wire _op2_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:232:39]
wire [10:0] op2_bits_end_result_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19]
wire [10:0] op2_bits_wraps_around_result_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19]
wire [10:0] op2_bits_end_result_1_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19]
wire [10:0] op2_bits_wraps_around_result_1_garbage = op2_bits_start_garbage; // @[ReservationStation.scala:199:19]
wire [13:0] _op2_bits_start_WIRE_data; // @[ReservationStation.scala:232:39]
wire op2_bits_end_result_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19]
wire op2_bits_end_result_1_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around_result_1_garbage_bit = op2_bits_start_garbage_bit; // @[ReservationStation.scala:199:19]
wire [13:0] op2_bits_start_data; // @[ReservationStation.scala:199:19]
wire op2_bits_end_is_acc_addr; // @[ReservationStation.scala:199:19]
wire op2_bits_end_accumulate; // @[ReservationStation.scala:199:19]
wire op2_bits_end_read_full_acc_row; // @[ReservationStation.scala:199:19]
wire [2:0] op2_bits_end_norm_cmd; // @[ReservationStation.scala:199:19]
wire [10:0] op2_bits_end_garbage; // @[ReservationStation.scala:199:19]
wire op2_bits_end_garbage_bit; // @[ReservationStation.scala:199:19]
wire [13:0] op2_bits_end_data; // @[ReservationStation.scala:199:19]
wire op2_bits_wraps_around; // @[ReservationStation.scala:199:19]
wire op2_valid; // @[ReservationStation.scala:199:19]
wire _dst_valid_T_6; // @[ReservationStation.scala:261:85]
assign new_entry_opa_is_dst = dst_valid; // @[ReservationStation.scala:171:23, :202:19]
wire dst_bits_end_result_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19]
wire dst_bits_end_result_1_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_1_is_acc_addr = dst_bits_start_is_acc_addr; // @[ReservationStation.scala:202:19]
wire dst_bits_end_result_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19]
wire dst_bits_end_result_1_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_1_accumulate = dst_bits_start_accumulate; // @[ReservationStation.scala:202:19]
wire dst_bits_end_result_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19]
wire dst_bits_end_result_1_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_1_read_full_acc_row = dst_bits_start_read_full_acc_row; // @[ReservationStation.scala:202:19]
wire [2:0] dst_bits_end_result_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19]
wire [2:0] dst_bits_wraps_around_result_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19]
wire [2:0] dst_bits_end_result_1_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19]
wire [2:0] dst_bits_wraps_around_result_1_norm_cmd = dst_bits_start_norm_cmd; // @[ReservationStation.scala:202:19]
wire [10:0] dst_bits_end_result_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19]
wire [10:0] dst_bits_wraps_around_result_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19]
wire [10:0] dst_bits_end_result_1_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19]
wire [10:0] dst_bits_wraps_around_result_1_garbage = dst_bits_start_garbage; // @[ReservationStation.scala:202:19]
wire dst_bits_end_result_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19]
wire dst_bits_end_result_1_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around_result_1_garbage_bit = dst_bits_start_garbage_bit; // @[ReservationStation.scala:202:19]
wire [13:0] dst_bits_start_data; // @[ReservationStation.scala:202:19]
wire dst_bits_end_is_acc_addr; // @[ReservationStation.scala:202:19]
wire dst_bits_end_accumulate; // @[ReservationStation.scala:202:19]
wire dst_bits_end_read_full_acc_row; // @[ReservationStation.scala:202:19]
wire [2:0] dst_bits_end_norm_cmd; // @[ReservationStation.scala:202:19]
wire [10:0] dst_bits_end_garbage; // @[ReservationStation.scala:202:19]
wire dst_bits_end_garbage_bit; // @[ReservationStation.scala:202:19]
wire [13:0] dst_bits_end_data; // @[ReservationStation.scala:202:19]
wire dst_bits_wraps_around; // @[ReservationStation.scala:202:19]
wire _GEN_20 = op1_valid ? op1_valid : op2_valid; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_valid; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_valid = _GEN_20; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_valid; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_valid = _GEN_20; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_21 = op1_valid ? op1_bits_start_is_acc_addr : op2_bits_start_is_acc_addr; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_start_is_acc_addr; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_start_is_acc_addr = _GEN_21; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_start_is_acc_addr; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_start_is_acc_addr = _GEN_21; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_22 = op1_valid ? op1_bits_start_accumulate : op2_bits_start_accumulate; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_start_accumulate; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_start_accumulate = _GEN_22; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_start_accumulate; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_start_accumulate = _GEN_22; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_23 = op1_valid ? op1_bits_start_read_full_acc_row : op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_start_read_full_acc_row; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_start_read_full_acc_row = _GEN_23; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_start_read_full_acc_row; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_start_read_full_acc_row = _GEN_23; // @[ReservationStation.scala:210:27, :212:27]
wire [2:0] _GEN_24 = op1_valid ? op1_bits_start_norm_cmd : op2_bits_start_norm_cmd; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire [2:0] _new_entry_opb_T_bits_start_norm_cmd; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_start_norm_cmd = _GEN_24; // @[ReservationStation.scala:210:27]
wire [2:0] _new_entry_opa_T_bits_start_norm_cmd; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_start_norm_cmd = _GEN_24; // @[ReservationStation.scala:210:27, :212:27]
wire [10:0] _GEN_25 = op1_valid ? op1_bits_start_garbage : op2_bits_start_garbage; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire [10:0] _new_entry_opb_T_bits_start_garbage; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_start_garbage = _GEN_25; // @[ReservationStation.scala:210:27]
wire [10:0] _new_entry_opa_T_bits_start_garbage; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_start_garbage = _GEN_25; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_26 = op1_valid ? op1_bits_start_garbage_bit : op2_bits_start_garbage_bit; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_start_garbage_bit; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_start_garbage_bit = _GEN_26; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_start_garbage_bit; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_start_garbage_bit = _GEN_26; // @[ReservationStation.scala:210:27, :212:27]
wire [13:0] _GEN_27 = op1_valid ? op1_bits_start_data : op2_bits_start_data; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire [13:0] _new_entry_opb_T_bits_start_data; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_start_data = _GEN_27; // @[ReservationStation.scala:210:27]
wire [13:0] _new_entry_opa_T_bits_start_data; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_start_data = _GEN_27; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_28 = op1_valid ? op1_bits_end_is_acc_addr : op2_bits_end_is_acc_addr; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_end_is_acc_addr; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_end_is_acc_addr = _GEN_28; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_end_is_acc_addr; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_end_is_acc_addr = _GEN_28; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_29 = op1_valid ? op1_bits_end_accumulate : op2_bits_end_accumulate; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_end_accumulate; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_end_accumulate = _GEN_29; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_end_accumulate; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_end_accumulate = _GEN_29; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_30 = op1_valid ? op1_bits_end_read_full_acc_row : op2_bits_end_read_full_acc_row; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_end_read_full_acc_row; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_end_read_full_acc_row = _GEN_30; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_end_read_full_acc_row; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_end_read_full_acc_row = _GEN_30; // @[ReservationStation.scala:210:27, :212:27]
wire [2:0] _GEN_31 = op1_valid ? op1_bits_end_norm_cmd : op2_bits_end_norm_cmd; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire [2:0] _new_entry_opb_T_bits_end_norm_cmd; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_end_norm_cmd = _GEN_31; // @[ReservationStation.scala:210:27]
wire [2:0] _new_entry_opa_T_bits_end_norm_cmd; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_end_norm_cmd = _GEN_31; // @[ReservationStation.scala:210:27, :212:27]
wire [10:0] _GEN_32 = op1_valid ? op1_bits_end_garbage : op2_bits_end_garbage; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire [10:0] _new_entry_opb_T_bits_end_garbage; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_end_garbage = _GEN_32; // @[ReservationStation.scala:210:27]
wire [10:0] _new_entry_opa_T_bits_end_garbage; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_end_garbage = _GEN_32; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_33 = op1_valid ? op1_bits_end_garbage_bit : op2_bits_end_garbage_bit; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_end_garbage_bit; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_end_garbage_bit = _GEN_33; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_end_garbage_bit; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_end_garbage_bit = _GEN_33; // @[ReservationStation.scala:210:27, :212:27]
wire [13:0] _GEN_34 = op1_valid ? op1_bits_end_data : op2_bits_end_data; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire [13:0] _new_entry_opb_T_bits_end_data; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_end_data = _GEN_34; // @[ReservationStation.scala:210:27]
wire [13:0] _new_entry_opa_T_bits_end_data; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_end_data = _GEN_34; // @[ReservationStation.scala:210:27, :212:27]
wire _GEN_35 = op1_valid ? op1_bits_wraps_around : op2_bits_wraps_around; // @[ReservationStation.scala:196:19, :199:19, :210:27]
wire _new_entry_opb_T_bits_wraps_around; // @[ReservationStation.scala:210:27]
assign _new_entry_opb_T_bits_wraps_around = _GEN_35; // @[ReservationStation.scala:210:27]
wire _new_entry_opa_T_bits_wraps_around; // @[ReservationStation.scala:212:27]
assign _new_entry_opa_T_bits_wraps_around = _GEN_35; // @[ReservationStation.scala:210:27, :212:27]
assign new_entry_opa_valid = dst_valid ? dst_valid : _new_entry_opa_T_valid; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_start_is_acc_addr = dst_valid ? dst_bits_start_is_acc_addr : _new_entry_opa_T_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_start_accumulate = dst_valid ? dst_bits_start_accumulate : _new_entry_opa_T_bits_start_accumulate; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_start_read_full_acc_row = dst_valid ? dst_bits_start_read_full_acc_row : _new_entry_opa_T_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_start_norm_cmd = dst_valid ? dst_bits_start_norm_cmd : _new_entry_opa_T_bits_start_norm_cmd; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_start_garbage = dst_valid ? dst_bits_start_garbage : _new_entry_opa_T_bits_start_garbage; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_start_garbage_bit = dst_valid ? dst_bits_start_garbage_bit : _new_entry_opa_T_bits_start_garbage_bit; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_start_data = dst_valid ? dst_bits_start_data : _new_entry_opa_T_bits_start_data; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_end_is_acc_addr = dst_valid ? dst_bits_end_is_acc_addr : _new_entry_opa_T_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_end_accumulate = dst_valid ? dst_bits_end_accumulate : _new_entry_opa_T_bits_end_accumulate; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_end_read_full_acc_row = dst_valid ? dst_bits_end_read_full_acc_row : _new_entry_opa_T_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_end_norm_cmd = dst_valid ? dst_bits_end_norm_cmd : _new_entry_opa_T_bits_end_norm_cmd; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_end_garbage = dst_valid ? dst_bits_end_garbage : _new_entry_opa_T_bits_end_garbage; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_end_garbage_bit = dst_valid ? dst_bits_end_garbage_bit : _new_entry_opa_T_bits_end_garbage_bit; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_end_data = dst_valid ? dst_bits_end_data : _new_entry_opa_T_bits_end_data; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opa_bits_wraps_around = dst_valid ? dst_bits_wraps_around : _new_entry_opa_T_bits_wraps_around; // @[ReservationStation.scala:171:23, :202:19, :208:22, :209:21, :212:{21,27}]
assign new_entry_opb_valid = dst_valid ? _new_entry_opb_T_valid : op2_valid; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_start_is_acc_addr = dst_valid ? _new_entry_opb_T_bits_start_is_acc_addr : op2_bits_start_is_acc_addr; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_start_accumulate = dst_valid ? _new_entry_opb_T_bits_start_accumulate : op2_bits_start_accumulate; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_start_read_full_acc_row = dst_valid ? _new_entry_opb_T_bits_start_read_full_acc_row : op2_bits_start_read_full_acc_row; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_start_norm_cmd = dst_valid ? _new_entry_opb_T_bits_start_norm_cmd : op2_bits_start_norm_cmd; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_start_garbage = dst_valid ? _new_entry_opb_T_bits_start_garbage : op2_bits_start_garbage; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_start_garbage_bit = dst_valid ? _new_entry_opb_T_bits_start_garbage_bit : op2_bits_start_garbage_bit; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_start_data = dst_valid ? _new_entry_opb_T_bits_start_data : op2_bits_start_data; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_end_is_acc_addr = dst_valid ? _new_entry_opb_T_bits_end_is_acc_addr : op2_bits_end_is_acc_addr; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_end_accumulate = dst_valid ? _new_entry_opb_T_bits_end_accumulate : op2_bits_end_accumulate; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_end_read_full_acc_row = dst_valid ? _new_entry_opb_T_bits_end_read_full_acc_row : op2_bits_end_read_full_acc_row; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_end_norm_cmd = dst_valid ? _new_entry_opb_T_bits_end_norm_cmd : op2_bits_end_norm_cmd; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_end_garbage = dst_valid ? _new_entry_opb_T_bits_end_garbage : op2_bits_end_garbage; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_end_garbage_bit = dst_valid ? _new_entry_opb_T_bits_end_garbage_bit : op2_bits_end_garbage_bit; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_end_data = dst_valid ? _new_entry_opb_T_bits_end_data : op2_bits_end_data; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
assign new_entry_opb_bits_wraps_around = dst_valid ? _new_entry_opb_T_bits_wraps_around : op2_bits_wraps_around; // @[ReservationStation.scala:171:23, :199:19, :202:19, :208:22, :210:{21,27}, :213:21]
wire _T_4831 = io_alloc_bits_cmd_inst_funct_0 == 7'h6; // @[ReservationStation.scala:26:7, :216:24]
wire _op1_valid_T; // @[ReservationStation.scala:216:24]
assign _op1_valid_T = _T_4831; // @[ReservationStation.scala:216:24]
wire _dst_valid_T; // @[ReservationStation.scala:261:24]
assign _dst_valid_T = _T_4831; // @[ReservationStation.scala:216:24, :261:24]
wire _is_ex_T; // @[ReservationStation.scala:296:23]
assign _is_ex_T = _T_4831; // @[ReservationStation.scala:216:24, :296:23]
assign _op1_valid_T_1 = _op1_valid_T | funct_is_compute; // @[ReservationStation.scala:188:59, :216:{24,40}]
assign op1_valid = _op1_valid_T_1; // @[ReservationStation.scala:196:19, :216:40]
wire _op1_bits_start_T_6; // @[ReservationStation.scala:217:39]
assign op1_bits_start_is_acc_addr = _op1_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:196:19, :217:39]
wire _op1_bits_start_T_5; // @[ReservationStation.scala:217:39]
assign op1_bits_start_accumulate = _op1_bits_start_WIRE_accumulate; // @[ReservationStation.scala:196:19, :217:39]
wire _op1_bits_start_T_4; // @[ReservationStation.scala:217:39]
assign op1_bits_start_read_full_acc_row = _op1_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:196:19, :217:39]
wire [2:0] _op1_bits_start_WIRE_3; // @[ReservationStation.scala:217:39]
assign op1_bits_start_norm_cmd = _op1_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:196:19, :217:39]
wire [10:0] _op1_bits_start_T_2; // @[ReservationStation.scala:217:39]
assign op1_bits_start_garbage = _op1_bits_start_WIRE_garbage; // @[ReservationStation.scala:196:19, :217:39]
wire _op1_bits_start_T_1; // @[ReservationStation.scala:217:39]
assign op1_bits_start_garbage_bit = _op1_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:196:19, :217:39]
wire [13:0] _op1_bits_start_T; // @[ReservationStation.scala:217:39]
assign op1_bits_start_data = _op1_bits_start_WIRE_data; // @[ReservationStation.scala:196:19, :217:39]
wire [31:0] _op1_bits_start_WIRE_1 = io_alloc_bits_cmd_rs1_0[31:0]; // @[ReservationStation.scala:26:7, :217:39]
assign _op1_bits_start_T = _op1_bits_start_WIRE_1[13:0]; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_data = _op1_bits_start_T; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_T_1 = _op1_bits_start_WIRE_1[14]; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_garbage_bit = _op1_bits_start_T_1; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_T_2 = _op1_bits_start_WIRE_1[25:15]; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_garbage = _op1_bits_start_T_2; // @[ReservationStation.scala:217:39]
wire [2:0] _op1_bits_start_T_3 = _op1_bits_start_WIRE_1[28:26]; // @[ReservationStation.scala:217:39]
wire [2:0] _op1_bits_start_WIRE_2 = _op1_bits_start_T_3; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_3 = _op1_bits_start_WIRE_2; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_norm_cmd = _op1_bits_start_WIRE_3; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_T_4 = _op1_bits_start_WIRE_1[29]; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_read_full_acc_row = _op1_bits_start_T_4; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_T_5 = _op1_bits_start_WIRE_1[30]; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_accumulate = _op1_bits_start_T_5; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_T_6 = _op1_bits_start_WIRE_1[31]; // @[ReservationStation.scala:217:39]
assign _op1_bits_start_WIRE_is_acc_addr = _op1_bits_start_T_6; // @[ReservationStation.scala:217:39]
wire [4:0] preload_rows = io_alloc_bits_cmd_rs1_0[52:48]; // @[ReservationStation.scala:26:7, :220:33]
wire [4:0] rows = io_alloc_bits_cmd_rs1_0[52:48]; // @[ReservationStation.scala:26:7, :220:33, :224:25]
wire [13:0] _op1_bits_end_result_data_T_1; // @[LocalAddr.scala:51:25]
wire [13:0] op1_bits_end_result_data; // @[LocalAddr.scala:50:26]
wire [14:0] _GEN_36 = {1'h0, op1_bits_start_data} + {10'h0, preload_rows}; // @[ReservationStation.scala:196:19, :220:33]
wire [14:0] _op1_bits_end_result_data_T; // @[LocalAddr.scala:51:25]
assign _op1_bits_end_result_data_T = _GEN_36; // @[LocalAddr.scala:51:25]
wire [14:0] op1_bits_wraps_around_sum; // @[LocalAddr.scala:71:20]
assign op1_bits_wraps_around_sum = _GEN_36; // @[LocalAddr.scala:51:25, :71:20]
assign _op1_bits_end_result_data_T_1 = _op1_bits_end_result_data_T[13:0]; // @[LocalAddr.scala:51:25]
assign op1_bits_end_result_data = _op1_bits_end_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25]
wire _op1_bits_wraps_around_overflow_T = op1_bits_wraps_around_sum[10]; // @[LocalAddr.scala:71:20, :73:40]
wire _op1_bits_wraps_around_overflow_T_1 = op1_bits_wraps_around_sum[14]; // @[LocalAddr.scala:71:20, :73:58]
wire op1_bits_wraps_around_overflow = op1_bits_start_is_acc_addr ? _op1_bits_wraps_around_overflow_T : _op1_bits_wraps_around_overflow_T_1; // @[ReservationStation.scala:196:19]
wire [13:0] _op1_bits_wraps_around_result_data_T; // @[LocalAddr.scala:76:23]
wire [13:0] op1_bits_wraps_around_result_data; // @[LocalAddr.scala:75:26]
assign _op1_bits_wraps_around_result_data_T = op1_bits_wraps_around_sum[13:0]; // @[LocalAddr.scala:71:20, :76:23]
assign op1_bits_wraps_around_result_data = _op1_bits_wraps_around_result_data_T; // @[LocalAddr.scala:75:26, :76:23]
wire [4:0] cols = io_alloc_bits_cmd_rs1_0[36:32]; // @[ReservationStation.scala:26:7, :225:25]
wire [4:0] _compute_rows_T = a_transpose ? cols : rows; // @[ReservationStation.scala:165:24, :224:25, :225:25, :226:29]
wire [18:0] compute_rows = {14'h0, _compute_rows_T} * {5'h0, a_stride}; // @[ReservationStation.scala:163:21, :226:{29,55}]
wire [13:0] op1_bits_end_result_1_data; // @[LocalAddr.scala:50:26]
wire [19:0] _GEN_37 = {6'h0, op1_bits_start_data} + {1'h0, compute_rows}; // @[ReservationStation.scala:196:19, :226:55]
wire [19:0] _op1_bits_end_result_data_T_2; // @[LocalAddr.scala:51:25]
assign _op1_bits_end_result_data_T_2 = _GEN_37; // @[LocalAddr.scala:51:25]
wire [19:0] op1_bits_wraps_around_sum_1; // @[LocalAddr.scala:71:20]
assign op1_bits_wraps_around_sum_1 = _GEN_37; // @[LocalAddr.scala:51:25, :71:20]
wire [18:0] _op1_bits_end_result_data_T_3 = _op1_bits_end_result_data_T_2[18:0]; // @[LocalAddr.scala:51:25]
assign op1_bits_end_result_1_data = _op1_bits_end_result_data_T_3[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
assign op1_bits_end_is_acc_addr = _T_4831 ? op1_bits_end_result_is_acc_addr : op1_bits_end_result_1_is_acc_addr; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20]
assign op1_bits_end_accumulate = _T_4831 ? op1_bits_end_result_accumulate : op1_bits_end_result_1_accumulate; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20]
assign op1_bits_end_read_full_acc_row = _T_4831 ? op1_bits_end_result_read_full_acc_row : op1_bits_end_result_1_read_full_acc_row; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20]
assign op1_bits_end_norm_cmd = _T_4831 ? op1_bits_end_result_norm_cmd : op1_bits_end_result_1_norm_cmd; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20]
assign op1_bits_end_garbage = _T_4831 ? op1_bits_end_result_garbage : op1_bits_end_result_1_garbage; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20]
assign op1_bits_end_garbage_bit = _T_4831 ? op1_bits_end_result_garbage_bit : op1_bits_end_result_1_garbage_bit; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20]
assign op1_bits_end_data = _T_4831 ? op1_bits_end_result_data : op1_bits_end_result_1_data; // @[ReservationStation.scala:196:19, :216:24, :218:34, :221:20, :227:20]
wire _op1_bits_wraps_around_overflow_T_2 = op1_bits_wraps_around_sum_1[10]; // @[LocalAddr.scala:71:20, :73:40]
wire _op1_bits_wraps_around_overflow_T_3 = op1_bits_wraps_around_sum_1[14]; // @[LocalAddr.scala:71:20, :73:58]
wire op1_bits_wraps_around_overflow_1 = op1_bits_start_is_acc_addr ? _op1_bits_wraps_around_overflow_T_2 : _op1_bits_wraps_around_overflow_T_3; // @[ReservationStation.scala:196:19]
wire [13:0] _op1_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:76:23]
wire [13:0] op1_bits_wraps_around_result_1_data; // @[LocalAddr.scala:75:26]
assign _op1_bits_wraps_around_result_data_T_1 = op1_bits_wraps_around_sum_1[13:0]; // @[LocalAddr.scala:71:20, :76:23]
assign op1_bits_wraps_around_result_1_data = _op1_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:75:26, :76:23]
assign op1_bits_wraps_around = _T_4831 ? op1_bits_wraps_around_overflow : op1_bits_wraps_around_overflow_1; // @[ReservationStation.scala:196:19, :216:24, :218:34, :222:29, :228:29]
wire _GEN_38 = io_alloc_bits_cmd_inst_funct_0 == 7'h3; // @[ReservationStation.scala:26:7, :231:44]
wire _op2_valid_T; // @[ReservationStation.scala:231:44]
assign _op2_valid_T = _GEN_38; // @[ReservationStation.scala:231:44]
wire _is_store_T; // @[ReservationStation.scala:297:26]
assign _is_store_T = _GEN_38; // @[ReservationStation.scala:231:44, :297:26]
assign _op2_valid_T_1 = funct_is_compute | _op2_valid_T; // @[ReservationStation.scala:188:59, :231:{35,44}]
assign op2_valid = _op2_valid_T_1; // @[ReservationStation.scala:199:19, :231:35]
wire _op2_bits_start_T_6; // @[ReservationStation.scala:232:39]
assign op2_bits_start_is_acc_addr = _op2_bits_start_WIRE_is_acc_addr; // @[ReservationStation.scala:199:19, :232:39]
wire _op2_bits_start_T_5; // @[ReservationStation.scala:232:39]
assign op2_bits_start_accumulate = _op2_bits_start_WIRE_accumulate; // @[ReservationStation.scala:199:19, :232:39]
wire _op2_bits_start_T_4; // @[ReservationStation.scala:232:39]
assign op2_bits_start_read_full_acc_row = _op2_bits_start_WIRE_read_full_acc_row; // @[ReservationStation.scala:199:19, :232:39]
wire [2:0] _op2_bits_start_WIRE_3; // @[ReservationStation.scala:232:39]
assign op2_bits_start_norm_cmd = _op2_bits_start_WIRE_norm_cmd; // @[ReservationStation.scala:199:19, :232:39]
wire [10:0] _op2_bits_start_T_2; // @[ReservationStation.scala:232:39]
assign op2_bits_start_garbage = _op2_bits_start_WIRE_garbage; // @[ReservationStation.scala:199:19, :232:39]
wire _op2_bits_start_T_1; // @[ReservationStation.scala:232:39]
assign op2_bits_start_garbage_bit = _op2_bits_start_WIRE_garbage_bit; // @[ReservationStation.scala:199:19, :232:39]
wire [13:0] _op2_bits_start_T; // @[ReservationStation.scala:232:39]
assign op2_bits_start_data = _op2_bits_start_WIRE_data; // @[ReservationStation.scala:199:19, :232:39]
wire [31:0] _op2_bits_start_WIRE_1 = io_alloc_bits_cmd_rs2_0[31:0]; // @[ReservationStation.scala:26:7, :232:39]
wire [31:0] _dst_bits_start_T = io_alloc_bits_cmd_rs2_0[31:0]; // @[ReservationStation.scala:26:7, :232:39, :262:30]
wire [31:0] _start_T = io_alloc_bits_cmd_rs2_0[31:0]; // @[ReservationStation.scala:26:7, :232:39, :281:28]
assign _op2_bits_start_T = _op2_bits_start_WIRE_1[13:0]; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_data = _op2_bits_start_T; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_T_1 = _op2_bits_start_WIRE_1[14]; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_garbage_bit = _op2_bits_start_T_1; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_T_2 = _op2_bits_start_WIRE_1[25:15]; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_garbage = _op2_bits_start_T_2; // @[ReservationStation.scala:232:39]
wire [2:0] _op2_bits_start_T_3 = _op2_bits_start_WIRE_1[28:26]; // @[ReservationStation.scala:232:39]
wire [2:0] _op2_bits_start_WIRE_2 = _op2_bits_start_T_3; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_3 = _op2_bits_start_WIRE_2; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_norm_cmd = _op2_bits_start_WIRE_3; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_T_4 = _op2_bits_start_WIRE_1[29]; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_read_full_acc_row = _op2_bits_start_T_4; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_T_5 = _op2_bits_start_WIRE_1[30]; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_accumulate = _op2_bits_start_T_5; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_T_6 = _op2_bits_start_WIRE_1[31]; // @[ReservationStation.scala:232:39]
assign _op2_bits_start_WIRE_is_acc_addr = _op2_bits_start_T_6; // @[ReservationStation.scala:232:39]
wire [4:0] compute_rows_1 = io_alloc_bits_cmd_rs2_0[52:48]; // @[ReservationStation.scala:26:7, :234:33]
wire [4:0] mvout_rows = io_alloc_bits_cmd_rs2_0[52:48]; // @[ReservationStation.scala:26:7, :234:33, :252:31]
wire [4:0] _preload_rows_T = io_alloc_bits_cmd_rs2_0[52:48]; // @[ReservationStation.scala:26:7, :234:33, :264:33]
wire [4:0] mvin_rows = io_alloc_bits_cmd_rs2_0[52:48]; // @[ReservationStation.scala:26:7, :234:33, :274:30]
wire [13:0] _op2_bits_end_result_data_T_1; // @[LocalAddr.scala:51:25]
wire [13:0] op2_bits_end_result_data; // @[LocalAddr.scala:50:26]
wire [14:0] _GEN_39 = {1'h0, op2_bits_start_data}; // @[ReservationStation.scala:199:19]
wire [14:0] _GEN_40 = _GEN_39 + {10'h0, compute_rows_1}; // @[ReservationStation.scala:234:33]
wire [14:0] _op2_bits_end_result_data_T; // @[LocalAddr.scala:51:25]
assign _op2_bits_end_result_data_T = _GEN_40; // @[LocalAddr.scala:51:25]
wire [14:0] op2_bits_wraps_around_sum; // @[LocalAddr.scala:71:20]
assign op2_bits_wraps_around_sum = _GEN_40; // @[LocalAddr.scala:51:25, :71:20]
assign _op2_bits_end_result_data_T_1 = _op2_bits_end_result_data_T[13:0]; // @[LocalAddr.scala:51:25]
assign op2_bits_end_result_data = _op2_bits_end_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25]
wire _op2_bits_wraps_around_overflow_T = op2_bits_wraps_around_sum[10]; // @[LocalAddr.scala:71:20, :73:40]
wire _op2_bits_wraps_around_overflow_T_1 = op2_bits_wraps_around_sum[14]; // @[LocalAddr.scala:71:20, :73:58]
wire op2_bits_wraps_around_overflow = op2_bits_start_is_acc_addr ? _op2_bits_wraps_around_overflow_T : _op2_bits_wraps_around_overflow_T_1; // @[ReservationStation.scala:199:19]
wire [13:0] _op2_bits_wraps_around_result_data_T; // @[LocalAddr.scala:76:23]
wire [13:0] op2_bits_wraps_around_result_data; // @[LocalAddr.scala:75:26]
assign _op2_bits_wraps_around_result_data_T = op2_bits_wraps_around_sum[13:0]; // @[LocalAddr.scala:71:20, :76:23]
assign op2_bits_wraps_around_result_data = _op2_bits_wraps_around_result_data_T; // @[LocalAddr.scala:75:26, :76:23]
wire acc_bank = op2_bits_start_data[9]; // @[ReservationStation.scala:199:19]
wire [13:0] next_bank_addr_data; // @[ReservationStation.scala:242:36]
wire [1:0] _next_bank_addr_data_T = {1'h0, acc_bank} + 2'h1; // @[ReservationStation.scala:244:40]
wire _next_bank_addr_data_T_1 = _next_bank_addr_data_T[0]; // @[ReservationStation.scala:244:40]
wire [9:0] _next_bank_addr_data_T_2 = {_next_bank_addr_data_T_1, 9'h0}; // @[ReservationStation.scala:244:{40,47}]
assign next_bank_addr_data = {4'h0, _next_bank_addr_data_T_2}; // @[ReservationStation.scala:242:36, :244:{27,47}]
wire _op2_bits_wraps_around_T = next_bank_addr_data[9]; // @[ReservationStation.scala:242:36]
wire _op2_bits_wraps_around_T_1 = ~_op2_bits_wraps_around_T; // @[ReservationStation.scala:247:58]
wire [6:0] mvout_cols = io_alloc_bits_cmd_rs2_0[38:32]; // @[ReservationStation.scala:26:7, :251:31]
wire [6:0] mvin_cols = io_alloc_bits_cmd_rs2_0[38:32]; // @[ReservationStation.scala:26:7, :251:31, :273:30]
wire [6:0] _mvout_mats_T = mvout_cols / 7'h10; // @[ReservationStation.scala:251:31, :254:35]
wire [6:0] _GEN_41 = mvout_cols % 7'h10; // @[ReservationStation.scala:251:31, :254:83]
wire [4:0] _mvout_mats_T_1 = _GEN_41[4:0]; // @[ReservationStation.scala:254:83]
wire _mvout_mats_T_2 = |_mvout_mats_T_1; // @[ReservationStation.scala:254:{83,98}]
wire [7:0] _mvout_mats_T_3 = {1'h0, _mvout_mats_T} + {7'h0, _mvout_mats_T_2}; // @[ReservationStation.scala:254:{35,69,98}]
wire [6:0] mvout_mats = _mvout_mats_T_3[6:0]; // @[ReservationStation.scala:254:69]
wire [7:0] _total_mvout_rows_T = {1'h0, mvout_mats} - 8'h1; // @[ReservationStation.scala:254:69, :255:43]
wire [6:0] _total_mvout_rows_T_1 = _total_mvout_rows_T[6:0]; // @[ReservationStation.scala:255:43]
wire [11:0] _total_mvout_rows_T_2 = {1'h0, _total_mvout_rows_T_1, 4'h0}; // @[ReservationStation.scala:255:{43,50}]
wire [12:0] _total_mvout_rows_T_3 = {1'h0, _total_mvout_rows_T_2} + {8'h0, mvout_rows}; // @[ReservationStation.scala:252:31, :255:{50,66}]
wire [11:0] total_mvout_rows = _total_mvout_rows_T_3[11:0]; // @[ReservationStation.scala:255:66]
wire [13:0] _op2_bits_end_result_data_T_3; // @[LocalAddr.scala:51:25]
wire [13:0] op2_bits_end_result_1_data; // @[LocalAddr.scala:50:26]
wire [14:0] _GEN_42 = _GEN_39 + {3'h0, total_mvout_rows}; // @[ReservationStation.scala:255:66]
wire [14:0] _op2_bits_end_result_data_T_2; // @[LocalAddr.scala:51:25]
assign _op2_bits_end_result_data_T_2 = _GEN_42; // @[LocalAddr.scala:51:25]
wire [14:0] op2_bits_wraps_around_sum_1; // @[LocalAddr.scala:71:20]
assign op2_bits_wraps_around_sum_1 = _GEN_42; // @[LocalAddr.scala:51:25, :71:20]
assign _op2_bits_end_result_data_T_3 = _op2_bits_end_result_data_T_2[13:0]; // @[LocalAddr.scala:51:25]
assign op2_bits_end_result_1_data = _op2_bits_end_result_data_T_3; // @[LocalAddr.scala:50:26, :51:25]
assign op2_bits_end_is_acc_addr = funct_is_compute ? op2_bits_end_result_is_acc_addr : pooling_is_enabled | op2_bits_end_result_1_is_acc_addr; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20]
assign op2_bits_end_accumulate = funct_is_compute ? op2_bits_end_result_accumulate : ~pooling_is_enabled & op2_bits_end_result_1_accumulate; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20]
assign op2_bits_end_read_full_acc_row = funct_is_compute ? op2_bits_end_result_read_full_acc_row : ~pooling_is_enabled & op2_bits_end_result_1_read_full_acc_row; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20]
assign op2_bits_end_norm_cmd = funct_is_compute ? op2_bits_end_result_norm_cmd : pooling_is_enabled ? 3'h0 : op2_bits_end_result_1_norm_cmd; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20]
assign op2_bits_end_garbage = funct_is_compute ? op2_bits_end_result_garbage : pooling_is_enabled ? 11'h0 : op2_bits_end_result_1_garbage; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20]
assign op2_bits_end_garbage_bit = funct_is_compute ? op2_bits_end_result_garbage_bit : ~pooling_is_enabled & op2_bits_end_result_1_garbage_bit; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :246:20, :257:20]
assign op2_bits_end_data = funct_is_compute ? op2_bits_end_result_data : pooling_is_enabled ? next_bank_addr_data : op2_bits_end_result_1_data; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :235:20, :237:37, :242:36, :246:20, :257:20]
wire _op2_bits_wraps_around_overflow_T_2 = op2_bits_wraps_around_sum_1[10]; // @[LocalAddr.scala:71:20, :73:40]
wire _op2_bits_wraps_around_overflow_T_3 = op2_bits_wraps_around_sum_1[14]; // @[LocalAddr.scala:71:20, :73:58]
wire op2_bits_wraps_around_overflow_1 = op2_bits_start_is_acc_addr ? _op2_bits_wraps_around_overflow_T_2 : _op2_bits_wraps_around_overflow_T_3; // @[ReservationStation.scala:199:19]
wire [13:0] _op2_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:76:23]
wire [13:0] op2_bits_wraps_around_result_1_data; // @[LocalAddr.scala:75:26]
assign _op2_bits_wraps_around_result_data_T_1 = op2_bits_wraps_around_sum_1[13:0]; // @[LocalAddr.scala:71:20, :76:23]
assign op2_bits_wraps_around_result_1_data = _op2_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:75:26, :76:23]
wire _op2_bits_wraps_around_T_2 = pooling_is_enabled | op2_bits_wraps_around_overflow_1; // @[ReservationStation.scala:168:31, :258:51]
assign op2_bits_wraps_around = funct_is_compute ? op2_bits_wraps_around_overflow : pooling_is_enabled ? _op2_bits_wraps_around_T_1 : _op2_bits_wraps_around_T_2; // @[ReservationStation.scala:168:31, :188:59, :199:19, :233:29, :236:29, :237:37, :247:{29,58}, :258:{29,51}]
wire _GEN_43 = io_alloc_bits_cmd_inst_funct_0 == 7'h2; // @[ReservationStation.scala:26:7, :261:49]
wire _dst_valid_T_1; // @[ReservationStation.scala:261:49]
assign _dst_valid_T_1 = _GEN_43; // @[ReservationStation.scala:261:49]
wire _is_load_T; // @[ReservationStation.scala:295:25]
assign _is_load_T = _GEN_43; // @[ReservationStation.scala:261:49, :295:25]
wire _dst_valid_T_2 = _dst_valid_T | _dst_valid_T_1; // @[ReservationStation.scala:261:{24,40,49}]
wire _GEN_44 = io_alloc_bits_cmd_inst_funct_0 == 7'h1; // @[ReservationStation.scala:26:7, :261:71]
wire _dst_valid_T_3; // @[ReservationStation.scala:261:71]
assign _dst_valid_T_3 = _GEN_44; // @[ReservationStation.scala:261:71]
wire _is_load_T_1; // @[ReservationStation.scala:295:47]
assign _is_load_T_1 = _GEN_44; // @[ReservationStation.scala:261:71, :295:47]
wire _dst_valid_T_4 = _dst_valid_T_2 | _dst_valid_T_3; // @[ReservationStation.scala:261:{40,62,71}]
wire _GEN_45 = io_alloc_bits_cmd_inst_funct_0 == 7'hE; // @[ReservationStation.scala:26:7, :261:94]
wire _dst_valid_T_5; // @[ReservationStation.scala:261:94]
assign _dst_valid_T_5 = _GEN_45; // @[ReservationStation.scala:261:94]
wire _is_load_T_3; // @[ReservationStation.scala:295:70]
assign _is_load_T_3 = _GEN_45; // @[ReservationStation.scala:261:94, :295:70]
assign _dst_valid_T_6 = _dst_valid_T_4 | _dst_valid_T_5; // @[ReservationStation.scala:261:{62,85,94}]
assign dst_valid = _dst_valid_T_6; // @[ReservationStation.scala:202:19, :261:85]
wire [31:0] _dst_bits_start_WIRE_1 = _dst_bits_start_T; // @[ReservationStation.scala:262:{30,46}]
wire _dst_bits_start_T_7; // @[ReservationStation.scala:262:46]
wire _dst_bits_start_T_6; // @[ReservationStation.scala:262:46]
wire _dst_bits_start_T_5; // @[ReservationStation.scala:262:46]
wire [2:0] _dst_bits_start_WIRE_3; // @[ReservationStation.scala:262:46]
wire [10:0] _dst_bits_start_T_3; // @[ReservationStation.scala:262:46]
wire _dst_bits_start_T_2; // @[ReservationStation.scala:262:46]
wire [13:0] _dst_bits_start_T_1; // @[ReservationStation.scala:262:46]
assign _dst_bits_start_T_1 = _dst_bits_start_WIRE_1[13:0]; // @[ReservationStation.scala:262:46]
wire [13:0] _dst_bits_start_WIRE_data = _dst_bits_start_T_1; // @[ReservationStation.scala:262:46]
assign _dst_bits_start_T_2 = _dst_bits_start_WIRE_1[14]; // @[ReservationStation.scala:262:46]
wire _dst_bits_start_WIRE_garbage_bit = _dst_bits_start_T_2; // @[ReservationStation.scala:262:46]
assign _dst_bits_start_T_3 = _dst_bits_start_WIRE_1[25:15]; // @[ReservationStation.scala:262:46]
wire [10:0] _dst_bits_start_WIRE_garbage = _dst_bits_start_T_3; // @[ReservationStation.scala:262:46]
wire [2:0] _dst_bits_start_T_4 = _dst_bits_start_WIRE_1[28:26]; // @[ReservationStation.scala:262:46]
wire [2:0] _dst_bits_start_WIRE_2 = _dst_bits_start_T_4; // @[ReservationStation.scala:262:46]
assign _dst_bits_start_WIRE_3 = _dst_bits_start_WIRE_2; // @[ReservationStation.scala:262:46]
wire [2:0] _dst_bits_start_WIRE_norm_cmd = _dst_bits_start_WIRE_3; // @[ReservationStation.scala:262:46]
assign _dst_bits_start_T_5 = _dst_bits_start_WIRE_1[29]; // @[ReservationStation.scala:262:46]
wire _dst_bits_start_WIRE_read_full_acc_row = _dst_bits_start_T_5; // @[ReservationStation.scala:262:46]
assign _dst_bits_start_T_6 = _dst_bits_start_WIRE_1[30]; // @[ReservationStation.scala:262:46]
wire _dst_bits_start_WIRE_accumulate = _dst_bits_start_T_6; // @[ReservationStation.scala:262:46]
assign _dst_bits_start_T_7 = _dst_bits_start_WIRE_1[31]; // @[ReservationStation.scala:262:46]
wire _dst_bits_start_WIRE_is_acc_addr = _dst_bits_start_T_7; // @[ReservationStation.scala:262:46]
wire [18:0] preload_rows_1 = {14'h0, _preload_rows_T} * {5'h0, c_stride}; // @[ReservationStation.scala:164:21, :264:{33,71}]
wire [13:0] dst_bits_end_result_data; // @[LocalAddr.scala:50:26]
wire [19:0] _GEN_46 = {6'h0, dst_bits_start_data} + {1'h0, preload_rows_1}; // @[ReservationStation.scala:202:19, :264:71]
wire [19:0] _dst_bits_end_result_data_T; // @[LocalAddr.scala:51:25]
assign _dst_bits_end_result_data_T = _GEN_46; // @[LocalAddr.scala:51:25]
wire [19:0] dst_bits_wraps_around_sum; // @[LocalAddr.scala:71:20]
assign dst_bits_wraps_around_sum = _GEN_46; // @[LocalAddr.scala:51:25, :71:20]
wire [18:0] _dst_bits_end_result_data_T_1 = _dst_bits_end_result_data_T[18:0]; // @[LocalAddr.scala:51:25]
assign dst_bits_end_result_data = _dst_bits_end_result_data_T_1[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
wire _dst_bits_wraps_around_overflow_T = dst_bits_wraps_around_sum[10]; // @[LocalAddr.scala:71:20, :73:40]
wire _dst_bits_wraps_around_overflow_T_1 = dst_bits_wraps_around_sum[14]; // @[LocalAddr.scala:71:20, :73:58]
wire dst_bits_wraps_around_overflow = dst_bits_start_is_acc_addr ? _dst_bits_wraps_around_overflow_T : _dst_bits_wraps_around_overflow_T_1; // @[ReservationStation.scala:202:19]
wire [13:0] _dst_bits_wraps_around_result_data_T; // @[LocalAddr.scala:76:23]
wire [13:0] dst_bits_wraps_around_result_data; // @[LocalAddr.scala:75:26]
assign _dst_bits_wraps_around_result_data_T = dst_bits_wraps_around_sum[13:0]; // @[LocalAddr.scala:71:20, :76:23]
assign dst_bits_wraps_around_result_data = _dst_bits_wraps_around_result_data_T; // @[LocalAddr.scala:75:26, :76:23]
wire _id_T = new_entry_cmd_cmd_inst_funct == 7'h1; // @[ReservationStation.scala:171:23, :268:63]
wire _id_T_1 = new_entry_cmd_cmd_inst_funct == 7'hE; // @[ReservationStation.scala:171:23, :269:39]
wire [1:0] _id_T_2 = {_id_T_1, 1'h0}; // @[Mux.scala:126:16]
wire [1:0] id = _id_T ? 2'h1 : _id_T_2; // @[Mux.scala:126:16]
wire [6:0] _mvin_mats_T = mvin_cols / 7'h10; // @[ReservationStation.scala:273:30, :276:33]
wire [6:0] _GEN_47 = mvin_cols % 7'h10; // @[ReservationStation.scala:273:30, :276:79]
wire [4:0] _mvin_mats_T_1 = _GEN_47[4:0]; // @[ReservationStation.scala:276:79]
wire _mvin_mats_T_2 = |_mvin_mats_T_1; // @[ReservationStation.scala:276:{79,94}]
wire [7:0] _mvin_mats_T_3 = {1'h0, _mvin_mats_T} + {7'h0, _mvin_mats_T_2}; // @[ReservationStation.scala:276:{33,66,94}]
wire [6:0] mvin_mats = _mvin_mats_T_3[6:0]; // @[ReservationStation.scala:276:66]
wire [7:0] _total_mvin_rows_T = {1'h0, mvin_mats} - 8'h1; // @[ReservationStation.scala:276:66, :277:41]
wire [6:0] _total_mvin_rows_T_1 = _total_mvin_rows_T[6:0]; // @[ReservationStation.scala:277:41]
wire [3:0][13:0] _GEN_48 = {{ld_block_strides_0}, {ld_block_strides_2}, {ld_block_strides_1}, {ld_block_strides_0}}; // @[ReservationStation.scala:166:29, :277:48]
wire [20:0] _total_mvin_rows_T_2 = {14'h0, _total_mvin_rows_T_1} * {7'h0, _GEN_48[id]}; // @[Mux.scala:126:16]
wire [21:0] _total_mvin_rows_T_3 = {1'h0, _total_mvin_rows_T_2} + {17'h0, mvin_rows}; // @[ReservationStation.scala:274:30, :277:{48,64}]
wire [20:0] total_mvin_rows = _total_mvin_rows_T_3[20:0]; // @[ReservationStation.scala:277:64]
wire [31:0] _start_WIRE = _start_T; // @[ReservationStation.scala:281:{28,44}]
wire _start_T_7; // @[ReservationStation.scala:281:44]
wire _start_T_6; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_is_acc_addr = start_is_acc_addr; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_1_is_acc_addr = start_is_acc_addr; // @[ReservationStation.scala:281:44]
wire _start_T_5; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_accumulate = start_accumulate; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_1_accumulate = start_accumulate; // @[ReservationStation.scala:281:44]
wire [2:0] _start_WIRE_2; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_read_full_acc_row = start_read_full_acc_row; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_1_read_full_acc_row = start_read_full_acc_row; // @[ReservationStation.scala:281:44]
wire [10:0] _start_T_3; // @[ReservationStation.scala:281:44]
wire [2:0] dst_bits_start_result_norm_cmd = start_norm_cmd; // @[ReservationStation.scala:281:44]
wire [2:0] dst_bits_start_result_1_norm_cmd = start_norm_cmd; // @[ReservationStation.scala:281:44]
wire _start_T_2; // @[ReservationStation.scala:281:44]
wire [10:0] dst_bits_start_result_garbage = start_garbage; // @[ReservationStation.scala:281:44]
wire [10:0] dst_bits_start_result_1_garbage = start_garbage; // @[ReservationStation.scala:281:44]
wire [13:0] _start_T_1; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_garbage_bit = start_garbage_bit; // @[ReservationStation.scala:281:44]
wire dst_bits_start_result_1_garbage_bit = start_garbage_bit; // @[ReservationStation.scala:281:44]
wire [13:0] start_data; // @[ReservationStation.scala:281:44]
wire [13:0] _dst_bits_start_T_8 = start_data; // @[ReservationStation.scala:281:44]
assign _start_T_1 = _start_WIRE[13:0]; // @[ReservationStation.scala:281:44]
assign start_data = _start_T_1; // @[ReservationStation.scala:281:44]
assign _start_T_2 = _start_WIRE[14]; // @[ReservationStation.scala:281:44]
assign start_garbage_bit = _start_T_2; // @[ReservationStation.scala:281:44]
assign _start_T_3 = _start_WIRE[25:15]; // @[ReservationStation.scala:281:44]
assign start_garbage = _start_T_3; // @[ReservationStation.scala:281:44]
wire [2:0] _start_T_4 = _start_WIRE[28:26]; // @[ReservationStation.scala:281:44]
wire [2:0] _start_WIRE_1 = _start_T_4; // @[ReservationStation.scala:281:44]
assign _start_WIRE_2 = _start_WIRE_1; // @[ReservationStation.scala:281:44]
assign start_norm_cmd = _start_WIRE_2; // @[ReservationStation.scala:281:44]
assign _start_T_5 = _start_WIRE[29]; // @[ReservationStation.scala:281:44]
assign start_read_full_acc_row = _start_T_5; // @[ReservationStation.scala:281:44]
assign _start_T_6 = _start_WIRE[30]; // @[ReservationStation.scala:281:44]
assign start_accumulate = _start_T_6; // @[ReservationStation.scala:281:44]
assign _start_T_7 = _start_WIRE[31]; // @[ReservationStation.scala:281:44]
assign start_is_acc_addr = _start_T_7; // @[ReservationStation.scala:281:44]
wire _dst_bits_start_T_9 = _dst_bits_start_T_8 > 14'h2000; // @[ReservationStation.scala:284:36]
wire [3:0][4:0] _GEN_49 = {{ld_pixel_repeats_0}, {ld_pixel_repeats_2}, {ld_pixel_repeats_1}, {ld_pixel_repeats_0}}; // @[ReservationStation.scala:169:29]
wire [14:0] _GEN_50 = {10'h0, _GEN_49[id]}; // @[Mux.scala:126:16]
wire [14:0] _dst_bits_start_underflow_T = _GEN_50 + 15'h2000; // @[LocalAddr.scala:86:35]
wire [14:0] _GEN_51 = {1'h0, start_data}; // @[ReservationStation.scala:281:44]
wire dst_bits_start_underflow = _GEN_51 < _dst_bits_start_underflow_T; // @[LocalAddr.scala:86:{26,35}]
wire [13:0] _dst_bits_start_result_data_T_2; // @[LocalAddr.scala:89:23]
wire [13:0] dst_bits_start_result_data; // @[LocalAddr.scala:88:26]
wire [14:0] _GEN_52 = _GEN_51 - _GEN_50; // @[LocalAddr.scala:86:{26,35}, :89:47]
wire [14:0] _dst_bits_start_result_data_T; // @[LocalAddr.scala:89:47]
assign _dst_bits_start_result_data_T = _GEN_52; // @[LocalAddr.scala:89:47]
wire [14:0] _dst_bits_start_result_data_T_3; // @[LocalAddr.scala:89:47]
assign _dst_bits_start_result_data_T_3 = _GEN_52; // @[LocalAddr.scala:89:47]
wire [13:0] _dst_bits_start_result_data_T_1 = _dst_bits_start_result_data_T[13:0]; // @[LocalAddr.scala:89:47]
assign _dst_bits_start_result_data_T_2 = dst_bits_start_underflow ? 14'h2000 : _dst_bits_start_result_data_T_1; // @[LocalAddr.scala:86:26, :89:{23,47}]
assign dst_bits_start_result_data = _dst_bits_start_result_data_T_2; // @[LocalAddr.scala:88:26, :89:23]
wire [5:0] _dst_bits_start_underflow_T_1 = {1'h0, _GEN_49[id]}; // @[Mux.scala:126:16]
wire dst_bits_start_underflow_1 = start_data < {8'h0, _dst_bits_start_underflow_T_1}; // @[ReservationStation.scala:281:44]
wire [13:0] _dst_bits_start_result_data_T_5; // @[LocalAddr.scala:89:23]
wire [13:0] dst_bits_start_result_1_data; // @[LocalAddr.scala:88:26]
wire [13:0] _dst_bits_start_result_data_T_4 = _dst_bits_start_result_data_T_3[13:0]; // @[LocalAddr.scala:89:47]
assign _dst_bits_start_result_data_T_5 = dst_bits_start_underflow_1 ? 14'h0 : _dst_bits_start_result_data_T_4; // @[LocalAddr.scala:86:26, :89:{23,47}]
assign dst_bits_start_result_1_data = _dst_bits_start_result_data_T_5; // @[LocalAddr.scala:88:26, :89:23]
wire _dst_bits_start_T_10_is_acc_addr = _dst_bits_start_T_9 ? dst_bits_start_result_is_acc_addr : dst_bits_start_result_1_is_acc_addr; // @[ReservationStation.scala:284:{14,36}]
wire _dst_bits_start_T_10_accumulate = _dst_bits_start_T_9 ? dst_bits_start_result_accumulate : dst_bits_start_result_1_accumulate; // @[ReservationStation.scala:284:{14,36}]
wire _dst_bits_start_T_10_read_full_acc_row = _dst_bits_start_T_9 ? dst_bits_start_result_read_full_acc_row : dst_bits_start_result_1_read_full_acc_row; // @[ReservationStation.scala:284:{14,36}]
wire [2:0] _dst_bits_start_T_10_norm_cmd = _dst_bits_start_T_9 ? dst_bits_start_result_norm_cmd : dst_bits_start_result_1_norm_cmd; // @[ReservationStation.scala:284:{14,36}]
wire [10:0] _dst_bits_start_T_10_garbage = _dst_bits_start_T_9 ? dst_bits_start_result_garbage : dst_bits_start_result_1_garbage; // @[ReservationStation.scala:284:{14,36}]
wire _dst_bits_start_T_10_garbage_bit = _dst_bits_start_T_9 ? dst_bits_start_result_garbage_bit : dst_bits_start_result_1_garbage_bit; // @[ReservationStation.scala:284:{14,36}]
wire [13:0] _dst_bits_start_T_10_data = _dst_bits_start_T_9 ? dst_bits_start_result_data : dst_bits_start_result_1_data; // @[ReservationStation.scala:284:{14,36}]
wire _dst_bits_start_T_11_is_acc_addr = start_is_acc_addr ? start_is_acc_addr : _dst_bits_start_T_10_is_acc_addr; // @[ReservationStation.scala:281:44, :283:30, :284:14]
wire _dst_bits_start_T_11_accumulate = start_is_acc_addr ? start_accumulate : _dst_bits_start_T_10_accumulate; // @[ReservationStation.scala:281:44, :283:30, :284:14]
wire _dst_bits_start_T_11_read_full_acc_row = start_is_acc_addr ? start_read_full_acc_row : _dst_bits_start_T_10_read_full_acc_row; // @[ReservationStation.scala:281:44, :283:30, :284:14]
wire [2:0] _dst_bits_start_T_11_norm_cmd = start_is_acc_addr ? start_norm_cmd : _dst_bits_start_T_10_norm_cmd; // @[ReservationStation.scala:281:44, :283:30, :284:14]
wire [10:0] _dst_bits_start_T_11_garbage = start_is_acc_addr ? start_garbage : _dst_bits_start_T_10_garbage; // @[ReservationStation.scala:281:44, :283:30, :284:14]
wire _dst_bits_start_T_11_garbage_bit = start_is_acc_addr ? start_garbage_bit : _dst_bits_start_T_10_garbage_bit; // @[ReservationStation.scala:281:44, :283:30, :284:14]
wire [13:0] _dst_bits_start_T_11_data = start_is_acc_addr ? start_data : _dst_bits_start_T_10_data; // @[ReservationStation.scala:281:44, :283:30, :284:14]
assign dst_bits_start_is_acc_addr = _T_4831 ? _dst_bits_start_WIRE_is_acc_addr : _dst_bits_start_T_11_is_acc_addr; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}]
assign dst_bits_start_accumulate = _T_4831 ? _dst_bits_start_WIRE_accumulate : _dst_bits_start_T_11_accumulate; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}]
assign dst_bits_start_read_full_acc_row = _T_4831 ? _dst_bits_start_WIRE_read_full_acc_row : _dst_bits_start_T_11_read_full_acc_row; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}]
assign dst_bits_start_norm_cmd = _T_4831 ? _dst_bits_start_WIRE_norm_cmd : _dst_bits_start_T_11_norm_cmd; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}]
assign dst_bits_start_garbage = _T_4831 ? _dst_bits_start_WIRE_garbage : _dst_bits_start_T_11_garbage; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}]
assign dst_bits_start_garbage_bit = _T_4831 ? _dst_bits_start_WIRE_garbage_bit : _dst_bits_start_T_11_garbage_bit; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}]
assign dst_bits_start_data = _T_4831 ? _dst_bits_start_WIRE_data : _dst_bits_start_T_11_data; // @[ReservationStation.scala:202:19, :216:24, :262:{20,46}, :263:34, :283:{24,30}]
wire [13:0] dst_bits_end_result_1_data; // @[LocalAddr.scala:50:26]
wire [21:0] _GEN_53 = {8'h0, dst_bits_start_data} + {1'h0, total_mvin_rows}; // @[ReservationStation.scala:202:19, :277:64]
wire [21:0] _dst_bits_end_result_data_T_2; // @[LocalAddr.scala:51:25]
assign _dst_bits_end_result_data_T_2 = _GEN_53; // @[LocalAddr.scala:51:25]
wire [21:0] dst_bits_wraps_around_sum_1; // @[LocalAddr.scala:71:20]
assign dst_bits_wraps_around_sum_1 = _GEN_53; // @[LocalAddr.scala:51:25, :71:20]
wire [20:0] _dst_bits_end_result_data_T_3 = _dst_bits_end_result_data_T_2[20:0]; // @[LocalAddr.scala:51:25]
assign dst_bits_end_result_1_data = _dst_bits_end_result_data_T_3[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
assign dst_bits_end_is_acc_addr = _T_4831 ? dst_bits_end_result_is_acc_addr : dst_bits_end_result_1_is_acc_addr; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20]
assign dst_bits_end_accumulate = _T_4831 ? dst_bits_end_result_accumulate : dst_bits_end_result_1_accumulate; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20]
assign dst_bits_end_read_full_acc_row = _T_4831 ? dst_bits_end_result_read_full_acc_row : dst_bits_end_result_1_read_full_acc_row; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20]
assign dst_bits_end_norm_cmd = _T_4831 ? dst_bits_end_result_norm_cmd : dst_bits_end_result_1_norm_cmd; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20]
assign dst_bits_end_garbage = _T_4831 ? dst_bits_end_result_garbage : dst_bits_end_result_1_garbage; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20]
assign dst_bits_end_garbage_bit = _T_4831 ? dst_bits_end_result_garbage_bit : dst_bits_end_result_1_garbage_bit; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20]
assign dst_bits_end_data = _T_4831 ? dst_bits_end_result_data : dst_bits_end_result_1_data; // @[ReservationStation.scala:202:19, :216:24, :263:34, :265:20, :291:20]
wire _dst_bits_wraps_around_overflow_T_2 = dst_bits_wraps_around_sum_1[10]; // @[LocalAddr.scala:71:20, :73:40]
wire _dst_bits_wraps_around_overflow_T_3 = dst_bits_wraps_around_sum_1[14]; // @[LocalAddr.scala:71:20, :73:58]
wire dst_bits_wraps_around_overflow_1 = dst_bits_start_is_acc_addr ? _dst_bits_wraps_around_overflow_T_2 : _dst_bits_wraps_around_overflow_T_3; // @[ReservationStation.scala:202:19]
wire [13:0] _dst_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:76:23]
wire [13:0] dst_bits_wraps_around_result_1_data; // @[LocalAddr.scala:75:26]
assign _dst_bits_wraps_around_result_data_T_1 = dst_bits_wraps_around_sum_1[13:0]; // @[LocalAddr.scala:71:20, :76:23]
assign dst_bits_wraps_around_result_1_data = _dst_bits_wraps_around_result_data_T_1; // @[LocalAddr.scala:75:26, :76:23]
assign dst_bits_wraps_around = _T_4831 ? dst_bits_wraps_around_overflow : dst_bits_wraps_around_overflow_1; // @[ReservationStation.scala:202:19, :216:24, :263:34, :266:29, :292:29]
wire _is_load_T_2 = _is_load_T | _is_load_T_1; // @[ReservationStation.scala:295:{25,38,47}]
wire _is_load_T_4 = _is_load_T_2 | _is_load_T_3; // @[ReservationStation.scala:295:{38,61,70}]
wire _is_load_T_6 = config_cmd_type == 2'h1; // @[ReservationStation.scala:189:34, :295:128]
wire _is_load_T_7 = _is_load_T_5 & _is_load_T_6; // @[ReservationStation.scala:295:{94,109,128}]
wire is_load = _is_load_T_4 | _is_load_T_7; // @[ReservationStation.scala:295:{61,84,109}]
wire _is_ex_T_1 = _is_ex_T | funct_is_compute; // @[ReservationStation.scala:188:59, :296:{23,39}]
wire _is_ex_T_3 = config_cmd_type == 2'h0; // @[ReservationStation.scala:189:34, :296:103]
wire _is_ex_T_4 = _is_ex_T_2 & _is_ex_T_3; // @[ReservationStation.scala:296:{69,84,103}]
wire is_ex = _is_ex_T_1 | _is_ex_T_4; // @[ReservationStation.scala:296:{39,59,84}]
wire _is_store_T_2 = config_cmd_type == 2'h2; // @[ReservationStation.scala:189:34, :297:85]
wire _is_store_T_3 = &config_cmd_type; // @[ReservationStation.scala:189:34, :297:121]
wire _is_store_T_4 = _is_store_T_2 | _is_store_T_3; // @[ReservationStation.scala:297:{85,102,121}]
wire _is_store_T_5 = _is_store_T_1 & _is_store_T_4; // @[ReservationStation.scala:297:{50,65,102}]
wire is_store = _is_store_T | _is_store_T_5; // @[ReservationStation.scala:297:{26,40,65}]
wire _is_norm_T_1 = &config_cmd_type; // @[ReservationStation.scala:189:34, :297:121, :298:59]
wire is_norm = _is_norm_T & _is_norm_T_1; // @[ReservationStation.scala:298:{25,40,59}]
wire [1:0] _new_entry_q_T_1 = {is_store, 1'h0}; // @[Mux.scala:30:73]
wire [1:0] _new_entry_q_T_3 = _new_entry_q_T_1; // @[Mux.scala:30:73]
wire [1:0] _new_entry_q_T_2 = {1'h0, is_ex}; // @[Mux.scala:30:73]
wire [1:0] _new_entry_q_T_4 = _new_entry_q_T_3 | _new_entry_q_T_2; // @[Mux.scala:30:73]
assign _new_entry_q_WIRE = _new_entry_q_T_4; // @[Mux.scala:30:73]
assign new_entry_q = _new_entry_q_WIRE; // @[Mux.scala:30:73]
wire not_config = ~new_entry_is_config; // @[ReservationStation.scala:171:23, :309:22]
wire _T_58 = entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_2144 = new_entry_opa_bits_start_is_acc_addr & new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23]
wire _T_115 = entries_ex_0_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_176 = entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_233 = entries_ex_1_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_294 = entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_351 = entries_ex_2_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_412 = entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_469 = entries_ex_3_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_530 = entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_587 = entries_ex_4_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_648 = entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_705 = entries_ex_5_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_766 = entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_823 = entries_ex_6_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_884 = entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_941 = entries_ex_7_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1002 = entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1059 = entries_ex_8_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1120 = entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1177 = entries_ex_9_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1238 = entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1295 = entries_ex_10_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1356 = entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1413 = entries_ex_11_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1474 = entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1531 = entries_ex_12_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1592 = entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1649 = entries_ex_13_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1710 = entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1767 = entries_ex_14_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1828 = entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1885 = entries_ex_15_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_1946 = entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_2005 = entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_2064 = entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_2123 = entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_2182 = entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3344 = new_entry_opa_bits_start_is_acc_addr & new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23]
wire _T_2265 = entries_ld_0_bits_opa_bits_start_is_acc_addr & entries_ld_0_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_2238 = entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3071 = new_entry_opb_bits_start_is_acc_addr & new_entry_opb_bits_start_accumulate; // @[ReservationStation.scala:171:23]
wire _T_2298 = entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2381 = entries_ld_1_bits_opa_bits_start_is_acc_addr & entries_ld_1_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_2354 = entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2414 = entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2497 = entries_ld_2_bits_opa_bits_start_is_acc_addr & entries_ld_2_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_2470 = entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2530 = entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2613 = entries_ld_3_bits_opa_bits_start_is_acc_addr & entries_ld_3_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_2586 = entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2646 = entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2729 = entries_ld_4_bits_opa_bits_start_is_acc_addr & entries_ld_4_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_2702 = entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2762 = entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2845 = entries_ld_5_bits_opa_bits_start_is_acc_addr & entries_ld_5_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_2818 = entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2878 = entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2961 = entries_ld_6_bits_opa_bits_start_is_acc_addr & entries_ld_6_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_2934 = entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_2994 = entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3077 = entries_ld_7_bits_opa_bits_start_is_acc_addr & entries_ld_7_bits_opa_bits_start_accumulate; // @[ReservationStation.scala:117:23]
wire _T_3050 = entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3143 = entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_3203 = entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_3263 = entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_3323 = entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:119:23, :171:23]
wire _T_3382 = entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_4776 = new_entry_opa_bits_start_is_acc_addr & new_entry_opa_bits_start_accumulate; // @[ReservationStation.scala:171:23]
wire _T_3441 = entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3500 = entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3559 = entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3618 = entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3677 = entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3736 = entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
wire _T_3795 = entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:117:23, :171:23]
assign new_entry_deps_ld_0 =
is_load
? entries_ld_0_valid & ~entries_ld_0_bits_issued
: is_ex
? entries_ld_0_valid & entries_ld_0_bits_opa_valid & not_config
& ((_T_2182 & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_0_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_0_bits_opa_bits_end_data) | entries_ld_0_bits_opa_bits_wraps_around) | _T_2182 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_0_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_0_bits_opa_bits_start_data) & (entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2265 & entries_ld_0_bits_opa_bits_start_read_full_acc_row & (&entries_ld_0_bits_opa_bits_start_data) & entries_ld_0_bits_opa_bits_start_garbage_bit)
| (_T_2238 & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_0_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_0_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_0_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_0_bits_opa_bits_end_data) | entries_ld_0_bits_opa_bits_wraps_around) | _T_2238 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_0_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_0_bits_opa_bits_start_data) & (entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_0_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2265 & entries_ld_0_bits_opa_bits_start_read_full_acc_row & (&entries_ld_0_bits_opa_bits_start_data) & entries_ld_0_bits_opa_bits_start_garbage_bit))
: entries_ld_0_valid & entries_ld_0_bits_opa_valid & not_config & (_T_3382 & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_0_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_0_bits_opa_bits_end_data) | entries_ld_0_bits_opa_bits_wraps_around) | _T_3382 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_0_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_0_bits_opa_bits_start_data) & (entries_ld_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_0_bits_opa_bits_start_is_acc_addr ? entries_ld_0_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_0_bits_opa_bits_start_is_acc_addr & entries_ld_0_bits_opa_bits_start_accumulate & entries_ld_0_bits_opa_bits_start_read_full_acc_row & (&entries_ld_0_bits_opa_bits_start_data) & entries_ld_0_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
assign new_entry_deps_ld_1 =
is_load
? entries_ld_1_valid & ~entries_ld_1_bits_issued
: is_ex
? entries_ld_1_valid & entries_ld_1_bits_opa_valid & not_config
& ((_T_2298 & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_1_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_1_bits_opa_bits_end_data) | entries_ld_1_bits_opa_bits_wraps_around) | _T_2298 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_1_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_1_bits_opa_bits_start_data) & (entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2381 & entries_ld_1_bits_opa_bits_start_read_full_acc_row & (&entries_ld_1_bits_opa_bits_start_data) & entries_ld_1_bits_opa_bits_start_garbage_bit)
| (_T_2354 & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_1_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_1_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_1_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_1_bits_opa_bits_end_data) | entries_ld_1_bits_opa_bits_wraps_around) | _T_2354 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_1_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_1_bits_opa_bits_start_data) & (entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_1_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2381 & entries_ld_1_bits_opa_bits_start_read_full_acc_row & (&entries_ld_1_bits_opa_bits_start_data) & entries_ld_1_bits_opa_bits_start_garbage_bit))
: entries_ld_1_valid & entries_ld_1_bits_opa_valid & not_config & (_T_3441 & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_1_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_1_bits_opa_bits_end_data) | entries_ld_1_bits_opa_bits_wraps_around) | _T_3441 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_1_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_1_bits_opa_bits_start_data) & (entries_ld_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_1_bits_opa_bits_start_is_acc_addr ? entries_ld_1_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_1_bits_opa_bits_start_is_acc_addr & entries_ld_1_bits_opa_bits_start_accumulate & entries_ld_1_bits_opa_bits_start_read_full_acc_row & (&entries_ld_1_bits_opa_bits_start_data) & entries_ld_1_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
assign new_entry_deps_ld_2 =
is_load
? entries_ld_2_valid & ~entries_ld_2_bits_issued
: is_ex
? entries_ld_2_valid & entries_ld_2_bits_opa_valid & not_config
& ((_T_2414 & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_2_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_2_bits_opa_bits_end_data) | entries_ld_2_bits_opa_bits_wraps_around) | _T_2414 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_2_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_2_bits_opa_bits_start_data) & (entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2497 & entries_ld_2_bits_opa_bits_start_read_full_acc_row & (&entries_ld_2_bits_opa_bits_start_data) & entries_ld_2_bits_opa_bits_start_garbage_bit)
| (_T_2470 & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_2_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_2_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_2_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_2_bits_opa_bits_end_data) | entries_ld_2_bits_opa_bits_wraps_around) | _T_2470 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_2_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_2_bits_opa_bits_start_data) & (entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_2_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2497 & entries_ld_2_bits_opa_bits_start_read_full_acc_row & (&entries_ld_2_bits_opa_bits_start_data) & entries_ld_2_bits_opa_bits_start_garbage_bit))
: entries_ld_2_valid & entries_ld_2_bits_opa_valid & not_config & (_T_3500 & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_2_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_2_bits_opa_bits_end_data) | entries_ld_2_bits_opa_bits_wraps_around) | _T_3500 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_2_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_2_bits_opa_bits_start_data) & (entries_ld_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_2_bits_opa_bits_start_is_acc_addr ? entries_ld_2_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_2_bits_opa_bits_start_is_acc_addr & entries_ld_2_bits_opa_bits_start_accumulate & entries_ld_2_bits_opa_bits_start_read_full_acc_row & (&entries_ld_2_bits_opa_bits_start_data) & entries_ld_2_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
assign new_entry_deps_ld_3 =
is_load
? entries_ld_3_valid & ~entries_ld_3_bits_issued
: is_ex
? entries_ld_3_valid & entries_ld_3_bits_opa_valid & not_config
& ((_T_2530 & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_3_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_3_bits_opa_bits_end_data) | entries_ld_3_bits_opa_bits_wraps_around) | _T_2530 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_3_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_3_bits_opa_bits_start_data) & (entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2613 & entries_ld_3_bits_opa_bits_start_read_full_acc_row & (&entries_ld_3_bits_opa_bits_start_data) & entries_ld_3_bits_opa_bits_start_garbage_bit)
| (_T_2586 & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_3_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_3_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_3_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_3_bits_opa_bits_end_data) | entries_ld_3_bits_opa_bits_wraps_around) | _T_2586 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_3_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_3_bits_opa_bits_start_data) & (entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_3_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2613 & entries_ld_3_bits_opa_bits_start_read_full_acc_row & (&entries_ld_3_bits_opa_bits_start_data) & entries_ld_3_bits_opa_bits_start_garbage_bit))
: entries_ld_3_valid & entries_ld_3_bits_opa_valid & not_config & (_T_3559 & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_3_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_3_bits_opa_bits_end_data) | entries_ld_3_bits_opa_bits_wraps_around) | _T_3559 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_3_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_3_bits_opa_bits_start_data) & (entries_ld_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_3_bits_opa_bits_start_is_acc_addr ? entries_ld_3_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_3_bits_opa_bits_start_is_acc_addr & entries_ld_3_bits_opa_bits_start_accumulate & entries_ld_3_bits_opa_bits_start_read_full_acc_row & (&entries_ld_3_bits_opa_bits_start_data) & entries_ld_3_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
assign new_entry_deps_ld_4 =
is_load
? entries_ld_4_valid & ~entries_ld_4_bits_issued
: is_ex
? entries_ld_4_valid & entries_ld_4_bits_opa_valid & not_config
& ((_T_2646 & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_4_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_4_bits_opa_bits_end_data) | entries_ld_4_bits_opa_bits_wraps_around) | _T_2646 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_4_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_4_bits_opa_bits_start_data) & (entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2729 & entries_ld_4_bits_opa_bits_start_read_full_acc_row & (&entries_ld_4_bits_opa_bits_start_data) & entries_ld_4_bits_opa_bits_start_garbage_bit)
| (_T_2702 & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_4_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_4_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_4_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_4_bits_opa_bits_end_data) | entries_ld_4_bits_opa_bits_wraps_around) | _T_2702 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_4_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_4_bits_opa_bits_start_data) & (entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_4_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2729 & entries_ld_4_bits_opa_bits_start_read_full_acc_row & (&entries_ld_4_bits_opa_bits_start_data) & entries_ld_4_bits_opa_bits_start_garbage_bit))
: entries_ld_4_valid & entries_ld_4_bits_opa_valid & not_config & (_T_3618 & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_4_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_4_bits_opa_bits_end_data) | entries_ld_4_bits_opa_bits_wraps_around) | _T_3618 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_4_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_4_bits_opa_bits_start_data) & (entries_ld_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_4_bits_opa_bits_start_is_acc_addr ? entries_ld_4_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_4_bits_opa_bits_start_is_acc_addr & entries_ld_4_bits_opa_bits_start_accumulate & entries_ld_4_bits_opa_bits_start_read_full_acc_row & (&entries_ld_4_bits_opa_bits_start_data) & entries_ld_4_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
assign new_entry_deps_ld_5 =
is_load
? entries_ld_5_valid & ~entries_ld_5_bits_issued
: is_ex
? entries_ld_5_valid & entries_ld_5_bits_opa_valid & not_config
& ((_T_2762 & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_5_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_5_bits_opa_bits_end_data) | entries_ld_5_bits_opa_bits_wraps_around) | _T_2762 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_5_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_5_bits_opa_bits_start_data) & (entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2845 & entries_ld_5_bits_opa_bits_start_read_full_acc_row & (&entries_ld_5_bits_opa_bits_start_data) & entries_ld_5_bits_opa_bits_start_garbage_bit)
| (_T_2818 & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_5_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_5_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_5_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_5_bits_opa_bits_end_data) | entries_ld_5_bits_opa_bits_wraps_around) | _T_2818 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_5_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_5_bits_opa_bits_start_data) & (entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_5_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2845 & entries_ld_5_bits_opa_bits_start_read_full_acc_row & (&entries_ld_5_bits_opa_bits_start_data) & entries_ld_5_bits_opa_bits_start_garbage_bit))
: entries_ld_5_valid & entries_ld_5_bits_opa_valid & not_config & (_T_3677 & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_5_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_5_bits_opa_bits_end_data) | entries_ld_5_bits_opa_bits_wraps_around) | _T_3677 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_5_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_5_bits_opa_bits_start_data) & (entries_ld_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_5_bits_opa_bits_start_is_acc_addr ? entries_ld_5_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_5_bits_opa_bits_start_is_acc_addr & entries_ld_5_bits_opa_bits_start_accumulate & entries_ld_5_bits_opa_bits_start_read_full_acc_row & (&entries_ld_5_bits_opa_bits_start_data) & entries_ld_5_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
assign new_entry_deps_ld_6 =
is_load
? entries_ld_6_valid & ~entries_ld_6_bits_issued
: is_ex
? entries_ld_6_valid & entries_ld_6_bits_opa_valid & not_config
& ((_T_2878 & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_6_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_6_bits_opa_bits_end_data) | entries_ld_6_bits_opa_bits_wraps_around) | _T_2878 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_6_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_6_bits_opa_bits_start_data) & (entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_2961 & entries_ld_6_bits_opa_bits_start_read_full_acc_row & (&entries_ld_6_bits_opa_bits_start_data) & entries_ld_6_bits_opa_bits_start_garbage_bit)
| (_T_2934 & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_6_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_6_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_6_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_6_bits_opa_bits_end_data) | entries_ld_6_bits_opa_bits_wraps_around) | _T_2934 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_6_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_6_bits_opa_bits_start_data) & (entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_6_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_2961 & entries_ld_6_bits_opa_bits_start_read_full_acc_row & (&entries_ld_6_bits_opa_bits_start_data) & entries_ld_6_bits_opa_bits_start_garbage_bit))
: entries_ld_6_valid & entries_ld_6_bits_opa_valid & not_config & (_T_3736 & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_6_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_6_bits_opa_bits_end_data) | entries_ld_6_bits_opa_bits_wraps_around) | _T_3736 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_6_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_6_bits_opa_bits_start_data) & (entries_ld_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_6_bits_opa_bits_start_is_acc_addr ? entries_ld_6_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_6_bits_opa_bits_start_is_acc_addr & entries_ld_6_bits_opa_bits_start_accumulate & entries_ld_6_bits_opa_bits_start_read_full_acc_row & (&entries_ld_6_bits_opa_bits_start_data) & entries_ld_6_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
assign new_entry_deps_ld_7 =
is_load
? entries_ld_7_valid & ~entries_ld_7_bits_issued
: is_ex
? entries_ld_7_valid & entries_ld_7_bits_opa_valid & not_config
& ((_T_2994 & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_7_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_7_bits_opa_bits_end_data) | entries_ld_7_bits_opa_bits_wraps_around) | _T_2994 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_7_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_7_bits_opa_bits_start_data) & (entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | _T_3077 & entries_ld_7_bits_opa_bits_start_read_full_acc_row & (&entries_ld_7_bits_opa_bits_start_data) & entries_ld_7_bits_opa_bits_start_garbage_bit)
| (_T_3050 & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[9:0] <= new_entry_opb_bits_start_data[9:0] : entries_ld_7_bits_opa_bits_start_data <= new_entry_opb_bits_start_data) & (new_entry_opb_bits_start_is_acc_addr == entries_ld_7_bits_opa_bits_end_is_acc_addr & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] < entries_ld_7_bits_opa_bits_end_data[9:0] : new_entry_opb_bits_start_data < entries_ld_7_bits_opa_bits_end_data) | entries_ld_7_bits_opa_bits_wraps_around) | _T_3050 & (new_entry_opb_bits_start_is_acc_addr ? new_entry_opb_bits_start_data[9:0] <= entries_ld_7_bits_opa_bits_start_data[9:0] : new_entry_opb_bits_start_data <= entries_ld_7_bits_opa_bits_start_data) & (entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opb_bits_end_is_acc_addr & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[9:0] < new_entry_opb_bits_end_data[9:0] : entries_ld_7_bits_opa_bits_start_data < new_entry_opb_bits_end_data) | new_entry_opb_bits_wraps_around)) & ~(_T_3071 & new_entry_opb_bits_start_read_full_acc_row & (&new_entry_opb_bits_start_data) & new_entry_opb_bits_start_garbage_bit | _T_3077 & entries_ld_7_bits_opa_bits_start_read_full_acc_row & (&entries_ld_7_bits_opa_bits_start_data) & entries_ld_7_bits_opa_bits_start_garbage_bit))
: entries_ld_7_valid & entries_ld_7_bits_opa_valid & not_config & (_T_3795 & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ld_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ld_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ld_7_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ld_7_bits_opa_bits_end_data) | entries_ld_7_bits_opa_bits_wraps_around) | _T_3795 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ld_7_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ld_7_bits_opa_bits_start_data) & (entries_ld_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ld_7_bits_opa_bits_start_is_acc_addr ? entries_ld_7_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ld_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ld_7_bits_opa_bits_start_is_acc_addr & entries_ld_7_bits_opa_bits_start_accumulate & entries_ld_7_bits_opa_bits_start_read_full_acc_row & (&entries_ld_7_bits_opa_bits_start_data) & entries_ld_7_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :117:23, :171:23, :295:84, :296:59, :309:22, :310:20, :312:{25,66,69}, :320:24, :322:{25,66,86,100}, :323:54, :332:{25,66,86,100}]
wire _T_3855 = entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_3915 = entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_3975 = entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4035 = entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4095 = entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4155 = entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4215 = entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4275 = entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4335 = entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4395 = entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4455 = entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4515 = entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4575 = entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4635 = entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4695 = entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
wire _T_4755 = entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_start_is_acc_addr; // @[ReservationStation.scala:118:23, :171:23]
assign new_entry_deps_ex_0 =
is_load
? entries_ex_0_valid & ~new_entry_is_config
& ((_T_58 & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_0_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_0_bits_opa_bits_end_data) | entries_ex_0_bits_opa_bits_wraps_around) | _T_58 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_0_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_0_bits_opa_bits_start_data) & (entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_0_bits_opa_bits_start_is_acc_addr & entries_ex_0_bits_opa_bits_start_accumulate & entries_ex_0_bits_opa_bits_start_read_full_acc_row & (&entries_ex_0_bits_opa_bits_start_data) & entries_ex_0_bits_opa_bits_start_garbage_bit) & entries_ex_0_bits_opa_valid
| (_T_115 & (entries_ex_0_bits_opb_bits_start_is_acc_addr ? entries_ex_0_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_0_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_0_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_0_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_0_bits_opb_bits_end_data) | entries_ex_0_bits_opb_bits_wraps_around) | _T_115 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_0_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_0_bits_opb_bits_start_data) & (entries_ex_0_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_0_bits_opb_bits_start_is_acc_addr ? entries_ex_0_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_0_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_0_bits_opb_bits_start_is_acc_addr & entries_ex_0_bits_opb_bits_start_accumulate & entries_ex_0_bits_opb_bits_start_read_full_acc_row & (&entries_ex_0_bits_opb_bits_start_data) & entries_ex_0_bits_opb_bits_start_garbage_bit) & entries_ex_0_bits_opb_valid)
: is_ex ? entries_ex_0_valid & ~entries_ex_0_bits_issued : entries_ex_0_valid & entries_ex_0_bits_opa_valid & not_config & entries_ex_0_bits_opa_is_dst & (_T_3855 & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_0_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_0_bits_opa_bits_end_data) | entries_ex_0_bits_opa_bits_wraps_around) | _T_3855 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_0_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_0_bits_opa_bits_start_data) & (entries_ex_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_0_bits_opa_bits_start_is_acc_addr ? entries_ex_0_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_0_bits_opa_bits_start_is_acc_addr & entries_ex_0_bits_opa_bits_start_accumulate & entries_ex_0_bits_opa_bits_start_read_full_acc_row & (&entries_ex_0_bits_opa_bits_start_data) & entries_ex_0_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_1 =
is_load
? entries_ex_1_valid & ~new_entry_is_config
& ((_T_176 & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_1_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_1_bits_opa_bits_end_data) | entries_ex_1_bits_opa_bits_wraps_around) | _T_176 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_1_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_1_bits_opa_bits_start_data) & (entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_1_bits_opa_bits_start_is_acc_addr & entries_ex_1_bits_opa_bits_start_accumulate & entries_ex_1_bits_opa_bits_start_read_full_acc_row & (&entries_ex_1_bits_opa_bits_start_data) & entries_ex_1_bits_opa_bits_start_garbage_bit) & entries_ex_1_bits_opa_valid
| (_T_233 & (entries_ex_1_bits_opb_bits_start_is_acc_addr ? entries_ex_1_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_1_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_1_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_1_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_1_bits_opb_bits_end_data) | entries_ex_1_bits_opb_bits_wraps_around) | _T_233 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_1_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_1_bits_opb_bits_start_data) & (entries_ex_1_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_1_bits_opb_bits_start_is_acc_addr ? entries_ex_1_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_1_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_1_bits_opb_bits_start_is_acc_addr & entries_ex_1_bits_opb_bits_start_accumulate & entries_ex_1_bits_opb_bits_start_read_full_acc_row & (&entries_ex_1_bits_opb_bits_start_data) & entries_ex_1_bits_opb_bits_start_garbage_bit) & entries_ex_1_bits_opb_valid)
: is_ex ? entries_ex_1_valid & ~entries_ex_1_bits_issued : entries_ex_1_valid & entries_ex_1_bits_opa_valid & not_config & entries_ex_1_bits_opa_is_dst & (_T_3915 & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_1_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_1_bits_opa_bits_end_data) | entries_ex_1_bits_opa_bits_wraps_around) | _T_3915 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_1_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_1_bits_opa_bits_start_data) & (entries_ex_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_1_bits_opa_bits_start_is_acc_addr ? entries_ex_1_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_1_bits_opa_bits_start_is_acc_addr & entries_ex_1_bits_opa_bits_start_accumulate & entries_ex_1_bits_opa_bits_start_read_full_acc_row & (&entries_ex_1_bits_opa_bits_start_data) & entries_ex_1_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_2 =
is_load
? entries_ex_2_valid & ~new_entry_is_config
& ((_T_294 & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_2_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_2_bits_opa_bits_end_data) | entries_ex_2_bits_opa_bits_wraps_around) | _T_294 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_2_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_2_bits_opa_bits_start_data) & (entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_2_bits_opa_bits_start_is_acc_addr & entries_ex_2_bits_opa_bits_start_accumulate & entries_ex_2_bits_opa_bits_start_read_full_acc_row & (&entries_ex_2_bits_opa_bits_start_data) & entries_ex_2_bits_opa_bits_start_garbage_bit) & entries_ex_2_bits_opa_valid
| (_T_351 & (entries_ex_2_bits_opb_bits_start_is_acc_addr ? entries_ex_2_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_2_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_2_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_2_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_2_bits_opb_bits_end_data) | entries_ex_2_bits_opb_bits_wraps_around) | _T_351 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_2_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_2_bits_opb_bits_start_data) & (entries_ex_2_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_2_bits_opb_bits_start_is_acc_addr ? entries_ex_2_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_2_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_2_bits_opb_bits_start_is_acc_addr & entries_ex_2_bits_opb_bits_start_accumulate & entries_ex_2_bits_opb_bits_start_read_full_acc_row & (&entries_ex_2_bits_opb_bits_start_data) & entries_ex_2_bits_opb_bits_start_garbage_bit) & entries_ex_2_bits_opb_valid)
: is_ex ? entries_ex_2_valid & ~entries_ex_2_bits_issued : entries_ex_2_valid & entries_ex_2_bits_opa_valid & not_config & entries_ex_2_bits_opa_is_dst & (_T_3975 & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_2_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_2_bits_opa_bits_end_data) | entries_ex_2_bits_opa_bits_wraps_around) | _T_3975 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_2_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_2_bits_opa_bits_start_data) & (entries_ex_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_2_bits_opa_bits_start_is_acc_addr ? entries_ex_2_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_2_bits_opa_bits_start_is_acc_addr & entries_ex_2_bits_opa_bits_start_accumulate & entries_ex_2_bits_opa_bits_start_read_full_acc_row & (&entries_ex_2_bits_opa_bits_start_data) & entries_ex_2_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_3 =
is_load
? entries_ex_3_valid & ~new_entry_is_config
& ((_T_412 & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_3_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_3_bits_opa_bits_end_data) | entries_ex_3_bits_opa_bits_wraps_around) | _T_412 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_3_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_3_bits_opa_bits_start_data) & (entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_3_bits_opa_bits_start_is_acc_addr & entries_ex_3_bits_opa_bits_start_accumulate & entries_ex_3_bits_opa_bits_start_read_full_acc_row & (&entries_ex_3_bits_opa_bits_start_data) & entries_ex_3_bits_opa_bits_start_garbage_bit) & entries_ex_3_bits_opa_valid
| (_T_469 & (entries_ex_3_bits_opb_bits_start_is_acc_addr ? entries_ex_3_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_3_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_3_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_3_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_3_bits_opb_bits_end_data) | entries_ex_3_bits_opb_bits_wraps_around) | _T_469 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_3_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_3_bits_opb_bits_start_data) & (entries_ex_3_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_3_bits_opb_bits_start_is_acc_addr ? entries_ex_3_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_3_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_3_bits_opb_bits_start_is_acc_addr & entries_ex_3_bits_opb_bits_start_accumulate & entries_ex_3_bits_opb_bits_start_read_full_acc_row & (&entries_ex_3_bits_opb_bits_start_data) & entries_ex_3_bits_opb_bits_start_garbage_bit) & entries_ex_3_bits_opb_valid)
: is_ex ? entries_ex_3_valid & ~entries_ex_3_bits_issued : entries_ex_3_valid & entries_ex_3_bits_opa_valid & not_config & entries_ex_3_bits_opa_is_dst & (_T_4035 & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_3_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_3_bits_opa_bits_end_data) | entries_ex_3_bits_opa_bits_wraps_around) | _T_4035 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_3_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_3_bits_opa_bits_start_data) & (entries_ex_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_3_bits_opa_bits_start_is_acc_addr ? entries_ex_3_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_3_bits_opa_bits_start_is_acc_addr & entries_ex_3_bits_opa_bits_start_accumulate & entries_ex_3_bits_opa_bits_start_read_full_acc_row & (&entries_ex_3_bits_opa_bits_start_data) & entries_ex_3_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_4 =
is_load
? entries_ex_4_valid & ~new_entry_is_config
& ((_T_530 & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_4_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_4_bits_opa_bits_end_data) | entries_ex_4_bits_opa_bits_wraps_around) | _T_530 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_4_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_4_bits_opa_bits_start_data) & (entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_4_bits_opa_bits_start_is_acc_addr & entries_ex_4_bits_opa_bits_start_accumulate & entries_ex_4_bits_opa_bits_start_read_full_acc_row & (&entries_ex_4_bits_opa_bits_start_data) & entries_ex_4_bits_opa_bits_start_garbage_bit) & entries_ex_4_bits_opa_valid
| (_T_587 & (entries_ex_4_bits_opb_bits_start_is_acc_addr ? entries_ex_4_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_4_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_4_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_4_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_4_bits_opb_bits_end_data) | entries_ex_4_bits_opb_bits_wraps_around) | _T_587 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_4_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_4_bits_opb_bits_start_data) & (entries_ex_4_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_4_bits_opb_bits_start_is_acc_addr ? entries_ex_4_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_4_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_4_bits_opb_bits_start_is_acc_addr & entries_ex_4_bits_opb_bits_start_accumulate & entries_ex_4_bits_opb_bits_start_read_full_acc_row & (&entries_ex_4_bits_opb_bits_start_data) & entries_ex_4_bits_opb_bits_start_garbage_bit) & entries_ex_4_bits_opb_valid)
: is_ex ? entries_ex_4_valid & ~entries_ex_4_bits_issued : entries_ex_4_valid & entries_ex_4_bits_opa_valid & not_config & entries_ex_4_bits_opa_is_dst & (_T_4095 & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_4_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_4_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_4_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_4_bits_opa_bits_end_data) | entries_ex_4_bits_opa_bits_wraps_around) | _T_4095 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_4_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_4_bits_opa_bits_start_data) & (entries_ex_4_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_4_bits_opa_bits_start_is_acc_addr ? entries_ex_4_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_4_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_4_bits_opa_bits_start_is_acc_addr & entries_ex_4_bits_opa_bits_start_accumulate & entries_ex_4_bits_opa_bits_start_read_full_acc_row & (&entries_ex_4_bits_opa_bits_start_data) & entries_ex_4_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_5 =
is_load
? entries_ex_5_valid & ~new_entry_is_config
& ((_T_648 & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_5_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_5_bits_opa_bits_end_data) | entries_ex_5_bits_opa_bits_wraps_around) | _T_648 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_5_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_5_bits_opa_bits_start_data) & (entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_5_bits_opa_bits_start_is_acc_addr & entries_ex_5_bits_opa_bits_start_accumulate & entries_ex_5_bits_opa_bits_start_read_full_acc_row & (&entries_ex_5_bits_opa_bits_start_data) & entries_ex_5_bits_opa_bits_start_garbage_bit) & entries_ex_5_bits_opa_valid
| (_T_705 & (entries_ex_5_bits_opb_bits_start_is_acc_addr ? entries_ex_5_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_5_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_5_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_5_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_5_bits_opb_bits_end_data) | entries_ex_5_bits_opb_bits_wraps_around) | _T_705 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_5_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_5_bits_opb_bits_start_data) & (entries_ex_5_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_5_bits_opb_bits_start_is_acc_addr ? entries_ex_5_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_5_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_5_bits_opb_bits_start_is_acc_addr & entries_ex_5_bits_opb_bits_start_accumulate & entries_ex_5_bits_opb_bits_start_read_full_acc_row & (&entries_ex_5_bits_opb_bits_start_data) & entries_ex_5_bits_opb_bits_start_garbage_bit) & entries_ex_5_bits_opb_valid)
: is_ex ? entries_ex_5_valid & ~entries_ex_5_bits_issued : entries_ex_5_valid & entries_ex_5_bits_opa_valid & not_config & entries_ex_5_bits_opa_is_dst & (_T_4155 & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_5_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_5_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_5_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_5_bits_opa_bits_end_data) | entries_ex_5_bits_opa_bits_wraps_around) | _T_4155 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_5_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_5_bits_opa_bits_start_data) & (entries_ex_5_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_5_bits_opa_bits_start_is_acc_addr ? entries_ex_5_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_5_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_5_bits_opa_bits_start_is_acc_addr & entries_ex_5_bits_opa_bits_start_accumulate & entries_ex_5_bits_opa_bits_start_read_full_acc_row & (&entries_ex_5_bits_opa_bits_start_data) & entries_ex_5_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_6 =
is_load
? entries_ex_6_valid & ~new_entry_is_config
& ((_T_766 & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_6_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_6_bits_opa_bits_end_data) | entries_ex_6_bits_opa_bits_wraps_around) | _T_766 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_6_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_6_bits_opa_bits_start_data) & (entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_6_bits_opa_bits_start_is_acc_addr & entries_ex_6_bits_opa_bits_start_accumulate & entries_ex_6_bits_opa_bits_start_read_full_acc_row & (&entries_ex_6_bits_opa_bits_start_data) & entries_ex_6_bits_opa_bits_start_garbage_bit) & entries_ex_6_bits_opa_valid
| (_T_823 & (entries_ex_6_bits_opb_bits_start_is_acc_addr ? entries_ex_6_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_6_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_6_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_6_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_6_bits_opb_bits_end_data) | entries_ex_6_bits_opb_bits_wraps_around) | _T_823 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_6_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_6_bits_opb_bits_start_data) & (entries_ex_6_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_6_bits_opb_bits_start_is_acc_addr ? entries_ex_6_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_6_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_6_bits_opb_bits_start_is_acc_addr & entries_ex_6_bits_opb_bits_start_accumulate & entries_ex_6_bits_opb_bits_start_read_full_acc_row & (&entries_ex_6_bits_opb_bits_start_data) & entries_ex_6_bits_opb_bits_start_garbage_bit) & entries_ex_6_bits_opb_valid)
: is_ex ? entries_ex_6_valid & ~entries_ex_6_bits_issued : entries_ex_6_valid & entries_ex_6_bits_opa_valid & not_config & entries_ex_6_bits_opa_is_dst & (_T_4215 & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_6_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_6_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_6_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_6_bits_opa_bits_end_data) | entries_ex_6_bits_opa_bits_wraps_around) | _T_4215 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_6_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_6_bits_opa_bits_start_data) & (entries_ex_6_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_6_bits_opa_bits_start_is_acc_addr ? entries_ex_6_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_6_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_6_bits_opa_bits_start_is_acc_addr & entries_ex_6_bits_opa_bits_start_accumulate & entries_ex_6_bits_opa_bits_start_read_full_acc_row & (&entries_ex_6_bits_opa_bits_start_data) & entries_ex_6_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_7 =
is_load
? entries_ex_7_valid & ~new_entry_is_config
& ((_T_884 & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_7_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_7_bits_opa_bits_end_data) | entries_ex_7_bits_opa_bits_wraps_around) | _T_884 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_7_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_7_bits_opa_bits_start_data) & (entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_7_bits_opa_bits_start_is_acc_addr & entries_ex_7_bits_opa_bits_start_accumulate & entries_ex_7_bits_opa_bits_start_read_full_acc_row & (&entries_ex_7_bits_opa_bits_start_data) & entries_ex_7_bits_opa_bits_start_garbage_bit) & entries_ex_7_bits_opa_valid
| (_T_941 & (entries_ex_7_bits_opb_bits_start_is_acc_addr ? entries_ex_7_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_7_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_7_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_7_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_7_bits_opb_bits_end_data) | entries_ex_7_bits_opb_bits_wraps_around) | _T_941 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_7_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_7_bits_opb_bits_start_data) & (entries_ex_7_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_7_bits_opb_bits_start_is_acc_addr ? entries_ex_7_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_7_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_7_bits_opb_bits_start_is_acc_addr & entries_ex_7_bits_opb_bits_start_accumulate & entries_ex_7_bits_opb_bits_start_read_full_acc_row & (&entries_ex_7_bits_opb_bits_start_data) & entries_ex_7_bits_opb_bits_start_garbage_bit) & entries_ex_7_bits_opb_valid)
: is_ex ? entries_ex_7_valid & ~entries_ex_7_bits_issued : entries_ex_7_valid & entries_ex_7_bits_opa_valid & not_config & entries_ex_7_bits_opa_is_dst & (_T_4275 & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_7_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_7_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_7_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_7_bits_opa_bits_end_data) | entries_ex_7_bits_opa_bits_wraps_around) | _T_4275 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_7_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_7_bits_opa_bits_start_data) & (entries_ex_7_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_7_bits_opa_bits_start_is_acc_addr ? entries_ex_7_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_7_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_7_bits_opa_bits_start_is_acc_addr & entries_ex_7_bits_opa_bits_start_accumulate & entries_ex_7_bits_opa_bits_start_read_full_acc_row & (&entries_ex_7_bits_opa_bits_start_data) & entries_ex_7_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_8 =
is_load
? entries_ex_8_valid & ~new_entry_is_config
& ((_T_1002 & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_8_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_8_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_8_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_8_bits_opa_bits_end_data) | entries_ex_8_bits_opa_bits_wraps_around) | _T_1002 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_8_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_8_bits_opa_bits_start_data) & (entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_8_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_8_bits_opa_bits_start_is_acc_addr & entries_ex_8_bits_opa_bits_start_accumulate & entries_ex_8_bits_opa_bits_start_read_full_acc_row & (&entries_ex_8_bits_opa_bits_start_data) & entries_ex_8_bits_opa_bits_start_garbage_bit) & entries_ex_8_bits_opa_valid
| (_T_1059 & (entries_ex_8_bits_opb_bits_start_is_acc_addr ? entries_ex_8_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_8_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_8_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_8_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_8_bits_opb_bits_end_data) | entries_ex_8_bits_opb_bits_wraps_around) | _T_1059 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_8_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_8_bits_opb_bits_start_data) & (entries_ex_8_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_8_bits_opb_bits_start_is_acc_addr ? entries_ex_8_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_8_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_8_bits_opb_bits_start_is_acc_addr & entries_ex_8_bits_opb_bits_start_accumulate & entries_ex_8_bits_opb_bits_start_read_full_acc_row & (&entries_ex_8_bits_opb_bits_start_data) & entries_ex_8_bits_opb_bits_start_garbage_bit) & entries_ex_8_bits_opb_valid)
: is_ex ? entries_ex_8_valid & ~entries_ex_8_bits_issued : entries_ex_8_valid & entries_ex_8_bits_opa_valid & not_config & entries_ex_8_bits_opa_is_dst & (_T_4335 & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_8_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_8_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_8_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_8_bits_opa_bits_end_data) | entries_ex_8_bits_opa_bits_wraps_around) | _T_4335 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_8_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_8_bits_opa_bits_start_data) & (entries_ex_8_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_8_bits_opa_bits_start_is_acc_addr ? entries_ex_8_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_8_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_8_bits_opa_bits_start_is_acc_addr & entries_ex_8_bits_opa_bits_start_accumulate & entries_ex_8_bits_opa_bits_start_read_full_acc_row & (&entries_ex_8_bits_opa_bits_start_data) & entries_ex_8_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_9 =
is_load
? entries_ex_9_valid & ~new_entry_is_config
& ((_T_1120 & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_9_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_9_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_9_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_9_bits_opa_bits_end_data) | entries_ex_9_bits_opa_bits_wraps_around) | _T_1120 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_9_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_9_bits_opa_bits_start_data) & (entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_9_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_9_bits_opa_bits_start_is_acc_addr & entries_ex_9_bits_opa_bits_start_accumulate & entries_ex_9_bits_opa_bits_start_read_full_acc_row & (&entries_ex_9_bits_opa_bits_start_data) & entries_ex_9_bits_opa_bits_start_garbage_bit) & entries_ex_9_bits_opa_valid
| (_T_1177 & (entries_ex_9_bits_opb_bits_start_is_acc_addr ? entries_ex_9_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_9_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_9_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_9_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_9_bits_opb_bits_end_data) | entries_ex_9_bits_opb_bits_wraps_around) | _T_1177 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_9_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_9_bits_opb_bits_start_data) & (entries_ex_9_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_9_bits_opb_bits_start_is_acc_addr ? entries_ex_9_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_9_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_9_bits_opb_bits_start_is_acc_addr & entries_ex_9_bits_opb_bits_start_accumulate & entries_ex_9_bits_opb_bits_start_read_full_acc_row & (&entries_ex_9_bits_opb_bits_start_data) & entries_ex_9_bits_opb_bits_start_garbage_bit) & entries_ex_9_bits_opb_valid)
: is_ex ? entries_ex_9_valid & ~entries_ex_9_bits_issued : entries_ex_9_valid & entries_ex_9_bits_opa_valid & not_config & entries_ex_9_bits_opa_is_dst & (_T_4395 & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_9_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_9_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_9_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_9_bits_opa_bits_end_data) | entries_ex_9_bits_opa_bits_wraps_around) | _T_4395 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_9_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_9_bits_opa_bits_start_data) & (entries_ex_9_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_9_bits_opa_bits_start_is_acc_addr ? entries_ex_9_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_9_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_9_bits_opa_bits_start_is_acc_addr & entries_ex_9_bits_opa_bits_start_accumulate & entries_ex_9_bits_opa_bits_start_read_full_acc_row & (&entries_ex_9_bits_opa_bits_start_data) & entries_ex_9_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_10 =
is_load
? entries_ex_10_valid & ~new_entry_is_config
& ((_T_1238 & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_10_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_10_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_10_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_10_bits_opa_bits_end_data) | entries_ex_10_bits_opa_bits_wraps_around) | _T_1238 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_10_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_10_bits_opa_bits_start_data) & (entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_10_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_10_bits_opa_bits_start_is_acc_addr & entries_ex_10_bits_opa_bits_start_accumulate & entries_ex_10_bits_opa_bits_start_read_full_acc_row & (&entries_ex_10_bits_opa_bits_start_data) & entries_ex_10_bits_opa_bits_start_garbage_bit) & entries_ex_10_bits_opa_valid
| (_T_1295 & (entries_ex_10_bits_opb_bits_start_is_acc_addr ? entries_ex_10_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_10_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_10_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_10_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_10_bits_opb_bits_end_data) | entries_ex_10_bits_opb_bits_wraps_around) | _T_1295 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_10_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_10_bits_opb_bits_start_data) & (entries_ex_10_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_10_bits_opb_bits_start_is_acc_addr ? entries_ex_10_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_10_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_10_bits_opb_bits_start_is_acc_addr & entries_ex_10_bits_opb_bits_start_accumulate & entries_ex_10_bits_opb_bits_start_read_full_acc_row & (&entries_ex_10_bits_opb_bits_start_data) & entries_ex_10_bits_opb_bits_start_garbage_bit) & entries_ex_10_bits_opb_valid)
: is_ex ? entries_ex_10_valid & ~entries_ex_10_bits_issued : entries_ex_10_valid & entries_ex_10_bits_opa_valid & not_config & entries_ex_10_bits_opa_is_dst & (_T_4455 & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_10_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_10_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_10_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_10_bits_opa_bits_end_data) | entries_ex_10_bits_opa_bits_wraps_around) | _T_4455 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_10_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_10_bits_opa_bits_start_data) & (entries_ex_10_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_10_bits_opa_bits_start_is_acc_addr ? entries_ex_10_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_10_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_10_bits_opa_bits_start_is_acc_addr & entries_ex_10_bits_opa_bits_start_accumulate & entries_ex_10_bits_opa_bits_start_read_full_acc_row & (&entries_ex_10_bits_opa_bits_start_data) & entries_ex_10_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_11 =
is_load
? entries_ex_11_valid & ~new_entry_is_config
& ((_T_1356 & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_11_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_11_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_11_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_11_bits_opa_bits_end_data) | entries_ex_11_bits_opa_bits_wraps_around) | _T_1356 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_11_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_11_bits_opa_bits_start_data) & (entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_11_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_11_bits_opa_bits_start_is_acc_addr & entries_ex_11_bits_opa_bits_start_accumulate & entries_ex_11_bits_opa_bits_start_read_full_acc_row & (&entries_ex_11_bits_opa_bits_start_data) & entries_ex_11_bits_opa_bits_start_garbage_bit) & entries_ex_11_bits_opa_valid
| (_T_1413 & (entries_ex_11_bits_opb_bits_start_is_acc_addr ? entries_ex_11_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_11_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_11_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_11_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_11_bits_opb_bits_end_data) | entries_ex_11_bits_opb_bits_wraps_around) | _T_1413 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_11_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_11_bits_opb_bits_start_data) & (entries_ex_11_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_11_bits_opb_bits_start_is_acc_addr ? entries_ex_11_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_11_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_11_bits_opb_bits_start_is_acc_addr & entries_ex_11_bits_opb_bits_start_accumulate & entries_ex_11_bits_opb_bits_start_read_full_acc_row & (&entries_ex_11_bits_opb_bits_start_data) & entries_ex_11_bits_opb_bits_start_garbage_bit) & entries_ex_11_bits_opb_valid)
: is_ex ? entries_ex_11_valid & ~entries_ex_11_bits_issued : entries_ex_11_valid & entries_ex_11_bits_opa_valid & not_config & entries_ex_11_bits_opa_is_dst & (_T_4515 & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_11_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_11_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_11_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_11_bits_opa_bits_end_data) | entries_ex_11_bits_opa_bits_wraps_around) | _T_4515 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_11_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_11_bits_opa_bits_start_data) & (entries_ex_11_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_11_bits_opa_bits_start_is_acc_addr ? entries_ex_11_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_11_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_11_bits_opa_bits_start_is_acc_addr & entries_ex_11_bits_opa_bits_start_accumulate & entries_ex_11_bits_opa_bits_start_read_full_acc_row & (&entries_ex_11_bits_opa_bits_start_data) & entries_ex_11_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_12 =
is_load
? entries_ex_12_valid & ~new_entry_is_config
& ((_T_1474 & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_12_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_12_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_12_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_12_bits_opa_bits_end_data) | entries_ex_12_bits_opa_bits_wraps_around) | _T_1474 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_12_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_12_bits_opa_bits_start_data) & (entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_12_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_12_bits_opa_bits_start_is_acc_addr & entries_ex_12_bits_opa_bits_start_accumulate & entries_ex_12_bits_opa_bits_start_read_full_acc_row & (&entries_ex_12_bits_opa_bits_start_data) & entries_ex_12_bits_opa_bits_start_garbage_bit) & entries_ex_12_bits_opa_valid
| (_T_1531 & (entries_ex_12_bits_opb_bits_start_is_acc_addr ? entries_ex_12_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_12_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_12_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_12_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_12_bits_opb_bits_end_data) | entries_ex_12_bits_opb_bits_wraps_around) | _T_1531 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_12_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_12_bits_opb_bits_start_data) & (entries_ex_12_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_12_bits_opb_bits_start_is_acc_addr ? entries_ex_12_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_12_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_12_bits_opb_bits_start_is_acc_addr & entries_ex_12_bits_opb_bits_start_accumulate & entries_ex_12_bits_opb_bits_start_read_full_acc_row & (&entries_ex_12_bits_opb_bits_start_data) & entries_ex_12_bits_opb_bits_start_garbage_bit) & entries_ex_12_bits_opb_valid)
: is_ex ? entries_ex_12_valid & ~entries_ex_12_bits_issued : entries_ex_12_valid & entries_ex_12_bits_opa_valid & not_config & entries_ex_12_bits_opa_is_dst & (_T_4575 & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_12_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_12_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_12_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_12_bits_opa_bits_end_data) | entries_ex_12_bits_opa_bits_wraps_around) | _T_4575 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_12_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_12_bits_opa_bits_start_data) & (entries_ex_12_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_12_bits_opa_bits_start_is_acc_addr ? entries_ex_12_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_12_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_12_bits_opa_bits_start_is_acc_addr & entries_ex_12_bits_opa_bits_start_accumulate & entries_ex_12_bits_opa_bits_start_read_full_acc_row & (&entries_ex_12_bits_opa_bits_start_data) & entries_ex_12_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_13 =
is_load
? entries_ex_13_valid & ~new_entry_is_config
& ((_T_1592 & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_13_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_13_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_13_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_13_bits_opa_bits_end_data) | entries_ex_13_bits_opa_bits_wraps_around) | _T_1592 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_13_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_13_bits_opa_bits_start_data) & (entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_13_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_13_bits_opa_bits_start_is_acc_addr & entries_ex_13_bits_opa_bits_start_accumulate & entries_ex_13_bits_opa_bits_start_read_full_acc_row & (&entries_ex_13_bits_opa_bits_start_data) & entries_ex_13_bits_opa_bits_start_garbage_bit) & entries_ex_13_bits_opa_valid
| (_T_1649 & (entries_ex_13_bits_opb_bits_start_is_acc_addr ? entries_ex_13_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_13_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_13_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_13_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_13_bits_opb_bits_end_data) | entries_ex_13_bits_opb_bits_wraps_around) | _T_1649 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_13_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_13_bits_opb_bits_start_data) & (entries_ex_13_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_13_bits_opb_bits_start_is_acc_addr ? entries_ex_13_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_13_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_13_bits_opb_bits_start_is_acc_addr & entries_ex_13_bits_opb_bits_start_accumulate & entries_ex_13_bits_opb_bits_start_read_full_acc_row & (&entries_ex_13_bits_opb_bits_start_data) & entries_ex_13_bits_opb_bits_start_garbage_bit) & entries_ex_13_bits_opb_valid)
: is_ex ? entries_ex_13_valid & ~entries_ex_13_bits_issued : entries_ex_13_valid & entries_ex_13_bits_opa_valid & not_config & entries_ex_13_bits_opa_is_dst & (_T_4635 & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_13_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_13_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_13_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_13_bits_opa_bits_end_data) | entries_ex_13_bits_opa_bits_wraps_around) | _T_4635 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_13_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_13_bits_opa_bits_start_data) & (entries_ex_13_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_13_bits_opa_bits_start_is_acc_addr ? entries_ex_13_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_13_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_13_bits_opa_bits_start_is_acc_addr & entries_ex_13_bits_opa_bits_start_accumulate & entries_ex_13_bits_opa_bits_start_read_full_acc_row & (&entries_ex_13_bits_opa_bits_start_data) & entries_ex_13_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_14 =
is_load
? entries_ex_14_valid & ~new_entry_is_config
& ((_T_1710 & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_14_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_14_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_14_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_14_bits_opa_bits_end_data) | entries_ex_14_bits_opa_bits_wraps_around) | _T_1710 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_14_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_14_bits_opa_bits_start_data) & (entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_14_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_14_bits_opa_bits_start_is_acc_addr & entries_ex_14_bits_opa_bits_start_accumulate & entries_ex_14_bits_opa_bits_start_read_full_acc_row & (&entries_ex_14_bits_opa_bits_start_data) & entries_ex_14_bits_opa_bits_start_garbage_bit) & entries_ex_14_bits_opa_valid
| (_T_1767 & (entries_ex_14_bits_opb_bits_start_is_acc_addr ? entries_ex_14_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_14_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_14_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_14_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_14_bits_opb_bits_end_data) | entries_ex_14_bits_opb_bits_wraps_around) | _T_1767 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_14_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_14_bits_opb_bits_start_data) & (entries_ex_14_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_14_bits_opb_bits_start_is_acc_addr ? entries_ex_14_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_14_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_14_bits_opb_bits_start_is_acc_addr & entries_ex_14_bits_opb_bits_start_accumulate & entries_ex_14_bits_opb_bits_start_read_full_acc_row & (&entries_ex_14_bits_opb_bits_start_data) & entries_ex_14_bits_opb_bits_start_garbage_bit) & entries_ex_14_bits_opb_valid)
: is_ex ? entries_ex_14_valid & ~entries_ex_14_bits_issued : entries_ex_14_valid & entries_ex_14_bits_opa_valid & not_config & entries_ex_14_bits_opa_is_dst & (_T_4695 & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_14_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_14_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_14_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_14_bits_opa_bits_end_data) | entries_ex_14_bits_opa_bits_wraps_around) | _T_4695 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_14_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_14_bits_opa_bits_start_data) & (entries_ex_14_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_14_bits_opa_bits_start_is_acc_addr ? entries_ex_14_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_14_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_14_bits_opa_bits_start_is_acc_addr & entries_ex_14_bits_opa_bits_start_accumulate & entries_ex_14_bits_opa_bits_start_read_full_acc_row & (&entries_ex_14_bits_opa_bits_start_data) & entries_ex_14_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_ex_15 =
is_load
? entries_ex_15_valid & ~new_entry_is_config
& ((_T_1828 & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_15_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_15_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_15_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_15_bits_opa_bits_end_data) | entries_ex_15_bits_opa_bits_wraps_around) | _T_1828 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_15_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_15_bits_opa_bits_start_data) & (entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_15_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_15_bits_opa_bits_start_is_acc_addr & entries_ex_15_bits_opa_bits_start_accumulate & entries_ex_15_bits_opa_bits_start_read_full_acc_row & (&entries_ex_15_bits_opa_bits_start_data) & entries_ex_15_bits_opa_bits_start_garbage_bit) & entries_ex_15_bits_opa_valid
| (_T_1885 & (entries_ex_15_bits_opb_bits_start_is_acc_addr ? entries_ex_15_bits_opb_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_15_bits_opb_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_15_bits_opb_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_15_bits_opb_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_15_bits_opb_bits_end_data) | entries_ex_15_bits_opb_bits_wraps_around) | _T_1885 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_15_bits_opb_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_15_bits_opb_bits_start_data) & (entries_ex_15_bits_opb_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_15_bits_opb_bits_start_is_acc_addr ? entries_ex_15_bits_opb_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_15_bits_opb_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_15_bits_opb_bits_start_is_acc_addr & entries_ex_15_bits_opb_bits_start_accumulate & entries_ex_15_bits_opb_bits_start_read_full_acc_row & (&entries_ex_15_bits_opb_bits_start_data) & entries_ex_15_bits_opb_bits_start_garbage_bit) & entries_ex_15_bits_opb_valid)
: is_ex ? entries_ex_15_valid & ~entries_ex_15_bits_issued : entries_ex_15_valid & entries_ex_15_bits_opa_valid & not_config & entries_ex_15_bits_opa_is_dst & (_T_4755 & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_ex_15_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_ex_15_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_ex_15_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_ex_15_bits_opa_bits_end_data) | entries_ex_15_bits_opa_bits_wraps_around) | _T_4755 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_ex_15_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_ex_15_bits_opa_bits_start_data) & (entries_ex_15_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_ex_15_bits_opa_bits_start_is_acc_addr ? entries_ex_15_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_ex_15_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_4776 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_ex_15_bits_opa_bits_start_is_acc_addr & entries_ex_15_bits_opa_bits_start_accumulate & entries_ex_15_bits_opa_bits_start_read_full_acc_row & (&entries_ex_15_bits_opa_bits_start_data) & entries_ex_15_bits_opa_bits_start_garbage_bit); // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :118:23, :171:23, :295:84, :296:59, :309:22, :310:20, :314:{25,66,90}, :315:{55,76}, :316:55, :320:24, :326:{25,66,69}, :335:{25,66,86,100}, :336:27]
assign new_entry_deps_st_0 =
is_load
? entries_st_0_valid & entries_st_0_bits_opa_valid & not_config & (_T_1946 & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_0_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_0_bits_opa_bits_end_data) | entries_st_0_bits_opa_bits_wraps_around) | _T_1946 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_0_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_0_bits_opa_bits_start_data) & (entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_0_bits_opa_bits_start_is_acc_addr & entries_st_0_bits_opa_bits_start_accumulate & entries_st_0_bits_opa_bits_start_read_full_acc_row & (&entries_st_0_bits_opa_bits_start_data) & entries_st_0_bits_opa_bits_start_garbage_bit)
: is_ex ? entries_st_0_valid & entries_st_0_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3143 & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_0_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_0_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_0_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_0_bits_opa_bits_end_data) | entries_st_0_bits_opa_bits_wraps_around) | _T_3143 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_0_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_0_bits_opa_bits_start_data) & (entries_st_0_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_0_bits_opa_bits_start_is_acc_addr ? entries_st_0_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_0_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_0_bits_opa_bits_start_is_acc_addr & entries_st_0_bits_opa_bits_start_accumulate & entries_st_0_bits_opa_bits_start_read_full_acc_row & (&entries_st_0_bits_opa_bits_start_data) & entries_st_0_bits_opa_bits_start_garbage_bit) : entries_st_0_valid & ~entries_st_0_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}]
assign new_entry_deps_st_1 =
is_load
? entries_st_1_valid & entries_st_1_bits_opa_valid & not_config & (_T_2005 & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_1_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_1_bits_opa_bits_end_data) | entries_st_1_bits_opa_bits_wraps_around) | _T_2005 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_1_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_1_bits_opa_bits_start_data) & (entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_1_bits_opa_bits_start_is_acc_addr & entries_st_1_bits_opa_bits_start_accumulate & entries_st_1_bits_opa_bits_start_read_full_acc_row & (&entries_st_1_bits_opa_bits_start_data) & entries_st_1_bits_opa_bits_start_garbage_bit)
: is_ex ? entries_st_1_valid & entries_st_1_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3203 & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_1_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_1_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_1_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_1_bits_opa_bits_end_data) | entries_st_1_bits_opa_bits_wraps_around) | _T_3203 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_1_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_1_bits_opa_bits_start_data) & (entries_st_1_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_1_bits_opa_bits_start_is_acc_addr ? entries_st_1_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_1_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_1_bits_opa_bits_start_is_acc_addr & entries_st_1_bits_opa_bits_start_accumulate & entries_st_1_bits_opa_bits_start_read_full_acc_row & (&entries_st_1_bits_opa_bits_start_data) & entries_st_1_bits_opa_bits_start_garbage_bit) : entries_st_1_valid & ~entries_st_1_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}]
assign new_entry_deps_st_2 =
is_load
? entries_st_2_valid & entries_st_2_bits_opa_valid & not_config & (_T_2064 & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_2_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_2_bits_opa_bits_end_data) | entries_st_2_bits_opa_bits_wraps_around) | _T_2064 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_2_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_2_bits_opa_bits_start_data) & (entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_2_bits_opa_bits_start_is_acc_addr & entries_st_2_bits_opa_bits_start_accumulate & entries_st_2_bits_opa_bits_start_read_full_acc_row & (&entries_st_2_bits_opa_bits_start_data) & entries_st_2_bits_opa_bits_start_garbage_bit)
: is_ex ? entries_st_2_valid & entries_st_2_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3263 & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_2_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_2_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_2_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_2_bits_opa_bits_end_data) | entries_st_2_bits_opa_bits_wraps_around) | _T_3263 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_2_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_2_bits_opa_bits_start_data) & (entries_st_2_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_2_bits_opa_bits_start_is_acc_addr ? entries_st_2_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_2_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_2_bits_opa_bits_start_is_acc_addr & entries_st_2_bits_opa_bits_start_accumulate & entries_st_2_bits_opa_bits_start_read_full_acc_row & (&entries_st_2_bits_opa_bits_start_data) & entries_st_2_bits_opa_bits_start_garbage_bit) : entries_st_2_valid & ~entries_st_2_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}]
assign new_entry_deps_st_3 =
is_load
? entries_st_3_valid & entries_st_3_bits_opa_valid & not_config & (_T_2123 & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_3_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_3_bits_opa_bits_end_data) | entries_st_3_bits_opa_bits_wraps_around) | _T_2123 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_3_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_3_bits_opa_bits_start_data) & (entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_2144 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_3_bits_opa_bits_start_is_acc_addr & entries_st_3_bits_opa_bits_start_accumulate & entries_st_3_bits_opa_bits_start_read_full_acc_row & (&entries_st_3_bits_opa_bits_start_data) & entries_st_3_bits_opa_bits_start_garbage_bit)
: is_ex ? entries_st_3_valid & entries_st_3_bits_opa_valid & not_config & new_entry_opa_is_dst & (_T_3323 & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[9:0] <= new_entry_opa_bits_start_data[9:0] : entries_st_3_bits_opa_bits_start_data <= new_entry_opa_bits_start_data) & (new_entry_opa_bits_start_is_acc_addr == entries_st_3_bits_opa_bits_end_is_acc_addr & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] < entries_st_3_bits_opa_bits_end_data[9:0] : new_entry_opa_bits_start_data < entries_st_3_bits_opa_bits_end_data) | entries_st_3_bits_opa_bits_wraps_around) | _T_3323 & (new_entry_opa_bits_start_is_acc_addr ? new_entry_opa_bits_start_data[9:0] <= entries_st_3_bits_opa_bits_start_data[9:0] : new_entry_opa_bits_start_data <= entries_st_3_bits_opa_bits_start_data) & (entries_st_3_bits_opa_bits_start_is_acc_addr == new_entry_opa_bits_end_is_acc_addr & (entries_st_3_bits_opa_bits_start_is_acc_addr ? entries_st_3_bits_opa_bits_start_data[9:0] < new_entry_opa_bits_end_data[9:0] : entries_st_3_bits_opa_bits_start_data < new_entry_opa_bits_end_data) | new_entry_opa_bits_wraps_around)) & ~(_T_3344 & new_entry_opa_bits_start_read_full_acc_row & (&new_entry_opa_bits_start_data) & new_entry_opa_bits_start_garbage_bit | entries_st_3_bits_opa_bits_start_is_acc_addr & entries_st_3_bits_opa_bits_start_accumulate & entries_st_3_bits_opa_bits_start_read_full_acc_row & (&entries_st_3_bits_opa_bits_start_data) & entries_st_3_bits_opa_bits_start_garbage_bit) : entries_st_3_valid & ~entries_st_3_bits_issued; // @[ReservationStation.scala:69:{30,52,76}, :70:{31,53,72}, :71:{9,30}, :119:23, :171:23, :295:84, :296:59, :309:22, :310:20, :318:{25,66,86,100}, :320:24, :328:{25,66,86,100,124}, :338:{25,66,69}]
wire _new_entry_complete_on_issue_T = new_entry_q != 2'h1; // @[ReservationStation.scala:171:23, :343:71]
assign _new_entry_complete_on_issue_T_1 = new_entry_is_config & _new_entry_complete_on_issue_T; // @[ReservationStation.scala:171:23, :343:{56,71}]
assign new_entry_complete_on_issue = _new_entry_complete_on_issue_T_1; // @[ReservationStation.scala:171:23, :343:56]
wire _T_4825 = new_entry_q == 2'h0; // @[ReservationStation.scala:171:23, :350:27]
wire [1:0] _GEN_54 = {1'h0, op1_valid} + {1'h0, op2_valid}; // @[ReservationStation.scala:196:19, :199:19, :351:33]
wire [1:0] _is_full_T; // @[ReservationStation.scala:351:33]
assign _is_full_T = _GEN_54; // @[ReservationStation.scala:351:33]
wire [1:0] _is_full_T_4; // @[ReservationStation.scala:351:33]
assign _is_full_T_4 = _GEN_54; // @[ReservationStation.scala:351:33]
wire [1:0] _is_full_T_8; // @[ReservationStation.scala:351:33]
assign _is_full_T_8 = _GEN_54; // @[ReservationStation.scala:351:33]
wire [1:0] _is_full_T_1 = _is_full_T; // @[ReservationStation.scala:351:33]
wire [2:0] _GEN_55 = {2'h0, dst_valid}; // @[ReservationStation.scala:202:19, :351:33]
wire [2:0] _is_full_T_2 = _GEN_55 + {1'h0, _is_full_T_1}; // @[ReservationStation.scala:351:33]
wire [1:0] _is_full_T_3 = _is_full_T_2[1:0]; // @[ReservationStation.scala:351:33]
wire is_full = _is_full_T_3[1]; // @[ReservationStation.scala:351:{33,72}]
wire _alloc_id_T = ~entries_ld_0_valid; // @[ReservationStation.scala:117:23, :355:104]
wire _alloc_id_T_1 = ~entries_ld_1_valid; // @[ReservationStation.scala:117:23, :355:104]
wire _alloc_id_T_2 = ~entries_ld_2_valid; // @[ReservationStation.scala:117:23, :355:104]
wire _alloc_id_T_3 = ~entries_ld_3_valid; // @[ReservationStation.scala:117:23, :355:104]
wire _alloc_id_T_4 = ~entries_ld_4_valid; // @[ReservationStation.scala:117:23, :355:104]
wire _alloc_id_T_5 = ~entries_ld_5_valid; // @[ReservationStation.scala:117:23, :355:104]
wire _alloc_id_T_6 = ~entries_ld_6_valid; // @[ReservationStation.scala:117:23, :355:104]
wire _alloc_id_T_7 = ~entries_ld_7_valid; // @[ReservationStation.scala:117:23, :355:104]
wire [2:0] _alloc_id_T_9 = {2'h3, ~_alloc_id_T_6}; // @[Mux.scala:126:16]
wire [2:0] _alloc_id_T_10 = _alloc_id_T_5 ? 3'h5 : _alloc_id_T_9; // @[Mux.scala:126:16]
wire [2:0] _alloc_id_T_11 = _alloc_id_T_4 ? 3'h4 : _alloc_id_T_10; // @[Mux.scala:126:16]
wire [2:0] _alloc_id_T_12 = _alloc_id_T_3 ? 3'h3 : _alloc_id_T_11; // @[Mux.scala:126:16]
wire [2:0] _alloc_id_T_13 = _alloc_id_T_2 ? 3'h2 : _alloc_id_T_12; // @[Mux.scala:126:16]
wire [2:0] _alloc_id_T_14 = _alloc_id_T_1 ? 3'h1 : _alloc_id_T_13; // @[Mux.scala:126:16]
wire [2:0] alloc_id = _alloc_id_T ? 3'h0 : _alloc_id_T_14; // @[Mux.scala:126:16]
wire [7:0] _GEN_56 = {{entries_ld_7_valid}, {entries_ld_6_valid}, {entries_ld_5_valid}, {entries_ld_4_valid}, {entries_ld_3_valid}, {entries_ld_2_valid}, {entries_ld_1_valid}, {entries_ld_0_valid}}; // @[ReservationStation.scala:117:23, :357:17]
wire _GEN_57 = _T_4825 & ~_GEN_56[alloc_id]; // @[Mux.scala:126:16]
wire _GEN_58 = alloc_id == 3'h0; // @[Mux.scala:126:16]
wire _GEN_59 = alloc_id == 3'h1; // @[Mux.scala:126:16]
wire _GEN_60 = alloc_id == 3'h2; // @[Mux.scala:126:16]
wire _GEN_61 = alloc_id == 3'h3; // @[Mux.scala:126:16]
wire _GEN_62 = alloc_id == 3'h4; // @[Mux.scala:126:16]
wire _GEN_63 = alloc_id == 3'h5; // @[Mux.scala:126:16]
wire _GEN_64 = alloc_id == 3'h6; // @[Mux.scala:126:16]
wire _GEN_65 = io_alloc_valid_0 & _T_4825 & ~_GEN_56[alloc_id]; // @[Mux.scala:126:16]
assign new_allocs_oh_ld_0 = _GEN_65 & _GEN_58; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ld_1 = _GEN_65 & _GEN_59; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ld_2 = _GEN_65 & _GEN_60; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ld_3 = _GEN_65 & _GEN_61; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ld_4 = _GEN_65 & _GEN_62; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ld_5 = _GEN_65 & _GEN_63; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ld_6 = _GEN_65 & _GEN_64; // @[ReservationStation.scala:174:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ld_7 = _GEN_65 & (&alloc_id); // @[Mux.scala:126:16]
wire _T_4822 = new_entry_q == 2'h1; // @[ReservationStation.scala:171:23, :350:27]
wire [1:0] _is_full_T_5 = _is_full_T_4; // @[ReservationStation.scala:351:33]
wire [2:0] _is_full_T_6 = _GEN_55 + {1'h0, _is_full_T_5}; // @[ReservationStation.scala:351:33]
wire [1:0] _is_full_T_7 = _is_full_T_6[1:0]; // @[ReservationStation.scala:351:33]
wire is_full_1 = _is_full_T_7[1]; // @[ReservationStation.scala:351:{33,72}]
wire _alloc_id_T_15 = ~entries_ex_0_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_16 = ~entries_ex_1_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_17 = ~entries_ex_2_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_18 = ~entries_ex_3_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_19 = ~entries_ex_4_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_20 = ~entries_ex_5_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_21 = ~entries_ex_6_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_22 = ~entries_ex_7_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_23 = ~entries_ex_8_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_24 = ~entries_ex_9_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_25 = ~entries_ex_10_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_26 = ~entries_ex_11_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_27 = ~entries_ex_12_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_28 = ~entries_ex_13_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_29 = ~entries_ex_14_valid; // @[ReservationStation.scala:118:23, :355:104]
wire _alloc_id_T_30 = ~entries_ex_15_valid; // @[ReservationStation.scala:118:23, :355:104]
wire [3:0] _alloc_id_T_32 = {3'h7, ~_alloc_id_T_29}; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_33 = _alloc_id_T_28 ? 4'hD : _alloc_id_T_32; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_34 = _alloc_id_T_27 ? 4'hC : _alloc_id_T_33; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_35 = _alloc_id_T_26 ? 4'hB : _alloc_id_T_34; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_36 = _alloc_id_T_25 ? 4'hA : _alloc_id_T_35; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_37 = _alloc_id_T_24 ? 4'h9 : _alloc_id_T_36; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_38 = _alloc_id_T_23 ? 4'h8 : _alloc_id_T_37; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_39 = _alloc_id_T_22 ? 4'h7 : _alloc_id_T_38; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_40 = _alloc_id_T_21 ? 4'h6 : _alloc_id_T_39; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_41 = _alloc_id_T_20 ? 4'h5 : _alloc_id_T_40; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_42 = _alloc_id_T_19 ? 4'h4 : _alloc_id_T_41; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_43 = _alloc_id_T_18 ? 4'h3 : _alloc_id_T_42; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_44 = _alloc_id_T_17 ? 4'h2 : _alloc_id_T_43; // @[Mux.scala:126:16]
wire [3:0] _alloc_id_T_45 = _alloc_id_T_16 ? 4'h1 : _alloc_id_T_44; // @[Mux.scala:126:16]
wire [3:0] alloc_id_1 = _alloc_id_T_15 ? 4'h0 : _alloc_id_T_45; // @[Mux.scala:126:16]
wire [15:0] _GEN_66 = {{entries_ex_15_valid}, {entries_ex_14_valid}, {entries_ex_13_valid}, {entries_ex_12_valid}, {entries_ex_11_valid}, {entries_ex_10_valid}, {entries_ex_9_valid}, {entries_ex_8_valid}, {entries_ex_7_valid}, {entries_ex_6_valid}, {entries_ex_5_valid}, {entries_ex_4_valid}, {entries_ex_3_valid}, {entries_ex_2_valid}, {entries_ex_1_valid}, {entries_ex_0_valid}}; // @[ReservationStation.scala:118:23, :357:17]
wire _GEN_67 = _T_4822 & ~_GEN_66[alloc_id_1]; // @[Mux.scala:126:16]
wire _GEN_68 = alloc_id_1 == 4'h0; // @[Mux.scala:126:16]
wire _GEN_69 = alloc_id_1 == 4'h1; // @[Mux.scala:126:16]
wire _GEN_70 = alloc_id_1 == 4'h2; // @[Mux.scala:126:16]
wire _GEN_71 = alloc_id_1 == 4'h3; // @[Mux.scala:126:16]
wire _GEN_72 = alloc_id_1 == 4'h4; // @[Mux.scala:126:16]
wire _GEN_73 = alloc_id_1 == 4'h5; // @[Mux.scala:126:16]
wire _GEN_74 = alloc_id_1 == 4'h6; // @[Mux.scala:126:16]
wire _GEN_75 = alloc_id_1 == 4'h7; // @[Mux.scala:126:16]
wire _GEN_76 = alloc_id_1 == 4'h8; // @[Mux.scala:126:16]
wire _GEN_77 = alloc_id_1 == 4'h9; // @[Mux.scala:126:16]
wire _GEN_78 = alloc_id_1 == 4'hA; // @[Mux.scala:126:16]
wire _GEN_79 = alloc_id_1 == 4'hB; // @[Mux.scala:126:16]
wire _GEN_80 = alloc_id_1 == 4'hC; // @[Mux.scala:126:16]
wire _GEN_81 = alloc_id_1 == 4'hD; // @[Mux.scala:126:16]
wire _GEN_82 = alloc_id_1 == 4'hE; // @[Mux.scala:126:16]
wire _GEN_83 = io_alloc_valid_0 & _GEN_67; // @[ReservationStation.scala:26:7, :179:26, :184:25, :350:34, :357:48, :358:28, :361:39]
assign new_allocs_oh_ex_0 = _GEN_83 & _GEN_68; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_1 = _GEN_83 & _GEN_69; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_2 = _GEN_83 & _GEN_70; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_3 = _GEN_83 & _GEN_71; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_4 = _GEN_83 & _GEN_72; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_5 = _GEN_83 & _GEN_73; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_6 = _GEN_83 & _GEN_74; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_7 = _GEN_83 & _GEN_75; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_8 = _GEN_83 & _GEN_76; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_9 = _GEN_83 & _GEN_77; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_10 = _GEN_83 & _GEN_78; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_11 = _GEN_83 & _GEN_79; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_12 = _GEN_83 & _GEN_80; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_13 = _GEN_83 & _GEN_81; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_14 = _GEN_83 & _GEN_82; // @[ReservationStation.scala:175:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_ex_15 = _GEN_83 & (&alloc_id_1); // @[Mux.scala:126:16]
wire _T_4827 = new_entry_q == 2'h2; // @[ReservationStation.scala:171:23, :350:27]
wire [1:0] _is_full_T_9 = _is_full_T_8; // @[ReservationStation.scala:351:33]
wire [2:0] _is_full_T_10 = _GEN_55 + {1'h0, _is_full_T_9}; // @[ReservationStation.scala:351:33]
wire [1:0] _is_full_T_11 = _is_full_T_10[1:0]; // @[ReservationStation.scala:351:33]
wire is_full_2 = _is_full_T_11[1]; // @[ReservationStation.scala:351:{33,72}]
wire _alloc_id_T_46 = ~entries_st_0_valid; // @[ReservationStation.scala:119:23, :355:104]
wire _alloc_id_T_47 = ~entries_st_1_valid; // @[ReservationStation.scala:119:23, :355:104]
wire _alloc_id_T_48 = ~entries_st_2_valid; // @[ReservationStation.scala:119:23, :355:104]
wire _alloc_id_T_49 = ~entries_st_3_valid; // @[ReservationStation.scala:119:23, :355:104]
wire [1:0] _alloc_id_T_51 = {1'h1, ~_alloc_id_T_48}; // @[Mux.scala:126:16]
wire [1:0] _alloc_id_T_52 = _alloc_id_T_47 ? 2'h1 : _alloc_id_T_51; // @[Mux.scala:126:16]
wire [1:0] alloc_id_2 = _alloc_id_T_46 ? 2'h0 : _alloc_id_T_52; // @[Mux.scala:126:16]
wire [3:0] _GEN_84 = {{entries_st_3_valid}, {entries_st_2_valid}, {entries_st_1_valid}, {entries_st_0_valid}}; // @[ReservationStation.scala:119:23, :357:17]
assign io_alloc_ready_0 = io_alloc_valid_0 & (_T_4827 ? ~_GEN_84[alloc_id_2] | _GEN_67 | _GEN_57 : _GEN_67 | _GEN_57); // @[Mux.scala:126:16]
wire _GEN_85 = alloc_id_2 == 2'h0; // @[Mux.scala:126:16]
wire _GEN_86 = alloc_id_2 == 2'h1; // @[Mux.scala:126:16]
wire _GEN_87 = alloc_id_2 == 2'h2; // @[Mux.scala:126:16]
wire _GEN_88 = io_alloc_valid_0 & _T_4827 & ~_GEN_84[alloc_id_2]; // @[Mux.scala:126:16]
assign new_allocs_oh_st_0 = _GEN_88 & _GEN_85; // @[ReservationStation.scala:176:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_st_1 = _GEN_88 & _GEN_86; // @[ReservationStation.scala:176:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_st_2 = _GEN_88 & _GEN_87; // @[ReservationStation.scala:176:30, :179:26, :184:25, :350:34, :357:48, :359:42, :361:39]
assign new_allocs_oh_st_3 = _GEN_88 & (&alloc_id_2); // @[Mux.scala:126:16]
wire [15:0] _a_stride_T = new_entry_cmd_cmd_rs1[31:16]; // @[ReservationStation.scala:171:23, :368:42]
wire [15:0] block_stride = new_entry_cmd_cmd_rs1[31:16]; // @[ReservationStation.scala:171:23, :368:42, :376:49]
wire [15:0] _c_stride_T = new_entry_cmd_cmd_rs2[63:48]; // @[ReservationStation.scala:171:23, :369:42]
wire set_only_strides = new_entry_cmd_cmd_rs1[7]; // @[ReservationStation.scala:171:23, :370:53]
wire _a_transpose_T = new_entry_cmd_cmd_rs1[8]; // @[ReservationStation.scala:171:23, :372:47]
wire [1:0] id_1 = new_entry_cmd_cmd_rs1[4:3]; // @[ReservationStation.scala:171:23, :375:39]
wire [4:0] _repeat_pixels_T = new_entry_cmd_cmd_rs1[12:8]; // @[ReservationStation.scala:171:23, :377:56]
wire _repeat_pixels_T_1 = |(_repeat_pixels_T[4:1]); // @[Util.scala:100:12]
wire [4:0] repeat_pixels = _repeat_pixels_T_1 ? _repeat_pixels_T : 5'h1; // @[Util.scala:100:{8,12}]
wire [5:0] _ld_pixel_repeats_T = {1'h0, repeat_pixels} - 6'h1; // @[Util.scala:100:8]
wire [4:0] _ld_pixel_repeats_T_1 = _ld_pixel_repeats_T[4:0]; // @[ReservationStation.scala:379:47]
wire [1:0] pool_stride = new_entry_cmd_cmd_rs1[5:4]; // @[ReservationStation.scala:171:23, :381:48]
wire _pooling_is_enabled_T = |pool_stride; // @[ReservationStation.scala:381:48, :382:43]
wire _issue_valids_T = entries_ld_0_bits_deps_ld_0 | entries_ld_0_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_1 = _issue_valids_T | entries_ld_0_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_2 = _issue_valids_T_1 | entries_ld_0_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_3 = _issue_valids_T_2 | entries_ld_0_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_4 = _issue_valids_T_3 | entries_ld_0_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_5 = _issue_valids_T_4 | entries_ld_0_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_6 = _issue_valids_T_5 | entries_ld_0_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_7 = entries_ld_0_bits_deps_ex_0 | entries_ld_0_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_8 = _issue_valids_T_7 | entries_ld_0_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_9 = _issue_valids_T_8 | entries_ld_0_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_10 = _issue_valids_T_9 | entries_ld_0_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_11 = _issue_valids_T_10 | entries_ld_0_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_12 = _issue_valids_T_11 | entries_ld_0_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_13 = _issue_valids_T_12 | entries_ld_0_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_14 = _issue_valids_T_13 | entries_ld_0_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_15 = _issue_valids_T_14 | entries_ld_0_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_16 = _issue_valids_T_15 | entries_ld_0_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_17 = _issue_valids_T_16 | entries_ld_0_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_18 = _issue_valids_T_17 | entries_ld_0_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_19 = _issue_valids_T_18 | entries_ld_0_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_20 = _issue_valids_T_19 | entries_ld_0_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_21 = _issue_valids_T_20 | entries_ld_0_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_22 = _issue_valids_T_6 | _issue_valids_T_21; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_23 = entries_ld_0_bits_deps_st_0 | entries_ld_0_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_24 = _issue_valids_T_23 | entries_ld_0_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_25 = _issue_valids_T_24 | entries_ld_0_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_26 = _issue_valids_T_22 | _issue_valids_T_25; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_27 = ~_issue_valids_T_26; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_28 = entries_ld_0_valid & _issue_valids_T_27; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_29 = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_0 = _issue_valids_T_28 & _issue_valids_T_29; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_30 = entries_ld_1_bits_deps_ld_0 | entries_ld_1_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_31 = _issue_valids_T_30 | entries_ld_1_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_32 = _issue_valids_T_31 | entries_ld_1_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_33 = _issue_valids_T_32 | entries_ld_1_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_34 = _issue_valids_T_33 | entries_ld_1_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_35 = _issue_valids_T_34 | entries_ld_1_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_36 = _issue_valids_T_35 | entries_ld_1_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_37 = entries_ld_1_bits_deps_ex_0 | entries_ld_1_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_38 = _issue_valids_T_37 | entries_ld_1_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_39 = _issue_valids_T_38 | entries_ld_1_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_40 = _issue_valids_T_39 | entries_ld_1_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_41 = _issue_valids_T_40 | entries_ld_1_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_42 = _issue_valids_T_41 | entries_ld_1_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_43 = _issue_valids_T_42 | entries_ld_1_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_44 = _issue_valids_T_43 | entries_ld_1_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_45 = _issue_valids_T_44 | entries_ld_1_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_46 = _issue_valids_T_45 | entries_ld_1_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_47 = _issue_valids_T_46 | entries_ld_1_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_48 = _issue_valids_T_47 | entries_ld_1_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_49 = _issue_valids_T_48 | entries_ld_1_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_50 = _issue_valids_T_49 | entries_ld_1_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_51 = _issue_valids_T_50 | entries_ld_1_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_52 = _issue_valids_T_36 | _issue_valids_T_51; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_53 = entries_ld_1_bits_deps_st_0 | entries_ld_1_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_54 = _issue_valids_T_53 | entries_ld_1_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_55 = _issue_valids_T_54 | entries_ld_1_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_56 = _issue_valids_T_52 | _issue_valids_T_55; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_57 = ~_issue_valids_T_56; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_58 = entries_ld_1_valid & _issue_valids_T_57; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_59 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_1 = _issue_valids_T_58 & _issue_valids_T_59; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_60 = entries_ld_2_bits_deps_ld_0 | entries_ld_2_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_61 = _issue_valids_T_60 | entries_ld_2_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_62 = _issue_valids_T_61 | entries_ld_2_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_63 = _issue_valids_T_62 | entries_ld_2_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_64 = _issue_valids_T_63 | entries_ld_2_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_65 = _issue_valids_T_64 | entries_ld_2_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_66 = _issue_valids_T_65 | entries_ld_2_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_67 = entries_ld_2_bits_deps_ex_0 | entries_ld_2_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_68 = _issue_valids_T_67 | entries_ld_2_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_69 = _issue_valids_T_68 | entries_ld_2_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_70 = _issue_valids_T_69 | entries_ld_2_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_71 = _issue_valids_T_70 | entries_ld_2_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_72 = _issue_valids_T_71 | entries_ld_2_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_73 = _issue_valids_T_72 | entries_ld_2_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_74 = _issue_valids_T_73 | entries_ld_2_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_75 = _issue_valids_T_74 | entries_ld_2_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_76 = _issue_valids_T_75 | entries_ld_2_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_77 = _issue_valids_T_76 | entries_ld_2_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_78 = _issue_valids_T_77 | entries_ld_2_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_79 = _issue_valids_T_78 | entries_ld_2_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_80 = _issue_valids_T_79 | entries_ld_2_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_81 = _issue_valids_T_80 | entries_ld_2_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_82 = _issue_valids_T_66 | _issue_valids_T_81; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_83 = entries_ld_2_bits_deps_st_0 | entries_ld_2_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_84 = _issue_valids_T_83 | entries_ld_2_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_85 = _issue_valids_T_84 | entries_ld_2_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_86 = _issue_valids_T_82 | _issue_valids_T_85; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_87 = ~_issue_valids_T_86; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_88 = entries_ld_2_valid & _issue_valids_T_87; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_89 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_2 = _issue_valids_T_88 & _issue_valids_T_89; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_90 = entries_ld_3_bits_deps_ld_0 | entries_ld_3_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_91 = _issue_valids_T_90 | entries_ld_3_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_92 = _issue_valids_T_91 | entries_ld_3_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_93 = _issue_valids_T_92 | entries_ld_3_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_94 = _issue_valids_T_93 | entries_ld_3_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_95 = _issue_valids_T_94 | entries_ld_3_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_96 = _issue_valids_T_95 | entries_ld_3_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_97 = entries_ld_3_bits_deps_ex_0 | entries_ld_3_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_98 = _issue_valids_T_97 | entries_ld_3_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_99 = _issue_valids_T_98 | entries_ld_3_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_100 = _issue_valids_T_99 | entries_ld_3_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_101 = _issue_valids_T_100 | entries_ld_3_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_102 = _issue_valids_T_101 | entries_ld_3_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_103 = _issue_valids_T_102 | entries_ld_3_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_104 = _issue_valids_T_103 | entries_ld_3_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_105 = _issue_valids_T_104 | entries_ld_3_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_106 = _issue_valids_T_105 | entries_ld_3_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_107 = _issue_valids_T_106 | entries_ld_3_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_108 = _issue_valids_T_107 | entries_ld_3_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_109 = _issue_valids_T_108 | entries_ld_3_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_110 = _issue_valids_T_109 | entries_ld_3_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_111 = _issue_valids_T_110 | entries_ld_3_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_112 = _issue_valids_T_96 | _issue_valids_T_111; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_113 = entries_ld_3_bits_deps_st_0 | entries_ld_3_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_114 = _issue_valids_T_113 | entries_ld_3_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_115 = _issue_valids_T_114 | entries_ld_3_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_116 = _issue_valids_T_112 | _issue_valids_T_115; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_117 = ~_issue_valids_T_116; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_118 = entries_ld_3_valid & _issue_valids_T_117; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_119 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_3 = _issue_valids_T_118 & _issue_valids_T_119; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_120 = entries_ld_4_bits_deps_ld_0 | entries_ld_4_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_121 = _issue_valids_T_120 | entries_ld_4_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_122 = _issue_valids_T_121 | entries_ld_4_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_123 = _issue_valids_T_122 | entries_ld_4_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_124 = _issue_valids_T_123 | entries_ld_4_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_125 = _issue_valids_T_124 | entries_ld_4_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_126 = _issue_valids_T_125 | entries_ld_4_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_127 = entries_ld_4_bits_deps_ex_0 | entries_ld_4_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_128 = _issue_valids_T_127 | entries_ld_4_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_129 = _issue_valids_T_128 | entries_ld_4_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_130 = _issue_valids_T_129 | entries_ld_4_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_131 = _issue_valids_T_130 | entries_ld_4_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_132 = _issue_valids_T_131 | entries_ld_4_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_133 = _issue_valids_T_132 | entries_ld_4_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_134 = _issue_valids_T_133 | entries_ld_4_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_135 = _issue_valids_T_134 | entries_ld_4_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_136 = _issue_valids_T_135 | entries_ld_4_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_137 = _issue_valids_T_136 | entries_ld_4_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_138 = _issue_valids_T_137 | entries_ld_4_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_139 = _issue_valids_T_138 | entries_ld_4_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_140 = _issue_valids_T_139 | entries_ld_4_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_141 = _issue_valids_T_140 | entries_ld_4_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_142 = _issue_valids_T_126 | _issue_valids_T_141; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_143 = entries_ld_4_bits_deps_st_0 | entries_ld_4_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_144 = _issue_valids_T_143 | entries_ld_4_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_145 = _issue_valids_T_144 | entries_ld_4_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_146 = _issue_valids_T_142 | _issue_valids_T_145; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_147 = ~_issue_valids_T_146; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_148 = entries_ld_4_valid & _issue_valids_T_147; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_149 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_4 = _issue_valids_T_148 & _issue_valids_T_149; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_150 = entries_ld_5_bits_deps_ld_0 | entries_ld_5_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_151 = _issue_valids_T_150 | entries_ld_5_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_152 = _issue_valids_T_151 | entries_ld_5_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_153 = _issue_valids_T_152 | entries_ld_5_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_154 = _issue_valids_T_153 | entries_ld_5_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_155 = _issue_valids_T_154 | entries_ld_5_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_156 = _issue_valids_T_155 | entries_ld_5_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_157 = entries_ld_5_bits_deps_ex_0 | entries_ld_5_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_158 = _issue_valids_T_157 | entries_ld_5_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_159 = _issue_valids_T_158 | entries_ld_5_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_160 = _issue_valids_T_159 | entries_ld_5_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_161 = _issue_valids_T_160 | entries_ld_5_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_162 = _issue_valids_T_161 | entries_ld_5_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_163 = _issue_valids_T_162 | entries_ld_5_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_164 = _issue_valids_T_163 | entries_ld_5_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_165 = _issue_valids_T_164 | entries_ld_5_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_166 = _issue_valids_T_165 | entries_ld_5_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_167 = _issue_valids_T_166 | entries_ld_5_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_168 = _issue_valids_T_167 | entries_ld_5_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_169 = _issue_valids_T_168 | entries_ld_5_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_170 = _issue_valids_T_169 | entries_ld_5_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_171 = _issue_valids_T_170 | entries_ld_5_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_172 = _issue_valids_T_156 | _issue_valids_T_171; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_173 = entries_ld_5_bits_deps_st_0 | entries_ld_5_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_174 = _issue_valids_T_173 | entries_ld_5_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_175 = _issue_valids_T_174 | entries_ld_5_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_176 = _issue_valids_T_172 | _issue_valids_T_175; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_177 = ~_issue_valids_T_176; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_178 = entries_ld_5_valid & _issue_valids_T_177; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_179 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_5 = _issue_valids_T_178 & _issue_valids_T_179; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_180 = entries_ld_6_bits_deps_ld_0 | entries_ld_6_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_181 = _issue_valids_T_180 | entries_ld_6_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_182 = _issue_valids_T_181 | entries_ld_6_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_183 = _issue_valids_T_182 | entries_ld_6_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_184 = _issue_valids_T_183 | entries_ld_6_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_185 = _issue_valids_T_184 | entries_ld_6_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_186 = _issue_valids_T_185 | entries_ld_6_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_187 = entries_ld_6_bits_deps_ex_0 | entries_ld_6_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_188 = _issue_valids_T_187 | entries_ld_6_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_189 = _issue_valids_T_188 | entries_ld_6_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_190 = _issue_valids_T_189 | entries_ld_6_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_191 = _issue_valids_T_190 | entries_ld_6_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_192 = _issue_valids_T_191 | entries_ld_6_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_193 = _issue_valids_T_192 | entries_ld_6_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_194 = _issue_valids_T_193 | entries_ld_6_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_195 = _issue_valids_T_194 | entries_ld_6_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_196 = _issue_valids_T_195 | entries_ld_6_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_197 = _issue_valids_T_196 | entries_ld_6_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_198 = _issue_valids_T_197 | entries_ld_6_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_199 = _issue_valids_T_198 | entries_ld_6_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_200 = _issue_valids_T_199 | entries_ld_6_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_201 = _issue_valids_T_200 | entries_ld_6_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_202 = _issue_valids_T_186 | _issue_valids_T_201; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_203 = entries_ld_6_bits_deps_st_0 | entries_ld_6_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_204 = _issue_valids_T_203 | entries_ld_6_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_205 = _issue_valids_T_204 | entries_ld_6_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_206 = _issue_valids_T_202 | _issue_valids_T_205; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_207 = ~_issue_valids_T_206; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_208 = entries_ld_6_valid & _issue_valids_T_207; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_209 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_6 = _issue_valids_T_208 & _issue_valids_T_209; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_210 = entries_ld_7_bits_deps_ld_0 | entries_ld_7_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_211 = _issue_valids_T_210 | entries_ld_7_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_212 = _issue_valids_T_211 | entries_ld_7_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_213 = _issue_valids_T_212 | entries_ld_7_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_214 = _issue_valids_T_213 | entries_ld_7_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_215 = _issue_valids_T_214 | entries_ld_7_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_216 = _issue_valids_T_215 | entries_ld_7_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :117:23]
wire _issue_valids_T_217 = entries_ld_7_bits_deps_ex_0 | entries_ld_7_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_218 = _issue_valids_T_217 | entries_ld_7_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_219 = _issue_valids_T_218 | entries_ld_7_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_220 = _issue_valids_T_219 | entries_ld_7_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_221 = _issue_valids_T_220 | entries_ld_7_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_222 = _issue_valids_T_221 | entries_ld_7_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_223 = _issue_valids_T_222 | entries_ld_7_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_224 = _issue_valids_T_223 | entries_ld_7_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_225 = _issue_valids_T_224 | entries_ld_7_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_226 = _issue_valids_T_225 | entries_ld_7_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_227 = _issue_valids_T_226 | entries_ld_7_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_228 = _issue_valids_T_227 | entries_ld_7_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_229 = _issue_valids_T_228 | entries_ld_7_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_230 = _issue_valids_T_229 | entries_ld_7_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_231 = _issue_valids_T_230 | entries_ld_7_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :117:23]
wire _issue_valids_T_232 = _issue_valids_T_216 | _issue_valids_T_231; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_233 = entries_ld_7_bits_deps_st_0 | entries_ld_7_bits_deps_st_1; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_234 = _issue_valids_T_233 | entries_ld_7_bits_deps_st_2; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_235 = _issue_valids_T_234 | entries_ld_7_bits_deps_st_3; // @[ReservationStation.scala:107:110, :117:23]
wire _issue_valids_T_236 = _issue_valids_T_232 | _issue_valids_T_235; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_237 = ~_issue_valids_T_236; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_238 = entries_ld_7_valid & _issue_valids_T_237; // @[ReservationStation.scala:107:39, :117:23, :395:54]
wire _issue_valids_T_239 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75]
wire issue_valids_7 = _issue_valids_T_238 & _issue_valids_T_239; // @[ReservationStation.scala:395:{54,72,75}]
wire [7:0] _issue_sel_enc_T = {issue_valids_7, 7'h0}; // @[Mux.scala:50:70]
wire [7:0] _issue_sel_enc_T_1 = issue_valids_6 ? 8'h40 : _issue_sel_enc_T; // @[Mux.scala:50:70]
wire [7:0] _issue_sel_enc_T_2 = issue_valids_5 ? 8'h20 : _issue_sel_enc_T_1; // @[Mux.scala:50:70]
wire [7:0] _issue_sel_enc_T_3 = issue_valids_4 ? 8'h10 : _issue_sel_enc_T_2; // @[Mux.scala:50:70]
wire [7:0] _issue_sel_enc_T_4 = issue_valids_3 ? 8'h8 : _issue_sel_enc_T_3; // @[Mux.scala:50:70]
wire [7:0] _issue_sel_enc_T_5 = issue_valids_2 ? 8'h4 : _issue_sel_enc_T_4; // @[Mux.scala:50:70]
wire [7:0] _issue_sel_enc_T_6 = issue_valids_1 ? 8'h2 : _issue_sel_enc_T_5; // @[Mux.scala:50:70]
wire [7:0] issue_sel_enc = issue_valids_0 ? 8'h1 : _issue_sel_enc_T_6; // @[Mux.scala:50:70]
wire issue_sel_0 = issue_sel_enc[0]; // @[OneHot.scala:83:30]
wire issue_sel_1 = issue_sel_enc[1]; // @[OneHot.scala:83:30]
wire issue_sel_2 = issue_sel_enc[2]; // @[OneHot.scala:83:30]
wire issue_sel_3 = issue_sel_enc[3]; // @[OneHot.scala:83:30]
wire issue_sel_4 = issue_sel_enc[4]; // @[OneHot.scala:83:30]
wire issue_sel_5 = issue_sel_enc[5]; // @[OneHot.scala:83:30]
wire issue_sel_6 = issue_sel_enc[6]; // @[OneHot.scala:83:30]
wire issue_sel_7 = issue_sel_enc[7]; // @[OneHot.scala:83:30]
wire [1:0] issue_id_lo_lo = {issue_sel_1, issue_sel_0}; // @[OneHot.scala:21:45, :83:30]
wire [1:0] issue_id_lo_hi = {issue_sel_3, issue_sel_2}; // @[OneHot.scala:21:45, :83:30]
wire [3:0] issue_id_lo = {issue_id_lo_hi, issue_id_lo_lo}; // @[OneHot.scala:21:45]
wire [1:0] issue_id_hi_lo = {issue_sel_5, issue_sel_4}; // @[OneHot.scala:21:45, :83:30]
wire [1:0] issue_id_hi_hi = {issue_sel_7, issue_sel_6}; // @[OneHot.scala:21:45, :83:30]
wire [3:0] issue_id_hi = {issue_id_hi_hi, issue_id_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] _issue_id_T = {issue_id_hi, issue_id_lo}; // @[OneHot.scala:21:45]
wire [3:0] issue_id_hi_1 = _issue_id_T[7:4]; // @[OneHot.scala:21:45, :30:18]
wire [3:0] issue_id_lo_1 = _issue_id_T[3:0]; // @[OneHot.scala:21:45, :31:18]
wire _issue_id_T_1 = |issue_id_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _issue_id_T_2 = issue_id_hi_1 | issue_id_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] issue_id_hi_2 = _issue_id_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] issue_id_lo_2 = _issue_id_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _issue_id_T_3 = |issue_id_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _issue_id_T_4 = issue_id_hi_2 | issue_id_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _issue_id_T_5 = _issue_id_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _issue_id_T_6 = {_issue_id_T_3, _issue_id_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] issue_id = {_issue_id_T_1, _issue_id_T_6}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _global_issue_id_T = {1'h0, issue_id}; // @[OneHot.scala:32:10]
assign global_issue_id = {2'h0, _global_issue_id_T}; // @[ReservationStation.scala:398:{30,53}]
assign io_issue_ld_rob_id_0 = global_issue_id; // @[ReservationStation.scala:26:7, :398:30]
wire _issue_entry_WIRE_142; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_q; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_is_config; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_opa_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_opa_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_opa_is_dst; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_issued; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_complete_on_issue; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_funct_0 = issue_entry_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_rs2_0 = issue_entry_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_rs1_0 = issue_entry_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_xd_0 = issue_entry_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_xs1_0 = issue_entry_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_xs2_0 = issue_entry_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_rd_0 = issue_entry_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_inst_opcode_0 = issue_entry_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_cmd_cmd_rs1; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_rs1_0 = issue_entry_bits_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_cmd_cmd_rs2; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_rs2_0 = issue_entry_bits_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_debug; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_debug_0 = issue_entry_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_cease; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_cease_0 = issue_entry_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_wfi_0 = issue_entry_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_cmd_cmd_status_isa; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_isa_0 = issue_entry_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_dprv_0 = issue_entry_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_dv; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_dv_0 = issue_entry_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_prv; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_prv_0 = issue_entry_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_v; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_v_0 = issue_entry_bits_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_sd; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_sd_0 = issue_entry_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_zero2_0 = issue_entry_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_mpv_0 = issue_entry_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_gva; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_gva_0 = issue_entry_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_mbe_0 = issue_entry_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_sbe_0 = issue_entry_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_sxl_0 = issue_entry_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_uxl_0 = issue_entry_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_sd_rv32_0 = issue_entry_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_zero1_0 = issue_entry_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_tsr_0 = issue_entry_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_tw; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_tw_0 = issue_entry_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_tvm_0 = issue_entry_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_mxr_0 = issue_entry_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_sum; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_sum_0 = issue_entry_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_mprv_0 = issue_entry_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_xs; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_xs_0 = issue_entry_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_fs; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_fs_0 = issue_entry_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_mpp_0 = issue_entry_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_cmd_cmd_status_vs; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_vs_0 = issue_entry_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_spp; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_spp_0 = issue_entry_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_mpie_0 = issue_entry_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_ube; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_ube_0 = issue_entry_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_spie; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_spie_0 = issue_entry_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_upie; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_upie_0 = issue_entry_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_mie; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_mie_0 = issue_entry_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_hie; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_hie_0 = issue_entry_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_sie; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_sie_0 = issue_entry_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_cmd_status_uie; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_cmd_status_uie_0 = issue_entry_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_rob_id_valid; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_rob_id_valid = issue_entry_bits_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_cmd_rob_id_bits; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_rob_id_bits = issue_entry_bits_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_from_matmul_fsm_0 = issue_entry_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_cmd_from_conv_fsm; // @[Mux.scala:30:73]
assign io_issue_ld_cmd_from_conv_fsm_0 = issue_entry_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ld_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_ex_15; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_st_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_st_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_st_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_deps_st_3; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_allocated_at; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_bits_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_bits_opa_bits_start_data; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_bits_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_bits_opa_bits_end_data; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_valid; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_0; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_1; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_2; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_3; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_4; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_5; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_6; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ld_7; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_0; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_1; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_2; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_3; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_4; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_5; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_6; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_7; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_8; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_9; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_10; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_11; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_12; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_13; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_14; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_ex_15; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_st_0; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_st_1; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_st_2; // @[Mux.scala:30:73]
wire issue_entry_bits_deps_st_3; // @[Mux.scala:30:73]
wire [1:0] issue_entry_bits_q; // @[Mux.scala:30:73]
wire issue_entry_bits_is_config; // @[Mux.scala:30:73]
wire issue_entry_bits_opa_is_dst; // @[Mux.scala:30:73]
wire issue_entry_bits_issued; // @[Mux.scala:30:73]
wire issue_entry_bits_complete_on_issue; // @[Mux.scala:30:73]
wire [31:0] issue_entry_bits_allocated_at; // @[Mux.scala:30:73]
wire issue_entry_valid; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_141; // @[Mux.scala:30:73]
assign issue_entry_bits_q = _issue_entry_WIRE_q; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_140; // @[Mux.scala:30:73]
assign issue_entry_bits_is_config = _issue_entry_WIRE_is_config; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_valid; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_valid = _issue_entry_WIRE_opa_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_start_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_start_is_acc_addr = _issue_entry_WIRE_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_start_accumulate; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_start_accumulate = _issue_entry_WIRE_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_116_bits_start_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_start_norm_cmd = _issue_entry_WIRE_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_116_bits_start_garbage; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_start_garbage = _issue_entry_WIRE_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_start_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_start_garbage_bit = _issue_entry_WIRE_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_116_bits_start_data; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_start_data = _issue_entry_WIRE_opa_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_end_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_end_is_acc_addr = _issue_entry_WIRE_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_end_accumulate; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_end_accumulate = _issue_entry_WIRE_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_116_bits_end_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_end_norm_cmd = _issue_entry_WIRE_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_116_bits_end_garbage; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_end_garbage = _issue_entry_WIRE_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_end_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_end_garbage_bit = _issue_entry_WIRE_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_116_bits_end_data; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_end_data = _issue_entry_WIRE_opa_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_116_bits_wraps_around; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_bits_wraps_around = _issue_entry_WIRE_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_115; // @[Mux.scala:30:73]
assign issue_entry_bits_opa_is_dst = _issue_entry_WIRE_opa_is_dst; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_90; // @[Mux.scala:30:73]
assign issue_entry_bits_issued = _issue_entry_WIRE_issued; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_89; // @[Mux.scala:30:73]
assign issue_entry_bits_complete_on_issue = _issue_entry_WIRE_complete_on_issue; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_33_cmd_inst_funct; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_funct = _issue_entry_WIRE_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_33_cmd_inst_rs2; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_rs2 = _issue_entry_WIRE_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_33_cmd_inst_rs1; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_rs1 = _issue_entry_WIRE_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_inst_xd; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_xd = _issue_entry_WIRE_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_inst_xs1; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_xs1 = _issue_entry_WIRE_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_inst_xs2; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_xs2 = _issue_entry_WIRE_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_33_cmd_inst_rd; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_rd = _issue_entry_WIRE_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_33_cmd_inst_opcode; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_inst_opcode = _issue_entry_WIRE_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_33_cmd_rs1; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_rs1 = _issue_entry_WIRE_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_33_cmd_rs2; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_rs2 = _issue_entry_WIRE_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_debug; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_debug = _issue_entry_WIRE_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_cease; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_cease = _issue_entry_WIRE_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_wfi; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_wfi = _issue_entry_WIRE_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_33_cmd_status_isa; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_isa = _issue_entry_WIRE_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_dprv; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_dprv = _issue_entry_WIRE_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_dv; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_dv = _issue_entry_WIRE_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_prv; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_prv = _issue_entry_WIRE_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_v; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_v = _issue_entry_WIRE_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_sd; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_sd = _issue_entry_WIRE_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_33_cmd_status_zero2; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_zero2 = _issue_entry_WIRE_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_mpv; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_mpv = _issue_entry_WIRE_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_gva; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_gva = _issue_entry_WIRE_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_mbe; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_mbe = _issue_entry_WIRE_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_sbe; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_sbe = _issue_entry_WIRE_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_sxl; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_sxl = _issue_entry_WIRE_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_uxl; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_uxl = _issue_entry_WIRE_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_sd_rv32; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_33_cmd_status_zero1; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_zero1 = _issue_entry_WIRE_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_tsr; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_tsr = _issue_entry_WIRE_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_tw; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_tw = _issue_entry_WIRE_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_tvm; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_tvm = _issue_entry_WIRE_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_mxr; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_mxr = _issue_entry_WIRE_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_sum; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_sum = _issue_entry_WIRE_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_mprv; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_mprv = _issue_entry_WIRE_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_xs; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_xs = _issue_entry_WIRE_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_fs; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_fs = _issue_entry_WIRE_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_mpp; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_mpp = _issue_entry_WIRE_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_33_cmd_status_vs; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_vs = _issue_entry_WIRE_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_spp; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_spp = _issue_entry_WIRE_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_mpie; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_mpie = _issue_entry_WIRE_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_ube; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_ube = _issue_entry_WIRE_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_spie; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_spie = _issue_entry_WIRE_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_upie; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_upie = _issue_entry_WIRE_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_mie; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_mie = _issue_entry_WIRE_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_hie; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_hie = _issue_entry_WIRE_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_sie; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_sie = _issue_entry_WIRE_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_cmd_status_uie; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_cmd_status_uie = _issue_entry_WIRE_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_rob_id_valid; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_rob_id_valid = _issue_entry_WIRE_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_33_rob_id_bits; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_rob_id_bits = _issue_entry_WIRE_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_from_matmul_fsm; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_from_matmul_fsm = _issue_entry_WIRE_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_33_from_conv_fsm; // @[Mux.scala:30:73]
assign issue_entry_bits_cmd_from_conv_fsm = _issue_entry_WIRE_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_0; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_0 = _issue_entry_WIRE_deps_ld_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_1; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_1 = _issue_entry_WIRE_deps_ld_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_2; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_2 = _issue_entry_WIRE_deps_ld_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_3; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_3 = _issue_entry_WIRE_deps_ld_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_4; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_4 = _issue_entry_WIRE_deps_ld_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_5; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_5 = _issue_entry_WIRE_deps_ld_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_6; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_6 = _issue_entry_WIRE_deps_ld_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_24_7; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ld_7 = _issue_entry_WIRE_deps_ld_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_0; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_0 = _issue_entry_WIRE_deps_ex_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_1; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_1 = _issue_entry_WIRE_deps_ex_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_2; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_2 = _issue_entry_WIRE_deps_ex_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_3; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_3 = _issue_entry_WIRE_deps_ex_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_4; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_4 = _issue_entry_WIRE_deps_ex_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_5; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_5 = _issue_entry_WIRE_deps_ex_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_6; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_6 = _issue_entry_WIRE_deps_ex_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_7; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_7 = _issue_entry_WIRE_deps_ex_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_8; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_8 = _issue_entry_WIRE_deps_ex_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_9; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_9 = _issue_entry_WIRE_deps_ex_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_10; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_10 = _issue_entry_WIRE_deps_ex_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_11; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_11 = _issue_entry_WIRE_deps_ex_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_12; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_12 = _issue_entry_WIRE_deps_ex_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_13; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_13 = _issue_entry_WIRE_deps_ex_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_14; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_14 = _issue_entry_WIRE_deps_ex_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_7_15; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_ex_15 = _issue_entry_WIRE_deps_ex_15; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_2_0; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_st_0 = _issue_entry_WIRE_deps_st_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_2_1; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_st_1 = _issue_entry_WIRE_deps_st_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_2_2; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_st_2 = _issue_entry_WIRE_deps_st_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_2_3; // @[Mux.scala:30:73]
assign issue_entry_bits_deps_st_3 = _issue_entry_WIRE_deps_st_3; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_1; // @[Mux.scala:30:73]
assign issue_entry_bits_allocated_at = _issue_entry_WIRE_allocated_at; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T = issue_sel_0 ? entries_ld_0_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1 = issue_sel_1 ? entries_ld_1_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_2 = issue_sel_2 ? entries_ld_2_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3 = issue_sel_3 ? entries_ld_3_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_4 = issue_sel_4 ? entries_ld_4_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5 = issue_sel_5 ? entries_ld_5_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_6 = issue_sel_6 ? entries_ld_6_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_7 = issue_sel_7 ? entries_ld_7_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_8 = _issue_entry_T | _issue_entry_T_1; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_9 = _issue_entry_T_8 | _issue_entry_T_2; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_10 = _issue_entry_T_9 | _issue_entry_T_3; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_11 = _issue_entry_T_10 | _issue_entry_T_4; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_12 = _issue_entry_T_11 | _issue_entry_T_5; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_13 = _issue_entry_T_12 | _issue_entry_T_6; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_14 = _issue_entry_T_13 | _issue_entry_T_7; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_1 = _issue_entry_T_14; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_allocated_at = _issue_entry_WIRE_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_3; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_st_0 = _issue_entry_WIRE_2_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_4; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_st_1 = _issue_entry_WIRE_2_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_5; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_st_2 = _issue_entry_WIRE_2_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_6; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_st_3 = _issue_entry_WIRE_2_3; // @[Mux.scala:30:73]
wire _issue_entry_T_15 = issue_sel_0 & entries_ld_0_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_16 = issue_sel_1 & entries_ld_1_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_17 = issue_sel_2 & entries_ld_2_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_18 = issue_sel_3 & entries_ld_3_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_19 = issue_sel_4 & entries_ld_4_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_20 = issue_sel_5 & entries_ld_5_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_21 = issue_sel_6 & entries_ld_6_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_22 = issue_sel_7 & entries_ld_7_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_23 = _issue_entry_T_15 | _issue_entry_T_16; // @[Mux.scala:30:73]
wire _issue_entry_T_24 = _issue_entry_T_23 | _issue_entry_T_17; // @[Mux.scala:30:73]
wire _issue_entry_T_25 = _issue_entry_T_24 | _issue_entry_T_18; // @[Mux.scala:30:73]
wire _issue_entry_T_26 = _issue_entry_T_25 | _issue_entry_T_19; // @[Mux.scala:30:73]
wire _issue_entry_T_27 = _issue_entry_T_26 | _issue_entry_T_20; // @[Mux.scala:30:73]
wire _issue_entry_T_28 = _issue_entry_T_27 | _issue_entry_T_21; // @[Mux.scala:30:73]
wire _issue_entry_T_29 = _issue_entry_T_28 | _issue_entry_T_22; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_3 = _issue_entry_T_29; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_2_0 = _issue_entry_WIRE_3; // @[Mux.scala:30:73]
wire _issue_entry_T_30 = issue_sel_0 & entries_ld_0_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_31 = issue_sel_1 & entries_ld_1_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_32 = issue_sel_2 & entries_ld_2_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_33 = issue_sel_3 & entries_ld_3_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_34 = issue_sel_4 & entries_ld_4_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_35 = issue_sel_5 & entries_ld_5_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_36 = issue_sel_6 & entries_ld_6_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_37 = issue_sel_7 & entries_ld_7_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_38 = _issue_entry_T_30 | _issue_entry_T_31; // @[Mux.scala:30:73]
wire _issue_entry_T_39 = _issue_entry_T_38 | _issue_entry_T_32; // @[Mux.scala:30:73]
wire _issue_entry_T_40 = _issue_entry_T_39 | _issue_entry_T_33; // @[Mux.scala:30:73]
wire _issue_entry_T_41 = _issue_entry_T_40 | _issue_entry_T_34; // @[Mux.scala:30:73]
wire _issue_entry_T_42 = _issue_entry_T_41 | _issue_entry_T_35; // @[Mux.scala:30:73]
wire _issue_entry_T_43 = _issue_entry_T_42 | _issue_entry_T_36; // @[Mux.scala:30:73]
wire _issue_entry_T_44 = _issue_entry_T_43 | _issue_entry_T_37; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_4 = _issue_entry_T_44; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_2_1 = _issue_entry_WIRE_4; // @[Mux.scala:30:73]
wire _issue_entry_T_45 = issue_sel_0 & entries_ld_0_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_46 = issue_sel_1 & entries_ld_1_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_47 = issue_sel_2 & entries_ld_2_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_48 = issue_sel_3 & entries_ld_3_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_49 = issue_sel_4 & entries_ld_4_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_50 = issue_sel_5 & entries_ld_5_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_51 = issue_sel_6 & entries_ld_6_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_52 = issue_sel_7 & entries_ld_7_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_53 = _issue_entry_T_45 | _issue_entry_T_46; // @[Mux.scala:30:73]
wire _issue_entry_T_54 = _issue_entry_T_53 | _issue_entry_T_47; // @[Mux.scala:30:73]
wire _issue_entry_T_55 = _issue_entry_T_54 | _issue_entry_T_48; // @[Mux.scala:30:73]
wire _issue_entry_T_56 = _issue_entry_T_55 | _issue_entry_T_49; // @[Mux.scala:30:73]
wire _issue_entry_T_57 = _issue_entry_T_56 | _issue_entry_T_50; // @[Mux.scala:30:73]
wire _issue_entry_T_58 = _issue_entry_T_57 | _issue_entry_T_51; // @[Mux.scala:30:73]
wire _issue_entry_T_59 = _issue_entry_T_58 | _issue_entry_T_52; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_5 = _issue_entry_T_59; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_2_2 = _issue_entry_WIRE_5; // @[Mux.scala:30:73]
wire _issue_entry_T_60 = issue_sel_0 & entries_ld_0_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_61 = issue_sel_1 & entries_ld_1_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_62 = issue_sel_2 & entries_ld_2_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_63 = issue_sel_3 & entries_ld_3_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_64 = issue_sel_4 & entries_ld_4_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_65 = issue_sel_5 & entries_ld_5_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_66 = issue_sel_6 & entries_ld_6_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_67 = issue_sel_7 & entries_ld_7_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_68 = _issue_entry_T_60 | _issue_entry_T_61; // @[Mux.scala:30:73]
wire _issue_entry_T_69 = _issue_entry_T_68 | _issue_entry_T_62; // @[Mux.scala:30:73]
wire _issue_entry_T_70 = _issue_entry_T_69 | _issue_entry_T_63; // @[Mux.scala:30:73]
wire _issue_entry_T_71 = _issue_entry_T_70 | _issue_entry_T_64; // @[Mux.scala:30:73]
wire _issue_entry_T_72 = _issue_entry_T_71 | _issue_entry_T_65; // @[Mux.scala:30:73]
wire _issue_entry_T_73 = _issue_entry_T_72 | _issue_entry_T_66; // @[Mux.scala:30:73]
wire _issue_entry_T_74 = _issue_entry_T_73 | _issue_entry_T_67; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_6 = _issue_entry_T_74; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_2_3 = _issue_entry_WIRE_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_8; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_0 = _issue_entry_WIRE_7_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_9; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_1 = _issue_entry_WIRE_7_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_10; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_2 = _issue_entry_WIRE_7_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_11; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_3 = _issue_entry_WIRE_7_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_12; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_4 = _issue_entry_WIRE_7_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_13; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_5 = _issue_entry_WIRE_7_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_14; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_6 = _issue_entry_WIRE_7_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_15; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_7 = _issue_entry_WIRE_7_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_16; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_8 = _issue_entry_WIRE_7_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_17; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_9 = _issue_entry_WIRE_7_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_18; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_10 = _issue_entry_WIRE_7_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_19; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_11 = _issue_entry_WIRE_7_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_20; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_12 = _issue_entry_WIRE_7_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_21; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_13 = _issue_entry_WIRE_7_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_22; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_14 = _issue_entry_WIRE_7_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_23; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ex_15 = _issue_entry_WIRE_7_15; // @[Mux.scala:30:73]
wire _issue_entry_T_75 = issue_sel_0 & entries_ld_0_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_76 = issue_sel_1 & entries_ld_1_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_77 = issue_sel_2 & entries_ld_2_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_78 = issue_sel_3 & entries_ld_3_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_79 = issue_sel_4 & entries_ld_4_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_80 = issue_sel_5 & entries_ld_5_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_81 = issue_sel_6 & entries_ld_6_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_82 = issue_sel_7 & entries_ld_7_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_83 = _issue_entry_T_75 | _issue_entry_T_76; // @[Mux.scala:30:73]
wire _issue_entry_T_84 = _issue_entry_T_83 | _issue_entry_T_77; // @[Mux.scala:30:73]
wire _issue_entry_T_85 = _issue_entry_T_84 | _issue_entry_T_78; // @[Mux.scala:30:73]
wire _issue_entry_T_86 = _issue_entry_T_85 | _issue_entry_T_79; // @[Mux.scala:30:73]
wire _issue_entry_T_87 = _issue_entry_T_86 | _issue_entry_T_80; // @[Mux.scala:30:73]
wire _issue_entry_T_88 = _issue_entry_T_87 | _issue_entry_T_81; // @[Mux.scala:30:73]
wire _issue_entry_T_89 = _issue_entry_T_88 | _issue_entry_T_82; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_8 = _issue_entry_T_89; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_0 = _issue_entry_WIRE_8; // @[Mux.scala:30:73]
wire _issue_entry_T_90 = issue_sel_0 & entries_ld_0_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_91 = issue_sel_1 & entries_ld_1_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_92 = issue_sel_2 & entries_ld_2_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_93 = issue_sel_3 & entries_ld_3_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_94 = issue_sel_4 & entries_ld_4_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_95 = issue_sel_5 & entries_ld_5_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_96 = issue_sel_6 & entries_ld_6_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_97 = issue_sel_7 & entries_ld_7_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_98 = _issue_entry_T_90 | _issue_entry_T_91; // @[Mux.scala:30:73]
wire _issue_entry_T_99 = _issue_entry_T_98 | _issue_entry_T_92; // @[Mux.scala:30:73]
wire _issue_entry_T_100 = _issue_entry_T_99 | _issue_entry_T_93; // @[Mux.scala:30:73]
wire _issue_entry_T_101 = _issue_entry_T_100 | _issue_entry_T_94; // @[Mux.scala:30:73]
wire _issue_entry_T_102 = _issue_entry_T_101 | _issue_entry_T_95; // @[Mux.scala:30:73]
wire _issue_entry_T_103 = _issue_entry_T_102 | _issue_entry_T_96; // @[Mux.scala:30:73]
wire _issue_entry_T_104 = _issue_entry_T_103 | _issue_entry_T_97; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_9 = _issue_entry_T_104; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_1 = _issue_entry_WIRE_9; // @[Mux.scala:30:73]
wire _issue_entry_T_105 = issue_sel_0 & entries_ld_0_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_106 = issue_sel_1 & entries_ld_1_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_107 = issue_sel_2 & entries_ld_2_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_108 = issue_sel_3 & entries_ld_3_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_109 = issue_sel_4 & entries_ld_4_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_110 = issue_sel_5 & entries_ld_5_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_111 = issue_sel_6 & entries_ld_6_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_112 = issue_sel_7 & entries_ld_7_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_113 = _issue_entry_T_105 | _issue_entry_T_106; // @[Mux.scala:30:73]
wire _issue_entry_T_114 = _issue_entry_T_113 | _issue_entry_T_107; // @[Mux.scala:30:73]
wire _issue_entry_T_115 = _issue_entry_T_114 | _issue_entry_T_108; // @[Mux.scala:30:73]
wire _issue_entry_T_116 = _issue_entry_T_115 | _issue_entry_T_109; // @[Mux.scala:30:73]
wire _issue_entry_T_117 = _issue_entry_T_116 | _issue_entry_T_110; // @[Mux.scala:30:73]
wire _issue_entry_T_118 = _issue_entry_T_117 | _issue_entry_T_111; // @[Mux.scala:30:73]
wire _issue_entry_T_119 = _issue_entry_T_118 | _issue_entry_T_112; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_10 = _issue_entry_T_119; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_2 = _issue_entry_WIRE_10; // @[Mux.scala:30:73]
wire _issue_entry_T_120 = issue_sel_0 & entries_ld_0_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_121 = issue_sel_1 & entries_ld_1_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_122 = issue_sel_2 & entries_ld_2_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_123 = issue_sel_3 & entries_ld_3_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_124 = issue_sel_4 & entries_ld_4_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_125 = issue_sel_5 & entries_ld_5_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_126 = issue_sel_6 & entries_ld_6_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_127 = issue_sel_7 & entries_ld_7_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_128 = _issue_entry_T_120 | _issue_entry_T_121; // @[Mux.scala:30:73]
wire _issue_entry_T_129 = _issue_entry_T_128 | _issue_entry_T_122; // @[Mux.scala:30:73]
wire _issue_entry_T_130 = _issue_entry_T_129 | _issue_entry_T_123; // @[Mux.scala:30:73]
wire _issue_entry_T_131 = _issue_entry_T_130 | _issue_entry_T_124; // @[Mux.scala:30:73]
wire _issue_entry_T_132 = _issue_entry_T_131 | _issue_entry_T_125; // @[Mux.scala:30:73]
wire _issue_entry_T_133 = _issue_entry_T_132 | _issue_entry_T_126; // @[Mux.scala:30:73]
wire _issue_entry_T_134 = _issue_entry_T_133 | _issue_entry_T_127; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_11 = _issue_entry_T_134; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_3 = _issue_entry_WIRE_11; // @[Mux.scala:30:73]
wire _issue_entry_T_135 = issue_sel_0 & entries_ld_0_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_136 = issue_sel_1 & entries_ld_1_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_137 = issue_sel_2 & entries_ld_2_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_138 = issue_sel_3 & entries_ld_3_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_139 = issue_sel_4 & entries_ld_4_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_140 = issue_sel_5 & entries_ld_5_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_141 = issue_sel_6 & entries_ld_6_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_142 = issue_sel_7 & entries_ld_7_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_143 = _issue_entry_T_135 | _issue_entry_T_136; // @[Mux.scala:30:73]
wire _issue_entry_T_144 = _issue_entry_T_143 | _issue_entry_T_137; // @[Mux.scala:30:73]
wire _issue_entry_T_145 = _issue_entry_T_144 | _issue_entry_T_138; // @[Mux.scala:30:73]
wire _issue_entry_T_146 = _issue_entry_T_145 | _issue_entry_T_139; // @[Mux.scala:30:73]
wire _issue_entry_T_147 = _issue_entry_T_146 | _issue_entry_T_140; // @[Mux.scala:30:73]
wire _issue_entry_T_148 = _issue_entry_T_147 | _issue_entry_T_141; // @[Mux.scala:30:73]
wire _issue_entry_T_149 = _issue_entry_T_148 | _issue_entry_T_142; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_12 = _issue_entry_T_149; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_4 = _issue_entry_WIRE_12; // @[Mux.scala:30:73]
wire _issue_entry_T_150 = issue_sel_0 & entries_ld_0_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_151 = issue_sel_1 & entries_ld_1_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_152 = issue_sel_2 & entries_ld_2_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_153 = issue_sel_3 & entries_ld_3_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_154 = issue_sel_4 & entries_ld_4_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_155 = issue_sel_5 & entries_ld_5_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_156 = issue_sel_6 & entries_ld_6_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_157 = issue_sel_7 & entries_ld_7_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_158 = _issue_entry_T_150 | _issue_entry_T_151; // @[Mux.scala:30:73]
wire _issue_entry_T_159 = _issue_entry_T_158 | _issue_entry_T_152; // @[Mux.scala:30:73]
wire _issue_entry_T_160 = _issue_entry_T_159 | _issue_entry_T_153; // @[Mux.scala:30:73]
wire _issue_entry_T_161 = _issue_entry_T_160 | _issue_entry_T_154; // @[Mux.scala:30:73]
wire _issue_entry_T_162 = _issue_entry_T_161 | _issue_entry_T_155; // @[Mux.scala:30:73]
wire _issue_entry_T_163 = _issue_entry_T_162 | _issue_entry_T_156; // @[Mux.scala:30:73]
wire _issue_entry_T_164 = _issue_entry_T_163 | _issue_entry_T_157; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_13 = _issue_entry_T_164; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_5 = _issue_entry_WIRE_13; // @[Mux.scala:30:73]
wire _issue_entry_T_165 = issue_sel_0 & entries_ld_0_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_166 = issue_sel_1 & entries_ld_1_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_167 = issue_sel_2 & entries_ld_2_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_168 = issue_sel_3 & entries_ld_3_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_169 = issue_sel_4 & entries_ld_4_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_170 = issue_sel_5 & entries_ld_5_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_171 = issue_sel_6 & entries_ld_6_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_172 = issue_sel_7 & entries_ld_7_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_173 = _issue_entry_T_165 | _issue_entry_T_166; // @[Mux.scala:30:73]
wire _issue_entry_T_174 = _issue_entry_T_173 | _issue_entry_T_167; // @[Mux.scala:30:73]
wire _issue_entry_T_175 = _issue_entry_T_174 | _issue_entry_T_168; // @[Mux.scala:30:73]
wire _issue_entry_T_176 = _issue_entry_T_175 | _issue_entry_T_169; // @[Mux.scala:30:73]
wire _issue_entry_T_177 = _issue_entry_T_176 | _issue_entry_T_170; // @[Mux.scala:30:73]
wire _issue_entry_T_178 = _issue_entry_T_177 | _issue_entry_T_171; // @[Mux.scala:30:73]
wire _issue_entry_T_179 = _issue_entry_T_178 | _issue_entry_T_172; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_14 = _issue_entry_T_179; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_6 = _issue_entry_WIRE_14; // @[Mux.scala:30:73]
wire _issue_entry_T_180 = issue_sel_0 & entries_ld_0_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_181 = issue_sel_1 & entries_ld_1_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_182 = issue_sel_2 & entries_ld_2_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_183 = issue_sel_3 & entries_ld_3_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_184 = issue_sel_4 & entries_ld_4_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_185 = issue_sel_5 & entries_ld_5_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_186 = issue_sel_6 & entries_ld_6_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_187 = issue_sel_7 & entries_ld_7_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_188 = _issue_entry_T_180 | _issue_entry_T_181; // @[Mux.scala:30:73]
wire _issue_entry_T_189 = _issue_entry_T_188 | _issue_entry_T_182; // @[Mux.scala:30:73]
wire _issue_entry_T_190 = _issue_entry_T_189 | _issue_entry_T_183; // @[Mux.scala:30:73]
wire _issue_entry_T_191 = _issue_entry_T_190 | _issue_entry_T_184; // @[Mux.scala:30:73]
wire _issue_entry_T_192 = _issue_entry_T_191 | _issue_entry_T_185; // @[Mux.scala:30:73]
wire _issue_entry_T_193 = _issue_entry_T_192 | _issue_entry_T_186; // @[Mux.scala:30:73]
wire _issue_entry_T_194 = _issue_entry_T_193 | _issue_entry_T_187; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_15 = _issue_entry_T_194; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_7 = _issue_entry_WIRE_15; // @[Mux.scala:30:73]
wire _issue_entry_T_195 = issue_sel_0 & entries_ld_0_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_196 = issue_sel_1 & entries_ld_1_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_197 = issue_sel_2 & entries_ld_2_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_198 = issue_sel_3 & entries_ld_3_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_199 = issue_sel_4 & entries_ld_4_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_200 = issue_sel_5 & entries_ld_5_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_201 = issue_sel_6 & entries_ld_6_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_202 = issue_sel_7 & entries_ld_7_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_203 = _issue_entry_T_195 | _issue_entry_T_196; // @[Mux.scala:30:73]
wire _issue_entry_T_204 = _issue_entry_T_203 | _issue_entry_T_197; // @[Mux.scala:30:73]
wire _issue_entry_T_205 = _issue_entry_T_204 | _issue_entry_T_198; // @[Mux.scala:30:73]
wire _issue_entry_T_206 = _issue_entry_T_205 | _issue_entry_T_199; // @[Mux.scala:30:73]
wire _issue_entry_T_207 = _issue_entry_T_206 | _issue_entry_T_200; // @[Mux.scala:30:73]
wire _issue_entry_T_208 = _issue_entry_T_207 | _issue_entry_T_201; // @[Mux.scala:30:73]
wire _issue_entry_T_209 = _issue_entry_T_208 | _issue_entry_T_202; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_16 = _issue_entry_T_209; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_8 = _issue_entry_WIRE_16; // @[Mux.scala:30:73]
wire _issue_entry_T_210 = issue_sel_0 & entries_ld_0_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_211 = issue_sel_1 & entries_ld_1_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_212 = issue_sel_2 & entries_ld_2_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_213 = issue_sel_3 & entries_ld_3_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_214 = issue_sel_4 & entries_ld_4_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_215 = issue_sel_5 & entries_ld_5_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_216 = issue_sel_6 & entries_ld_6_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_217 = issue_sel_7 & entries_ld_7_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_218 = _issue_entry_T_210 | _issue_entry_T_211; // @[Mux.scala:30:73]
wire _issue_entry_T_219 = _issue_entry_T_218 | _issue_entry_T_212; // @[Mux.scala:30:73]
wire _issue_entry_T_220 = _issue_entry_T_219 | _issue_entry_T_213; // @[Mux.scala:30:73]
wire _issue_entry_T_221 = _issue_entry_T_220 | _issue_entry_T_214; // @[Mux.scala:30:73]
wire _issue_entry_T_222 = _issue_entry_T_221 | _issue_entry_T_215; // @[Mux.scala:30:73]
wire _issue_entry_T_223 = _issue_entry_T_222 | _issue_entry_T_216; // @[Mux.scala:30:73]
wire _issue_entry_T_224 = _issue_entry_T_223 | _issue_entry_T_217; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_17 = _issue_entry_T_224; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_9 = _issue_entry_WIRE_17; // @[Mux.scala:30:73]
wire _issue_entry_T_225 = issue_sel_0 & entries_ld_0_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_226 = issue_sel_1 & entries_ld_1_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_227 = issue_sel_2 & entries_ld_2_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_228 = issue_sel_3 & entries_ld_3_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_229 = issue_sel_4 & entries_ld_4_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_230 = issue_sel_5 & entries_ld_5_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_231 = issue_sel_6 & entries_ld_6_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_232 = issue_sel_7 & entries_ld_7_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_233 = _issue_entry_T_225 | _issue_entry_T_226; // @[Mux.scala:30:73]
wire _issue_entry_T_234 = _issue_entry_T_233 | _issue_entry_T_227; // @[Mux.scala:30:73]
wire _issue_entry_T_235 = _issue_entry_T_234 | _issue_entry_T_228; // @[Mux.scala:30:73]
wire _issue_entry_T_236 = _issue_entry_T_235 | _issue_entry_T_229; // @[Mux.scala:30:73]
wire _issue_entry_T_237 = _issue_entry_T_236 | _issue_entry_T_230; // @[Mux.scala:30:73]
wire _issue_entry_T_238 = _issue_entry_T_237 | _issue_entry_T_231; // @[Mux.scala:30:73]
wire _issue_entry_T_239 = _issue_entry_T_238 | _issue_entry_T_232; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_18 = _issue_entry_T_239; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_10 = _issue_entry_WIRE_18; // @[Mux.scala:30:73]
wire _issue_entry_T_240 = issue_sel_0 & entries_ld_0_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_241 = issue_sel_1 & entries_ld_1_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_242 = issue_sel_2 & entries_ld_2_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_243 = issue_sel_3 & entries_ld_3_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_244 = issue_sel_4 & entries_ld_4_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_245 = issue_sel_5 & entries_ld_5_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_246 = issue_sel_6 & entries_ld_6_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_247 = issue_sel_7 & entries_ld_7_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_248 = _issue_entry_T_240 | _issue_entry_T_241; // @[Mux.scala:30:73]
wire _issue_entry_T_249 = _issue_entry_T_248 | _issue_entry_T_242; // @[Mux.scala:30:73]
wire _issue_entry_T_250 = _issue_entry_T_249 | _issue_entry_T_243; // @[Mux.scala:30:73]
wire _issue_entry_T_251 = _issue_entry_T_250 | _issue_entry_T_244; // @[Mux.scala:30:73]
wire _issue_entry_T_252 = _issue_entry_T_251 | _issue_entry_T_245; // @[Mux.scala:30:73]
wire _issue_entry_T_253 = _issue_entry_T_252 | _issue_entry_T_246; // @[Mux.scala:30:73]
wire _issue_entry_T_254 = _issue_entry_T_253 | _issue_entry_T_247; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_19 = _issue_entry_T_254; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_11 = _issue_entry_WIRE_19; // @[Mux.scala:30:73]
wire _issue_entry_T_255 = issue_sel_0 & entries_ld_0_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_256 = issue_sel_1 & entries_ld_1_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_257 = issue_sel_2 & entries_ld_2_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_258 = issue_sel_3 & entries_ld_3_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_259 = issue_sel_4 & entries_ld_4_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_260 = issue_sel_5 & entries_ld_5_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_261 = issue_sel_6 & entries_ld_6_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_262 = issue_sel_7 & entries_ld_7_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_263 = _issue_entry_T_255 | _issue_entry_T_256; // @[Mux.scala:30:73]
wire _issue_entry_T_264 = _issue_entry_T_263 | _issue_entry_T_257; // @[Mux.scala:30:73]
wire _issue_entry_T_265 = _issue_entry_T_264 | _issue_entry_T_258; // @[Mux.scala:30:73]
wire _issue_entry_T_266 = _issue_entry_T_265 | _issue_entry_T_259; // @[Mux.scala:30:73]
wire _issue_entry_T_267 = _issue_entry_T_266 | _issue_entry_T_260; // @[Mux.scala:30:73]
wire _issue_entry_T_268 = _issue_entry_T_267 | _issue_entry_T_261; // @[Mux.scala:30:73]
wire _issue_entry_T_269 = _issue_entry_T_268 | _issue_entry_T_262; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_20 = _issue_entry_T_269; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_12 = _issue_entry_WIRE_20; // @[Mux.scala:30:73]
wire _issue_entry_T_270 = issue_sel_0 & entries_ld_0_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_271 = issue_sel_1 & entries_ld_1_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_272 = issue_sel_2 & entries_ld_2_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_273 = issue_sel_3 & entries_ld_3_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_274 = issue_sel_4 & entries_ld_4_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_275 = issue_sel_5 & entries_ld_5_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_276 = issue_sel_6 & entries_ld_6_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_277 = issue_sel_7 & entries_ld_7_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_278 = _issue_entry_T_270 | _issue_entry_T_271; // @[Mux.scala:30:73]
wire _issue_entry_T_279 = _issue_entry_T_278 | _issue_entry_T_272; // @[Mux.scala:30:73]
wire _issue_entry_T_280 = _issue_entry_T_279 | _issue_entry_T_273; // @[Mux.scala:30:73]
wire _issue_entry_T_281 = _issue_entry_T_280 | _issue_entry_T_274; // @[Mux.scala:30:73]
wire _issue_entry_T_282 = _issue_entry_T_281 | _issue_entry_T_275; // @[Mux.scala:30:73]
wire _issue_entry_T_283 = _issue_entry_T_282 | _issue_entry_T_276; // @[Mux.scala:30:73]
wire _issue_entry_T_284 = _issue_entry_T_283 | _issue_entry_T_277; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_21 = _issue_entry_T_284; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_13 = _issue_entry_WIRE_21; // @[Mux.scala:30:73]
wire _issue_entry_T_285 = issue_sel_0 & entries_ld_0_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_286 = issue_sel_1 & entries_ld_1_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_287 = issue_sel_2 & entries_ld_2_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_288 = issue_sel_3 & entries_ld_3_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_289 = issue_sel_4 & entries_ld_4_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_290 = issue_sel_5 & entries_ld_5_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_291 = issue_sel_6 & entries_ld_6_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_292 = issue_sel_7 & entries_ld_7_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_293 = _issue_entry_T_285 | _issue_entry_T_286; // @[Mux.scala:30:73]
wire _issue_entry_T_294 = _issue_entry_T_293 | _issue_entry_T_287; // @[Mux.scala:30:73]
wire _issue_entry_T_295 = _issue_entry_T_294 | _issue_entry_T_288; // @[Mux.scala:30:73]
wire _issue_entry_T_296 = _issue_entry_T_295 | _issue_entry_T_289; // @[Mux.scala:30:73]
wire _issue_entry_T_297 = _issue_entry_T_296 | _issue_entry_T_290; // @[Mux.scala:30:73]
wire _issue_entry_T_298 = _issue_entry_T_297 | _issue_entry_T_291; // @[Mux.scala:30:73]
wire _issue_entry_T_299 = _issue_entry_T_298 | _issue_entry_T_292; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_22 = _issue_entry_T_299; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_14 = _issue_entry_WIRE_22; // @[Mux.scala:30:73]
wire _issue_entry_T_300 = issue_sel_0 & entries_ld_0_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_301 = issue_sel_1 & entries_ld_1_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_302 = issue_sel_2 & entries_ld_2_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_303 = issue_sel_3 & entries_ld_3_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_304 = issue_sel_4 & entries_ld_4_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_305 = issue_sel_5 & entries_ld_5_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_306 = issue_sel_6 & entries_ld_6_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_307 = issue_sel_7 & entries_ld_7_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_308 = _issue_entry_T_300 | _issue_entry_T_301; // @[Mux.scala:30:73]
wire _issue_entry_T_309 = _issue_entry_T_308 | _issue_entry_T_302; // @[Mux.scala:30:73]
wire _issue_entry_T_310 = _issue_entry_T_309 | _issue_entry_T_303; // @[Mux.scala:30:73]
wire _issue_entry_T_311 = _issue_entry_T_310 | _issue_entry_T_304; // @[Mux.scala:30:73]
wire _issue_entry_T_312 = _issue_entry_T_311 | _issue_entry_T_305; // @[Mux.scala:30:73]
wire _issue_entry_T_313 = _issue_entry_T_312 | _issue_entry_T_306; // @[Mux.scala:30:73]
wire _issue_entry_T_314 = _issue_entry_T_313 | _issue_entry_T_307; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_23 = _issue_entry_T_314; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_7_15 = _issue_entry_WIRE_23; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_25; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_0 = _issue_entry_WIRE_24_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_26; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_1 = _issue_entry_WIRE_24_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_27; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_2 = _issue_entry_WIRE_24_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_28; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_3 = _issue_entry_WIRE_24_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_29; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_4 = _issue_entry_WIRE_24_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_30; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_5 = _issue_entry_WIRE_24_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_31; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_6 = _issue_entry_WIRE_24_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_32; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_deps_ld_7 = _issue_entry_WIRE_24_7; // @[Mux.scala:30:73]
wire _issue_entry_T_315 = issue_sel_0 & entries_ld_0_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_316 = issue_sel_1 & entries_ld_1_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_317 = issue_sel_2 & entries_ld_2_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_318 = issue_sel_3 & entries_ld_3_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_319 = issue_sel_4 & entries_ld_4_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_320 = issue_sel_5 & entries_ld_5_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_321 = issue_sel_6 & entries_ld_6_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_322 = issue_sel_7 & entries_ld_7_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_323 = _issue_entry_T_315 | _issue_entry_T_316; // @[Mux.scala:30:73]
wire _issue_entry_T_324 = _issue_entry_T_323 | _issue_entry_T_317; // @[Mux.scala:30:73]
wire _issue_entry_T_325 = _issue_entry_T_324 | _issue_entry_T_318; // @[Mux.scala:30:73]
wire _issue_entry_T_326 = _issue_entry_T_325 | _issue_entry_T_319; // @[Mux.scala:30:73]
wire _issue_entry_T_327 = _issue_entry_T_326 | _issue_entry_T_320; // @[Mux.scala:30:73]
wire _issue_entry_T_328 = _issue_entry_T_327 | _issue_entry_T_321; // @[Mux.scala:30:73]
wire _issue_entry_T_329 = _issue_entry_T_328 | _issue_entry_T_322; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_25 = _issue_entry_T_329; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_0 = _issue_entry_WIRE_25; // @[Mux.scala:30:73]
wire _issue_entry_T_330 = issue_sel_0 & entries_ld_0_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_331 = issue_sel_1 & entries_ld_1_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_332 = issue_sel_2 & entries_ld_2_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_333 = issue_sel_3 & entries_ld_3_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_334 = issue_sel_4 & entries_ld_4_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_335 = issue_sel_5 & entries_ld_5_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_336 = issue_sel_6 & entries_ld_6_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_337 = issue_sel_7 & entries_ld_7_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_338 = _issue_entry_T_330 | _issue_entry_T_331; // @[Mux.scala:30:73]
wire _issue_entry_T_339 = _issue_entry_T_338 | _issue_entry_T_332; // @[Mux.scala:30:73]
wire _issue_entry_T_340 = _issue_entry_T_339 | _issue_entry_T_333; // @[Mux.scala:30:73]
wire _issue_entry_T_341 = _issue_entry_T_340 | _issue_entry_T_334; // @[Mux.scala:30:73]
wire _issue_entry_T_342 = _issue_entry_T_341 | _issue_entry_T_335; // @[Mux.scala:30:73]
wire _issue_entry_T_343 = _issue_entry_T_342 | _issue_entry_T_336; // @[Mux.scala:30:73]
wire _issue_entry_T_344 = _issue_entry_T_343 | _issue_entry_T_337; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_26 = _issue_entry_T_344; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_1 = _issue_entry_WIRE_26; // @[Mux.scala:30:73]
wire _issue_entry_T_345 = issue_sel_0 & entries_ld_0_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_346 = issue_sel_1 & entries_ld_1_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_347 = issue_sel_2 & entries_ld_2_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_348 = issue_sel_3 & entries_ld_3_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_349 = issue_sel_4 & entries_ld_4_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_350 = issue_sel_5 & entries_ld_5_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_351 = issue_sel_6 & entries_ld_6_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_352 = issue_sel_7 & entries_ld_7_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_353 = _issue_entry_T_345 | _issue_entry_T_346; // @[Mux.scala:30:73]
wire _issue_entry_T_354 = _issue_entry_T_353 | _issue_entry_T_347; // @[Mux.scala:30:73]
wire _issue_entry_T_355 = _issue_entry_T_354 | _issue_entry_T_348; // @[Mux.scala:30:73]
wire _issue_entry_T_356 = _issue_entry_T_355 | _issue_entry_T_349; // @[Mux.scala:30:73]
wire _issue_entry_T_357 = _issue_entry_T_356 | _issue_entry_T_350; // @[Mux.scala:30:73]
wire _issue_entry_T_358 = _issue_entry_T_357 | _issue_entry_T_351; // @[Mux.scala:30:73]
wire _issue_entry_T_359 = _issue_entry_T_358 | _issue_entry_T_352; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_27 = _issue_entry_T_359; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_2 = _issue_entry_WIRE_27; // @[Mux.scala:30:73]
wire _issue_entry_T_360 = issue_sel_0 & entries_ld_0_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_361 = issue_sel_1 & entries_ld_1_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_362 = issue_sel_2 & entries_ld_2_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_363 = issue_sel_3 & entries_ld_3_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_364 = issue_sel_4 & entries_ld_4_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_365 = issue_sel_5 & entries_ld_5_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_366 = issue_sel_6 & entries_ld_6_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_367 = issue_sel_7 & entries_ld_7_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_368 = _issue_entry_T_360 | _issue_entry_T_361; // @[Mux.scala:30:73]
wire _issue_entry_T_369 = _issue_entry_T_368 | _issue_entry_T_362; // @[Mux.scala:30:73]
wire _issue_entry_T_370 = _issue_entry_T_369 | _issue_entry_T_363; // @[Mux.scala:30:73]
wire _issue_entry_T_371 = _issue_entry_T_370 | _issue_entry_T_364; // @[Mux.scala:30:73]
wire _issue_entry_T_372 = _issue_entry_T_371 | _issue_entry_T_365; // @[Mux.scala:30:73]
wire _issue_entry_T_373 = _issue_entry_T_372 | _issue_entry_T_366; // @[Mux.scala:30:73]
wire _issue_entry_T_374 = _issue_entry_T_373 | _issue_entry_T_367; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_28 = _issue_entry_T_374; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_3 = _issue_entry_WIRE_28; // @[Mux.scala:30:73]
wire _issue_entry_T_375 = issue_sel_0 & entries_ld_0_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_376 = issue_sel_1 & entries_ld_1_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_377 = issue_sel_2 & entries_ld_2_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_378 = issue_sel_3 & entries_ld_3_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_379 = issue_sel_4 & entries_ld_4_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_380 = issue_sel_5 & entries_ld_5_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_381 = issue_sel_6 & entries_ld_6_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_382 = issue_sel_7 & entries_ld_7_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_383 = _issue_entry_T_375 | _issue_entry_T_376; // @[Mux.scala:30:73]
wire _issue_entry_T_384 = _issue_entry_T_383 | _issue_entry_T_377; // @[Mux.scala:30:73]
wire _issue_entry_T_385 = _issue_entry_T_384 | _issue_entry_T_378; // @[Mux.scala:30:73]
wire _issue_entry_T_386 = _issue_entry_T_385 | _issue_entry_T_379; // @[Mux.scala:30:73]
wire _issue_entry_T_387 = _issue_entry_T_386 | _issue_entry_T_380; // @[Mux.scala:30:73]
wire _issue_entry_T_388 = _issue_entry_T_387 | _issue_entry_T_381; // @[Mux.scala:30:73]
wire _issue_entry_T_389 = _issue_entry_T_388 | _issue_entry_T_382; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_29 = _issue_entry_T_389; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_4 = _issue_entry_WIRE_29; // @[Mux.scala:30:73]
wire _issue_entry_T_390 = issue_sel_0 & entries_ld_0_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_391 = issue_sel_1 & entries_ld_1_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_392 = issue_sel_2 & entries_ld_2_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_393 = issue_sel_3 & entries_ld_3_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_394 = issue_sel_4 & entries_ld_4_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_395 = issue_sel_5 & entries_ld_5_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_396 = issue_sel_6 & entries_ld_6_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_397 = issue_sel_7 & entries_ld_7_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_398 = _issue_entry_T_390 | _issue_entry_T_391; // @[Mux.scala:30:73]
wire _issue_entry_T_399 = _issue_entry_T_398 | _issue_entry_T_392; // @[Mux.scala:30:73]
wire _issue_entry_T_400 = _issue_entry_T_399 | _issue_entry_T_393; // @[Mux.scala:30:73]
wire _issue_entry_T_401 = _issue_entry_T_400 | _issue_entry_T_394; // @[Mux.scala:30:73]
wire _issue_entry_T_402 = _issue_entry_T_401 | _issue_entry_T_395; // @[Mux.scala:30:73]
wire _issue_entry_T_403 = _issue_entry_T_402 | _issue_entry_T_396; // @[Mux.scala:30:73]
wire _issue_entry_T_404 = _issue_entry_T_403 | _issue_entry_T_397; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_30 = _issue_entry_T_404; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_5 = _issue_entry_WIRE_30; // @[Mux.scala:30:73]
wire _issue_entry_T_405 = issue_sel_0 & entries_ld_0_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_406 = issue_sel_1 & entries_ld_1_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_407 = issue_sel_2 & entries_ld_2_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_408 = issue_sel_3 & entries_ld_3_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_409 = issue_sel_4 & entries_ld_4_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_410 = issue_sel_5 & entries_ld_5_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_411 = issue_sel_6 & entries_ld_6_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_412 = issue_sel_7 & entries_ld_7_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_413 = _issue_entry_T_405 | _issue_entry_T_406; // @[Mux.scala:30:73]
wire _issue_entry_T_414 = _issue_entry_T_413 | _issue_entry_T_407; // @[Mux.scala:30:73]
wire _issue_entry_T_415 = _issue_entry_T_414 | _issue_entry_T_408; // @[Mux.scala:30:73]
wire _issue_entry_T_416 = _issue_entry_T_415 | _issue_entry_T_409; // @[Mux.scala:30:73]
wire _issue_entry_T_417 = _issue_entry_T_416 | _issue_entry_T_410; // @[Mux.scala:30:73]
wire _issue_entry_T_418 = _issue_entry_T_417 | _issue_entry_T_411; // @[Mux.scala:30:73]
wire _issue_entry_T_419 = _issue_entry_T_418 | _issue_entry_T_412; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_31 = _issue_entry_T_419; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_6 = _issue_entry_WIRE_31; // @[Mux.scala:30:73]
wire _issue_entry_T_420 = issue_sel_0 & entries_ld_0_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_421 = issue_sel_1 & entries_ld_1_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_422 = issue_sel_2 & entries_ld_2_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_423 = issue_sel_3 & entries_ld_3_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_424 = issue_sel_4 & entries_ld_4_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_425 = issue_sel_5 & entries_ld_5_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_426 = issue_sel_6 & entries_ld_6_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_427 = issue_sel_7 & entries_ld_7_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_428 = _issue_entry_T_420 | _issue_entry_T_421; // @[Mux.scala:30:73]
wire _issue_entry_T_429 = _issue_entry_T_428 | _issue_entry_T_422; // @[Mux.scala:30:73]
wire _issue_entry_T_430 = _issue_entry_T_429 | _issue_entry_T_423; // @[Mux.scala:30:73]
wire _issue_entry_T_431 = _issue_entry_T_430 | _issue_entry_T_424; // @[Mux.scala:30:73]
wire _issue_entry_T_432 = _issue_entry_T_431 | _issue_entry_T_425; // @[Mux.scala:30:73]
wire _issue_entry_T_433 = _issue_entry_T_432 | _issue_entry_T_426; // @[Mux.scala:30:73]
wire _issue_entry_T_434 = _issue_entry_T_433 | _issue_entry_T_427; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_32 = _issue_entry_T_434; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_24_7 = _issue_entry_WIRE_32; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_39_inst_funct; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_funct = _issue_entry_WIRE_33_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_39_inst_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_rs2 = _issue_entry_WIRE_33_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_39_inst_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_rs1 = _issue_entry_WIRE_33_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_inst_xd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_xd = _issue_entry_WIRE_33_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_inst_xs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_xs1 = _issue_entry_WIRE_33_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_inst_xs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_xs2 = _issue_entry_WIRE_33_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_39_inst_rd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_rd = _issue_entry_WIRE_33_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_39_inst_opcode; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_inst_opcode = _issue_entry_WIRE_33_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_39_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_rs1 = _issue_entry_WIRE_33_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_39_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_rs2 = _issue_entry_WIRE_33_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_debug; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_debug = _issue_entry_WIRE_33_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_cease; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_cease = _issue_entry_WIRE_33_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_wfi; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_wfi = _issue_entry_WIRE_33_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_39_status_isa; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_isa = _issue_entry_WIRE_33_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_dprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_dprv = _issue_entry_WIRE_33_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_dv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_dv = _issue_entry_WIRE_33_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_prv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_prv = _issue_entry_WIRE_33_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_v; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_v = _issue_entry_WIRE_33_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_sd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_sd = _issue_entry_WIRE_33_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_39_status_zero2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_zero2 = _issue_entry_WIRE_33_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_mpv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_mpv = _issue_entry_WIRE_33_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_gva; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_gva = _issue_entry_WIRE_33_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_mbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_mbe = _issue_entry_WIRE_33_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_sbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_sbe = _issue_entry_WIRE_33_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_sxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_sxl = _issue_entry_WIRE_33_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_uxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_uxl = _issue_entry_WIRE_33_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_sd_rv32; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_33_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_39_status_zero1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_zero1 = _issue_entry_WIRE_33_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_tsr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_tsr = _issue_entry_WIRE_33_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_tw; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_tw = _issue_entry_WIRE_33_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_tvm; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_tvm = _issue_entry_WIRE_33_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_mxr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_mxr = _issue_entry_WIRE_33_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_sum; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_sum = _issue_entry_WIRE_33_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_mprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_mprv = _issue_entry_WIRE_33_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_xs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_xs = _issue_entry_WIRE_33_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_fs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_fs = _issue_entry_WIRE_33_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_mpp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_mpp = _issue_entry_WIRE_33_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_39_status_vs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_vs = _issue_entry_WIRE_33_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_spp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_spp = _issue_entry_WIRE_33_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_mpie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_mpie = _issue_entry_WIRE_33_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_ube; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_ube = _issue_entry_WIRE_33_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_spie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_spie = _issue_entry_WIRE_33_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_upie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_upie = _issue_entry_WIRE_33_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_mie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_mie = _issue_entry_WIRE_33_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_hie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_hie = _issue_entry_WIRE_33_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_sie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_sie = _issue_entry_WIRE_33_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_39_status_uie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_cmd_status_uie = _issue_entry_WIRE_33_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_36_valid; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_rob_id_valid = _issue_entry_WIRE_33_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_36_bits; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_rob_id_bits = _issue_entry_WIRE_33_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_35; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_from_matmul_fsm = _issue_entry_WIRE_33_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_34; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_cmd_from_conv_fsm = _issue_entry_WIRE_33_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_T_435 = issue_sel_0 & entries_ld_0_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_436 = issue_sel_1 & entries_ld_1_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_437 = issue_sel_2 & entries_ld_2_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_438 = issue_sel_3 & entries_ld_3_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_439 = issue_sel_4 & entries_ld_4_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_440 = issue_sel_5 & entries_ld_5_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_441 = issue_sel_6 & entries_ld_6_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_442 = issue_sel_7 & entries_ld_7_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_443 = _issue_entry_T_435 | _issue_entry_T_436; // @[Mux.scala:30:73]
wire _issue_entry_T_444 = _issue_entry_T_443 | _issue_entry_T_437; // @[Mux.scala:30:73]
wire _issue_entry_T_445 = _issue_entry_T_444 | _issue_entry_T_438; // @[Mux.scala:30:73]
wire _issue_entry_T_446 = _issue_entry_T_445 | _issue_entry_T_439; // @[Mux.scala:30:73]
wire _issue_entry_T_447 = _issue_entry_T_446 | _issue_entry_T_440; // @[Mux.scala:30:73]
wire _issue_entry_T_448 = _issue_entry_T_447 | _issue_entry_T_441; // @[Mux.scala:30:73]
wire _issue_entry_T_449 = _issue_entry_T_448 | _issue_entry_T_442; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_34 = _issue_entry_T_449; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_from_conv_fsm = _issue_entry_WIRE_34; // @[Mux.scala:30:73]
wire _issue_entry_T_450 = issue_sel_0 & entries_ld_0_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_451 = issue_sel_1 & entries_ld_1_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_452 = issue_sel_2 & entries_ld_2_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_453 = issue_sel_3 & entries_ld_3_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_454 = issue_sel_4 & entries_ld_4_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_455 = issue_sel_5 & entries_ld_5_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_456 = issue_sel_6 & entries_ld_6_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_457 = issue_sel_7 & entries_ld_7_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_458 = _issue_entry_T_450 | _issue_entry_T_451; // @[Mux.scala:30:73]
wire _issue_entry_T_459 = _issue_entry_T_458 | _issue_entry_T_452; // @[Mux.scala:30:73]
wire _issue_entry_T_460 = _issue_entry_T_459 | _issue_entry_T_453; // @[Mux.scala:30:73]
wire _issue_entry_T_461 = _issue_entry_T_460 | _issue_entry_T_454; // @[Mux.scala:30:73]
wire _issue_entry_T_462 = _issue_entry_T_461 | _issue_entry_T_455; // @[Mux.scala:30:73]
wire _issue_entry_T_463 = _issue_entry_T_462 | _issue_entry_T_456; // @[Mux.scala:30:73]
wire _issue_entry_T_464 = _issue_entry_T_463 | _issue_entry_T_457; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_35 = _issue_entry_T_464; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_from_matmul_fsm = _issue_entry_WIRE_35; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_38; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_rob_id_valid = _issue_entry_WIRE_36_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_37; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_rob_id_bits = _issue_entry_WIRE_36_bits; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_465 = issue_sel_0 ? entries_ld_0_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_466 = issue_sel_1 ? entries_ld_1_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_467 = issue_sel_2 ? entries_ld_2_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_468 = issue_sel_3 ? entries_ld_3_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_469 = issue_sel_4 ? entries_ld_4_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_470 = issue_sel_5 ? entries_ld_5_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_471 = issue_sel_6 ? entries_ld_6_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_472 = issue_sel_7 ? entries_ld_7_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_473 = _issue_entry_T_465 | _issue_entry_T_466; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_474 = _issue_entry_T_473 | _issue_entry_T_467; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_475 = _issue_entry_T_474 | _issue_entry_T_468; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_476 = _issue_entry_T_475 | _issue_entry_T_469; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_477 = _issue_entry_T_476 | _issue_entry_T_470; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_478 = _issue_entry_T_477 | _issue_entry_T_471; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_479 = _issue_entry_T_478 | _issue_entry_T_472; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_37 = _issue_entry_T_479; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_36_bits = _issue_entry_WIRE_37; // @[Mux.scala:30:73]
wire _issue_entry_T_480 = issue_sel_0 & entries_ld_0_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_481 = issue_sel_1 & entries_ld_1_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_482 = issue_sel_2 & entries_ld_2_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_483 = issue_sel_3 & entries_ld_3_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_484 = issue_sel_4 & entries_ld_4_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_485 = issue_sel_5 & entries_ld_5_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_486 = issue_sel_6 & entries_ld_6_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_487 = issue_sel_7 & entries_ld_7_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_488 = _issue_entry_T_480 | _issue_entry_T_481; // @[Mux.scala:30:73]
wire _issue_entry_T_489 = _issue_entry_T_488 | _issue_entry_T_482; // @[Mux.scala:30:73]
wire _issue_entry_T_490 = _issue_entry_T_489 | _issue_entry_T_483; // @[Mux.scala:30:73]
wire _issue_entry_T_491 = _issue_entry_T_490 | _issue_entry_T_484; // @[Mux.scala:30:73]
wire _issue_entry_T_492 = _issue_entry_T_491 | _issue_entry_T_485; // @[Mux.scala:30:73]
wire _issue_entry_T_493 = _issue_entry_T_492 | _issue_entry_T_486; // @[Mux.scala:30:73]
wire _issue_entry_T_494 = _issue_entry_T_493 | _issue_entry_T_487; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_38 = _issue_entry_T_494; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_36_valid = _issue_entry_WIRE_38; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_80_funct; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_funct = _issue_entry_WIRE_39_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_80_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_rs2 = _issue_entry_WIRE_39_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_80_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_rs1 = _issue_entry_WIRE_39_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_80_xd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_xd = _issue_entry_WIRE_39_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_80_xs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_xs1 = _issue_entry_WIRE_39_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_80_xs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_xs2 = _issue_entry_WIRE_39_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_80_rd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_rd = _issue_entry_WIRE_39_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_80_opcode; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_inst_opcode = _issue_entry_WIRE_39_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_79; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_rs1 = _issue_entry_WIRE_39_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_78; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_rs2 = _issue_entry_WIRE_39_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_debug; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_debug = _issue_entry_WIRE_39_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_cease; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_cease = _issue_entry_WIRE_39_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_wfi; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_wfi = _issue_entry_WIRE_39_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_40_isa; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_isa = _issue_entry_WIRE_39_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_dprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_dprv = _issue_entry_WIRE_39_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_dv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_dv = _issue_entry_WIRE_39_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_prv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_prv = _issue_entry_WIRE_39_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_v; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_v = _issue_entry_WIRE_39_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_sd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_sd = _issue_entry_WIRE_39_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_40_zero2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_zero2 = _issue_entry_WIRE_39_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_mpv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_mpv = _issue_entry_WIRE_39_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_gva; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_gva = _issue_entry_WIRE_39_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_mbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_mbe = _issue_entry_WIRE_39_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_sbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_sbe = _issue_entry_WIRE_39_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_sxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_sxl = _issue_entry_WIRE_39_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_uxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_uxl = _issue_entry_WIRE_39_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_sd_rv32; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_sd_rv32 = _issue_entry_WIRE_39_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_40_zero1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_zero1 = _issue_entry_WIRE_39_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_tsr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_tsr = _issue_entry_WIRE_39_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_tw; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_tw = _issue_entry_WIRE_39_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_tvm; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_tvm = _issue_entry_WIRE_39_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_mxr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_mxr = _issue_entry_WIRE_39_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_sum; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_sum = _issue_entry_WIRE_39_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_mprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_mprv = _issue_entry_WIRE_39_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_xs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_xs = _issue_entry_WIRE_39_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_fs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_fs = _issue_entry_WIRE_39_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_mpp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_mpp = _issue_entry_WIRE_39_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_40_vs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_vs = _issue_entry_WIRE_39_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_spp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_spp = _issue_entry_WIRE_39_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_mpie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_mpie = _issue_entry_WIRE_39_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_ube; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_ube = _issue_entry_WIRE_39_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_spie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_spie = _issue_entry_WIRE_39_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_upie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_upie = _issue_entry_WIRE_39_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_mie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_mie = _issue_entry_WIRE_39_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_hie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_hie = _issue_entry_WIRE_39_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_sie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_sie = _issue_entry_WIRE_39_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_40_uie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_33_cmd_status_uie = _issue_entry_WIRE_39_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_77; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_debug = _issue_entry_WIRE_40_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_76; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_cease = _issue_entry_WIRE_40_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_75; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_wfi = _issue_entry_WIRE_40_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_74; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_isa = _issue_entry_WIRE_40_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_73; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_dprv = _issue_entry_WIRE_40_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_72; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_dv = _issue_entry_WIRE_40_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_71; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_prv = _issue_entry_WIRE_40_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_70; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_v = _issue_entry_WIRE_40_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_69; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_sd = _issue_entry_WIRE_40_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_68; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_zero2 = _issue_entry_WIRE_40_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_67; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_mpv = _issue_entry_WIRE_40_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_66; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_gva = _issue_entry_WIRE_40_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_65; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_mbe = _issue_entry_WIRE_40_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_64; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_sbe = _issue_entry_WIRE_40_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_63; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_sxl = _issue_entry_WIRE_40_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_62; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_uxl = _issue_entry_WIRE_40_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_61; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_sd_rv32 = _issue_entry_WIRE_40_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_60; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_zero1 = _issue_entry_WIRE_40_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_59; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_tsr = _issue_entry_WIRE_40_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_58; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_tw = _issue_entry_WIRE_40_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_57; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_tvm = _issue_entry_WIRE_40_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_56; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_mxr = _issue_entry_WIRE_40_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_55; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_sum = _issue_entry_WIRE_40_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_54; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_mprv = _issue_entry_WIRE_40_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_53; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_xs = _issue_entry_WIRE_40_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_52; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_fs = _issue_entry_WIRE_40_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_51; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_mpp = _issue_entry_WIRE_40_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_50; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_vs = _issue_entry_WIRE_40_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_49; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_spp = _issue_entry_WIRE_40_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_48; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_mpie = _issue_entry_WIRE_40_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_47; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_ube = _issue_entry_WIRE_40_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_46; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_spie = _issue_entry_WIRE_40_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_45; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_upie = _issue_entry_WIRE_40_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_44; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_mie = _issue_entry_WIRE_40_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_43; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_hie = _issue_entry_WIRE_40_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_42; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_sie = _issue_entry_WIRE_40_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_41; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_status_uie = _issue_entry_WIRE_40_uie; // @[Mux.scala:30:73]
wire _issue_entry_T_495 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_496 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_497 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_498 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_499 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_500 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_501 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_502 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_503 = _issue_entry_T_495 | _issue_entry_T_496; // @[Mux.scala:30:73]
wire _issue_entry_T_504 = _issue_entry_T_503 | _issue_entry_T_497; // @[Mux.scala:30:73]
wire _issue_entry_T_505 = _issue_entry_T_504 | _issue_entry_T_498; // @[Mux.scala:30:73]
wire _issue_entry_T_506 = _issue_entry_T_505 | _issue_entry_T_499; // @[Mux.scala:30:73]
wire _issue_entry_T_507 = _issue_entry_T_506 | _issue_entry_T_500; // @[Mux.scala:30:73]
wire _issue_entry_T_508 = _issue_entry_T_507 | _issue_entry_T_501; // @[Mux.scala:30:73]
wire _issue_entry_T_509 = _issue_entry_T_508 | _issue_entry_T_502; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_41 = _issue_entry_T_509; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_uie = _issue_entry_WIRE_41; // @[Mux.scala:30:73]
wire _issue_entry_T_510 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_511 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_512 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_513 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_514 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_515 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_516 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_517 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_518 = _issue_entry_T_510 | _issue_entry_T_511; // @[Mux.scala:30:73]
wire _issue_entry_T_519 = _issue_entry_T_518 | _issue_entry_T_512; // @[Mux.scala:30:73]
wire _issue_entry_T_520 = _issue_entry_T_519 | _issue_entry_T_513; // @[Mux.scala:30:73]
wire _issue_entry_T_521 = _issue_entry_T_520 | _issue_entry_T_514; // @[Mux.scala:30:73]
wire _issue_entry_T_522 = _issue_entry_T_521 | _issue_entry_T_515; // @[Mux.scala:30:73]
wire _issue_entry_T_523 = _issue_entry_T_522 | _issue_entry_T_516; // @[Mux.scala:30:73]
wire _issue_entry_T_524 = _issue_entry_T_523 | _issue_entry_T_517; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_42 = _issue_entry_T_524; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_sie = _issue_entry_WIRE_42; // @[Mux.scala:30:73]
wire _issue_entry_T_525 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_526 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_527 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_528 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_529 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_530 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_531 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_532 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_533 = _issue_entry_T_525 | _issue_entry_T_526; // @[Mux.scala:30:73]
wire _issue_entry_T_534 = _issue_entry_T_533 | _issue_entry_T_527; // @[Mux.scala:30:73]
wire _issue_entry_T_535 = _issue_entry_T_534 | _issue_entry_T_528; // @[Mux.scala:30:73]
wire _issue_entry_T_536 = _issue_entry_T_535 | _issue_entry_T_529; // @[Mux.scala:30:73]
wire _issue_entry_T_537 = _issue_entry_T_536 | _issue_entry_T_530; // @[Mux.scala:30:73]
wire _issue_entry_T_538 = _issue_entry_T_537 | _issue_entry_T_531; // @[Mux.scala:30:73]
wire _issue_entry_T_539 = _issue_entry_T_538 | _issue_entry_T_532; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_43 = _issue_entry_T_539; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_hie = _issue_entry_WIRE_43; // @[Mux.scala:30:73]
wire _issue_entry_T_540 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_541 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_542 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_543 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_544 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_545 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_546 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_547 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_548 = _issue_entry_T_540 | _issue_entry_T_541; // @[Mux.scala:30:73]
wire _issue_entry_T_549 = _issue_entry_T_548 | _issue_entry_T_542; // @[Mux.scala:30:73]
wire _issue_entry_T_550 = _issue_entry_T_549 | _issue_entry_T_543; // @[Mux.scala:30:73]
wire _issue_entry_T_551 = _issue_entry_T_550 | _issue_entry_T_544; // @[Mux.scala:30:73]
wire _issue_entry_T_552 = _issue_entry_T_551 | _issue_entry_T_545; // @[Mux.scala:30:73]
wire _issue_entry_T_553 = _issue_entry_T_552 | _issue_entry_T_546; // @[Mux.scala:30:73]
wire _issue_entry_T_554 = _issue_entry_T_553 | _issue_entry_T_547; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_44 = _issue_entry_T_554; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_mie = _issue_entry_WIRE_44; // @[Mux.scala:30:73]
wire _issue_entry_T_555 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_556 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_557 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_558 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_559 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_560 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_561 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_562 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_563 = _issue_entry_T_555 | _issue_entry_T_556; // @[Mux.scala:30:73]
wire _issue_entry_T_564 = _issue_entry_T_563 | _issue_entry_T_557; // @[Mux.scala:30:73]
wire _issue_entry_T_565 = _issue_entry_T_564 | _issue_entry_T_558; // @[Mux.scala:30:73]
wire _issue_entry_T_566 = _issue_entry_T_565 | _issue_entry_T_559; // @[Mux.scala:30:73]
wire _issue_entry_T_567 = _issue_entry_T_566 | _issue_entry_T_560; // @[Mux.scala:30:73]
wire _issue_entry_T_568 = _issue_entry_T_567 | _issue_entry_T_561; // @[Mux.scala:30:73]
wire _issue_entry_T_569 = _issue_entry_T_568 | _issue_entry_T_562; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_45 = _issue_entry_T_569; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_upie = _issue_entry_WIRE_45; // @[Mux.scala:30:73]
wire _issue_entry_T_570 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_571 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_572 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_573 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_574 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_575 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_576 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_577 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_578 = _issue_entry_T_570 | _issue_entry_T_571; // @[Mux.scala:30:73]
wire _issue_entry_T_579 = _issue_entry_T_578 | _issue_entry_T_572; // @[Mux.scala:30:73]
wire _issue_entry_T_580 = _issue_entry_T_579 | _issue_entry_T_573; // @[Mux.scala:30:73]
wire _issue_entry_T_581 = _issue_entry_T_580 | _issue_entry_T_574; // @[Mux.scala:30:73]
wire _issue_entry_T_582 = _issue_entry_T_581 | _issue_entry_T_575; // @[Mux.scala:30:73]
wire _issue_entry_T_583 = _issue_entry_T_582 | _issue_entry_T_576; // @[Mux.scala:30:73]
wire _issue_entry_T_584 = _issue_entry_T_583 | _issue_entry_T_577; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_46 = _issue_entry_T_584; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_spie = _issue_entry_WIRE_46; // @[Mux.scala:30:73]
wire _issue_entry_T_585 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_586 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_587 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_588 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_589 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_590 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_591 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_592 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_593 = _issue_entry_T_585 | _issue_entry_T_586; // @[Mux.scala:30:73]
wire _issue_entry_T_594 = _issue_entry_T_593 | _issue_entry_T_587; // @[Mux.scala:30:73]
wire _issue_entry_T_595 = _issue_entry_T_594 | _issue_entry_T_588; // @[Mux.scala:30:73]
wire _issue_entry_T_596 = _issue_entry_T_595 | _issue_entry_T_589; // @[Mux.scala:30:73]
wire _issue_entry_T_597 = _issue_entry_T_596 | _issue_entry_T_590; // @[Mux.scala:30:73]
wire _issue_entry_T_598 = _issue_entry_T_597 | _issue_entry_T_591; // @[Mux.scala:30:73]
wire _issue_entry_T_599 = _issue_entry_T_598 | _issue_entry_T_592; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_47 = _issue_entry_T_599; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_ube = _issue_entry_WIRE_47; // @[Mux.scala:30:73]
wire _issue_entry_T_600 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_601 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_602 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_603 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_604 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_605 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_606 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_607 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_608 = _issue_entry_T_600 | _issue_entry_T_601; // @[Mux.scala:30:73]
wire _issue_entry_T_609 = _issue_entry_T_608 | _issue_entry_T_602; // @[Mux.scala:30:73]
wire _issue_entry_T_610 = _issue_entry_T_609 | _issue_entry_T_603; // @[Mux.scala:30:73]
wire _issue_entry_T_611 = _issue_entry_T_610 | _issue_entry_T_604; // @[Mux.scala:30:73]
wire _issue_entry_T_612 = _issue_entry_T_611 | _issue_entry_T_605; // @[Mux.scala:30:73]
wire _issue_entry_T_613 = _issue_entry_T_612 | _issue_entry_T_606; // @[Mux.scala:30:73]
wire _issue_entry_T_614 = _issue_entry_T_613 | _issue_entry_T_607; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_48 = _issue_entry_T_614; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_mpie = _issue_entry_WIRE_48; // @[Mux.scala:30:73]
wire _issue_entry_T_615 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_616 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_617 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_618 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_619 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_620 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_621 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_622 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_623 = _issue_entry_T_615 | _issue_entry_T_616; // @[Mux.scala:30:73]
wire _issue_entry_T_624 = _issue_entry_T_623 | _issue_entry_T_617; // @[Mux.scala:30:73]
wire _issue_entry_T_625 = _issue_entry_T_624 | _issue_entry_T_618; // @[Mux.scala:30:73]
wire _issue_entry_T_626 = _issue_entry_T_625 | _issue_entry_T_619; // @[Mux.scala:30:73]
wire _issue_entry_T_627 = _issue_entry_T_626 | _issue_entry_T_620; // @[Mux.scala:30:73]
wire _issue_entry_T_628 = _issue_entry_T_627 | _issue_entry_T_621; // @[Mux.scala:30:73]
wire _issue_entry_T_629 = _issue_entry_T_628 | _issue_entry_T_622; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_49 = _issue_entry_T_629; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_spp = _issue_entry_WIRE_49; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_630 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_631 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_632 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_633 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_634 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_635 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_636 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_637 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_638 = _issue_entry_T_630 | _issue_entry_T_631; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_639 = _issue_entry_T_638 | _issue_entry_T_632; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_640 = _issue_entry_T_639 | _issue_entry_T_633; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_641 = _issue_entry_T_640 | _issue_entry_T_634; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_642 = _issue_entry_T_641 | _issue_entry_T_635; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_643 = _issue_entry_T_642 | _issue_entry_T_636; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_644 = _issue_entry_T_643 | _issue_entry_T_637; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_50 = _issue_entry_T_644; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_vs = _issue_entry_WIRE_50; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_645 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_646 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_647 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_648 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_649 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_650 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_651 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_652 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_653 = _issue_entry_T_645 | _issue_entry_T_646; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_654 = _issue_entry_T_653 | _issue_entry_T_647; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_655 = _issue_entry_T_654 | _issue_entry_T_648; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_656 = _issue_entry_T_655 | _issue_entry_T_649; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_657 = _issue_entry_T_656 | _issue_entry_T_650; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_658 = _issue_entry_T_657 | _issue_entry_T_651; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_659 = _issue_entry_T_658 | _issue_entry_T_652; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_51 = _issue_entry_T_659; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_mpp = _issue_entry_WIRE_51; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_660 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_661 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_662 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_663 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_664 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_665 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_666 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_667 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_668 = _issue_entry_T_660 | _issue_entry_T_661; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_669 = _issue_entry_T_668 | _issue_entry_T_662; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_670 = _issue_entry_T_669 | _issue_entry_T_663; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_671 = _issue_entry_T_670 | _issue_entry_T_664; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_672 = _issue_entry_T_671 | _issue_entry_T_665; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_673 = _issue_entry_T_672 | _issue_entry_T_666; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_674 = _issue_entry_T_673 | _issue_entry_T_667; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_52 = _issue_entry_T_674; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_fs = _issue_entry_WIRE_52; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_675 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_676 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_677 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_678 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_679 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_680 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_681 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_682 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_683 = _issue_entry_T_675 | _issue_entry_T_676; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_684 = _issue_entry_T_683 | _issue_entry_T_677; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_685 = _issue_entry_T_684 | _issue_entry_T_678; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_686 = _issue_entry_T_685 | _issue_entry_T_679; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_687 = _issue_entry_T_686 | _issue_entry_T_680; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_688 = _issue_entry_T_687 | _issue_entry_T_681; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_689 = _issue_entry_T_688 | _issue_entry_T_682; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_53 = _issue_entry_T_689; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_xs = _issue_entry_WIRE_53; // @[Mux.scala:30:73]
wire _issue_entry_T_690 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_691 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_692 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_693 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_694 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_695 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_696 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_697 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_698 = _issue_entry_T_690 | _issue_entry_T_691; // @[Mux.scala:30:73]
wire _issue_entry_T_699 = _issue_entry_T_698 | _issue_entry_T_692; // @[Mux.scala:30:73]
wire _issue_entry_T_700 = _issue_entry_T_699 | _issue_entry_T_693; // @[Mux.scala:30:73]
wire _issue_entry_T_701 = _issue_entry_T_700 | _issue_entry_T_694; // @[Mux.scala:30:73]
wire _issue_entry_T_702 = _issue_entry_T_701 | _issue_entry_T_695; // @[Mux.scala:30:73]
wire _issue_entry_T_703 = _issue_entry_T_702 | _issue_entry_T_696; // @[Mux.scala:30:73]
wire _issue_entry_T_704 = _issue_entry_T_703 | _issue_entry_T_697; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_54 = _issue_entry_T_704; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_mprv = _issue_entry_WIRE_54; // @[Mux.scala:30:73]
wire _issue_entry_T_705 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_706 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_707 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_708 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_709 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_710 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_711 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_712 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_713 = _issue_entry_T_705 | _issue_entry_T_706; // @[Mux.scala:30:73]
wire _issue_entry_T_714 = _issue_entry_T_713 | _issue_entry_T_707; // @[Mux.scala:30:73]
wire _issue_entry_T_715 = _issue_entry_T_714 | _issue_entry_T_708; // @[Mux.scala:30:73]
wire _issue_entry_T_716 = _issue_entry_T_715 | _issue_entry_T_709; // @[Mux.scala:30:73]
wire _issue_entry_T_717 = _issue_entry_T_716 | _issue_entry_T_710; // @[Mux.scala:30:73]
wire _issue_entry_T_718 = _issue_entry_T_717 | _issue_entry_T_711; // @[Mux.scala:30:73]
wire _issue_entry_T_719 = _issue_entry_T_718 | _issue_entry_T_712; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_55 = _issue_entry_T_719; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_sum = _issue_entry_WIRE_55; // @[Mux.scala:30:73]
wire _issue_entry_T_720 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_721 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_722 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_723 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_724 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_725 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_726 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_727 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_728 = _issue_entry_T_720 | _issue_entry_T_721; // @[Mux.scala:30:73]
wire _issue_entry_T_729 = _issue_entry_T_728 | _issue_entry_T_722; // @[Mux.scala:30:73]
wire _issue_entry_T_730 = _issue_entry_T_729 | _issue_entry_T_723; // @[Mux.scala:30:73]
wire _issue_entry_T_731 = _issue_entry_T_730 | _issue_entry_T_724; // @[Mux.scala:30:73]
wire _issue_entry_T_732 = _issue_entry_T_731 | _issue_entry_T_725; // @[Mux.scala:30:73]
wire _issue_entry_T_733 = _issue_entry_T_732 | _issue_entry_T_726; // @[Mux.scala:30:73]
wire _issue_entry_T_734 = _issue_entry_T_733 | _issue_entry_T_727; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_56 = _issue_entry_T_734; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_mxr = _issue_entry_WIRE_56; // @[Mux.scala:30:73]
wire _issue_entry_T_735 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_736 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_737 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_738 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_739 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_740 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_741 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_742 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_743 = _issue_entry_T_735 | _issue_entry_T_736; // @[Mux.scala:30:73]
wire _issue_entry_T_744 = _issue_entry_T_743 | _issue_entry_T_737; // @[Mux.scala:30:73]
wire _issue_entry_T_745 = _issue_entry_T_744 | _issue_entry_T_738; // @[Mux.scala:30:73]
wire _issue_entry_T_746 = _issue_entry_T_745 | _issue_entry_T_739; // @[Mux.scala:30:73]
wire _issue_entry_T_747 = _issue_entry_T_746 | _issue_entry_T_740; // @[Mux.scala:30:73]
wire _issue_entry_T_748 = _issue_entry_T_747 | _issue_entry_T_741; // @[Mux.scala:30:73]
wire _issue_entry_T_749 = _issue_entry_T_748 | _issue_entry_T_742; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_57 = _issue_entry_T_749; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_tvm = _issue_entry_WIRE_57; // @[Mux.scala:30:73]
wire _issue_entry_T_750 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_751 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_752 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_753 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_754 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_755 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_756 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_757 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_758 = _issue_entry_T_750 | _issue_entry_T_751; // @[Mux.scala:30:73]
wire _issue_entry_T_759 = _issue_entry_T_758 | _issue_entry_T_752; // @[Mux.scala:30:73]
wire _issue_entry_T_760 = _issue_entry_T_759 | _issue_entry_T_753; // @[Mux.scala:30:73]
wire _issue_entry_T_761 = _issue_entry_T_760 | _issue_entry_T_754; // @[Mux.scala:30:73]
wire _issue_entry_T_762 = _issue_entry_T_761 | _issue_entry_T_755; // @[Mux.scala:30:73]
wire _issue_entry_T_763 = _issue_entry_T_762 | _issue_entry_T_756; // @[Mux.scala:30:73]
wire _issue_entry_T_764 = _issue_entry_T_763 | _issue_entry_T_757; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_58 = _issue_entry_T_764; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_tw = _issue_entry_WIRE_58; // @[Mux.scala:30:73]
wire _issue_entry_T_765 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_766 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_767 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_768 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_769 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_770 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_771 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_772 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_773 = _issue_entry_T_765 | _issue_entry_T_766; // @[Mux.scala:30:73]
wire _issue_entry_T_774 = _issue_entry_T_773 | _issue_entry_T_767; // @[Mux.scala:30:73]
wire _issue_entry_T_775 = _issue_entry_T_774 | _issue_entry_T_768; // @[Mux.scala:30:73]
wire _issue_entry_T_776 = _issue_entry_T_775 | _issue_entry_T_769; // @[Mux.scala:30:73]
wire _issue_entry_T_777 = _issue_entry_T_776 | _issue_entry_T_770; // @[Mux.scala:30:73]
wire _issue_entry_T_778 = _issue_entry_T_777 | _issue_entry_T_771; // @[Mux.scala:30:73]
wire _issue_entry_T_779 = _issue_entry_T_778 | _issue_entry_T_772; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_59 = _issue_entry_T_779; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_tsr = _issue_entry_WIRE_59; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_780 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_781 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_782 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_783 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_784 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_785 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_786 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_787 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_788 = _issue_entry_T_780 | _issue_entry_T_781; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_789 = _issue_entry_T_788 | _issue_entry_T_782; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_790 = _issue_entry_T_789 | _issue_entry_T_783; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_791 = _issue_entry_T_790 | _issue_entry_T_784; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_792 = _issue_entry_T_791 | _issue_entry_T_785; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_793 = _issue_entry_T_792 | _issue_entry_T_786; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_794 = _issue_entry_T_793 | _issue_entry_T_787; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_60 = _issue_entry_T_794; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_zero1 = _issue_entry_WIRE_60; // @[Mux.scala:30:73]
wire _issue_entry_T_795 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_796 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_797 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_798 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_799 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_800 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_801 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_802 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_803 = _issue_entry_T_795 | _issue_entry_T_796; // @[Mux.scala:30:73]
wire _issue_entry_T_804 = _issue_entry_T_803 | _issue_entry_T_797; // @[Mux.scala:30:73]
wire _issue_entry_T_805 = _issue_entry_T_804 | _issue_entry_T_798; // @[Mux.scala:30:73]
wire _issue_entry_T_806 = _issue_entry_T_805 | _issue_entry_T_799; // @[Mux.scala:30:73]
wire _issue_entry_T_807 = _issue_entry_T_806 | _issue_entry_T_800; // @[Mux.scala:30:73]
wire _issue_entry_T_808 = _issue_entry_T_807 | _issue_entry_T_801; // @[Mux.scala:30:73]
wire _issue_entry_T_809 = _issue_entry_T_808 | _issue_entry_T_802; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_61 = _issue_entry_T_809; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_sd_rv32 = _issue_entry_WIRE_61; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_810 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_811 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_812 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_813 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_814 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_815 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_816 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_817 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_818 = _issue_entry_T_810 | _issue_entry_T_811; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_819 = _issue_entry_T_818 | _issue_entry_T_812; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_820 = _issue_entry_T_819 | _issue_entry_T_813; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_821 = _issue_entry_T_820 | _issue_entry_T_814; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_822 = _issue_entry_T_821 | _issue_entry_T_815; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_823 = _issue_entry_T_822 | _issue_entry_T_816; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_824 = _issue_entry_T_823 | _issue_entry_T_817; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_62 = _issue_entry_T_824; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_uxl = _issue_entry_WIRE_62; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_825 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_826 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_827 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_828 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_829 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_830 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_831 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_832 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_833 = _issue_entry_T_825 | _issue_entry_T_826; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_834 = _issue_entry_T_833 | _issue_entry_T_827; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_835 = _issue_entry_T_834 | _issue_entry_T_828; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_836 = _issue_entry_T_835 | _issue_entry_T_829; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_837 = _issue_entry_T_836 | _issue_entry_T_830; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_838 = _issue_entry_T_837 | _issue_entry_T_831; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_839 = _issue_entry_T_838 | _issue_entry_T_832; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_63 = _issue_entry_T_839; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_sxl = _issue_entry_WIRE_63; // @[Mux.scala:30:73]
wire _issue_entry_T_840 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_841 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_842 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_843 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_844 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_845 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_846 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_847 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_848 = _issue_entry_T_840 | _issue_entry_T_841; // @[Mux.scala:30:73]
wire _issue_entry_T_849 = _issue_entry_T_848 | _issue_entry_T_842; // @[Mux.scala:30:73]
wire _issue_entry_T_850 = _issue_entry_T_849 | _issue_entry_T_843; // @[Mux.scala:30:73]
wire _issue_entry_T_851 = _issue_entry_T_850 | _issue_entry_T_844; // @[Mux.scala:30:73]
wire _issue_entry_T_852 = _issue_entry_T_851 | _issue_entry_T_845; // @[Mux.scala:30:73]
wire _issue_entry_T_853 = _issue_entry_T_852 | _issue_entry_T_846; // @[Mux.scala:30:73]
wire _issue_entry_T_854 = _issue_entry_T_853 | _issue_entry_T_847; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_64 = _issue_entry_T_854; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_sbe = _issue_entry_WIRE_64; // @[Mux.scala:30:73]
wire _issue_entry_T_855 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_856 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_857 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_858 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_859 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_860 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_861 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_862 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_863 = _issue_entry_T_855 | _issue_entry_T_856; // @[Mux.scala:30:73]
wire _issue_entry_T_864 = _issue_entry_T_863 | _issue_entry_T_857; // @[Mux.scala:30:73]
wire _issue_entry_T_865 = _issue_entry_T_864 | _issue_entry_T_858; // @[Mux.scala:30:73]
wire _issue_entry_T_866 = _issue_entry_T_865 | _issue_entry_T_859; // @[Mux.scala:30:73]
wire _issue_entry_T_867 = _issue_entry_T_866 | _issue_entry_T_860; // @[Mux.scala:30:73]
wire _issue_entry_T_868 = _issue_entry_T_867 | _issue_entry_T_861; // @[Mux.scala:30:73]
wire _issue_entry_T_869 = _issue_entry_T_868 | _issue_entry_T_862; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_65 = _issue_entry_T_869; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_mbe = _issue_entry_WIRE_65; // @[Mux.scala:30:73]
wire _issue_entry_T_870 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_871 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_872 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_873 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_874 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_875 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_876 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_877 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_878 = _issue_entry_T_870 | _issue_entry_T_871; // @[Mux.scala:30:73]
wire _issue_entry_T_879 = _issue_entry_T_878 | _issue_entry_T_872; // @[Mux.scala:30:73]
wire _issue_entry_T_880 = _issue_entry_T_879 | _issue_entry_T_873; // @[Mux.scala:30:73]
wire _issue_entry_T_881 = _issue_entry_T_880 | _issue_entry_T_874; // @[Mux.scala:30:73]
wire _issue_entry_T_882 = _issue_entry_T_881 | _issue_entry_T_875; // @[Mux.scala:30:73]
wire _issue_entry_T_883 = _issue_entry_T_882 | _issue_entry_T_876; // @[Mux.scala:30:73]
wire _issue_entry_T_884 = _issue_entry_T_883 | _issue_entry_T_877; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_66 = _issue_entry_T_884; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_gva = _issue_entry_WIRE_66; // @[Mux.scala:30:73]
wire _issue_entry_T_885 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_886 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_887 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_888 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_889 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_890 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_891 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_892 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_893 = _issue_entry_T_885 | _issue_entry_T_886; // @[Mux.scala:30:73]
wire _issue_entry_T_894 = _issue_entry_T_893 | _issue_entry_T_887; // @[Mux.scala:30:73]
wire _issue_entry_T_895 = _issue_entry_T_894 | _issue_entry_T_888; // @[Mux.scala:30:73]
wire _issue_entry_T_896 = _issue_entry_T_895 | _issue_entry_T_889; // @[Mux.scala:30:73]
wire _issue_entry_T_897 = _issue_entry_T_896 | _issue_entry_T_890; // @[Mux.scala:30:73]
wire _issue_entry_T_898 = _issue_entry_T_897 | _issue_entry_T_891; // @[Mux.scala:30:73]
wire _issue_entry_T_899 = _issue_entry_T_898 | _issue_entry_T_892; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_67 = _issue_entry_T_899; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_mpv = _issue_entry_WIRE_67; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_900 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_901 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_902 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_903 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_904 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_905 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_906 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_907 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_908 = _issue_entry_T_900 | _issue_entry_T_901; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_909 = _issue_entry_T_908 | _issue_entry_T_902; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_910 = _issue_entry_T_909 | _issue_entry_T_903; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_911 = _issue_entry_T_910 | _issue_entry_T_904; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_912 = _issue_entry_T_911 | _issue_entry_T_905; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_913 = _issue_entry_T_912 | _issue_entry_T_906; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_914 = _issue_entry_T_913 | _issue_entry_T_907; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_68 = _issue_entry_T_914; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_zero2 = _issue_entry_WIRE_68; // @[Mux.scala:30:73]
wire _issue_entry_T_915 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_916 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_917 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_918 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_919 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_920 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_921 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_922 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_923 = _issue_entry_T_915 | _issue_entry_T_916; // @[Mux.scala:30:73]
wire _issue_entry_T_924 = _issue_entry_T_923 | _issue_entry_T_917; // @[Mux.scala:30:73]
wire _issue_entry_T_925 = _issue_entry_T_924 | _issue_entry_T_918; // @[Mux.scala:30:73]
wire _issue_entry_T_926 = _issue_entry_T_925 | _issue_entry_T_919; // @[Mux.scala:30:73]
wire _issue_entry_T_927 = _issue_entry_T_926 | _issue_entry_T_920; // @[Mux.scala:30:73]
wire _issue_entry_T_928 = _issue_entry_T_927 | _issue_entry_T_921; // @[Mux.scala:30:73]
wire _issue_entry_T_929 = _issue_entry_T_928 | _issue_entry_T_922; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_69 = _issue_entry_T_929; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_sd = _issue_entry_WIRE_69; // @[Mux.scala:30:73]
wire _issue_entry_T_930 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_931 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_932 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_933 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_934 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_935 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_936 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_937 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_938 = _issue_entry_T_930 | _issue_entry_T_931; // @[Mux.scala:30:73]
wire _issue_entry_T_939 = _issue_entry_T_938 | _issue_entry_T_932; // @[Mux.scala:30:73]
wire _issue_entry_T_940 = _issue_entry_T_939 | _issue_entry_T_933; // @[Mux.scala:30:73]
wire _issue_entry_T_941 = _issue_entry_T_940 | _issue_entry_T_934; // @[Mux.scala:30:73]
wire _issue_entry_T_942 = _issue_entry_T_941 | _issue_entry_T_935; // @[Mux.scala:30:73]
wire _issue_entry_T_943 = _issue_entry_T_942 | _issue_entry_T_936; // @[Mux.scala:30:73]
wire _issue_entry_T_944 = _issue_entry_T_943 | _issue_entry_T_937; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_70 = _issue_entry_T_944; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_v = _issue_entry_WIRE_70; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_945 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_946 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_947 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_948 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_949 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_950 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_951 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_952 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_953 = _issue_entry_T_945 | _issue_entry_T_946; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_954 = _issue_entry_T_953 | _issue_entry_T_947; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_955 = _issue_entry_T_954 | _issue_entry_T_948; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_956 = _issue_entry_T_955 | _issue_entry_T_949; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_957 = _issue_entry_T_956 | _issue_entry_T_950; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_958 = _issue_entry_T_957 | _issue_entry_T_951; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_959 = _issue_entry_T_958 | _issue_entry_T_952; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_71 = _issue_entry_T_959; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_prv = _issue_entry_WIRE_71; // @[Mux.scala:30:73]
wire _issue_entry_T_960 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_961 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_962 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_963 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_964 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_965 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_966 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_967 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_968 = _issue_entry_T_960 | _issue_entry_T_961; // @[Mux.scala:30:73]
wire _issue_entry_T_969 = _issue_entry_T_968 | _issue_entry_T_962; // @[Mux.scala:30:73]
wire _issue_entry_T_970 = _issue_entry_T_969 | _issue_entry_T_963; // @[Mux.scala:30:73]
wire _issue_entry_T_971 = _issue_entry_T_970 | _issue_entry_T_964; // @[Mux.scala:30:73]
wire _issue_entry_T_972 = _issue_entry_T_971 | _issue_entry_T_965; // @[Mux.scala:30:73]
wire _issue_entry_T_973 = _issue_entry_T_972 | _issue_entry_T_966; // @[Mux.scala:30:73]
wire _issue_entry_T_974 = _issue_entry_T_973 | _issue_entry_T_967; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_72 = _issue_entry_T_974; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_dv = _issue_entry_WIRE_72; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_975 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_976 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_977 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_978 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_979 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_980 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_981 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_982 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_983 = _issue_entry_T_975 | _issue_entry_T_976; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_984 = _issue_entry_T_983 | _issue_entry_T_977; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_985 = _issue_entry_T_984 | _issue_entry_T_978; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_986 = _issue_entry_T_985 | _issue_entry_T_979; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_987 = _issue_entry_T_986 | _issue_entry_T_980; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_988 = _issue_entry_T_987 | _issue_entry_T_981; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_989 = _issue_entry_T_988 | _issue_entry_T_982; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_73 = _issue_entry_T_989; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_dprv = _issue_entry_WIRE_73; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_990 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_991 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_992 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_993 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_994 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_995 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_996 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_997 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_998 = _issue_entry_T_990 | _issue_entry_T_991; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_999 = _issue_entry_T_998 | _issue_entry_T_992; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1000 = _issue_entry_T_999 | _issue_entry_T_993; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1001 = _issue_entry_T_1000 | _issue_entry_T_994; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1002 = _issue_entry_T_1001 | _issue_entry_T_995; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1003 = _issue_entry_T_1002 | _issue_entry_T_996; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1004 = _issue_entry_T_1003 | _issue_entry_T_997; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_74 = _issue_entry_T_1004; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_isa = _issue_entry_WIRE_74; // @[Mux.scala:30:73]
wire _issue_entry_T_1005 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1006 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1007 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1008 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1009 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1010 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1011 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1012 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_1013 = _issue_entry_T_1005 | _issue_entry_T_1006; // @[Mux.scala:30:73]
wire _issue_entry_T_1014 = _issue_entry_T_1013 | _issue_entry_T_1007; // @[Mux.scala:30:73]
wire _issue_entry_T_1015 = _issue_entry_T_1014 | _issue_entry_T_1008; // @[Mux.scala:30:73]
wire _issue_entry_T_1016 = _issue_entry_T_1015 | _issue_entry_T_1009; // @[Mux.scala:30:73]
wire _issue_entry_T_1017 = _issue_entry_T_1016 | _issue_entry_T_1010; // @[Mux.scala:30:73]
wire _issue_entry_T_1018 = _issue_entry_T_1017 | _issue_entry_T_1011; // @[Mux.scala:30:73]
wire _issue_entry_T_1019 = _issue_entry_T_1018 | _issue_entry_T_1012; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_75 = _issue_entry_T_1019; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_wfi = _issue_entry_WIRE_75; // @[Mux.scala:30:73]
wire _issue_entry_T_1020 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1021 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1022 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1023 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1024 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1025 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1026 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1027 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_1028 = _issue_entry_T_1020 | _issue_entry_T_1021; // @[Mux.scala:30:73]
wire _issue_entry_T_1029 = _issue_entry_T_1028 | _issue_entry_T_1022; // @[Mux.scala:30:73]
wire _issue_entry_T_1030 = _issue_entry_T_1029 | _issue_entry_T_1023; // @[Mux.scala:30:73]
wire _issue_entry_T_1031 = _issue_entry_T_1030 | _issue_entry_T_1024; // @[Mux.scala:30:73]
wire _issue_entry_T_1032 = _issue_entry_T_1031 | _issue_entry_T_1025; // @[Mux.scala:30:73]
wire _issue_entry_T_1033 = _issue_entry_T_1032 | _issue_entry_T_1026; // @[Mux.scala:30:73]
wire _issue_entry_T_1034 = _issue_entry_T_1033 | _issue_entry_T_1027; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_76 = _issue_entry_T_1034; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_cease = _issue_entry_WIRE_76; // @[Mux.scala:30:73]
wire _issue_entry_T_1035 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1036 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1037 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1038 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1039 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1040 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1041 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1042 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_1043 = _issue_entry_T_1035 | _issue_entry_T_1036; // @[Mux.scala:30:73]
wire _issue_entry_T_1044 = _issue_entry_T_1043 | _issue_entry_T_1037; // @[Mux.scala:30:73]
wire _issue_entry_T_1045 = _issue_entry_T_1044 | _issue_entry_T_1038; // @[Mux.scala:30:73]
wire _issue_entry_T_1046 = _issue_entry_T_1045 | _issue_entry_T_1039; // @[Mux.scala:30:73]
wire _issue_entry_T_1047 = _issue_entry_T_1046 | _issue_entry_T_1040; // @[Mux.scala:30:73]
wire _issue_entry_T_1048 = _issue_entry_T_1047 | _issue_entry_T_1041; // @[Mux.scala:30:73]
wire _issue_entry_T_1049 = _issue_entry_T_1048 | _issue_entry_T_1042; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_77 = _issue_entry_T_1049; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_40_debug = _issue_entry_WIRE_77; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1050 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1051 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1052 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1053 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1054 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1055 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1056 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1057 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1058 = _issue_entry_T_1050 | _issue_entry_T_1051; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1059 = _issue_entry_T_1058 | _issue_entry_T_1052; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1060 = _issue_entry_T_1059 | _issue_entry_T_1053; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1061 = _issue_entry_T_1060 | _issue_entry_T_1054; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1062 = _issue_entry_T_1061 | _issue_entry_T_1055; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1063 = _issue_entry_T_1062 | _issue_entry_T_1056; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1064 = _issue_entry_T_1063 | _issue_entry_T_1057; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_78 = _issue_entry_T_1064; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_rs2 = _issue_entry_WIRE_78; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1065 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1066 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1067 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1068 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1069 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1070 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1071 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1072 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_1073 = _issue_entry_T_1065 | _issue_entry_T_1066; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1074 = _issue_entry_T_1073 | _issue_entry_T_1067; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1075 = _issue_entry_T_1074 | _issue_entry_T_1068; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1076 = _issue_entry_T_1075 | _issue_entry_T_1069; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1077 = _issue_entry_T_1076 | _issue_entry_T_1070; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1078 = _issue_entry_T_1077 | _issue_entry_T_1071; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_1079 = _issue_entry_T_1078 | _issue_entry_T_1072; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_79 = _issue_entry_T_1079; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_rs1 = _issue_entry_WIRE_79; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_88; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_funct = _issue_entry_WIRE_80_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_87; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_rs2 = _issue_entry_WIRE_80_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_86; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_rs1 = _issue_entry_WIRE_80_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_85; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_xd = _issue_entry_WIRE_80_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_84; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_xs1 = _issue_entry_WIRE_80_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_83; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_xs2 = _issue_entry_WIRE_80_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_82; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_rd = _issue_entry_WIRE_80_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_81; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_39_inst_opcode = _issue_entry_WIRE_80_opcode; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1080 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1081 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1082 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1083 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1084 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1085 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1086 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1087 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1088 = _issue_entry_T_1080 | _issue_entry_T_1081; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1089 = _issue_entry_T_1088 | _issue_entry_T_1082; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1090 = _issue_entry_T_1089 | _issue_entry_T_1083; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1091 = _issue_entry_T_1090 | _issue_entry_T_1084; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1092 = _issue_entry_T_1091 | _issue_entry_T_1085; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1093 = _issue_entry_T_1092 | _issue_entry_T_1086; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1094 = _issue_entry_T_1093 | _issue_entry_T_1087; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_81 = _issue_entry_T_1094; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_opcode = _issue_entry_WIRE_81; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1095 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1096 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1097 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1098 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1099 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1100 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1101 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1102 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1103 = _issue_entry_T_1095 | _issue_entry_T_1096; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1104 = _issue_entry_T_1103 | _issue_entry_T_1097; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1105 = _issue_entry_T_1104 | _issue_entry_T_1098; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1106 = _issue_entry_T_1105 | _issue_entry_T_1099; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1107 = _issue_entry_T_1106 | _issue_entry_T_1100; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1108 = _issue_entry_T_1107 | _issue_entry_T_1101; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1109 = _issue_entry_T_1108 | _issue_entry_T_1102; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_82 = _issue_entry_T_1109; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_rd = _issue_entry_WIRE_82; // @[Mux.scala:30:73]
wire _issue_entry_T_1110 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1111 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1112 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1113 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1114 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1115 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1116 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1117 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1118 = _issue_entry_T_1110 | _issue_entry_T_1111; // @[Mux.scala:30:73]
wire _issue_entry_T_1119 = _issue_entry_T_1118 | _issue_entry_T_1112; // @[Mux.scala:30:73]
wire _issue_entry_T_1120 = _issue_entry_T_1119 | _issue_entry_T_1113; // @[Mux.scala:30:73]
wire _issue_entry_T_1121 = _issue_entry_T_1120 | _issue_entry_T_1114; // @[Mux.scala:30:73]
wire _issue_entry_T_1122 = _issue_entry_T_1121 | _issue_entry_T_1115; // @[Mux.scala:30:73]
wire _issue_entry_T_1123 = _issue_entry_T_1122 | _issue_entry_T_1116; // @[Mux.scala:30:73]
wire _issue_entry_T_1124 = _issue_entry_T_1123 | _issue_entry_T_1117; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_83 = _issue_entry_T_1124; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_xs2 = _issue_entry_WIRE_83; // @[Mux.scala:30:73]
wire _issue_entry_T_1125 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1126 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1127 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1128 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1129 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1130 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1131 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1132 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1133 = _issue_entry_T_1125 | _issue_entry_T_1126; // @[Mux.scala:30:73]
wire _issue_entry_T_1134 = _issue_entry_T_1133 | _issue_entry_T_1127; // @[Mux.scala:30:73]
wire _issue_entry_T_1135 = _issue_entry_T_1134 | _issue_entry_T_1128; // @[Mux.scala:30:73]
wire _issue_entry_T_1136 = _issue_entry_T_1135 | _issue_entry_T_1129; // @[Mux.scala:30:73]
wire _issue_entry_T_1137 = _issue_entry_T_1136 | _issue_entry_T_1130; // @[Mux.scala:30:73]
wire _issue_entry_T_1138 = _issue_entry_T_1137 | _issue_entry_T_1131; // @[Mux.scala:30:73]
wire _issue_entry_T_1139 = _issue_entry_T_1138 | _issue_entry_T_1132; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_84 = _issue_entry_T_1139; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_xs1 = _issue_entry_WIRE_84; // @[Mux.scala:30:73]
wire _issue_entry_T_1140 = issue_sel_0 & entries_ld_0_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1141 = issue_sel_1 & entries_ld_1_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1142 = issue_sel_2 & entries_ld_2_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1143 = issue_sel_3 & entries_ld_3_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1144 = issue_sel_4 & entries_ld_4_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1145 = issue_sel_5 & entries_ld_5_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1146 = issue_sel_6 & entries_ld_6_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1147 = issue_sel_7 & entries_ld_7_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_1148 = _issue_entry_T_1140 | _issue_entry_T_1141; // @[Mux.scala:30:73]
wire _issue_entry_T_1149 = _issue_entry_T_1148 | _issue_entry_T_1142; // @[Mux.scala:30:73]
wire _issue_entry_T_1150 = _issue_entry_T_1149 | _issue_entry_T_1143; // @[Mux.scala:30:73]
wire _issue_entry_T_1151 = _issue_entry_T_1150 | _issue_entry_T_1144; // @[Mux.scala:30:73]
wire _issue_entry_T_1152 = _issue_entry_T_1151 | _issue_entry_T_1145; // @[Mux.scala:30:73]
wire _issue_entry_T_1153 = _issue_entry_T_1152 | _issue_entry_T_1146; // @[Mux.scala:30:73]
wire _issue_entry_T_1154 = _issue_entry_T_1153 | _issue_entry_T_1147; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_85 = _issue_entry_T_1154; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_xd = _issue_entry_WIRE_85; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1155 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1156 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1157 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1158 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1159 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1160 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1161 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1162 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1163 = _issue_entry_T_1155 | _issue_entry_T_1156; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1164 = _issue_entry_T_1163 | _issue_entry_T_1157; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1165 = _issue_entry_T_1164 | _issue_entry_T_1158; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1166 = _issue_entry_T_1165 | _issue_entry_T_1159; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1167 = _issue_entry_T_1166 | _issue_entry_T_1160; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1168 = _issue_entry_T_1167 | _issue_entry_T_1161; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1169 = _issue_entry_T_1168 | _issue_entry_T_1162; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_86 = _issue_entry_T_1169; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_rs1 = _issue_entry_WIRE_86; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1170 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1171 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1172 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1173 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1174 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1175 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1176 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1177 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_1178 = _issue_entry_T_1170 | _issue_entry_T_1171; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1179 = _issue_entry_T_1178 | _issue_entry_T_1172; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1180 = _issue_entry_T_1179 | _issue_entry_T_1173; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1181 = _issue_entry_T_1180 | _issue_entry_T_1174; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1182 = _issue_entry_T_1181 | _issue_entry_T_1175; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1183 = _issue_entry_T_1182 | _issue_entry_T_1176; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_1184 = _issue_entry_T_1183 | _issue_entry_T_1177; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_87 = _issue_entry_T_1184; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_rs2 = _issue_entry_WIRE_87; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1185 = issue_sel_0 ? entries_ld_0_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1186 = issue_sel_1 ? entries_ld_1_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1187 = issue_sel_2 ? entries_ld_2_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1188 = issue_sel_3 ? entries_ld_3_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1189 = issue_sel_4 ? entries_ld_4_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1190 = issue_sel_5 ? entries_ld_5_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1191 = issue_sel_6 ? entries_ld_6_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1192 = issue_sel_7 ? entries_ld_7_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_1193 = _issue_entry_T_1185 | _issue_entry_T_1186; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1194 = _issue_entry_T_1193 | _issue_entry_T_1187; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1195 = _issue_entry_T_1194 | _issue_entry_T_1188; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1196 = _issue_entry_T_1195 | _issue_entry_T_1189; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1197 = _issue_entry_T_1196 | _issue_entry_T_1190; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1198 = _issue_entry_T_1197 | _issue_entry_T_1191; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_1199 = _issue_entry_T_1198 | _issue_entry_T_1192; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_88 = _issue_entry_T_1199; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_80_funct = _issue_entry_WIRE_88; // @[Mux.scala:30:73]
wire _issue_entry_T_1200 = issue_sel_0 & entries_ld_0_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1201 = issue_sel_1 & entries_ld_1_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1202 = issue_sel_2 & entries_ld_2_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1203 = issue_sel_3 & entries_ld_3_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1204 = issue_sel_4 & entries_ld_4_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1205 = issue_sel_5 & entries_ld_5_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1206 = issue_sel_6 & entries_ld_6_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1207 = issue_sel_7 & entries_ld_7_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_1208 = _issue_entry_T_1200 | _issue_entry_T_1201; // @[Mux.scala:30:73]
wire _issue_entry_T_1209 = _issue_entry_T_1208 | _issue_entry_T_1202; // @[Mux.scala:30:73]
wire _issue_entry_T_1210 = _issue_entry_T_1209 | _issue_entry_T_1203; // @[Mux.scala:30:73]
wire _issue_entry_T_1211 = _issue_entry_T_1210 | _issue_entry_T_1204; // @[Mux.scala:30:73]
wire _issue_entry_T_1212 = _issue_entry_T_1211 | _issue_entry_T_1205; // @[Mux.scala:30:73]
wire _issue_entry_T_1213 = _issue_entry_T_1212 | _issue_entry_T_1206; // @[Mux.scala:30:73]
wire _issue_entry_T_1214 = _issue_entry_T_1213 | _issue_entry_T_1207; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_89 = _issue_entry_T_1214; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_complete_on_issue = _issue_entry_WIRE_89; // @[Mux.scala:30:73]
wire _issue_entry_T_1215 = issue_sel_0 & entries_ld_0_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1216 = issue_sel_1 & entries_ld_1_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1217 = issue_sel_2 & entries_ld_2_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1218 = issue_sel_3 & entries_ld_3_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1219 = issue_sel_4 & entries_ld_4_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1220 = issue_sel_5 & entries_ld_5_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1221 = issue_sel_6 & entries_ld_6_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1222 = issue_sel_7 & entries_ld_7_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_1223 = _issue_entry_T_1215 | _issue_entry_T_1216; // @[Mux.scala:30:73]
wire _issue_entry_T_1224 = _issue_entry_T_1223 | _issue_entry_T_1217; // @[Mux.scala:30:73]
wire _issue_entry_T_1225 = _issue_entry_T_1224 | _issue_entry_T_1218; // @[Mux.scala:30:73]
wire _issue_entry_T_1226 = _issue_entry_T_1225 | _issue_entry_T_1219; // @[Mux.scala:30:73]
wire _issue_entry_T_1227 = _issue_entry_T_1226 | _issue_entry_T_1220; // @[Mux.scala:30:73]
wire _issue_entry_T_1228 = _issue_entry_T_1227 | _issue_entry_T_1221; // @[Mux.scala:30:73]
wire _issue_entry_T_1229 = _issue_entry_T_1228 | _issue_entry_T_1222; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_90 = _issue_entry_T_1229; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_issued = _issue_entry_WIRE_90; // @[Mux.scala:30:73]
wire _issue_entry_T_1486 = issue_sel_0 & entries_ld_0_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1487 = issue_sel_1 & entries_ld_1_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1488 = issue_sel_2 & entries_ld_2_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1489 = issue_sel_3 & entries_ld_3_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1490 = issue_sel_4 & entries_ld_4_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1491 = issue_sel_5 & entries_ld_5_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1492 = issue_sel_6 & entries_ld_6_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1493 = issue_sel_7 & entries_ld_7_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_1494 = _issue_entry_T_1486 | _issue_entry_T_1487; // @[Mux.scala:30:73]
wire _issue_entry_T_1495 = _issue_entry_T_1494 | _issue_entry_T_1488; // @[Mux.scala:30:73]
wire _issue_entry_T_1496 = _issue_entry_T_1495 | _issue_entry_T_1489; // @[Mux.scala:30:73]
wire _issue_entry_T_1497 = _issue_entry_T_1496 | _issue_entry_T_1490; // @[Mux.scala:30:73]
wire _issue_entry_T_1498 = _issue_entry_T_1497 | _issue_entry_T_1491; // @[Mux.scala:30:73]
wire _issue_entry_T_1499 = _issue_entry_T_1498 | _issue_entry_T_1492; // @[Mux.scala:30:73]
wire _issue_entry_T_1500 = _issue_entry_T_1499 | _issue_entry_T_1493; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_115 = _issue_entry_T_1500; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_is_dst = _issue_entry_WIRE_115; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_139; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_valid = _issue_entry_WIRE_116_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_start_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_start_is_acc_addr = _issue_entry_WIRE_116_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_start_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_start_accumulate = _issue_entry_WIRE_116_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_start_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_116_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_117_start_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_start_norm_cmd = _issue_entry_WIRE_116_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_117_start_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_start_garbage = _issue_entry_WIRE_116_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_start_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_start_garbage_bit = _issue_entry_WIRE_116_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_117_start_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_start_data = _issue_entry_WIRE_116_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_end_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_end_is_acc_addr = _issue_entry_WIRE_116_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_end_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_end_accumulate = _issue_entry_WIRE_116_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_end_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_116_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_117_end_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_end_norm_cmd = _issue_entry_WIRE_116_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_117_end_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_end_garbage = _issue_entry_WIRE_116_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_end_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_end_garbage_bit = _issue_entry_WIRE_116_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_117_end_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_end_data = _issue_entry_WIRE_116_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_117_wraps_around; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_opa_bits_wraps_around = _issue_entry_WIRE_116_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_129_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_start_is_acc_addr = _issue_entry_WIRE_117_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_129_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_start_accumulate = _issue_entry_WIRE_117_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_129_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_start_read_full_acc_row = _issue_entry_WIRE_117_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_129_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_start_norm_cmd = _issue_entry_WIRE_117_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_129_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_start_garbage = _issue_entry_WIRE_117_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_129_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_start_garbage_bit = _issue_entry_WIRE_117_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_129_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_start_data = _issue_entry_WIRE_117_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_119_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_end_is_acc_addr = _issue_entry_WIRE_117_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_119_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_end_accumulate = _issue_entry_WIRE_117_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_119_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_end_read_full_acc_row = _issue_entry_WIRE_117_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_119_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_end_norm_cmd = _issue_entry_WIRE_117_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_119_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_end_garbage = _issue_entry_WIRE_117_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_119_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_end_garbage_bit = _issue_entry_WIRE_117_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_119_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_end_data = _issue_entry_WIRE_117_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_118; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_bits_wraps_around = _issue_entry_WIRE_117_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_T_1501 = issue_sel_0 & entries_ld_0_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1502 = issue_sel_1 & entries_ld_1_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1503 = issue_sel_2 & entries_ld_2_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1504 = issue_sel_3 & entries_ld_3_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1505 = issue_sel_4 & entries_ld_4_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1506 = issue_sel_5 & entries_ld_5_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1507 = issue_sel_6 & entries_ld_6_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1508 = issue_sel_7 & entries_ld_7_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_1509 = _issue_entry_T_1501 | _issue_entry_T_1502; // @[Mux.scala:30:73]
wire _issue_entry_T_1510 = _issue_entry_T_1509 | _issue_entry_T_1503; // @[Mux.scala:30:73]
wire _issue_entry_T_1511 = _issue_entry_T_1510 | _issue_entry_T_1504; // @[Mux.scala:30:73]
wire _issue_entry_T_1512 = _issue_entry_T_1511 | _issue_entry_T_1505; // @[Mux.scala:30:73]
wire _issue_entry_T_1513 = _issue_entry_T_1512 | _issue_entry_T_1506; // @[Mux.scala:30:73]
wire _issue_entry_T_1514 = _issue_entry_T_1513 | _issue_entry_T_1507; // @[Mux.scala:30:73]
wire _issue_entry_T_1515 = _issue_entry_T_1514 | _issue_entry_T_1508; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_118 = _issue_entry_T_1515; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_wraps_around = _issue_entry_WIRE_118; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_128; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_end_is_acc_addr = _issue_entry_WIRE_119_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_127; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_end_accumulate = _issue_entry_WIRE_119_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_126; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_end_read_full_acc_row = _issue_entry_WIRE_119_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_123; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_end_norm_cmd = _issue_entry_WIRE_119_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_122; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_end_garbage = _issue_entry_WIRE_119_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_121; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_end_garbage_bit = _issue_entry_WIRE_119_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_120; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_end_data = _issue_entry_WIRE_119_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1516 = issue_sel_0 ? entries_ld_0_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1517 = issue_sel_1 ? entries_ld_1_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1518 = issue_sel_2 ? entries_ld_2_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1519 = issue_sel_3 ? entries_ld_3_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1520 = issue_sel_4 ? entries_ld_4_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1521 = issue_sel_5 ? entries_ld_5_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1522 = issue_sel_6 ? entries_ld_6_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1523 = issue_sel_7 ? entries_ld_7_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1524 = _issue_entry_T_1516 | _issue_entry_T_1517; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1525 = _issue_entry_T_1524 | _issue_entry_T_1518; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1526 = _issue_entry_T_1525 | _issue_entry_T_1519; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1527 = _issue_entry_T_1526 | _issue_entry_T_1520; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1528 = _issue_entry_T_1527 | _issue_entry_T_1521; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1529 = _issue_entry_T_1528 | _issue_entry_T_1522; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1530 = _issue_entry_T_1529 | _issue_entry_T_1523; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_120 = _issue_entry_T_1530; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_119_data = _issue_entry_WIRE_120; // @[Mux.scala:30:73]
wire _issue_entry_T_1531 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1532 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1533 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1534 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1535 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1536 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1537 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1538 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1539 = _issue_entry_T_1531 | _issue_entry_T_1532; // @[Mux.scala:30:73]
wire _issue_entry_T_1540 = _issue_entry_T_1539 | _issue_entry_T_1533; // @[Mux.scala:30:73]
wire _issue_entry_T_1541 = _issue_entry_T_1540 | _issue_entry_T_1534; // @[Mux.scala:30:73]
wire _issue_entry_T_1542 = _issue_entry_T_1541 | _issue_entry_T_1535; // @[Mux.scala:30:73]
wire _issue_entry_T_1543 = _issue_entry_T_1542 | _issue_entry_T_1536; // @[Mux.scala:30:73]
wire _issue_entry_T_1544 = _issue_entry_T_1543 | _issue_entry_T_1537; // @[Mux.scala:30:73]
wire _issue_entry_T_1545 = _issue_entry_T_1544 | _issue_entry_T_1538; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_121 = _issue_entry_T_1545; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_119_garbage_bit = _issue_entry_WIRE_121; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1546 = issue_sel_0 ? entries_ld_0_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1547 = issue_sel_1 ? entries_ld_1_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1548 = issue_sel_2 ? entries_ld_2_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1549 = issue_sel_3 ? entries_ld_3_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1550 = issue_sel_4 ? entries_ld_4_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1551 = issue_sel_5 ? entries_ld_5_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1552 = issue_sel_6 ? entries_ld_6_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1553 = issue_sel_7 ? entries_ld_7_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1554 = _issue_entry_T_1546 | _issue_entry_T_1547; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1555 = _issue_entry_T_1554 | _issue_entry_T_1548; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1556 = _issue_entry_T_1555 | _issue_entry_T_1549; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1557 = _issue_entry_T_1556 | _issue_entry_T_1550; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1558 = _issue_entry_T_1557 | _issue_entry_T_1551; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1559 = _issue_entry_T_1558 | _issue_entry_T_1552; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1560 = _issue_entry_T_1559 | _issue_entry_T_1553; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_122 = _issue_entry_T_1560; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_119_garbage = _issue_entry_WIRE_122; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1562 = issue_sel_0 ? _issue_entry_T_1561 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1564 = issue_sel_1 ? _issue_entry_T_1563 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1566 = issue_sel_2 ? _issue_entry_T_1565 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1568 = issue_sel_3 ? _issue_entry_T_1567 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1570 = issue_sel_4 ? _issue_entry_T_1569 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1572 = issue_sel_5 ? _issue_entry_T_1571 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1574 = issue_sel_6 ? _issue_entry_T_1573 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1576 = issue_sel_7 ? _issue_entry_T_1575 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1577 = _issue_entry_T_1562 | _issue_entry_T_1564; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1578 = _issue_entry_T_1577 | _issue_entry_T_1566; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1579 = _issue_entry_T_1578 | _issue_entry_T_1568; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1580 = _issue_entry_T_1579 | _issue_entry_T_1570; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1581 = _issue_entry_T_1580 | _issue_entry_T_1572; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1582 = _issue_entry_T_1581 | _issue_entry_T_1574; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1583 = _issue_entry_T_1582 | _issue_entry_T_1576; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_124 = _issue_entry_T_1583; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_125; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_119_norm_cmd = _issue_entry_WIRE_123; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_125 = _issue_entry_WIRE_124; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_123 = _issue_entry_WIRE_125; // @[Mux.scala:30:73]
wire _issue_entry_T_1584 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1585 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1586 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1587 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1588 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1589 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1590 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1591 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1592 = _issue_entry_T_1584 | _issue_entry_T_1585; // @[Mux.scala:30:73]
wire _issue_entry_T_1593 = _issue_entry_T_1592 | _issue_entry_T_1586; // @[Mux.scala:30:73]
wire _issue_entry_T_1594 = _issue_entry_T_1593 | _issue_entry_T_1587; // @[Mux.scala:30:73]
wire _issue_entry_T_1595 = _issue_entry_T_1594 | _issue_entry_T_1588; // @[Mux.scala:30:73]
wire _issue_entry_T_1596 = _issue_entry_T_1595 | _issue_entry_T_1589; // @[Mux.scala:30:73]
wire _issue_entry_T_1597 = _issue_entry_T_1596 | _issue_entry_T_1590; // @[Mux.scala:30:73]
wire _issue_entry_T_1598 = _issue_entry_T_1597 | _issue_entry_T_1591; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_126 = _issue_entry_T_1598; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_119_read_full_acc_row = _issue_entry_WIRE_126; // @[Mux.scala:30:73]
wire _issue_entry_T_1599 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1600 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1601 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1602 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1603 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1604 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1605 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1606 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1607 = _issue_entry_T_1599 | _issue_entry_T_1600; // @[Mux.scala:30:73]
wire _issue_entry_T_1608 = _issue_entry_T_1607 | _issue_entry_T_1601; // @[Mux.scala:30:73]
wire _issue_entry_T_1609 = _issue_entry_T_1608 | _issue_entry_T_1602; // @[Mux.scala:30:73]
wire _issue_entry_T_1610 = _issue_entry_T_1609 | _issue_entry_T_1603; // @[Mux.scala:30:73]
wire _issue_entry_T_1611 = _issue_entry_T_1610 | _issue_entry_T_1604; // @[Mux.scala:30:73]
wire _issue_entry_T_1612 = _issue_entry_T_1611 | _issue_entry_T_1605; // @[Mux.scala:30:73]
wire _issue_entry_T_1613 = _issue_entry_T_1612 | _issue_entry_T_1606; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_127 = _issue_entry_T_1613; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_119_accumulate = _issue_entry_WIRE_127; // @[Mux.scala:30:73]
wire _issue_entry_T_1614 = issue_sel_0 & entries_ld_0_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1615 = issue_sel_1 & entries_ld_1_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1616 = issue_sel_2 & entries_ld_2_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1617 = issue_sel_3 & entries_ld_3_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1618 = issue_sel_4 & entries_ld_4_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1619 = issue_sel_5 & entries_ld_5_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1620 = issue_sel_6 & entries_ld_6_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1621 = issue_sel_7 & entries_ld_7_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1622 = _issue_entry_T_1614 | _issue_entry_T_1615; // @[Mux.scala:30:73]
wire _issue_entry_T_1623 = _issue_entry_T_1622 | _issue_entry_T_1616; // @[Mux.scala:30:73]
wire _issue_entry_T_1624 = _issue_entry_T_1623 | _issue_entry_T_1617; // @[Mux.scala:30:73]
wire _issue_entry_T_1625 = _issue_entry_T_1624 | _issue_entry_T_1618; // @[Mux.scala:30:73]
wire _issue_entry_T_1626 = _issue_entry_T_1625 | _issue_entry_T_1619; // @[Mux.scala:30:73]
wire _issue_entry_T_1627 = _issue_entry_T_1626 | _issue_entry_T_1620; // @[Mux.scala:30:73]
wire _issue_entry_T_1628 = _issue_entry_T_1627 | _issue_entry_T_1621; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_128 = _issue_entry_T_1628; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_119_is_acc_addr = _issue_entry_WIRE_128; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_138; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_start_is_acc_addr = _issue_entry_WIRE_129_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_137; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_start_accumulate = _issue_entry_WIRE_129_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_136; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_start_read_full_acc_row = _issue_entry_WIRE_129_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_133; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_start_norm_cmd = _issue_entry_WIRE_129_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_132; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_start_garbage = _issue_entry_WIRE_129_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_131; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_start_garbage_bit = _issue_entry_WIRE_129_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_130; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_117_start_data = _issue_entry_WIRE_129_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1629 = issue_sel_0 ? entries_ld_0_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1630 = issue_sel_1 ? entries_ld_1_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1631 = issue_sel_2 ? entries_ld_2_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1632 = issue_sel_3 ? entries_ld_3_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1633 = issue_sel_4 ? entries_ld_4_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1634 = issue_sel_5 ? entries_ld_5_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1635 = issue_sel_6 ? entries_ld_6_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1636 = issue_sel_7 ? entries_ld_7_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_1637 = _issue_entry_T_1629 | _issue_entry_T_1630; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1638 = _issue_entry_T_1637 | _issue_entry_T_1631; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1639 = _issue_entry_T_1638 | _issue_entry_T_1632; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1640 = _issue_entry_T_1639 | _issue_entry_T_1633; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1641 = _issue_entry_T_1640 | _issue_entry_T_1634; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1642 = _issue_entry_T_1641 | _issue_entry_T_1635; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_1643 = _issue_entry_T_1642 | _issue_entry_T_1636; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_130 = _issue_entry_T_1643; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_129_data = _issue_entry_WIRE_130; // @[Mux.scala:30:73]
wire _issue_entry_T_1644 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1645 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1646 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1647 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1648 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1649 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1650 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1651 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_1652 = _issue_entry_T_1644 | _issue_entry_T_1645; // @[Mux.scala:30:73]
wire _issue_entry_T_1653 = _issue_entry_T_1652 | _issue_entry_T_1646; // @[Mux.scala:30:73]
wire _issue_entry_T_1654 = _issue_entry_T_1653 | _issue_entry_T_1647; // @[Mux.scala:30:73]
wire _issue_entry_T_1655 = _issue_entry_T_1654 | _issue_entry_T_1648; // @[Mux.scala:30:73]
wire _issue_entry_T_1656 = _issue_entry_T_1655 | _issue_entry_T_1649; // @[Mux.scala:30:73]
wire _issue_entry_T_1657 = _issue_entry_T_1656 | _issue_entry_T_1650; // @[Mux.scala:30:73]
wire _issue_entry_T_1658 = _issue_entry_T_1657 | _issue_entry_T_1651; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_131 = _issue_entry_T_1658; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_129_garbage_bit = _issue_entry_WIRE_131; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1659 = issue_sel_0 ? entries_ld_0_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1660 = issue_sel_1 ? entries_ld_1_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1661 = issue_sel_2 ? entries_ld_2_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1662 = issue_sel_3 ? entries_ld_3_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1663 = issue_sel_4 ? entries_ld_4_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1664 = issue_sel_5 ? entries_ld_5_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1665 = issue_sel_6 ? entries_ld_6_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1666 = issue_sel_7 ? entries_ld_7_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_1667 = _issue_entry_T_1659 | _issue_entry_T_1660; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1668 = _issue_entry_T_1667 | _issue_entry_T_1661; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1669 = _issue_entry_T_1668 | _issue_entry_T_1662; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1670 = _issue_entry_T_1669 | _issue_entry_T_1663; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1671 = _issue_entry_T_1670 | _issue_entry_T_1664; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1672 = _issue_entry_T_1671 | _issue_entry_T_1665; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_1673 = _issue_entry_T_1672 | _issue_entry_T_1666; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_132 = _issue_entry_T_1673; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_129_garbage = _issue_entry_WIRE_132; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1675 = issue_sel_0 ? _issue_entry_T_1674 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1677 = issue_sel_1 ? _issue_entry_T_1676 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1679 = issue_sel_2 ? _issue_entry_T_1678 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1681 = issue_sel_3 ? _issue_entry_T_1680 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1683 = issue_sel_4 ? _issue_entry_T_1682 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1685 = issue_sel_5 ? _issue_entry_T_1684 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1687 = issue_sel_6 ? _issue_entry_T_1686 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1689 = issue_sel_7 ? _issue_entry_T_1688 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_1690 = _issue_entry_T_1675 | _issue_entry_T_1677; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1691 = _issue_entry_T_1690 | _issue_entry_T_1679; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1692 = _issue_entry_T_1691 | _issue_entry_T_1681; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1693 = _issue_entry_T_1692 | _issue_entry_T_1683; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1694 = _issue_entry_T_1693 | _issue_entry_T_1685; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1695 = _issue_entry_T_1694 | _issue_entry_T_1687; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_1696 = _issue_entry_T_1695 | _issue_entry_T_1689; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_134 = _issue_entry_T_1696; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_135; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_129_norm_cmd = _issue_entry_WIRE_133; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_135 = _issue_entry_WIRE_134; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_133 = _issue_entry_WIRE_135; // @[Mux.scala:30:73]
wire _issue_entry_T_1697 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1698 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1699 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1700 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1701 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1702 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1703 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1704 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_1705 = _issue_entry_T_1697 | _issue_entry_T_1698; // @[Mux.scala:30:73]
wire _issue_entry_T_1706 = _issue_entry_T_1705 | _issue_entry_T_1699; // @[Mux.scala:30:73]
wire _issue_entry_T_1707 = _issue_entry_T_1706 | _issue_entry_T_1700; // @[Mux.scala:30:73]
wire _issue_entry_T_1708 = _issue_entry_T_1707 | _issue_entry_T_1701; // @[Mux.scala:30:73]
wire _issue_entry_T_1709 = _issue_entry_T_1708 | _issue_entry_T_1702; // @[Mux.scala:30:73]
wire _issue_entry_T_1710 = _issue_entry_T_1709 | _issue_entry_T_1703; // @[Mux.scala:30:73]
wire _issue_entry_T_1711 = _issue_entry_T_1710 | _issue_entry_T_1704; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_136 = _issue_entry_T_1711; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_129_read_full_acc_row = _issue_entry_WIRE_136; // @[Mux.scala:30:73]
wire _issue_entry_T_1712 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1713 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1714 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1715 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1716 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1717 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1718 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1719 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_1720 = _issue_entry_T_1712 | _issue_entry_T_1713; // @[Mux.scala:30:73]
wire _issue_entry_T_1721 = _issue_entry_T_1720 | _issue_entry_T_1714; // @[Mux.scala:30:73]
wire _issue_entry_T_1722 = _issue_entry_T_1721 | _issue_entry_T_1715; // @[Mux.scala:30:73]
wire _issue_entry_T_1723 = _issue_entry_T_1722 | _issue_entry_T_1716; // @[Mux.scala:30:73]
wire _issue_entry_T_1724 = _issue_entry_T_1723 | _issue_entry_T_1717; // @[Mux.scala:30:73]
wire _issue_entry_T_1725 = _issue_entry_T_1724 | _issue_entry_T_1718; // @[Mux.scala:30:73]
wire _issue_entry_T_1726 = _issue_entry_T_1725 | _issue_entry_T_1719; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_137 = _issue_entry_T_1726; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_129_accumulate = _issue_entry_WIRE_137; // @[Mux.scala:30:73]
wire _issue_entry_T_1727 = issue_sel_0 & entries_ld_0_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1728 = issue_sel_1 & entries_ld_1_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1729 = issue_sel_2 & entries_ld_2_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1730 = issue_sel_3 & entries_ld_3_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1731 = issue_sel_4 & entries_ld_4_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1732 = issue_sel_5 & entries_ld_5_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1733 = issue_sel_6 & entries_ld_6_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1734 = issue_sel_7 & entries_ld_7_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_1735 = _issue_entry_T_1727 | _issue_entry_T_1728; // @[Mux.scala:30:73]
wire _issue_entry_T_1736 = _issue_entry_T_1735 | _issue_entry_T_1729; // @[Mux.scala:30:73]
wire _issue_entry_T_1737 = _issue_entry_T_1736 | _issue_entry_T_1730; // @[Mux.scala:30:73]
wire _issue_entry_T_1738 = _issue_entry_T_1737 | _issue_entry_T_1731; // @[Mux.scala:30:73]
wire _issue_entry_T_1739 = _issue_entry_T_1738 | _issue_entry_T_1732; // @[Mux.scala:30:73]
wire _issue_entry_T_1740 = _issue_entry_T_1739 | _issue_entry_T_1733; // @[Mux.scala:30:73]
wire _issue_entry_T_1741 = _issue_entry_T_1740 | _issue_entry_T_1734; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_138 = _issue_entry_T_1741; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_129_is_acc_addr = _issue_entry_WIRE_138; // @[Mux.scala:30:73]
wire _issue_entry_T_1742 = issue_sel_0 & entries_ld_0_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1743 = issue_sel_1 & entries_ld_1_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1744 = issue_sel_2 & entries_ld_2_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1745 = issue_sel_3 & entries_ld_3_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1746 = issue_sel_4 & entries_ld_4_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1747 = issue_sel_5 & entries_ld_5_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1748 = issue_sel_6 & entries_ld_6_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1749 = issue_sel_7 & entries_ld_7_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1750 = _issue_entry_T_1742 | _issue_entry_T_1743; // @[Mux.scala:30:73]
wire _issue_entry_T_1751 = _issue_entry_T_1750 | _issue_entry_T_1744; // @[Mux.scala:30:73]
wire _issue_entry_T_1752 = _issue_entry_T_1751 | _issue_entry_T_1745; // @[Mux.scala:30:73]
wire _issue_entry_T_1753 = _issue_entry_T_1752 | _issue_entry_T_1746; // @[Mux.scala:30:73]
wire _issue_entry_T_1754 = _issue_entry_T_1753 | _issue_entry_T_1747; // @[Mux.scala:30:73]
wire _issue_entry_T_1755 = _issue_entry_T_1754 | _issue_entry_T_1748; // @[Mux.scala:30:73]
wire _issue_entry_T_1756 = _issue_entry_T_1755 | _issue_entry_T_1749; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_139 = _issue_entry_T_1756; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_116_valid = _issue_entry_WIRE_139; // @[Mux.scala:30:73]
wire _issue_entry_T_1757 = issue_sel_0 & entries_ld_0_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1758 = issue_sel_1 & entries_ld_1_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1759 = issue_sel_2 & entries_ld_2_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1760 = issue_sel_3 & entries_ld_3_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1761 = issue_sel_4 & entries_ld_4_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1762 = issue_sel_5 & entries_ld_5_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1763 = issue_sel_6 & entries_ld_6_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1764 = issue_sel_7 & entries_ld_7_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_1765 = _issue_entry_T_1757 | _issue_entry_T_1758; // @[Mux.scala:30:73]
wire _issue_entry_T_1766 = _issue_entry_T_1765 | _issue_entry_T_1759; // @[Mux.scala:30:73]
wire _issue_entry_T_1767 = _issue_entry_T_1766 | _issue_entry_T_1760; // @[Mux.scala:30:73]
wire _issue_entry_T_1768 = _issue_entry_T_1767 | _issue_entry_T_1761; // @[Mux.scala:30:73]
wire _issue_entry_T_1769 = _issue_entry_T_1768 | _issue_entry_T_1762; // @[Mux.scala:30:73]
wire _issue_entry_T_1770 = _issue_entry_T_1769 | _issue_entry_T_1763; // @[Mux.scala:30:73]
wire _issue_entry_T_1771 = _issue_entry_T_1770 | _issue_entry_T_1764; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_140 = _issue_entry_T_1771; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_is_config = _issue_entry_WIRE_140; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_1772 = issue_sel_0 ? entries_ld_0_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1773 = issue_sel_1 ? entries_ld_1_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1774 = issue_sel_2 ? entries_ld_2_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1775 = issue_sel_3 ? entries_ld_3_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1776 = issue_sel_4 ? entries_ld_4_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1777 = issue_sel_5 ? entries_ld_5_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1778 = issue_sel_6 ? entries_ld_6_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1779 = issue_sel_7 ? entries_ld_7_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_1780 = _issue_entry_T_1772 | _issue_entry_T_1773; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_1781 = _issue_entry_T_1780 | _issue_entry_T_1774; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_1782 = _issue_entry_T_1781 | _issue_entry_T_1775; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_1783 = _issue_entry_T_1782 | _issue_entry_T_1776; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_1784 = _issue_entry_T_1783 | _issue_entry_T_1777; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_1785 = _issue_entry_T_1784 | _issue_entry_T_1778; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_1786 = _issue_entry_T_1785 | _issue_entry_T_1779; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_141 = _issue_entry_T_1786; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_q = _issue_entry_WIRE_141; // @[Mux.scala:30:73]
wire _issue_entry_T_1787 = issue_sel_0 & entries_ld_0_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1788 = issue_sel_1 & entries_ld_1_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1789 = issue_sel_2 & entries_ld_2_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1790 = issue_sel_3 & entries_ld_3_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1791 = issue_sel_4 & entries_ld_4_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1792 = issue_sel_5 & entries_ld_5_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1793 = issue_sel_6 & entries_ld_6_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1794 = issue_sel_7 & entries_ld_7_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_1795 = _issue_entry_T_1787 | _issue_entry_T_1788; // @[Mux.scala:30:73]
wire _issue_entry_T_1796 = _issue_entry_T_1795 | _issue_entry_T_1789; // @[Mux.scala:30:73]
wire _issue_entry_T_1797 = _issue_entry_T_1796 | _issue_entry_T_1790; // @[Mux.scala:30:73]
wire _issue_entry_T_1798 = _issue_entry_T_1797 | _issue_entry_T_1791; // @[Mux.scala:30:73]
wire _issue_entry_T_1799 = _issue_entry_T_1798 | _issue_entry_T_1792; // @[Mux.scala:30:73]
wire _issue_entry_T_1800 = _issue_entry_T_1799 | _issue_entry_T_1793; // @[Mux.scala:30:73]
wire _issue_entry_T_1801 = _issue_entry_T_1800 | _issue_entry_T_1794; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_142 = _issue_entry_T_1801; // @[Mux.scala:30:73]
assign issue_entry_valid = _issue_entry_WIRE_142; // @[Mux.scala:30:73]
wire _io_issue_ld_valid_T = issue_valids_0 | issue_valids_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ld_valid_T_1 = _io_issue_ld_valid_T | issue_valids_2; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ld_valid_T_2 = _io_issue_ld_valid_T_1 | issue_valids_3; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ld_valid_T_3 = _io_issue_ld_valid_T_2 | issue_valids_4; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ld_valid_T_4 = _io_issue_ld_valid_T_3 | issue_valids_5; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ld_valid_T_5 = _io_issue_ld_valid_T_4 | issue_valids_6; // @[ReservationStation.scala:395:72, :404:38]
assign _io_issue_ld_valid_T_6 = _io_issue_ld_valid_T_5 | issue_valids_7; // @[ReservationStation.scala:395:72, :404:38]
assign io_issue_ld_valid_0 = _io_issue_ld_valid_T_6; // @[ReservationStation.scala:26:7, :404:38]
wire _T_5013 = io_issue_ld_valid_0 & io_issue_ld_ready_0; // @[ReservationStation.scala:22:20, :26:7]
wire _entries_ld_0_valid_T = ~entries_ld_0_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire _entries_ld_1_valid_T = ~entries_ld_1_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire _entries_ld_2_valid_T = ~entries_ld_2_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire _entries_ld_3_valid_T = ~entries_ld_3_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire _entries_ld_4_valid_T = ~entries_ld_4_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire _entries_ld_5_valid_T = ~entries_ld_5_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire _entries_ld_6_valid_T = ~entries_ld_6_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire _entries_ld_7_valid_T = ~entries_ld_7_bits_complete_on_issue; // @[ReservationStation.scala:117:23, :417:22]
wire [7:0] _GEN_89 = {{entries_ld_7_bits_complete_on_issue}, {entries_ld_6_bits_complete_on_issue}, {entries_ld_5_bits_complete_on_issue}, {entries_ld_4_bits_complete_on_issue}, {entries_ld_3_bits_complete_on_issue}, {entries_ld_2_bits_complete_on_issue}, {entries_ld_1_bits_complete_on_issue}, {entries_ld_0_bits_complete_on_issue}}; // @[ReservationStation.scala:117:23, :440:71]
wire [7:0] _GEN_90 = {{entries_ld_7_bits_cmd_from_conv_fsm}, {entries_ld_6_bits_cmd_from_conv_fsm}, {entries_ld_5_bits_cmd_from_conv_fsm}, {entries_ld_4_bits_cmd_from_conv_fsm}, {entries_ld_3_bits_cmd_from_conv_fsm}, {entries_ld_2_bits_cmd_from_conv_fsm}, {entries_ld_1_bits_cmd_from_conv_fsm}, {entries_ld_0_bits_cmd_from_conv_fsm}}; // @[ReservationStation.scala:117:23, :440:71]
wire _GEN_91 = _GEN_89[issue_id] & _GEN_90[issue_id]; // @[OneHot.scala:32:10]
wire _conv_ld_issue_completed_T; // @[ReservationStation.scala:440:71]
assign _conv_ld_issue_completed_T = _GEN_91; // @[ReservationStation.scala:440:71]
wire _conv_st_issue_completed_T; // @[ReservationStation.scala:441:71]
assign _conv_st_issue_completed_T = _GEN_91; // @[ReservationStation.scala:440:71, :441:71]
wire _conv_ex_issue_completed_T; // @[ReservationStation.scala:442:71]
assign _conv_ex_issue_completed_T = _GEN_91; // @[ReservationStation.scala:440:71, :442:71]
assign conv_ld_issue_completed = _T_5013 & _conv_ld_issue_completed_T; // @[ReservationStation.scala:22:20, :138:41, :413:20, :440:{24,71}]
wire [7:0] _GEN_92 = {{entries_ld_7_bits_cmd_from_matmul_fsm}, {entries_ld_6_bits_cmd_from_matmul_fsm}, {entries_ld_5_bits_cmd_from_matmul_fsm}, {entries_ld_4_bits_cmd_from_matmul_fsm}, {entries_ld_3_bits_cmd_from_matmul_fsm}, {entries_ld_2_bits_cmd_from_matmul_fsm}, {entries_ld_1_bits_cmd_from_matmul_fsm}, {entries_ld_0_bits_cmd_from_matmul_fsm}}; // @[ReservationStation.scala:117:23, :444:73]
wire _GEN_93 = _GEN_89[issue_id] & _GEN_92[issue_id]; // @[OneHot.scala:32:10]
wire _matmul_ld_issue_completed_T; // @[ReservationStation.scala:444:73]
assign _matmul_ld_issue_completed_T = _GEN_93; // @[ReservationStation.scala:444:73]
wire _matmul_st_issue_completed_T; // @[ReservationStation.scala:445:73]
assign _matmul_st_issue_completed_T = _GEN_93; // @[ReservationStation.scala:444:73, :445:73]
wire _matmul_ex_issue_completed_T; // @[ReservationStation.scala:446:73]
assign _matmul_ex_issue_completed_T = _GEN_93; // @[ReservationStation.scala:444:73, :446:73]
assign matmul_ld_issue_completed = _T_5013 & _matmul_ld_issue_completed_T; // @[ReservationStation.scala:22:20, :146:43, :413:20, :444:{24,73}]
wire _issue_valids_T_240 = entries_ex_0_bits_deps_ld_0 | entries_ex_0_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_241 = _issue_valids_T_240 | entries_ex_0_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_242 = _issue_valids_T_241 | entries_ex_0_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_243 = _issue_valids_T_242 | entries_ex_0_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_244 = _issue_valids_T_243 | entries_ex_0_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_245 = _issue_valids_T_244 | entries_ex_0_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_246 = _issue_valids_T_245 | entries_ex_0_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_247 = entries_ex_0_bits_deps_ex_0 | entries_ex_0_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_248 = _issue_valids_T_247 | entries_ex_0_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_249 = _issue_valids_T_248 | entries_ex_0_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_250 = _issue_valids_T_249 | entries_ex_0_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_251 = _issue_valids_T_250 | entries_ex_0_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_252 = _issue_valids_T_251 | entries_ex_0_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_253 = _issue_valids_T_252 | entries_ex_0_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_254 = _issue_valids_T_253 | entries_ex_0_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_255 = _issue_valids_T_254 | entries_ex_0_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_256 = _issue_valids_T_255 | entries_ex_0_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_257 = _issue_valids_T_256 | entries_ex_0_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_258 = _issue_valids_T_257 | entries_ex_0_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_259 = _issue_valids_T_258 | entries_ex_0_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_260 = _issue_valids_T_259 | entries_ex_0_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_261 = _issue_valids_T_260 | entries_ex_0_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_262 = _issue_valids_T_246 | _issue_valids_T_261; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_263 = entries_ex_0_bits_deps_st_0 | entries_ex_0_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_264 = _issue_valids_T_263 | entries_ex_0_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_265 = _issue_valids_T_264 | entries_ex_0_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_266 = _issue_valids_T_262 | _issue_valids_T_265; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_267 = ~_issue_valids_T_266; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_268 = entries_ex_0_valid & _issue_valids_T_267; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_269 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_0_1 = _issue_valids_T_268 & _issue_valids_T_269; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_270 = entries_ex_1_bits_deps_ld_0 | entries_ex_1_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_271 = _issue_valids_T_270 | entries_ex_1_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_272 = _issue_valids_T_271 | entries_ex_1_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_273 = _issue_valids_T_272 | entries_ex_1_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_274 = _issue_valids_T_273 | entries_ex_1_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_275 = _issue_valids_T_274 | entries_ex_1_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_276 = _issue_valids_T_275 | entries_ex_1_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_277 = entries_ex_1_bits_deps_ex_0 | entries_ex_1_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_278 = _issue_valids_T_277 | entries_ex_1_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_279 = _issue_valids_T_278 | entries_ex_1_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_280 = _issue_valids_T_279 | entries_ex_1_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_281 = _issue_valids_T_280 | entries_ex_1_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_282 = _issue_valids_T_281 | entries_ex_1_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_283 = _issue_valids_T_282 | entries_ex_1_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_284 = _issue_valids_T_283 | entries_ex_1_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_285 = _issue_valids_T_284 | entries_ex_1_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_286 = _issue_valids_T_285 | entries_ex_1_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_287 = _issue_valids_T_286 | entries_ex_1_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_288 = _issue_valids_T_287 | entries_ex_1_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_289 = _issue_valids_T_288 | entries_ex_1_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_290 = _issue_valids_T_289 | entries_ex_1_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_291 = _issue_valids_T_290 | entries_ex_1_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_292 = _issue_valids_T_276 | _issue_valids_T_291; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_293 = entries_ex_1_bits_deps_st_0 | entries_ex_1_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_294 = _issue_valids_T_293 | entries_ex_1_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_295 = _issue_valids_T_294 | entries_ex_1_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_296 = _issue_valids_T_292 | _issue_valids_T_295; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_297 = ~_issue_valids_T_296; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_298 = entries_ex_1_valid & _issue_valids_T_297; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_299 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_1_1 = _issue_valids_T_298 & _issue_valids_T_299; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_300 = entries_ex_2_bits_deps_ld_0 | entries_ex_2_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_301 = _issue_valids_T_300 | entries_ex_2_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_302 = _issue_valids_T_301 | entries_ex_2_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_303 = _issue_valids_T_302 | entries_ex_2_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_304 = _issue_valids_T_303 | entries_ex_2_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_305 = _issue_valids_T_304 | entries_ex_2_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_306 = _issue_valids_T_305 | entries_ex_2_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_307 = entries_ex_2_bits_deps_ex_0 | entries_ex_2_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_308 = _issue_valids_T_307 | entries_ex_2_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_309 = _issue_valids_T_308 | entries_ex_2_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_310 = _issue_valids_T_309 | entries_ex_2_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_311 = _issue_valids_T_310 | entries_ex_2_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_312 = _issue_valids_T_311 | entries_ex_2_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_313 = _issue_valids_T_312 | entries_ex_2_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_314 = _issue_valids_T_313 | entries_ex_2_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_315 = _issue_valids_T_314 | entries_ex_2_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_316 = _issue_valids_T_315 | entries_ex_2_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_317 = _issue_valids_T_316 | entries_ex_2_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_318 = _issue_valids_T_317 | entries_ex_2_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_319 = _issue_valids_T_318 | entries_ex_2_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_320 = _issue_valids_T_319 | entries_ex_2_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_321 = _issue_valids_T_320 | entries_ex_2_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_322 = _issue_valids_T_306 | _issue_valids_T_321; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_323 = entries_ex_2_bits_deps_st_0 | entries_ex_2_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_324 = _issue_valids_T_323 | entries_ex_2_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_325 = _issue_valids_T_324 | entries_ex_2_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_326 = _issue_valids_T_322 | _issue_valids_T_325; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_327 = ~_issue_valids_T_326; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_328 = entries_ex_2_valid & _issue_valids_T_327; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_329 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_2_1 = _issue_valids_T_328 & _issue_valids_T_329; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_330 = entries_ex_3_bits_deps_ld_0 | entries_ex_3_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_331 = _issue_valids_T_330 | entries_ex_3_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_332 = _issue_valids_T_331 | entries_ex_3_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_333 = _issue_valids_T_332 | entries_ex_3_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_334 = _issue_valids_T_333 | entries_ex_3_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_335 = _issue_valids_T_334 | entries_ex_3_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_336 = _issue_valids_T_335 | entries_ex_3_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_337 = entries_ex_3_bits_deps_ex_0 | entries_ex_3_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_338 = _issue_valids_T_337 | entries_ex_3_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_339 = _issue_valids_T_338 | entries_ex_3_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_340 = _issue_valids_T_339 | entries_ex_3_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_341 = _issue_valids_T_340 | entries_ex_3_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_342 = _issue_valids_T_341 | entries_ex_3_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_343 = _issue_valids_T_342 | entries_ex_3_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_344 = _issue_valids_T_343 | entries_ex_3_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_345 = _issue_valids_T_344 | entries_ex_3_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_346 = _issue_valids_T_345 | entries_ex_3_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_347 = _issue_valids_T_346 | entries_ex_3_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_348 = _issue_valids_T_347 | entries_ex_3_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_349 = _issue_valids_T_348 | entries_ex_3_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_350 = _issue_valids_T_349 | entries_ex_3_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_351 = _issue_valids_T_350 | entries_ex_3_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_352 = _issue_valids_T_336 | _issue_valids_T_351; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_353 = entries_ex_3_bits_deps_st_0 | entries_ex_3_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_354 = _issue_valids_T_353 | entries_ex_3_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_355 = _issue_valids_T_354 | entries_ex_3_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_356 = _issue_valids_T_352 | _issue_valids_T_355; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_357 = ~_issue_valids_T_356; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_358 = entries_ex_3_valid & _issue_valids_T_357; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_359 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_3_1 = _issue_valids_T_358 & _issue_valids_T_359; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_360 = entries_ex_4_bits_deps_ld_0 | entries_ex_4_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_361 = _issue_valids_T_360 | entries_ex_4_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_362 = _issue_valids_T_361 | entries_ex_4_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_363 = _issue_valids_T_362 | entries_ex_4_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_364 = _issue_valids_T_363 | entries_ex_4_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_365 = _issue_valids_T_364 | entries_ex_4_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_366 = _issue_valids_T_365 | entries_ex_4_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_367 = entries_ex_4_bits_deps_ex_0 | entries_ex_4_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_368 = _issue_valids_T_367 | entries_ex_4_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_369 = _issue_valids_T_368 | entries_ex_4_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_370 = _issue_valids_T_369 | entries_ex_4_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_371 = _issue_valids_T_370 | entries_ex_4_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_372 = _issue_valids_T_371 | entries_ex_4_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_373 = _issue_valids_T_372 | entries_ex_4_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_374 = _issue_valids_T_373 | entries_ex_4_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_375 = _issue_valids_T_374 | entries_ex_4_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_376 = _issue_valids_T_375 | entries_ex_4_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_377 = _issue_valids_T_376 | entries_ex_4_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_378 = _issue_valids_T_377 | entries_ex_4_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_379 = _issue_valids_T_378 | entries_ex_4_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_380 = _issue_valids_T_379 | entries_ex_4_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_381 = _issue_valids_T_380 | entries_ex_4_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_382 = _issue_valids_T_366 | _issue_valids_T_381; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_383 = entries_ex_4_bits_deps_st_0 | entries_ex_4_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_384 = _issue_valids_T_383 | entries_ex_4_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_385 = _issue_valids_T_384 | entries_ex_4_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_386 = _issue_valids_T_382 | _issue_valids_T_385; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_387 = ~_issue_valids_T_386; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_388 = entries_ex_4_valid & _issue_valids_T_387; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_389 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_4_1 = _issue_valids_T_388 & _issue_valids_T_389; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_390 = entries_ex_5_bits_deps_ld_0 | entries_ex_5_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_391 = _issue_valids_T_390 | entries_ex_5_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_392 = _issue_valids_T_391 | entries_ex_5_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_393 = _issue_valids_T_392 | entries_ex_5_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_394 = _issue_valids_T_393 | entries_ex_5_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_395 = _issue_valids_T_394 | entries_ex_5_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_396 = _issue_valids_T_395 | entries_ex_5_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_397 = entries_ex_5_bits_deps_ex_0 | entries_ex_5_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_398 = _issue_valids_T_397 | entries_ex_5_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_399 = _issue_valids_T_398 | entries_ex_5_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_400 = _issue_valids_T_399 | entries_ex_5_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_401 = _issue_valids_T_400 | entries_ex_5_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_402 = _issue_valids_T_401 | entries_ex_5_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_403 = _issue_valids_T_402 | entries_ex_5_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_404 = _issue_valids_T_403 | entries_ex_5_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_405 = _issue_valids_T_404 | entries_ex_5_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_406 = _issue_valids_T_405 | entries_ex_5_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_407 = _issue_valids_T_406 | entries_ex_5_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_408 = _issue_valids_T_407 | entries_ex_5_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_409 = _issue_valids_T_408 | entries_ex_5_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_410 = _issue_valids_T_409 | entries_ex_5_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_411 = _issue_valids_T_410 | entries_ex_5_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_412 = _issue_valids_T_396 | _issue_valids_T_411; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_413 = entries_ex_5_bits_deps_st_0 | entries_ex_5_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_414 = _issue_valids_T_413 | entries_ex_5_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_415 = _issue_valids_T_414 | entries_ex_5_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_416 = _issue_valids_T_412 | _issue_valids_T_415; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_417 = ~_issue_valids_T_416; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_418 = entries_ex_5_valid & _issue_valids_T_417; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_419 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_5_1 = _issue_valids_T_418 & _issue_valids_T_419; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_420 = entries_ex_6_bits_deps_ld_0 | entries_ex_6_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_421 = _issue_valids_T_420 | entries_ex_6_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_422 = _issue_valids_T_421 | entries_ex_6_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_423 = _issue_valids_T_422 | entries_ex_6_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_424 = _issue_valids_T_423 | entries_ex_6_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_425 = _issue_valids_T_424 | entries_ex_6_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_426 = _issue_valids_T_425 | entries_ex_6_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_427 = entries_ex_6_bits_deps_ex_0 | entries_ex_6_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_428 = _issue_valids_T_427 | entries_ex_6_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_429 = _issue_valids_T_428 | entries_ex_6_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_430 = _issue_valids_T_429 | entries_ex_6_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_431 = _issue_valids_T_430 | entries_ex_6_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_432 = _issue_valids_T_431 | entries_ex_6_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_433 = _issue_valids_T_432 | entries_ex_6_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_434 = _issue_valids_T_433 | entries_ex_6_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_435 = _issue_valids_T_434 | entries_ex_6_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_436 = _issue_valids_T_435 | entries_ex_6_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_437 = _issue_valids_T_436 | entries_ex_6_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_438 = _issue_valids_T_437 | entries_ex_6_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_439 = _issue_valids_T_438 | entries_ex_6_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_440 = _issue_valids_T_439 | entries_ex_6_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_441 = _issue_valids_T_440 | entries_ex_6_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_442 = _issue_valids_T_426 | _issue_valids_T_441; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_443 = entries_ex_6_bits_deps_st_0 | entries_ex_6_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_444 = _issue_valids_T_443 | entries_ex_6_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_445 = _issue_valids_T_444 | entries_ex_6_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_446 = _issue_valids_T_442 | _issue_valids_T_445; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_447 = ~_issue_valids_T_446; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_448 = entries_ex_6_valid & _issue_valids_T_447; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_449 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_6_1 = _issue_valids_T_448 & _issue_valids_T_449; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_450 = entries_ex_7_bits_deps_ld_0 | entries_ex_7_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_451 = _issue_valids_T_450 | entries_ex_7_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_452 = _issue_valids_T_451 | entries_ex_7_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_453 = _issue_valids_T_452 | entries_ex_7_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_454 = _issue_valids_T_453 | entries_ex_7_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_455 = _issue_valids_T_454 | entries_ex_7_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_456 = _issue_valids_T_455 | entries_ex_7_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_457 = entries_ex_7_bits_deps_ex_0 | entries_ex_7_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_458 = _issue_valids_T_457 | entries_ex_7_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_459 = _issue_valids_T_458 | entries_ex_7_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_460 = _issue_valids_T_459 | entries_ex_7_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_461 = _issue_valids_T_460 | entries_ex_7_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_462 = _issue_valids_T_461 | entries_ex_7_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_463 = _issue_valids_T_462 | entries_ex_7_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_464 = _issue_valids_T_463 | entries_ex_7_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_465 = _issue_valids_T_464 | entries_ex_7_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_466 = _issue_valids_T_465 | entries_ex_7_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_467 = _issue_valids_T_466 | entries_ex_7_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_468 = _issue_valids_T_467 | entries_ex_7_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_469 = _issue_valids_T_468 | entries_ex_7_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_470 = _issue_valids_T_469 | entries_ex_7_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_471 = _issue_valids_T_470 | entries_ex_7_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_472 = _issue_valids_T_456 | _issue_valids_T_471; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_473 = entries_ex_7_bits_deps_st_0 | entries_ex_7_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_474 = _issue_valids_T_473 | entries_ex_7_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_475 = _issue_valids_T_474 | entries_ex_7_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_476 = _issue_valids_T_472 | _issue_valids_T_475; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_477 = ~_issue_valids_T_476; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_478 = entries_ex_7_valid & _issue_valids_T_477; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_479 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_7_1 = _issue_valids_T_478 & _issue_valids_T_479; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_480 = entries_ex_8_bits_deps_ld_0 | entries_ex_8_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_481 = _issue_valids_T_480 | entries_ex_8_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_482 = _issue_valids_T_481 | entries_ex_8_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_483 = _issue_valids_T_482 | entries_ex_8_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_484 = _issue_valids_T_483 | entries_ex_8_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_485 = _issue_valids_T_484 | entries_ex_8_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_486 = _issue_valids_T_485 | entries_ex_8_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_487 = entries_ex_8_bits_deps_ex_0 | entries_ex_8_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_488 = _issue_valids_T_487 | entries_ex_8_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_489 = _issue_valids_T_488 | entries_ex_8_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_490 = _issue_valids_T_489 | entries_ex_8_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_491 = _issue_valids_T_490 | entries_ex_8_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_492 = _issue_valids_T_491 | entries_ex_8_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_493 = _issue_valids_T_492 | entries_ex_8_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_494 = _issue_valids_T_493 | entries_ex_8_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_495 = _issue_valids_T_494 | entries_ex_8_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_496 = _issue_valids_T_495 | entries_ex_8_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_497 = _issue_valids_T_496 | entries_ex_8_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_498 = _issue_valids_T_497 | entries_ex_8_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_499 = _issue_valids_T_498 | entries_ex_8_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_500 = _issue_valids_T_499 | entries_ex_8_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_501 = _issue_valids_T_500 | entries_ex_8_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_502 = _issue_valids_T_486 | _issue_valids_T_501; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_503 = entries_ex_8_bits_deps_st_0 | entries_ex_8_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_504 = _issue_valids_T_503 | entries_ex_8_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_505 = _issue_valids_T_504 | entries_ex_8_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_506 = _issue_valids_T_502 | _issue_valids_T_505; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_507 = ~_issue_valids_T_506; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_508 = entries_ex_8_valid & _issue_valids_T_507; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_509 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_8 = _issue_valids_T_508 & _issue_valids_T_509; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_510 = entries_ex_9_bits_deps_ld_0 | entries_ex_9_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_511 = _issue_valids_T_510 | entries_ex_9_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_512 = _issue_valids_T_511 | entries_ex_9_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_513 = _issue_valids_T_512 | entries_ex_9_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_514 = _issue_valids_T_513 | entries_ex_9_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_515 = _issue_valids_T_514 | entries_ex_9_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_516 = _issue_valids_T_515 | entries_ex_9_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_517 = entries_ex_9_bits_deps_ex_0 | entries_ex_9_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_518 = _issue_valids_T_517 | entries_ex_9_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_519 = _issue_valids_T_518 | entries_ex_9_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_520 = _issue_valids_T_519 | entries_ex_9_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_521 = _issue_valids_T_520 | entries_ex_9_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_522 = _issue_valids_T_521 | entries_ex_9_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_523 = _issue_valids_T_522 | entries_ex_9_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_524 = _issue_valids_T_523 | entries_ex_9_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_525 = _issue_valids_T_524 | entries_ex_9_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_526 = _issue_valids_T_525 | entries_ex_9_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_527 = _issue_valids_T_526 | entries_ex_9_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_528 = _issue_valids_T_527 | entries_ex_9_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_529 = _issue_valids_T_528 | entries_ex_9_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_530 = _issue_valids_T_529 | entries_ex_9_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_531 = _issue_valids_T_530 | entries_ex_9_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_532 = _issue_valids_T_516 | _issue_valids_T_531; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_533 = entries_ex_9_bits_deps_st_0 | entries_ex_9_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_534 = _issue_valids_T_533 | entries_ex_9_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_535 = _issue_valids_T_534 | entries_ex_9_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_536 = _issue_valids_T_532 | _issue_valids_T_535; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_537 = ~_issue_valids_T_536; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_538 = entries_ex_9_valid & _issue_valids_T_537; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_539 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_9 = _issue_valids_T_538 & _issue_valids_T_539; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_540 = entries_ex_10_bits_deps_ld_0 | entries_ex_10_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_541 = _issue_valids_T_540 | entries_ex_10_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_542 = _issue_valids_T_541 | entries_ex_10_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_543 = _issue_valids_T_542 | entries_ex_10_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_544 = _issue_valids_T_543 | entries_ex_10_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_545 = _issue_valids_T_544 | entries_ex_10_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_546 = _issue_valids_T_545 | entries_ex_10_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_547 = entries_ex_10_bits_deps_ex_0 | entries_ex_10_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_548 = _issue_valids_T_547 | entries_ex_10_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_549 = _issue_valids_T_548 | entries_ex_10_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_550 = _issue_valids_T_549 | entries_ex_10_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_551 = _issue_valids_T_550 | entries_ex_10_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_552 = _issue_valids_T_551 | entries_ex_10_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_553 = _issue_valids_T_552 | entries_ex_10_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_554 = _issue_valids_T_553 | entries_ex_10_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_555 = _issue_valids_T_554 | entries_ex_10_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_556 = _issue_valids_T_555 | entries_ex_10_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_557 = _issue_valids_T_556 | entries_ex_10_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_558 = _issue_valids_T_557 | entries_ex_10_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_559 = _issue_valids_T_558 | entries_ex_10_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_560 = _issue_valids_T_559 | entries_ex_10_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_561 = _issue_valids_T_560 | entries_ex_10_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_562 = _issue_valids_T_546 | _issue_valids_T_561; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_563 = entries_ex_10_bits_deps_st_0 | entries_ex_10_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_564 = _issue_valids_T_563 | entries_ex_10_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_565 = _issue_valids_T_564 | entries_ex_10_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_566 = _issue_valids_T_562 | _issue_valids_T_565; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_567 = ~_issue_valids_T_566; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_568 = entries_ex_10_valid & _issue_valids_T_567; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_569 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_10 = _issue_valids_T_568 & _issue_valids_T_569; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_570 = entries_ex_11_bits_deps_ld_0 | entries_ex_11_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_571 = _issue_valids_T_570 | entries_ex_11_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_572 = _issue_valids_T_571 | entries_ex_11_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_573 = _issue_valids_T_572 | entries_ex_11_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_574 = _issue_valids_T_573 | entries_ex_11_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_575 = _issue_valids_T_574 | entries_ex_11_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_576 = _issue_valids_T_575 | entries_ex_11_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_577 = entries_ex_11_bits_deps_ex_0 | entries_ex_11_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_578 = _issue_valids_T_577 | entries_ex_11_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_579 = _issue_valids_T_578 | entries_ex_11_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_580 = _issue_valids_T_579 | entries_ex_11_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_581 = _issue_valids_T_580 | entries_ex_11_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_582 = _issue_valids_T_581 | entries_ex_11_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_583 = _issue_valids_T_582 | entries_ex_11_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_584 = _issue_valids_T_583 | entries_ex_11_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_585 = _issue_valids_T_584 | entries_ex_11_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_586 = _issue_valids_T_585 | entries_ex_11_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_587 = _issue_valids_T_586 | entries_ex_11_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_588 = _issue_valids_T_587 | entries_ex_11_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_589 = _issue_valids_T_588 | entries_ex_11_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_590 = _issue_valids_T_589 | entries_ex_11_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_591 = _issue_valids_T_590 | entries_ex_11_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_592 = _issue_valids_T_576 | _issue_valids_T_591; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_593 = entries_ex_11_bits_deps_st_0 | entries_ex_11_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_594 = _issue_valids_T_593 | entries_ex_11_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_595 = _issue_valids_T_594 | entries_ex_11_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_596 = _issue_valids_T_592 | _issue_valids_T_595; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_597 = ~_issue_valids_T_596; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_598 = entries_ex_11_valid & _issue_valids_T_597; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_599 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_11 = _issue_valids_T_598 & _issue_valids_T_599; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_600 = entries_ex_12_bits_deps_ld_0 | entries_ex_12_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_601 = _issue_valids_T_600 | entries_ex_12_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_602 = _issue_valids_T_601 | entries_ex_12_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_603 = _issue_valids_T_602 | entries_ex_12_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_604 = _issue_valids_T_603 | entries_ex_12_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_605 = _issue_valids_T_604 | entries_ex_12_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_606 = _issue_valids_T_605 | entries_ex_12_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_607 = entries_ex_12_bits_deps_ex_0 | entries_ex_12_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_608 = _issue_valids_T_607 | entries_ex_12_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_609 = _issue_valids_T_608 | entries_ex_12_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_610 = _issue_valids_T_609 | entries_ex_12_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_611 = _issue_valids_T_610 | entries_ex_12_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_612 = _issue_valids_T_611 | entries_ex_12_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_613 = _issue_valids_T_612 | entries_ex_12_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_614 = _issue_valids_T_613 | entries_ex_12_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_615 = _issue_valids_T_614 | entries_ex_12_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_616 = _issue_valids_T_615 | entries_ex_12_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_617 = _issue_valids_T_616 | entries_ex_12_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_618 = _issue_valids_T_617 | entries_ex_12_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_619 = _issue_valids_T_618 | entries_ex_12_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_620 = _issue_valids_T_619 | entries_ex_12_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_621 = _issue_valids_T_620 | entries_ex_12_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_622 = _issue_valids_T_606 | _issue_valids_T_621; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_623 = entries_ex_12_bits_deps_st_0 | entries_ex_12_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_624 = _issue_valids_T_623 | entries_ex_12_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_625 = _issue_valids_T_624 | entries_ex_12_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_626 = _issue_valids_T_622 | _issue_valids_T_625; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_627 = ~_issue_valids_T_626; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_628 = entries_ex_12_valid & _issue_valids_T_627; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_629 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_12 = _issue_valids_T_628 & _issue_valids_T_629; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_630 = entries_ex_13_bits_deps_ld_0 | entries_ex_13_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_631 = _issue_valids_T_630 | entries_ex_13_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_632 = _issue_valids_T_631 | entries_ex_13_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_633 = _issue_valids_T_632 | entries_ex_13_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_634 = _issue_valids_T_633 | entries_ex_13_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_635 = _issue_valids_T_634 | entries_ex_13_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_636 = _issue_valids_T_635 | entries_ex_13_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_637 = entries_ex_13_bits_deps_ex_0 | entries_ex_13_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_638 = _issue_valids_T_637 | entries_ex_13_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_639 = _issue_valids_T_638 | entries_ex_13_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_640 = _issue_valids_T_639 | entries_ex_13_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_641 = _issue_valids_T_640 | entries_ex_13_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_642 = _issue_valids_T_641 | entries_ex_13_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_643 = _issue_valids_T_642 | entries_ex_13_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_644 = _issue_valids_T_643 | entries_ex_13_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_645 = _issue_valids_T_644 | entries_ex_13_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_646 = _issue_valids_T_645 | entries_ex_13_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_647 = _issue_valids_T_646 | entries_ex_13_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_648 = _issue_valids_T_647 | entries_ex_13_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_649 = _issue_valids_T_648 | entries_ex_13_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_650 = _issue_valids_T_649 | entries_ex_13_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_651 = _issue_valids_T_650 | entries_ex_13_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_652 = _issue_valids_T_636 | _issue_valids_T_651; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_653 = entries_ex_13_bits_deps_st_0 | entries_ex_13_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_654 = _issue_valids_T_653 | entries_ex_13_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_655 = _issue_valids_T_654 | entries_ex_13_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_656 = _issue_valids_T_652 | _issue_valids_T_655; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_657 = ~_issue_valids_T_656; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_658 = entries_ex_13_valid & _issue_valids_T_657; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_659 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_13 = _issue_valids_T_658 & _issue_valids_T_659; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_660 = entries_ex_14_bits_deps_ld_0 | entries_ex_14_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_661 = _issue_valids_T_660 | entries_ex_14_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_662 = _issue_valids_T_661 | entries_ex_14_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_663 = _issue_valids_T_662 | entries_ex_14_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_664 = _issue_valids_T_663 | entries_ex_14_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_665 = _issue_valids_T_664 | entries_ex_14_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_666 = _issue_valids_T_665 | entries_ex_14_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_667 = entries_ex_14_bits_deps_ex_0 | entries_ex_14_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_668 = _issue_valids_T_667 | entries_ex_14_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_669 = _issue_valids_T_668 | entries_ex_14_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_670 = _issue_valids_T_669 | entries_ex_14_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_671 = _issue_valids_T_670 | entries_ex_14_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_672 = _issue_valids_T_671 | entries_ex_14_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_673 = _issue_valids_T_672 | entries_ex_14_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_674 = _issue_valids_T_673 | entries_ex_14_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_675 = _issue_valids_T_674 | entries_ex_14_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_676 = _issue_valids_T_675 | entries_ex_14_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_677 = _issue_valids_T_676 | entries_ex_14_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_678 = _issue_valids_T_677 | entries_ex_14_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_679 = _issue_valids_T_678 | entries_ex_14_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_680 = _issue_valids_T_679 | entries_ex_14_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_681 = _issue_valids_T_680 | entries_ex_14_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_682 = _issue_valids_T_666 | _issue_valids_T_681; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_683 = entries_ex_14_bits_deps_st_0 | entries_ex_14_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_684 = _issue_valids_T_683 | entries_ex_14_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_685 = _issue_valids_T_684 | entries_ex_14_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_686 = _issue_valids_T_682 | _issue_valids_T_685; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_687 = ~_issue_valids_T_686; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_688 = entries_ex_14_valid & _issue_valids_T_687; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_689 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_14 = _issue_valids_T_688 & _issue_valids_T_689; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_690 = entries_ex_15_bits_deps_ld_0 | entries_ex_15_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_691 = _issue_valids_T_690 | entries_ex_15_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_692 = _issue_valids_T_691 | entries_ex_15_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_693 = _issue_valids_T_692 | entries_ex_15_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_694 = _issue_valids_T_693 | entries_ex_15_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_695 = _issue_valids_T_694 | entries_ex_15_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_696 = _issue_valids_T_695 | entries_ex_15_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :118:23]
wire _issue_valids_T_697 = entries_ex_15_bits_deps_ex_0 | entries_ex_15_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_698 = _issue_valids_T_697 | entries_ex_15_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_699 = _issue_valids_T_698 | entries_ex_15_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_700 = _issue_valids_T_699 | entries_ex_15_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_701 = _issue_valids_T_700 | entries_ex_15_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_702 = _issue_valids_T_701 | entries_ex_15_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_703 = _issue_valids_T_702 | entries_ex_15_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_704 = _issue_valids_T_703 | entries_ex_15_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_705 = _issue_valids_T_704 | entries_ex_15_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_706 = _issue_valids_T_705 | entries_ex_15_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_707 = _issue_valids_T_706 | entries_ex_15_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_708 = _issue_valids_T_707 | entries_ex_15_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_709 = _issue_valids_T_708 | entries_ex_15_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_710 = _issue_valids_T_709 | entries_ex_15_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_711 = _issue_valids_T_710 | entries_ex_15_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :118:23]
wire _issue_valids_T_712 = _issue_valids_T_696 | _issue_valids_T_711; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_713 = entries_ex_15_bits_deps_st_0 | entries_ex_15_bits_deps_st_1; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_714 = _issue_valids_T_713 | entries_ex_15_bits_deps_st_2; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_715 = _issue_valids_T_714 | entries_ex_15_bits_deps_st_3; // @[ReservationStation.scala:107:110, :118:23]
wire _issue_valids_T_716 = _issue_valids_T_712 | _issue_valids_T_715; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_717 = ~_issue_valids_T_716; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_718 = entries_ex_15_valid & _issue_valids_T_717; // @[ReservationStation.scala:107:39, :118:23, :395:54]
wire _issue_valids_T_719 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75]
wire issue_valids_15 = _issue_valids_T_718 & _issue_valids_T_719; // @[ReservationStation.scala:395:{54,72,75}]
wire [15:0] _issue_sel_enc_T_7 = {issue_valids_15, 15'h0}; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_8 = issue_valids_14 ? 16'h4000 : _issue_sel_enc_T_7; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_9 = issue_valids_13 ? 16'h2000 : _issue_sel_enc_T_8; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_10 = issue_valids_12 ? 16'h1000 : _issue_sel_enc_T_9; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_11 = issue_valids_11 ? 16'h800 : _issue_sel_enc_T_10; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_12 = issue_valids_10 ? 16'h400 : _issue_sel_enc_T_11; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_13 = issue_valids_9 ? 16'h200 : _issue_sel_enc_T_12; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_14 = issue_valids_8 ? 16'h100 : _issue_sel_enc_T_13; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_15 = issue_valids_7_1 ? 16'h80 : _issue_sel_enc_T_14; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_16 = issue_valids_6_1 ? 16'h40 : _issue_sel_enc_T_15; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_17 = issue_valids_5_1 ? 16'h20 : _issue_sel_enc_T_16; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_18 = issue_valids_4_1 ? 16'h10 : _issue_sel_enc_T_17; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_19 = issue_valids_3_1 ? 16'h8 : _issue_sel_enc_T_18; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_20 = issue_valids_2_1 ? 16'h4 : _issue_sel_enc_T_19; // @[Mux.scala:50:70]
wire [15:0] _issue_sel_enc_T_21 = issue_valids_1_1 ? 16'h2 : _issue_sel_enc_T_20; // @[Mux.scala:50:70]
wire [15:0] issue_sel_enc_1 = issue_valids_0_1 ? 16'h1 : _issue_sel_enc_T_21; // @[Mux.scala:50:70]
wire issue_sel_0_1 = issue_sel_enc_1[0]; // @[OneHot.scala:83:30]
wire issue_sel_1_1 = issue_sel_enc_1[1]; // @[OneHot.scala:83:30]
wire issue_sel_2_1 = issue_sel_enc_1[2]; // @[OneHot.scala:83:30]
wire issue_sel_3_1 = issue_sel_enc_1[3]; // @[OneHot.scala:83:30]
wire issue_sel_4_1 = issue_sel_enc_1[4]; // @[OneHot.scala:83:30]
wire issue_sel_5_1 = issue_sel_enc_1[5]; // @[OneHot.scala:83:30]
wire issue_sel_6_1 = issue_sel_enc_1[6]; // @[OneHot.scala:83:30]
wire issue_sel_7_1 = issue_sel_enc_1[7]; // @[OneHot.scala:83:30]
wire issue_sel_8 = issue_sel_enc_1[8]; // @[OneHot.scala:83:30]
wire issue_sel_9 = issue_sel_enc_1[9]; // @[OneHot.scala:83:30]
wire issue_sel_10 = issue_sel_enc_1[10]; // @[OneHot.scala:83:30]
wire issue_sel_11 = issue_sel_enc_1[11]; // @[OneHot.scala:83:30]
wire issue_sel_12 = issue_sel_enc_1[12]; // @[OneHot.scala:83:30]
wire issue_sel_13 = issue_sel_enc_1[13]; // @[OneHot.scala:83:30]
wire issue_sel_14 = issue_sel_enc_1[14]; // @[OneHot.scala:83:30]
wire issue_sel_15 = issue_sel_enc_1[15]; // @[OneHot.scala:83:30]
wire [1:0] issue_id_lo_lo_lo = {issue_sel_1_1, issue_sel_0_1}; // @[OneHot.scala:21:45, :83:30]
wire [1:0] issue_id_lo_lo_hi = {issue_sel_3_1, issue_sel_2_1}; // @[OneHot.scala:21:45, :83:30]
wire [3:0] issue_id_lo_lo_1 = {issue_id_lo_lo_hi, issue_id_lo_lo_lo}; // @[OneHot.scala:21:45]
wire [1:0] issue_id_lo_hi_lo = {issue_sel_5_1, issue_sel_4_1}; // @[OneHot.scala:21:45, :83:30]
wire [1:0] issue_id_lo_hi_hi = {issue_sel_7_1, issue_sel_6_1}; // @[OneHot.scala:21:45, :83:30]
wire [3:0] issue_id_lo_hi_1 = {issue_id_lo_hi_hi, issue_id_lo_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] issue_id_lo_3 = {issue_id_lo_hi_1, issue_id_lo_lo_1}; // @[OneHot.scala:21:45]
wire [1:0] issue_id_hi_lo_lo = {issue_sel_9, issue_sel_8}; // @[OneHot.scala:21:45, :83:30]
wire [1:0] issue_id_hi_lo_hi = {issue_sel_11, issue_sel_10}; // @[OneHot.scala:21:45, :83:30]
wire [3:0] issue_id_hi_lo_1 = {issue_id_hi_lo_hi, issue_id_hi_lo_lo}; // @[OneHot.scala:21:45]
wire [1:0] issue_id_hi_hi_lo = {issue_sel_13, issue_sel_12}; // @[OneHot.scala:21:45, :83:30]
wire [1:0] issue_id_hi_hi_hi = {issue_sel_15, issue_sel_14}; // @[OneHot.scala:21:45, :83:30]
wire [3:0] issue_id_hi_hi_1 = {issue_id_hi_hi_hi, issue_id_hi_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] issue_id_hi_3 = {issue_id_hi_hi_1, issue_id_hi_lo_1}; // @[OneHot.scala:21:45]
wire [15:0] _issue_id_T_7 = {issue_id_hi_3, issue_id_lo_3}; // @[OneHot.scala:21:45]
wire [7:0] issue_id_hi_4 = _issue_id_T_7[15:8]; // @[OneHot.scala:21:45, :30:18]
wire [7:0] issue_id_lo_4 = _issue_id_T_7[7:0]; // @[OneHot.scala:21:45, :31:18]
wire _issue_id_T_8 = |issue_id_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _issue_id_T_9 = issue_id_hi_4 | issue_id_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] issue_id_hi_5 = _issue_id_T_9[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] issue_id_lo_5 = _issue_id_T_9[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _issue_id_T_10 = |issue_id_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _issue_id_T_11 = issue_id_hi_5 | issue_id_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] issue_id_hi_6 = _issue_id_T_11[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] issue_id_lo_6 = _issue_id_T_11[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _issue_id_T_12 = |issue_id_hi_6; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _issue_id_T_13 = issue_id_hi_6 | issue_id_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _issue_id_T_14 = _issue_id_T_13[1]; // @[OneHot.scala:32:28]
wire [1:0] _issue_id_T_15 = {_issue_id_T_12, _issue_id_T_14}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _issue_id_T_16 = {_issue_id_T_10, _issue_id_T_15}; // @[OneHot.scala:32:{10,14}]
wire [3:0] issue_id_1 = {_issue_id_T_8, _issue_id_T_16}; // @[OneHot.scala:32:{10,14}]
assign global_issue_id_1 = {2'h1, issue_id_1}; // @[OneHot.scala:32:10]
assign io_issue_ex_rob_id_0 = global_issue_id_1; // @[ReservationStation.scala:26:7, :398:30]
wire _issue_entry_WIRE_285; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_q; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_is_config; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_143_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_143_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_143_opa_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_143_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_143_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_143_opa_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opa_is_dst; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_143_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_143_opb_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_143_opb_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_143_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_143_opb_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_143_opb_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_opb_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_issued; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_complete_on_issue; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_143_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_funct_0 = issue_entry_1_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_143_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_rs2_0 = issue_entry_1_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_143_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_rs1_0 = issue_entry_1_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_xd_0 = issue_entry_1_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_xs1_0 = issue_entry_1_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_xs2_0 = issue_entry_1_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_143_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_rd_0 = issue_entry_1_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_143_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_inst_opcode_0 = issue_entry_1_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_143_cmd_cmd_rs1; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_rs1_0 = issue_entry_1_bits_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_143_cmd_cmd_rs2; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_rs2_0 = issue_entry_1_bits_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_debug; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_debug_0 = issue_entry_1_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_cease; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_cease_0 = issue_entry_1_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_wfi_0 = issue_entry_1_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_143_cmd_cmd_status_isa; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_isa_0 = issue_entry_1_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_dprv_0 = issue_entry_1_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_dv; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_dv_0 = issue_entry_1_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_prv; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_prv_0 = issue_entry_1_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_v; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_v_0 = issue_entry_1_bits_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_sd; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_sd_0 = issue_entry_1_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_143_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_zero2_0 = issue_entry_1_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_mpv_0 = issue_entry_1_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_gva; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_gva_0 = issue_entry_1_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_mbe_0 = issue_entry_1_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_sbe_0 = issue_entry_1_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_sxl_0 = issue_entry_1_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_uxl_0 = issue_entry_1_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_sd_rv32_0 = issue_entry_1_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_143_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_zero1_0 = issue_entry_1_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_tsr_0 = issue_entry_1_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_tw; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_tw_0 = issue_entry_1_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_tvm_0 = issue_entry_1_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_mxr_0 = issue_entry_1_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_sum; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_sum_0 = issue_entry_1_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_mprv_0 = issue_entry_1_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_xs; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_xs_0 = issue_entry_1_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_fs; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_fs_0 = issue_entry_1_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_mpp_0 = issue_entry_1_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_143_cmd_cmd_status_vs; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_vs_0 = issue_entry_1_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_spp; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_spp_0 = issue_entry_1_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_mpie_0 = issue_entry_1_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_ube; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_ube_0 = issue_entry_1_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_spie; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_spie_0 = issue_entry_1_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_upie; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_upie_0 = issue_entry_1_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_mie; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_mie_0 = issue_entry_1_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_hie; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_hie_0 = issue_entry_1_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_sie; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_sie_0 = issue_entry_1_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_cmd_status_uie; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_cmd_status_uie_0 = issue_entry_1_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_rob_id_valid; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_rob_id_valid = issue_entry_1_bits_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_143_cmd_rob_id_bits; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_rob_id_bits = issue_entry_1_bits_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_from_matmul_fsm_0 = issue_entry_1_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_cmd_from_conv_fsm; // @[Mux.scala:30:73]
assign io_issue_ex_cmd_from_conv_fsm_0 = issue_entry_1_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ld_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_ex_15; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_st_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_st_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_st_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_143_deps_st_3; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_143_allocated_at; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_1_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_1_bits_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_1_bits_opa_bits_start_data; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_1_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_1_bits_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_1_bits_opa_bits_end_data; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_valid; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_start_accumulate; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_1_bits_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_1_bits_opb_bits_start_garbage; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_1_bits_opb_bits_start_data; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_end_accumulate; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_1_bits_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_1_bits_opb_bits_end_garbage; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_1_bits_opb_bits_end_data; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_bits_wraps_around; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opb_valid; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_0; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_1; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_2; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_3; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_4; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_5; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_6; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ld_7; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_0; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_1; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_2; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_3; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_4; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_5; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_6; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_7; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_8; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_9; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_10; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_11; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_12; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_13; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_14; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_ex_15; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_st_0; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_st_1; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_st_2; // @[Mux.scala:30:73]
wire issue_entry_1_bits_deps_st_3; // @[Mux.scala:30:73]
wire [1:0] issue_entry_1_bits_q; // @[Mux.scala:30:73]
wire issue_entry_1_bits_is_config; // @[Mux.scala:30:73]
wire issue_entry_1_bits_opa_is_dst; // @[Mux.scala:30:73]
wire issue_entry_1_bits_issued; // @[Mux.scala:30:73]
wire issue_entry_1_bits_complete_on_issue; // @[Mux.scala:30:73]
wire [31:0] issue_entry_1_bits_allocated_at; // @[Mux.scala:30:73]
wire issue_entry_1_valid; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_284; // @[Mux.scala:30:73]
assign issue_entry_1_bits_q = _issue_entry_WIRE_143_q; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_283; // @[Mux.scala:30:73]
assign issue_entry_1_bits_is_config = _issue_entry_WIRE_143_is_config; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_valid; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_valid = _issue_entry_WIRE_143_opa_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_start_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_start_is_acc_addr = _issue_entry_WIRE_143_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_start_accumulate; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_start_accumulate = _issue_entry_WIRE_143_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_143_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_259_bits_start_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_start_norm_cmd = _issue_entry_WIRE_143_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_259_bits_start_garbage; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_start_garbage = _issue_entry_WIRE_143_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_start_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_start_garbage_bit = _issue_entry_WIRE_143_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_259_bits_start_data; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_start_data = _issue_entry_WIRE_143_opa_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_end_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_end_is_acc_addr = _issue_entry_WIRE_143_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_end_accumulate; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_end_accumulate = _issue_entry_WIRE_143_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_143_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_259_bits_end_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_end_norm_cmd = _issue_entry_WIRE_143_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_259_bits_end_garbage; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_end_garbage = _issue_entry_WIRE_143_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_end_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_end_garbage_bit = _issue_entry_WIRE_143_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_259_bits_end_data; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_end_data = _issue_entry_WIRE_143_opa_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_259_bits_wraps_around; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_bits_wraps_around = _issue_entry_WIRE_143_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_258; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opa_is_dst = _issue_entry_WIRE_143_opa_is_dst; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_valid; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_valid = _issue_entry_WIRE_143_opb_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_start_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_start_is_acc_addr = _issue_entry_WIRE_143_opb_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_start_accumulate; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_start_accumulate = _issue_entry_WIRE_143_opb_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_start_read_full_acc_row = _issue_entry_WIRE_143_opb_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_234_bits_start_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_start_norm_cmd = _issue_entry_WIRE_143_opb_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_234_bits_start_garbage; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_start_garbage = _issue_entry_WIRE_143_opb_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_start_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_start_garbage_bit = _issue_entry_WIRE_143_opb_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_234_bits_start_data; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_start_data = _issue_entry_WIRE_143_opb_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_end_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_end_is_acc_addr = _issue_entry_WIRE_143_opb_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_end_accumulate; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_end_accumulate = _issue_entry_WIRE_143_opb_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_end_read_full_acc_row = _issue_entry_WIRE_143_opb_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_234_bits_end_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_end_norm_cmd = _issue_entry_WIRE_143_opb_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_234_bits_end_garbage; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_end_garbage = _issue_entry_WIRE_143_opb_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_end_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_end_garbage_bit = _issue_entry_WIRE_143_opb_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_234_bits_end_data; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_end_data = _issue_entry_WIRE_143_opb_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_234_bits_wraps_around; // @[Mux.scala:30:73]
assign issue_entry_1_bits_opb_bits_wraps_around = _issue_entry_WIRE_143_opb_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_233; // @[Mux.scala:30:73]
assign issue_entry_1_bits_issued = _issue_entry_WIRE_143_issued; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_232; // @[Mux.scala:30:73]
assign issue_entry_1_bits_complete_on_issue = _issue_entry_WIRE_143_complete_on_issue; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_176_cmd_inst_funct; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_funct = _issue_entry_WIRE_143_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_176_cmd_inst_rs2; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_rs2 = _issue_entry_WIRE_143_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_176_cmd_inst_rs1; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_rs1 = _issue_entry_WIRE_143_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_inst_xd; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_xd = _issue_entry_WIRE_143_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_inst_xs1; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_xs1 = _issue_entry_WIRE_143_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_inst_xs2; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_xs2 = _issue_entry_WIRE_143_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_176_cmd_inst_rd; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_rd = _issue_entry_WIRE_143_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_176_cmd_inst_opcode; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_inst_opcode = _issue_entry_WIRE_143_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_176_cmd_rs1; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_rs1 = _issue_entry_WIRE_143_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_176_cmd_rs2; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_rs2 = _issue_entry_WIRE_143_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_debug; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_debug = _issue_entry_WIRE_143_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_cease; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_cease = _issue_entry_WIRE_143_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_wfi; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_wfi = _issue_entry_WIRE_143_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_176_cmd_status_isa; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_isa = _issue_entry_WIRE_143_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_dprv; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_dprv = _issue_entry_WIRE_143_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_dv; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_dv = _issue_entry_WIRE_143_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_prv; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_prv = _issue_entry_WIRE_143_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_v; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_v = _issue_entry_WIRE_143_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_sd; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_sd = _issue_entry_WIRE_143_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_176_cmd_status_zero2; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_zero2 = _issue_entry_WIRE_143_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_mpv; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_mpv = _issue_entry_WIRE_143_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_gva; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_gva = _issue_entry_WIRE_143_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_mbe; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_mbe = _issue_entry_WIRE_143_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_sbe; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_sbe = _issue_entry_WIRE_143_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_sxl; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_sxl = _issue_entry_WIRE_143_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_uxl; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_uxl = _issue_entry_WIRE_143_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_sd_rv32; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_143_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_176_cmd_status_zero1; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_zero1 = _issue_entry_WIRE_143_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_tsr; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_tsr = _issue_entry_WIRE_143_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_tw; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_tw = _issue_entry_WIRE_143_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_tvm; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_tvm = _issue_entry_WIRE_143_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_mxr; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_mxr = _issue_entry_WIRE_143_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_sum; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_sum = _issue_entry_WIRE_143_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_mprv; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_mprv = _issue_entry_WIRE_143_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_xs; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_xs = _issue_entry_WIRE_143_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_fs; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_fs = _issue_entry_WIRE_143_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_mpp; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_mpp = _issue_entry_WIRE_143_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_176_cmd_status_vs; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_vs = _issue_entry_WIRE_143_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_spp; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_spp = _issue_entry_WIRE_143_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_mpie; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_mpie = _issue_entry_WIRE_143_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_ube; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_ube = _issue_entry_WIRE_143_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_spie; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_spie = _issue_entry_WIRE_143_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_upie; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_upie = _issue_entry_WIRE_143_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_mie; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_mie = _issue_entry_WIRE_143_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_hie; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_hie = _issue_entry_WIRE_143_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_sie; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_sie = _issue_entry_WIRE_143_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_cmd_status_uie; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_cmd_status_uie = _issue_entry_WIRE_143_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_rob_id_valid; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_rob_id_valid = _issue_entry_WIRE_143_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_176_rob_id_bits; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_rob_id_bits = _issue_entry_WIRE_143_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_from_matmul_fsm; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_from_matmul_fsm = _issue_entry_WIRE_143_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_176_from_conv_fsm; // @[Mux.scala:30:73]
assign issue_entry_1_bits_cmd_from_conv_fsm = _issue_entry_WIRE_143_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_0; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_0 = _issue_entry_WIRE_143_deps_ld_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_1; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_1 = _issue_entry_WIRE_143_deps_ld_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_2; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_2 = _issue_entry_WIRE_143_deps_ld_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_3; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_3 = _issue_entry_WIRE_143_deps_ld_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_4; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_4 = _issue_entry_WIRE_143_deps_ld_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_5; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_5 = _issue_entry_WIRE_143_deps_ld_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_6; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_6 = _issue_entry_WIRE_143_deps_ld_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_167_7; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ld_7 = _issue_entry_WIRE_143_deps_ld_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_0; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_0 = _issue_entry_WIRE_143_deps_ex_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_1; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_1 = _issue_entry_WIRE_143_deps_ex_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_2; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_2 = _issue_entry_WIRE_143_deps_ex_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_3; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_3 = _issue_entry_WIRE_143_deps_ex_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_4; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_4 = _issue_entry_WIRE_143_deps_ex_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_5; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_5 = _issue_entry_WIRE_143_deps_ex_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_6; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_6 = _issue_entry_WIRE_143_deps_ex_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_7; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_7 = _issue_entry_WIRE_143_deps_ex_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_8; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_8 = _issue_entry_WIRE_143_deps_ex_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_9; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_9 = _issue_entry_WIRE_143_deps_ex_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_10; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_10 = _issue_entry_WIRE_143_deps_ex_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_11; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_11 = _issue_entry_WIRE_143_deps_ex_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_12; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_12 = _issue_entry_WIRE_143_deps_ex_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_13; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_13 = _issue_entry_WIRE_143_deps_ex_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_14; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_14 = _issue_entry_WIRE_143_deps_ex_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_150_15; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_ex_15 = _issue_entry_WIRE_143_deps_ex_15; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_145_0; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_st_0 = _issue_entry_WIRE_143_deps_st_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_145_1; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_st_1 = _issue_entry_WIRE_143_deps_st_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_145_2; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_st_2 = _issue_entry_WIRE_143_deps_st_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_145_3; // @[Mux.scala:30:73]
assign issue_entry_1_bits_deps_st_3 = _issue_entry_WIRE_143_deps_st_3; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_144; // @[Mux.scala:30:73]
assign issue_entry_1_bits_allocated_at = _issue_entry_WIRE_143_allocated_at; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1802 = issue_sel_0_1 ? entries_ex_0_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1803 = issue_sel_1_1 ? entries_ex_1_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1804 = issue_sel_2_1 ? entries_ex_2_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1805 = issue_sel_3_1 ? entries_ex_3_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1806 = issue_sel_4_1 ? entries_ex_4_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1807 = issue_sel_5_1 ? entries_ex_5_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1808 = issue_sel_6_1 ? entries_ex_6_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1809 = issue_sel_7_1 ? entries_ex_7_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1810 = issue_sel_8 ? entries_ex_8_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1811 = issue_sel_9 ? entries_ex_9_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1812 = issue_sel_10 ? entries_ex_10_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1813 = issue_sel_11 ? entries_ex_11_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1814 = issue_sel_12 ? entries_ex_12_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1815 = issue_sel_13 ? entries_ex_13_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1816 = issue_sel_14 ? entries_ex_14_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1817 = issue_sel_15 ? entries_ex_15_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_1818 = _issue_entry_T_1802 | _issue_entry_T_1803; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1819 = _issue_entry_T_1818 | _issue_entry_T_1804; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1820 = _issue_entry_T_1819 | _issue_entry_T_1805; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1821 = _issue_entry_T_1820 | _issue_entry_T_1806; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1822 = _issue_entry_T_1821 | _issue_entry_T_1807; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1823 = _issue_entry_T_1822 | _issue_entry_T_1808; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1824 = _issue_entry_T_1823 | _issue_entry_T_1809; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1825 = _issue_entry_T_1824 | _issue_entry_T_1810; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1826 = _issue_entry_T_1825 | _issue_entry_T_1811; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1827 = _issue_entry_T_1826 | _issue_entry_T_1812; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1828 = _issue_entry_T_1827 | _issue_entry_T_1813; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1829 = _issue_entry_T_1828 | _issue_entry_T_1814; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1830 = _issue_entry_T_1829 | _issue_entry_T_1815; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1831 = _issue_entry_T_1830 | _issue_entry_T_1816; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_1832 = _issue_entry_T_1831 | _issue_entry_T_1817; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_144 = _issue_entry_T_1832; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_allocated_at = _issue_entry_WIRE_144; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_146; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_st_0 = _issue_entry_WIRE_145_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_147; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_st_1 = _issue_entry_WIRE_145_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_148; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_st_2 = _issue_entry_WIRE_145_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_149; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_st_3 = _issue_entry_WIRE_145_3; // @[Mux.scala:30:73]
wire _issue_entry_T_1833 = issue_sel_0_1 & entries_ex_0_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1834 = issue_sel_1_1 & entries_ex_1_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1835 = issue_sel_2_1 & entries_ex_2_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1836 = issue_sel_3_1 & entries_ex_3_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1837 = issue_sel_4_1 & entries_ex_4_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1838 = issue_sel_5_1 & entries_ex_5_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1839 = issue_sel_6_1 & entries_ex_6_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1840 = issue_sel_7_1 & entries_ex_7_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1841 = issue_sel_8 & entries_ex_8_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1842 = issue_sel_9 & entries_ex_9_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1843 = issue_sel_10 & entries_ex_10_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1844 = issue_sel_11 & entries_ex_11_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1845 = issue_sel_12 & entries_ex_12_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1846 = issue_sel_13 & entries_ex_13_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1847 = issue_sel_14 & entries_ex_14_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1848 = issue_sel_15 & entries_ex_15_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1849 = _issue_entry_T_1833 | _issue_entry_T_1834; // @[Mux.scala:30:73]
wire _issue_entry_T_1850 = _issue_entry_T_1849 | _issue_entry_T_1835; // @[Mux.scala:30:73]
wire _issue_entry_T_1851 = _issue_entry_T_1850 | _issue_entry_T_1836; // @[Mux.scala:30:73]
wire _issue_entry_T_1852 = _issue_entry_T_1851 | _issue_entry_T_1837; // @[Mux.scala:30:73]
wire _issue_entry_T_1853 = _issue_entry_T_1852 | _issue_entry_T_1838; // @[Mux.scala:30:73]
wire _issue_entry_T_1854 = _issue_entry_T_1853 | _issue_entry_T_1839; // @[Mux.scala:30:73]
wire _issue_entry_T_1855 = _issue_entry_T_1854 | _issue_entry_T_1840; // @[Mux.scala:30:73]
wire _issue_entry_T_1856 = _issue_entry_T_1855 | _issue_entry_T_1841; // @[Mux.scala:30:73]
wire _issue_entry_T_1857 = _issue_entry_T_1856 | _issue_entry_T_1842; // @[Mux.scala:30:73]
wire _issue_entry_T_1858 = _issue_entry_T_1857 | _issue_entry_T_1843; // @[Mux.scala:30:73]
wire _issue_entry_T_1859 = _issue_entry_T_1858 | _issue_entry_T_1844; // @[Mux.scala:30:73]
wire _issue_entry_T_1860 = _issue_entry_T_1859 | _issue_entry_T_1845; // @[Mux.scala:30:73]
wire _issue_entry_T_1861 = _issue_entry_T_1860 | _issue_entry_T_1846; // @[Mux.scala:30:73]
wire _issue_entry_T_1862 = _issue_entry_T_1861 | _issue_entry_T_1847; // @[Mux.scala:30:73]
wire _issue_entry_T_1863 = _issue_entry_T_1862 | _issue_entry_T_1848; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_146 = _issue_entry_T_1863; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_145_0 = _issue_entry_WIRE_146; // @[Mux.scala:30:73]
wire _issue_entry_T_1864 = issue_sel_0_1 & entries_ex_0_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1865 = issue_sel_1_1 & entries_ex_1_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1866 = issue_sel_2_1 & entries_ex_2_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1867 = issue_sel_3_1 & entries_ex_3_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1868 = issue_sel_4_1 & entries_ex_4_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1869 = issue_sel_5_1 & entries_ex_5_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1870 = issue_sel_6_1 & entries_ex_6_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1871 = issue_sel_7_1 & entries_ex_7_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1872 = issue_sel_8 & entries_ex_8_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1873 = issue_sel_9 & entries_ex_9_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1874 = issue_sel_10 & entries_ex_10_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1875 = issue_sel_11 & entries_ex_11_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1876 = issue_sel_12 & entries_ex_12_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1877 = issue_sel_13 & entries_ex_13_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1878 = issue_sel_14 & entries_ex_14_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1879 = issue_sel_15 & entries_ex_15_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1880 = _issue_entry_T_1864 | _issue_entry_T_1865; // @[Mux.scala:30:73]
wire _issue_entry_T_1881 = _issue_entry_T_1880 | _issue_entry_T_1866; // @[Mux.scala:30:73]
wire _issue_entry_T_1882 = _issue_entry_T_1881 | _issue_entry_T_1867; // @[Mux.scala:30:73]
wire _issue_entry_T_1883 = _issue_entry_T_1882 | _issue_entry_T_1868; // @[Mux.scala:30:73]
wire _issue_entry_T_1884 = _issue_entry_T_1883 | _issue_entry_T_1869; // @[Mux.scala:30:73]
wire _issue_entry_T_1885 = _issue_entry_T_1884 | _issue_entry_T_1870; // @[Mux.scala:30:73]
wire _issue_entry_T_1886 = _issue_entry_T_1885 | _issue_entry_T_1871; // @[Mux.scala:30:73]
wire _issue_entry_T_1887 = _issue_entry_T_1886 | _issue_entry_T_1872; // @[Mux.scala:30:73]
wire _issue_entry_T_1888 = _issue_entry_T_1887 | _issue_entry_T_1873; // @[Mux.scala:30:73]
wire _issue_entry_T_1889 = _issue_entry_T_1888 | _issue_entry_T_1874; // @[Mux.scala:30:73]
wire _issue_entry_T_1890 = _issue_entry_T_1889 | _issue_entry_T_1875; // @[Mux.scala:30:73]
wire _issue_entry_T_1891 = _issue_entry_T_1890 | _issue_entry_T_1876; // @[Mux.scala:30:73]
wire _issue_entry_T_1892 = _issue_entry_T_1891 | _issue_entry_T_1877; // @[Mux.scala:30:73]
wire _issue_entry_T_1893 = _issue_entry_T_1892 | _issue_entry_T_1878; // @[Mux.scala:30:73]
wire _issue_entry_T_1894 = _issue_entry_T_1893 | _issue_entry_T_1879; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_147 = _issue_entry_T_1894; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_145_1 = _issue_entry_WIRE_147; // @[Mux.scala:30:73]
wire _issue_entry_T_1895 = issue_sel_0_1 & entries_ex_0_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1896 = issue_sel_1_1 & entries_ex_1_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1897 = issue_sel_2_1 & entries_ex_2_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1898 = issue_sel_3_1 & entries_ex_3_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1899 = issue_sel_4_1 & entries_ex_4_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1900 = issue_sel_5_1 & entries_ex_5_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1901 = issue_sel_6_1 & entries_ex_6_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1902 = issue_sel_7_1 & entries_ex_7_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1903 = issue_sel_8 & entries_ex_8_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1904 = issue_sel_9 & entries_ex_9_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1905 = issue_sel_10 & entries_ex_10_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1906 = issue_sel_11 & entries_ex_11_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1907 = issue_sel_12 & entries_ex_12_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1908 = issue_sel_13 & entries_ex_13_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1909 = issue_sel_14 & entries_ex_14_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1910 = issue_sel_15 & entries_ex_15_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_1911 = _issue_entry_T_1895 | _issue_entry_T_1896; // @[Mux.scala:30:73]
wire _issue_entry_T_1912 = _issue_entry_T_1911 | _issue_entry_T_1897; // @[Mux.scala:30:73]
wire _issue_entry_T_1913 = _issue_entry_T_1912 | _issue_entry_T_1898; // @[Mux.scala:30:73]
wire _issue_entry_T_1914 = _issue_entry_T_1913 | _issue_entry_T_1899; // @[Mux.scala:30:73]
wire _issue_entry_T_1915 = _issue_entry_T_1914 | _issue_entry_T_1900; // @[Mux.scala:30:73]
wire _issue_entry_T_1916 = _issue_entry_T_1915 | _issue_entry_T_1901; // @[Mux.scala:30:73]
wire _issue_entry_T_1917 = _issue_entry_T_1916 | _issue_entry_T_1902; // @[Mux.scala:30:73]
wire _issue_entry_T_1918 = _issue_entry_T_1917 | _issue_entry_T_1903; // @[Mux.scala:30:73]
wire _issue_entry_T_1919 = _issue_entry_T_1918 | _issue_entry_T_1904; // @[Mux.scala:30:73]
wire _issue_entry_T_1920 = _issue_entry_T_1919 | _issue_entry_T_1905; // @[Mux.scala:30:73]
wire _issue_entry_T_1921 = _issue_entry_T_1920 | _issue_entry_T_1906; // @[Mux.scala:30:73]
wire _issue_entry_T_1922 = _issue_entry_T_1921 | _issue_entry_T_1907; // @[Mux.scala:30:73]
wire _issue_entry_T_1923 = _issue_entry_T_1922 | _issue_entry_T_1908; // @[Mux.scala:30:73]
wire _issue_entry_T_1924 = _issue_entry_T_1923 | _issue_entry_T_1909; // @[Mux.scala:30:73]
wire _issue_entry_T_1925 = _issue_entry_T_1924 | _issue_entry_T_1910; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_148 = _issue_entry_T_1925; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_145_2 = _issue_entry_WIRE_148; // @[Mux.scala:30:73]
wire _issue_entry_T_1926 = issue_sel_0_1 & entries_ex_0_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1927 = issue_sel_1_1 & entries_ex_1_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1928 = issue_sel_2_1 & entries_ex_2_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1929 = issue_sel_3_1 & entries_ex_3_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1930 = issue_sel_4_1 & entries_ex_4_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1931 = issue_sel_5_1 & entries_ex_5_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1932 = issue_sel_6_1 & entries_ex_6_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1933 = issue_sel_7_1 & entries_ex_7_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1934 = issue_sel_8 & entries_ex_8_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1935 = issue_sel_9 & entries_ex_9_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1936 = issue_sel_10 & entries_ex_10_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1937 = issue_sel_11 & entries_ex_11_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1938 = issue_sel_12 & entries_ex_12_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1939 = issue_sel_13 & entries_ex_13_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1940 = issue_sel_14 & entries_ex_14_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1941 = issue_sel_15 & entries_ex_15_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_1942 = _issue_entry_T_1926 | _issue_entry_T_1927; // @[Mux.scala:30:73]
wire _issue_entry_T_1943 = _issue_entry_T_1942 | _issue_entry_T_1928; // @[Mux.scala:30:73]
wire _issue_entry_T_1944 = _issue_entry_T_1943 | _issue_entry_T_1929; // @[Mux.scala:30:73]
wire _issue_entry_T_1945 = _issue_entry_T_1944 | _issue_entry_T_1930; // @[Mux.scala:30:73]
wire _issue_entry_T_1946 = _issue_entry_T_1945 | _issue_entry_T_1931; // @[Mux.scala:30:73]
wire _issue_entry_T_1947 = _issue_entry_T_1946 | _issue_entry_T_1932; // @[Mux.scala:30:73]
wire _issue_entry_T_1948 = _issue_entry_T_1947 | _issue_entry_T_1933; // @[Mux.scala:30:73]
wire _issue_entry_T_1949 = _issue_entry_T_1948 | _issue_entry_T_1934; // @[Mux.scala:30:73]
wire _issue_entry_T_1950 = _issue_entry_T_1949 | _issue_entry_T_1935; // @[Mux.scala:30:73]
wire _issue_entry_T_1951 = _issue_entry_T_1950 | _issue_entry_T_1936; // @[Mux.scala:30:73]
wire _issue_entry_T_1952 = _issue_entry_T_1951 | _issue_entry_T_1937; // @[Mux.scala:30:73]
wire _issue_entry_T_1953 = _issue_entry_T_1952 | _issue_entry_T_1938; // @[Mux.scala:30:73]
wire _issue_entry_T_1954 = _issue_entry_T_1953 | _issue_entry_T_1939; // @[Mux.scala:30:73]
wire _issue_entry_T_1955 = _issue_entry_T_1954 | _issue_entry_T_1940; // @[Mux.scala:30:73]
wire _issue_entry_T_1956 = _issue_entry_T_1955 | _issue_entry_T_1941; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_149 = _issue_entry_T_1956; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_145_3 = _issue_entry_WIRE_149; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_151; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_0 = _issue_entry_WIRE_150_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_152; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_1 = _issue_entry_WIRE_150_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_153; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_2 = _issue_entry_WIRE_150_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_154; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_3 = _issue_entry_WIRE_150_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_155; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_4 = _issue_entry_WIRE_150_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_156; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_5 = _issue_entry_WIRE_150_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_157; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_6 = _issue_entry_WIRE_150_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_158; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_7 = _issue_entry_WIRE_150_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_159; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_8 = _issue_entry_WIRE_150_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_160; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_9 = _issue_entry_WIRE_150_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_161; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_10 = _issue_entry_WIRE_150_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_162; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_11 = _issue_entry_WIRE_150_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_163; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_12 = _issue_entry_WIRE_150_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_164; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_13 = _issue_entry_WIRE_150_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_165; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_14 = _issue_entry_WIRE_150_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_166; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ex_15 = _issue_entry_WIRE_150_15; // @[Mux.scala:30:73]
wire _issue_entry_T_1957 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1958 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1959 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1960 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1961 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1962 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1963 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1964 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1965 = issue_sel_8 & entries_ex_8_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1966 = issue_sel_9 & entries_ex_9_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1967 = issue_sel_10 & entries_ex_10_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1968 = issue_sel_11 & entries_ex_11_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1969 = issue_sel_12 & entries_ex_12_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1970 = issue_sel_13 & entries_ex_13_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1971 = issue_sel_14 & entries_ex_14_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1972 = issue_sel_15 & entries_ex_15_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_1973 = _issue_entry_T_1957 | _issue_entry_T_1958; // @[Mux.scala:30:73]
wire _issue_entry_T_1974 = _issue_entry_T_1973 | _issue_entry_T_1959; // @[Mux.scala:30:73]
wire _issue_entry_T_1975 = _issue_entry_T_1974 | _issue_entry_T_1960; // @[Mux.scala:30:73]
wire _issue_entry_T_1976 = _issue_entry_T_1975 | _issue_entry_T_1961; // @[Mux.scala:30:73]
wire _issue_entry_T_1977 = _issue_entry_T_1976 | _issue_entry_T_1962; // @[Mux.scala:30:73]
wire _issue_entry_T_1978 = _issue_entry_T_1977 | _issue_entry_T_1963; // @[Mux.scala:30:73]
wire _issue_entry_T_1979 = _issue_entry_T_1978 | _issue_entry_T_1964; // @[Mux.scala:30:73]
wire _issue_entry_T_1980 = _issue_entry_T_1979 | _issue_entry_T_1965; // @[Mux.scala:30:73]
wire _issue_entry_T_1981 = _issue_entry_T_1980 | _issue_entry_T_1966; // @[Mux.scala:30:73]
wire _issue_entry_T_1982 = _issue_entry_T_1981 | _issue_entry_T_1967; // @[Mux.scala:30:73]
wire _issue_entry_T_1983 = _issue_entry_T_1982 | _issue_entry_T_1968; // @[Mux.scala:30:73]
wire _issue_entry_T_1984 = _issue_entry_T_1983 | _issue_entry_T_1969; // @[Mux.scala:30:73]
wire _issue_entry_T_1985 = _issue_entry_T_1984 | _issue_entry_T_1970; // @[Mux.scala:30:73]
wire _issue_entry_T_1986 = _issue_entry_T_1985 | _issue_entry_T_1971; // @[Mux.scala:30:73]
wire _issue_entry_T_1987 = _issue_entry_T_1986 | _issue_entry_T_1972; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_151 = _issue_entry_T_1987; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_0 = _issue_entry_WIRE_151; // @[Mux.scala:30:73]
wire _issue_entry_T_1988 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1989 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1990 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1991 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1992 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1993 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1994 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1995 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1996 = issue_sel_8 & entries_ex_8_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1997 = issue_sel_9 & entries_ex_9_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1998 = issue_sel_10 & entries_ex_10_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_1999 = issue_sel_11 & entries_ex_11_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2000 = issue_sel_12 & entries_ex_12_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2001 = issue_sel_13 & entries_ex_13_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2002 = issue_sel_14 & entries_ex_14_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2003 = issue_sel_15 & entries_ex_15_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2004 = _issue_entry_T_1988 | _issue_entry_T_1989; // @[Mux.scala:30:73]
wire _issue_entry_T_2005 = _issue_entry_T_2004 | _issue_entry_T_1990; // @[Mux.scala:30:73]
wire _issue_entry_T_2006 = _issue_entry_T_2005 | _issue_entry_T_1991; // @[Mux.scala:30:73]
wire _issue_entry_T_2007 = _issue_entry_T_2006 | _issue_entry_T_1992; // @[Mux.scala:30:73]
wire _issue_entry_T_2008 = _issue_entry_T_2007 | _issue_entry_T_1993; // @[Mux.scala:30:73]
wire _issue_entry_T_2009 = _issue_entry_T_2008 | _issue_entry_T_1994; // @[Mux.scala:30:73]
wire _issue_entry_T_2010 = _issue_entry_T_2009 | _issue_entry_T_1995; // @[Mux.scala:30:73]
wire _issue_entry_T_2011 = _issue_entry_T_2010 | _issue_entry_T_1996; // @[Mux.scala:30:73]
wire _issue_entry_T_2012 = _issue_entry_T_2011 | _issue_entry_T_1997; // @[Mux.scala:30:73]
wire _issue_entry_T_2013 = _issue_entry_T_2012 | _issue_entry_T_1998; // @[Mux.scala:30:73]
wire _issue_entry_T_2014 = _issue_entry_T_2013 | _issue_entry_T_1999; // @[Mux.scala:30:73]
wire _issue_entry_T_2015 = _issue_entry_T_2014 | _issue_entry_T_2000; // @[Mux.scala:30:73]
wire _issue_entry_T_2016 = _issue_entry_T_2015 | _issue_entry_T_2001; // @[Mux.scala:30:73]
wire _issue_entry_T_2017 = _issue_entry_T_2016 | _issue_entry_T_2002; // @[Mux.scala:30:73]
wire _issue_entry_T_2018 = _issue_entry_T_2017 | _issue_entry_T_2003; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_152 = _issue_entry_T_2018; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_1 = _issue_entry_WIRE_152; // @[Mux.scala:30:73]
wire _issue_entry_T_2019 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2020 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2021 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2022 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2023 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2024 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2025 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2026 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2027 = issue_sel_8 & entries_ex_8_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2028 = issue_sel_9 & entries_ex_9_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2029 = issue_sel_10 & entries_ex_10_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2030 = issue_sel_11 & entries_ex_11_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2031 = issue_sel_12 & entries_ex_12_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2032 = issue_sel_13 & entries_ex_13_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2033 = issue_sel_14 & entries_ex_14_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2034 = issue_sel_15 & entries_ex_15_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2035 = _issue_entry_T_2019 | _issue_entry_T_2020; // @[Mux.scala:30:73]
wire _issue_entry_T_2036 = _issue_entry_T_2035 | _issue_entry_T_2021; // @[Mux.scala:30:73]
wire _issue_entry_T_2037 = _issue_entry_T_2036 | _issue_entry_T_2022; // @[Mux.scala:30:73]
wire _issue_entry_T_2038 = _issue_entry_T_2037 | _issue_entry_T_2023; // @[Mux.scala:30:73]
wire _issue_entry_T_2039 = _issue_entry_T_2038 | _issue_entry_T_2024; // @[Mux.scala:30:73]
wire _issue_entry_T_2040 = _issue_entry_T_2039 | _issue_entry_T_2025; // @[Mux.scala:30:73]
wire _issue_entry_T_2041 = _issue_entry_T_2040 | _issue_entry_T_2026; // @[Mux.scala:30:73]
wire _issue_entry_T_2042 = _issue_entry_T_2041 | _issue_entry_T_2027; // @[Mux.scala:30:73]
wire _issue_entry_T_2043 = _issue_entry_T_2042 | _issue_entry_T_2028; // @[Mux.scala:30:73]
wire _issue_entry_T_2044 = _issue_entry_T_2043 | _issue_entry_T_2029; // @[Mux.scala:30:73]
wire _issue_entry_T_2045 = _issue_entry_T_2044 | _issue_entry_T_2030; // @[Mux.scala:30:73]
wire _issue_entry_T_2046 = _issue_entry_T_2045 | _issue_entry_T_2031; // @[Mux.scala:30:73]
wire _issue_entry_T_2047 = _issue_entry_T_2046 | _issue_entry_T_2032; // @[Mux.scala:30:73]
wire _issue_entry_T_2048 = _issue_entry_T_2047 | _issue_entry_T_2033; // @[Mux.scala:30:73]
wire _issue_entry_T_2049 = _issue_entry_T_2048 | _issue_entry_T_2034; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_153 = _issue_entry_T_2049; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_2 = _issue_entry_WIRE_153; // @[Mux.scala:30:73]
wire _issue_entry_T_2050 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2051 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2052 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2053 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2054 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2055 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2056 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2057 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2058 = issue_sel_8 & entries_ex_8_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2059 = issue_sel_9 & entries_ex_9_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2060 = issue_sel_10 & entries_ex_10_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2061 = issue_sel_11 & entries_ex_11_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2062 = issue_sel_12 & entries_ex_12_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2063 = issue_sel_13 & entries_ex_13_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2064 = issue_sel_14 & entries_ex_14_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2065 = issue_sel_15 & entries_ex_15_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2066 = _issue_entry_T_2050 | _issue_entry_T_2051; // @[Mux.scala:30:73]
wire _issue_entry_T_2067 = _issue_entry_T_2066 | _issue_entry_T_2052; // @[Mux.scala:30:73]
wire _issue_entry_T_2068 = _issue_entry_T_2067 | _issue_entry_T_2053; // @[Mux.scala:30:73]
wire _issue_entry_T_2069 = _issue_entry_T_2068 | _issue_entry_T_2054; // @[Mux.scala:30:73]
wire _issue_entry_T_2070 = _issue_entry_T_2069 | _issue_entry_T_2055; // @[Mux.scala:30:73]
wire _issue_entry_T_2071 = _issue_entry_T_2070 | _issue_entry_T_2056; // @[Mux.scala:30:73]
wire _issue_entry_T_2072 = _issue_entry_T_2071 | _issue_entry_T_2057; // @[Mux.scala:30:73]
wire _issue_entry_T_2073 = _issue_entry_T_2072 | _issue_entry_T_2058; // @[Mux.scala:30:73]
wire _issue_entry_T_2074 = _issue_entry_T_2073 | _issue_entry_T_2059; // @[Mux.scala:30:73]
wire _issue_entry_T_2075 = _issue_entry_T_2074 | _issue_entry_T_2060; // @[Mux.scala:30:73]
wire _issue_entry_T_2076 = _issue_entry_T_2075 | _issue_entry_T_2061; // @[Mux.scala:30:73]
wire _issue_entry_T_2077 = _issue_entry_T_2076 | _issue_entry_T_2062; // @[Mux.scala:30:73]
wire _issue_entry_T_2078 = _issue_entry_T_2077 | _issue_entry_T_2063; // @[Mux.scala:30:73]
wire _issue_entry_T_2079 = _issue_entry_T_2078 | _issue_entry_T_2064; // @[Mux.scala:30:73]
wire _issue_entry_T_2080 = _issue_entry_T_2079 | _issue_entry_T_2065; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_154 = _issue_entry_T_2080; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_3 = _issue_entry_WIRE_154; // @[Mux.scala:30:73]
wire _issue_entry_T_2081 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2082 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2083 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2084 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2085 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2086 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2087 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2088 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2089 = issue_sel_8 & entries_ex_8_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2090 = issue_sel_9 & entries_ex_9_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2091 = issue_sel_10 & entries_ex_10_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2092 = issue_sel_11 & entries_ex_11_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2093 = issue_sel_12 & entries_ex_12_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2094 = issue_sel_13 & entries_ex_13_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2095 = issue_sel_14 & entries_ex_14_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2096 = issue_sel_15 & entries_ex_15_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2097 = _issue_entry_T_2081 | _issue_entry_T_2082; // @[Mux.scala:30:73]
wire _issue_entry_T_2098 = _issue_entry_T_2097 | _issue_entry_T_2083; // @[Mux.scala:30:73]
wire _issue_entry_T_2099 = _issue_entry_T_2098 | _issue_entry_T_2084; // @[Mux.scala:30:73]
wire _issue_entry_T_2100 = _issue_entry_T_2099 | _issue_entry_T_2085; // @[Mux.scala:30:73]
wire _issue_entry_T_2101 = _issue_entry_T_2100 | _issue_entry_T_2086; // @[Mux.scala:30:73]
wire _issue_entry_T_2102 = _issue_entry_T_2101 | _issue_entry_T_2087; // @[Mux.scala:30:73]
wire _issue_entry_T_2103 = _issue_entry_T_2102 | _issue_entry_T_2088; // @[Mux.scala:30:73]
wire _issue_entry_T_2104 = _issue_entry_T_2103 | _issue_entry_T_2089; // @[Mux.scala:30:73]
wire _issue_entry_T_2105 = _issue_entry_T_2104 | _issue_entry_T_2090; // @[Mux.scala:30:73]
wire _issue_entry_T_2106 = _issue_entry_T_2105 | _issue_entry_T_2091; // @[Mux.scala:30:73]
wire _issue_entry_T_2107 = _issue_entry_T_2106 | _issue_entry_T_2092; // @[Mux.scala:30:73]
wire _issue_entry_T_2108 = _issue_entry_T_2107 | _issue_entry_T_2093; // @[Mux.scala:30:73]
wire _issue_entry_T_2109 = _issue_entry_T_2108 | _issue_entry_T_2094; // @[Mux.scala:30:73]
wire _issue_entry_T_2110 = _issue_entry_T_2109 | _issue_entry_T_2095; // @[Mux.scala:30:73]
wire _issue_entry_T_2111 = _issue_entry_T_2110 | _issue_entry_T_2096; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_155 = _issue_entry_T_2111; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_4 = _issue_entry_WIRE_155; // @[Mux.scala:30:73]
wire _issue_entry_T_2112 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2113 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2114 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2115 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2116 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2117 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2118 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2119 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2120 = issue_sel_8 & entries_ex_8_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2121 = issue_sel_9 & entries_ex_9_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2122 = issue_sel_10 & entries_ex_10_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2123 = issue_sel_11 & entries_ex_11_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2124 = issue_sel_12 & entries_ex_12_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2125 = issue_sel_13 & entries_ex_13_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2126 = issue_sel_14 & entries_ex_14_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2127 = issue_sel_15 & entries_ex_15_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2128 = _issue_entry_T_2112 | _issue_entry_T_2113; // @[Mux.scala:30:73]
wire _issue_entry_T_2129 = _issue_entry_T_2128 | _issue_entry_T_2114; // @[Mux.scala:30:73]
wire _issue_entry_T_2130 = _issue_entry_T_2129 | _issue_entry_T_2115; // @[Mux.scala:30:73]
wire _issue_entry_T_2131 = _issue_entry_T_2130 | _issue_entry_T_2116; // @[Mux.scala:30:73]
wire _issue_entry_T_2132 = _issue_entry_T_2131 | _issue_entry_T_2117; // @[Mux.scala:30:73]
wire _issue_entry_T_2133 = _issue_entry_T_2132 | _issue_entry_T_2118; // @[Mux.scala:30:73]
wire _issue_entry_T_2134 = _issue_entry_T_2133 | _issue_entry_T_2119; // @[Mux.scala:30:73]
wire _issue_entry_T_2135 = _issue_entry_T_2134 | _issue_entry_T_2120; // @[Mux.scala:30:73]
wire _issue_entry_T_2136 = _issue_entry_T_2135 | _issue_entry_T_2121; // @[Mux.scala:30:73]
wire _issue_entry_T_2137 = _issue_entry_T_2136 | _issue_entry_T_2122; // @[Mux.scala:30:73]
wire _issue_entry_T_2138 = _issue_entry_T_2137 | _issue_entry_T_2123; // @[Mux.scala:30:73]
wire _issue_entry_T_2139 = _issue_entry_T_2138 | _issue_entry_T_2124; // @[Mux.scala:30:73]
wire _issue_entry_T_2140 = _issue_entry_T_2139 | _issue_entry_T_2125; // @[Mux.scala:30:73]
wire _issue_entry_T_2141 = _issue_entry_T_2140 | _issue_entry_T_2126; // @[Mux.scala:30:73]
wire _issue_entry_T_2142 = _issue_entry_T_2141 | _issue_entry_T_2127; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_156 = _issue_entry_T_2142; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_5 = _issue_entry_WIRE_156; // @[Mux.scala:30:73]
wire _issue_entry_T_2143 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2144 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2145 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2146 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2147 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2148 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2149 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2150 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2151 = issue_sel_8 & entries_ex_8_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2152 = issue_sel_9 & entries_ex_9_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2153 = issue_sel_10 & entries_ex_10_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2154 = issue_sel_11 & entries_ex_11_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2155 = issue_sel_12 & entries_ex_12_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2156 = issue_sel_13 & entries_ex_13_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2157 = issue_sel_14 & entries_ex_14_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2158 = issue_sel_15 & entries_ex_15_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2159 = _issue_entry_T_2143 | _issue_entry_T_2144; // @[Mux.scala:30:73]
wire _issue_entry_T_2160 = _issue_entry_T_2159 | _issue_entry_T_2145; // @[Mux.scala:30:73]
wire _issue_entry_T_2161 = _issue_entry_T_2160 | _issue_entry_T_2146; // @[Mux.scala:30:73]
wire _issue_entry_T_2162 = _issue_entry_T_2161 | _issue_entry_T_2147; // @[Mux.scala:30:73]
wire _issue_entry_T_2163 = _issue_entry_T_2162 | _issue_entry_T_2148; // @[Mux.scala:30:73]
wire _issue_entry_T_2164 = _issue_entry_T_2163 | _issue_entry_T_2149; // @[Mux.scala:30:73]
wire _issue_entry_T_2165 = _issue_entry_T_2164 | _issue_entry_T_2150; // @[Mux.scala:30:73]
wire _issue_entry_T_2166 = _issue_entry_T_2165 | _issue_entry_T_2151; // @[Mux.scala:30:73]
wire _issue_entry_T_2167 = _issue_entry_T_2166 | _issue_entry_T_2152; // @[Mux.scala:30:73]
wire _issue_entry_T_2168 = _issue_entry_T_2167 | _issue_entry_T_2153; // @[Mux.scala:30:73]
wire _issue_entry_T_2169 = _issue_entry_T_2168 | _issue_entry_T_2154; // @[Mux.scala:30:73]
wire _issue_entry_T_2170 = _issue_entry_T_2169 | _issue_entry_T_2155; // @[Mux.scala:30:73]
wire _issue_entry_T_2171 = _issue_entry_T_2170 | _issue_entry_T_2156; // @[Mux.scala:30:73]
wire _issue_entry_T_2172 = _issue_entry_T_2171 | _issue_entry_T_2157; // @[Mux.scala:30:73]
wire _issue_entry_T_2173 = _issue_entry_T_2172 | _issue_entry_T_2158; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_157 = _issue_entry_T_2173; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_6 = _issue_entry_WIRE_157; // @[Mux.scala:30:73]
wire _issue_entry_T_2174 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2175 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2176 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2177 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2178 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2179 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2180 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2181 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2182 = issue_sel_8 & entries_ex_8_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2183 = issue_sel_9 & entries_ex_9_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2184 = issue_sel_10 & entries_ex_10_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2185 = issue_sel_11 & entries_ex_11_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2186 = issue_sel_12 & entries_ex_12_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2187 = issue_sel_13 & entries_ex_13_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2188 = issue_sel_14 & entries_ex_14_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2189 = issue_sel_15 & entries_ex_15_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2190 = _issue_entry_T_2174 | _issue_entry_T_2175; // @[Mux.scala:30:73]
wire _issue_entry_T_2191 = _issue_entry_T_2190 | _issue_entry_T_2176; // @[Mux.scala:30:73]
wire _issue_entry_T_2192 = _issue_entry_T_2191 | _issue_entry_T_2177; // @[Mux.scala:30:73]
wire _issue_entry_T_2193 = _issue_entry_T_2192 | _issue_entry_T_2178; // @[Mux.scala:30:73]
wire _issue_entry_T_2194 = _issue_entry_T_2193 | _issue_entry_T_2179; // @[Mux.scala:30:73]
wire _issue_entry_T_2195 = _issue_entry_T_2194 | _issue_entry_T_2180; // @[Mux.scala:30:73]
wire _issue_entry_T_2196 = _issue_entry_T_2195 | _issue_entry_T_2181; // @[Mux.scala:30:73]
wire _issue_entry_T_2197 = _issue_entry_T_2196 | _issue_entry_T_2182; // @[Mux.scala:30:73]
wire _issue_entry_T_2198 = _issue_entry_T_2197 | _issue_entry_T_2183; // @[Mux.scala:30:73]
wire _issue_entry_T_2199 = _issue_entry_T_2198 | _issue_entry_T_2184; // @[Mux.scala:30:73]
wire _issue_entry_T_2200 = _issue_entry_T_2199 | _issue_entry_T_2185; // @[Mux.scala:30:73]
wire _issue_entry_T_2201 = _issue_entry_T_2200 | _issue_entry_T_2186; // @[Mux.scala:30:73]
wire _issue_entry_T_2202 = _issue_entry_T_2201 | _issue_entry_T_2187; // @[Mux.scala:30:73]
wire _issue_entry_T_2203 = _issue_entry_T_2202 | _issue_entry_T_2188; // @[Mux.scala:30:73]
wire _issue_entry_T_2204 = _issue_entry_T_2203 | _issue_entry_T_2189; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_158 = _issue_entry_T_2204; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_7 = _issue_entry_WIRE_158; // @[Mux.scala:30:73]
wire _issue_entry_T_2205 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2206 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2207 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2208 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2209 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2210 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2211 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2212 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2213 = issue_sel_8 & entries_ex_8_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2214 = issue_sel_9 & entries_ex_9_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2215 = issue_sel_10 & entries_ex_10_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2216 = issue_sel_11 & entries_ex_11_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2217 = issue_sel_12 & entries_ex_12_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2218 = issue_sel_13 & entries_ex_13_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2219 = issue_sel_14 & entries_ex_14_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2220 = issue_sel_15 & entries_ex_15_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_2221 = _issue_entry_T_2205 | _issue_entry_T_2206; // @[Mux.scala:30:73]
wire _issue_entry_T_2222 = _issue_entry_T_2221 | _issue_entry_T_2207; // @[Mux.scala:30:73]
wire _issue_entry_T_2223 = _issue_entry_T_2222 | _issue_entry_T_2208; // @[Mux.scala:30:73]
wire _issue_entry_T_2224 = _issue_entry_T_2223 | _issue_entry_T_2209; // @[Mux.scala:30:73]
wire _issue_entry_T_2225 = _issue_entry_T_2224 | _issue_entry_T_2210; // @[Mux.scala:30:73]
wire _issue_entry_T_2226 = _issue_entry_T_2225 | _issue_entry_T_2211; // @[Mux.scala:30:73]
wire _issue_entry_T_2227 = _issue_entry_T_2226 | _issue_entry_T_2212; // @[Mux.scala:30:73]
wire _issue_entry_T_2228 = _issue_entry_T_2227 | _issue_entry_T_2213; // @[Mux.scala:30:73]
wire _issue_entry_T_2229 = _issue_entry_T_2228 | _issue_entry_T_2214; // @[Mux.scala:30:73]
wire _issue_entry_T_2230 = _issue_entry_T_2229 | _issue_entry_T_2215; // @[Mux.scala:30:73]
wire _issue_entry_T_2231 = _issue_entry_T_2230 | _issue_entry_T_2216; // @[Mux.scala:30:73]
wire _issue_entry_T_2232 = _issue_entry_T_2231 | _issue_entry_T_2217; // @[Mux.scala:30:73]
wire _issue_entry_T_2233 = _issue_entry_T_2232 | _issue_entry_T_2218; // @[Mux.scala:30:73]
wire _issue_entry_T_2234 = _issue_entry_T_2233 | _issue_entry_T_2219; // @[Mux.scala:30:73]
wire _issue_entry_T_2235 = _issue_entry_T_2234 | _issue_entry_T_2220; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_159 = _issue_entry_T_2235; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_8 = _issue_entry_WIRE_159; // @[Mux.scala:30:73]
wire _issue_entry_T_2236 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2237 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2238 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2239 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2240 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2241 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2242 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2243 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2244 = issue_sel_8 & entries_ex_8_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2245 = issue_sel_9 & entries_ex_9_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2246 = issue_sel_10 & entries_ex_10_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2247 = issue_sel_11 & entries_ex_11_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2248 = issue_sel_12 & entries_ex_12_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2249 = issue_sel_13 & entries_ex_13_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2250 = issue_sel_14 & entries_ex_14_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2251 = issue_sel_15 & entries_ex_15_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_2252 = _issue_entry_T_2236 | _issue_entry_T_2237; // @[Mux.scala:30:73]
wire _issue_entry_T_2253 = _issue_entry_T_2252 | _issue_entry_T_2238; // @[Mux.scala:30:73]
wire _issue_entry_T_2254 = _issue_entry_T_2253 | _issue_entry_T_2239; // @[Mux.scala:30:73]
wire _issue_entry_T_2255 = _issue_entry_T_2254 | _issue_entry_T_2240; // @[Mux.scala:30:73]
wire _issue_entry_T_2256 = _issue_entry_T_2255 | _issue_entry_T_2241; // @[Mux.scala:30:73]
wire _issue_entry_T_2257 = _issue_entry_T_2256 | _issue_entry_T_2242; // @[Mux.scala:30:73]
wire _issue_entry_T_2258 = _issue_entry_T_2257 | _issue_entry_T_2243; // @[Mux.scala:30:73]
wire _issue_entry_T_2259 = _issue_entry_T_2258 | _issue_entry_T_2244; // @[Mux.scala:30:73]
wire _issue_entry_T_2260 = _issue_entry_T_2259 | _issue_entry_T_2245; // @[Mux.scala:30:73]
wire _issue_entry_T_2261 = _issue_entry_T_2260 | _issue_entry_T_2246; // @[Mux.scala:30:73]
wire _issue_entry_T_2262 = _issue_entry_T_2261 | _issue_entry_T_2247; // @[Mux.scala:30:73]
wire _issue_entry_T_2263 = _issue_entry_T_2262 | _issue_entry_T_2248; // @[Mux.scala:30:73]
wire _issue_entry_T_2264 = _issue_entry_T_2263 | _issue_entry_T_2249; // @[Mux.scala:30:73]
wire _issue_entry_T_2265 = _issue_entry_T_2264 | _issue_entry_T_2250; // @[Mux.scala:30:73]
wire _issue_entry_T_2266 = _issue_entry_T_2265 | _issue_entry_T_2251; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_160 = _issue_entry_T_2266; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_9 = _issue_entry_WIRE_160; // @[Mux.scala:30:73]
wire _issue_entry_T_2267 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2268 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2269 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2270 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2271 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2272 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2273 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2274 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2275 = issue_sel_8 & entries_ex_8_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2276 = issue_sel_9 & entries_ex_9_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2277 = issue_sel_10 & entries_ex_10_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2278 = issue_sel_11 & entries_ex_11_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2279 = issue_sel_12 & entries_ex_12_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2280 = issue_sel_13 & entries_ex_13_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2281 = issue_sel_14 & entries_ex_14_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2282 = issue_sel_15 & entries_ex_15_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_2283 = _issue_entry_T_2267 | _issue_entry_T_2268; // @[Mux.scala:30:73]
wire _issue_entry_T_2284 = _issue_entry_T_2283 | _issue_entry_T_2269; // @[Mux.scala:30:73]
wire _issue_entry_T_2285 = _issue_entry_T_2284 | _issue_entry_T_2270; // @[Mux.scala:30:73]
wire _issue_entry_T_2286 = _issue_entry_T_2285 | _issue_entry_T_2271; // @[Mux.scala:30:73]
wire _issue_entry_T_2287 = _issue_entry_T_2286 | _issue_entry_T_2272; // @[Mux.scala:30:73]
wire _issue_entry_T_2288 = _issue_entry_T_2287 | _issue_entry_T_2273; // @[Mux.scala:30:73]
wire _issue_entry_T_2289 = _issue_entry_T_2288 | _issue_entry_T_2274; // @[Mux.scala:30:73]
wire _issue_entry_T_2290 = _issue_entry_T_2289 | _issue_entry_T_2275; // @[Mux.scala:30:73]
wire _issue_entry_T_2291 = _issue_entry_T_2290 | _issue_entry_T_2276; // @[Mux.scala:30:73]
wire _issue_entry_T_2292 = _issue_entry_T_2291 | _issue_entry_T_2277; // @[Mux.scala:30:73]
wire _issue_entry_T_2293 = _issue_entry_T_2292 | _issue_entry_T_2278; // @[Mux.scala:30:73]
wire _issue_entry_T_2294 = _issue_entry_T_2293 | _issue_entry_T_2279; // @[Mux.scala:30:73]
wire _issue_entry_T_2295 = _issue_entry_T_2294 | _issue_entry_T_2280; // @[Mux.scala:30:73]
wire _issue_entry_T_2296 = _issue_entry_T_2295 | _issue_entry_T_2281; // @[Mux.scala:30:73]
wire _issue_entry_T_2297 = _issue_entry_T_2296 | _issue_entry_T_2282; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_161 = _issue_entry_T_2297; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_10 = _issue_entry_WIRE_161; // @[Mux.scala:30:73]
wire _issue_entry_T_2298 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2299 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2300 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2301 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2302 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2303 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2304 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2305 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2306 = issue_sel_8 & entries_ex_8_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2307 = issue_sel_9 & entries_ex_9_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2308 = issue_sel_10 & entries_ex_10_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2309 = issue_sel_11 & entries_ex_11_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2310 = issue_sel_12 & entries_ex_12_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2311 = issue_sel_13 & entries_ex_13_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2312 = issue_sel_14 & entries_ex_14_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2313 = issue_sel_15 & entries_ex_15_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_2314 = _issue_entry_T_2298 | _issue_entry_T_2299; // @[Mux.scala:30:73]
wire _issue_entry_T_2315 = _issue_entry_T_2314 | _issue_entry_T_2300; // @[Mux.scala:30:73]
wire _issue_entry_T_2316 = _issue_entry_T_2315 | _issue_entry_T_2301; // @[Mux.scala:30:73]
wire _issue_entry_T_2317 = _issue_entry_T_2316 | _issue_entry_T_2302; // @[Mux.scala:30:73]
wire _issue_entry_T_2318 = _issue_entry_T_2317 | _issue_entry_T_2303; // @[Mux.scala:30:73]
wire _issue_entry_T_2319 = _issue_entry_T_2318 | _issue_entry_T_2304; // @[Mux.scala:30:73]
wire _issue_entry_T_2320 = _issue_entry_T_2319 | _issue_entry_T_2305; // @[Mux.scala:30:73]
wire _issue_entry_T_2321 = _issue_entry_T_2320 | _issue_entry_T_2306; // @[Mux.scala:30:73]
wire _issue_entry_T_2322 = _issue_entry_T_2321 | _issue_entry_T_2307; // @[Mux.scala:30:73]
wire _issue_entry_T_2323 = _issue_entry_T_2322 | _issue_entry_T_2308; // @[Mux.scala:30:73]
wire _issue_entry_T_2324 = _issue_entry_T_2323 | _issue_entry_T_2309; // @[Mux.scala:30:73]
wire _issue_entry_T_2325 = _issue_entry_T_2324 | _issue_entry_T_2310; // @[Mux.scala:30:73]
wire _issue_entry_T_2326 = _issue_entry_T_2325 | _issue_entry_T_2311; // @[Mux.scala:30:73]
wire _issue_entry_T_2327 = _issue_entry_T_2326 | _issue_entry_T_2312; // @[Mux.scala:30:73]
wire _issue_entry_T_2328 = _issue_entry_T_2327 | _issue_entry_T_2313; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_162 = _issue_entry_T_2328; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_11 = _issue_entry_WIRE_162; // @[Mux.scala:30:73]
wire _issue_entry_T_2329 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2330 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2331 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2332 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2333 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2334 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2335 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2336 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2337 = issue_sel_8 & entries_ex_8_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2338 = issue_sel_9 & entries_ex_9_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2339 = issue_sel_10 & entries_ex_10_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2340 = issue_sel_11 & entries_ex_11_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2341 = issue_sel_12 & entries_ex_12_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2342 = issue_sel_13 & entries_ex_13_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2343 = issue_sel_14 & entries_ex_14_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2344 = issue_sel_15 & entries_ex_15_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_2345 = _issue_entry_T_2329 | _issue_entry_T_2330; // @[Mux.scala:30:73]
wire _issue_entry_T_2346 = _issue_entry_T_2345 | _issue_entry_T_2331; // @[Mux.scala:30:73]
wire _issue_entry_T_2347 = _issue_entry_T_2346 | _issue_entry_T_2332; // @[Mux.scala:30:73]
wire _issue_entry_T_2348 = _issue_entry_T_2347 | _issue_entry_T_2333; // @[Mux.scala:30:73]
wire _issue_entry_T_2349 = _issue_entry_T_2348 | _issue_entry_T_2334; // @[Mux.scala:30:73]
wire _issue_entry_T_2350 = _issue_entry_T_2349 | _issue_entry_T_2335; // @[Mux.scala:30:73]
wire _issue_entry_T_2351 = _issue_entry_T_2350 | _issue_entry_T_2336; // @[Mux.scala:30:73]
wire _issue_entry_T_2352 = _issue_entry_T_2351 | _issue_entry_T_2337; // @[Mux.scala:30:73]
wire _issue_entry_T_2353 = _issue_entry_T_2352 | _issue_entry_T_2338; // @[Mux.scala:30:73]
wire _issue_entry_T_2354 = _issue_entry_T_2353 | _issue_entry_T_2339; // @[Mux.scala:30:73]
wire _issue_entry_T_2355 = _issue_entry_T_2354 | _issue_entry_T_2340; // @[Mux.scala:30:73]
wire _issue_entry_T_2356 = _issue_entry_T_2355 | _issue_entry_T_2341; // @[Mux.scala:30:73]
wire _issue_entry_T_2357 = _issue_entry_T_2356 | _issue_entry_T_2342; // @[Mux.scala:30:73]
wire _issue_entry_T_2358 = _issue_entry_T_2357 | _issue_entry_T_2343; // @[Mux.scala:30:73]
wire _issue_entry_T_2359 = _issue_entry_T_2358 | _issue_entry_T_2344; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_163 = _issue_entry_T_2359; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_12 = _issue_entry_WIRE_163; // @[Mux.scala:30:73]
wire _issue_entry_T_2360 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2361 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2362 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2363 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2364 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2365 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2366 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2367 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2368 = issue_sel_8 & entries_ex_8_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2369 = issue_sel_9 & entries_ex_9_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2370 = issue_sel_10 & entries_ex_10_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2371 = issue_sel_11 & entries_ex_11_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2372 = issue_sel_12 & entries_ex_12_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2373 = issue_sel_13 & entries_ex_13_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2374 = issue_sel_14 & entries_ex_14_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2375 = issue_sel_15 & entries_ex_15_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_2376 = _issue_entry_T_2360 | _issue_entry_T_2361; // @[Mux.scala:30:73]
wire _issue_entry_T_2377 = _issue_entry_T_2376 | _issue_entry_T_2362; // @[Mux.scala:30:73]
wire _issue_entry_T_2378 = _issue_entry_T_2377 | _issue_entry_T_2363; // @[Mux.scala:30:73]
wire _issue_entry_T_2379 = _issue_entry_T_2378 | _issue_entry_T_2364; // @[Mux.scala:30:73]
wire _issue_entry_T_2380 = _issue_entry_T_2379 | _issue_entry_T_2365; // @[Mux.scala:30:73]
wire _issue_entry_T_2381 = _issue_entry_T_2380 | _issue_entry_T_2366; // @[Mux.scala:30:73]
wire _issue_entry_T_2382 = _issue_entry_T_2381 | _issue_entry_T_2367; // @[Mux.scala:30:73]
wire _issue_entry_T_2383 = _issue_entry_T_2382 | _issue_entry_T_2368; // @[Mux.scala:30:73]
wire _issue_entry_T_2384 = _issue_entry_T_2383 | _issue_entry_T_2369; // @[Mux.scala:30:73]
wire _issue_entry_T_2385 = _issue_entry_T_2384 | _issue_entry_T_2370; // @[Mux.scala:30:73]
wire _issue_entry_T_2386 = _issue_entry_T_2385 | _issue_entry_T_2371; // @[Mux.scala:30:73]
wire _issue_entry_T_2387 = _issue_entry_T_2386 | _issue_entry_T_2372; // @[Mux.scala:30:73]
wire _issue_entry_T_2388 = _issue_entry_T_2387 | _issue_entry_T_2373; // @[Mux.scala:30:73]
wire _issue_entry_T_2389 = _issue_entry_T_2388 | _issue_entry_T_2374; // @[Mux.scala:30:73]
wire _issue_entry_T_2390 = _issue_entry_T_2389 | _issue_entry_T_2375; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_164 = _issue_entry_T_2390; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_13 = _issue_entry_WIRE_164; // @[Mux.scala:30:73]
wire _issue_entry_T_2391 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2392 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2393 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2394 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2395 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2396 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2397 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2398 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2399 = issue_sel_8 & entries_ex_8_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2400 = issue_sel_9 & entries_ex_9_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2401 = issue_sel_10 & entries_ex_10_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2402 = issue_sel_11 & entries_ex_11_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2403 = issue_sel_12 & entries_ex_12_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2404 = issue_sel_13 & entries_ex_13_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2405 = issue_sel_14 & entries_ex_14_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2406 = issue_sel_15 & entries_ex_15_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_2407 = _issue_entry_T_2391 | _issue_entry_T_2392; // @[Mux.scala:30:73]
wire _issue_entry_T_2408 = _issue_entry_T_2407 | _issue_entry_T_2393; // @[Mux.scala:30:73]
wire _issue_entry_T_2409 = _issue_entry_T_2408 | _issue_entry_T_2394; // @[Mux.scala:30:73]
wire _issue_entry_T_2410 = _issue_entry_T_2409 | _issue_entry_T_2395; // @[Mux.scala:30:73]
wire _issue_entry_T_2411 = _issue_entry_T_2410 | _issue_entry_T_2396; // @[Mux.scala:30:73]
wire _issue_entry_T_2412 = _issue_entry_T_2411 | _issue_entry_T_2397; // @[Mux.scala:30:73]
wire _issue_entry_T_2413 = _issue_entry_T_2412 | _issue_entry_T_2398; // @[Mux.scala:30:73]
wire _issue_entry_T_2414 = _issue_entry_T_2413 | _issue_entry_T_2399; // @[Mux.scala:30:73]
wire _issue_entry_T_2415 = _issue_entry_T_2414 | _issue_entry_T_2400; // @[Mux.scala:30:73]
wire _issue_entry_T_2416 = _issue_entry_T_2415 | _issue_entry_T_2401; // @[Mux.scala:30:73]
wire _issue_entry_T_2417 = _issue_entry_T_2416 | _issue_entry_T_2402; // @[Mux.scala:30:73]
wire _issue_entry_T_2418 = _issue_entry_T_2417 | _issue_entry_T_2403; // @[Mux.scala:30:73]
wire _issue_entry_T_2419 = _issue_entry_T_2418 | _issue_entry_T_2404; // @[Mux.scala:30:73]
wire _issue_entry_T_2420 = _issue_entry_T_2419 | _issue_entry_T_2405; // @[Mux.scala:30:73]
wire _issue_entry_T_2421 = _issue_entry_T_2420 | _issue_entry_T_2406; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_165 = _issue_entry_T_2421; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_14 = _issue_entry_WIRE_165; // @[Mux.scala:30:73]
wire _issue_entry_T_2422 = issue_sel_0_1 & entries_ex_0_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2423 = issue_sel_1_1 & entries_ex_1_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2424 = issue_sel_2_1 & entries_ex_2_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2425 = issue_sel_3_1 & entries_ex_3_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2426 = issue_sel_4_1 & entries_ex_4_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2427 = issue_sel_5_1 & entries_ex_5_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2428 = issue_sel_6_1 & entries_ex_6_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2429 = issue_sel_7_1 & entries_ex_7_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2430 = issue_sel_8 & entries_ex_8_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2431 = issue_sel_9 & entries_ex_9_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2432 = issue_sel_10 & entries_ex_10_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2433 = issue_sel_11 & entries_ex_11_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2434 = issue_sel_12 & entries_ex_12_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2435 = issue_sel_13 & entries_ex_13_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2436 = issue_sel_14 & entries_ex_14_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2437 = issue_sel_15 & entries_ex_15_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_2438 = _issue_entry_T_2422 | _issue_entry_T_2423; // @[Mux.scala:30:73]
wire _issue_entry_T_2439 = _issue_entry_T_2438 | _issue_entry_T_2424; // @[Mux.scala:30:73]
wire _issue_entry_T_2440 = _issue_entry_T_2439 | _issue_entry_T_2425; // @[Mux.scala:30:73]
wire _issue_entry_T_2441 = _issue_entry_T_2440 | _issue_entry_T_2426; // @[Mux.scala:30:73]
wire _issue_entry_T_2442 = _issue_entry_T_2441 | _issue_entry_T_2427; // @[Mux.scala:30:73]
wire _issue_entry_T_2443 = _issue_entry_T_2442 | _issue_entry_T_2428; // @[Mux.scala:30:73]
wire _issue_entry_T_2444 = _issue_entry_T_2443 | _issue_entry_T_2429; // @[Mux.scala:30:73]
wire _issue_entry_T_2445 = _issue_entry_T_2444 | _issue_entry_T_2430; // @[Mux.scala:30:73]
wire _issue_entry_T_2446 = _issue_entry_T_2445 | _issue_entry_T_2431; // @[Mux.scala:30:73]
wire _issue_entry_T_2447 = _issue_entry_T_2446 | _issue_entry_T_2432; // @[Mux.scala:30:73]
wire _issue_entry_T_2448 = _issue_entry_T_2447 | _issue_entry_T_2433; // @[Mux.scala:30:73]
wire _issue_entry_T_2449 = _issue_entry_T_2448 | _issue_entry_T_2434; // @[Mux.scala:30:73]
wire _issue_entry_T_2450 = _issue_entry_T_2449 | _issue_entry_T_2435; // @[Mux.scala:30:73]
wire _issue_entry_T_2451 = _issue_entry_T_2450 | _issue_entry_T_2436; // @[Mux.scala:30:73]
wire _issue_entry_T_2452 = _issue_entry_T_2451 | _issue_entry_T_2437; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_166 = _issue_entry_T_2452; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_150_15 = _issue_entry_WIRE_166; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_168; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_0 = _issue_entry_WIRE_167_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_169; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_1 = _issue_entry_WIRE_167_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_170; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_2 = _issue_entry_WIRE_167_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_171; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_3 = _issue_entry_WIRE_167_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_172; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_4 = _issue_entry_WIRE_167_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_173; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_5 = _issue_entry_WIRE_167_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_174; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_6 = _issue_entry_WIRE_167_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_175; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_deps_ld_7 = _issue_entry_WIRE_167_7; // @[Mux.scala:30:73]
wire _issue_entry_T_2453 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2454 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2455 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2456 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2457 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2458 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2459 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2460 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2461 = issue_sel_8 & entries_ex_8_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2462 = issue_sel_9 & entries_ex_9_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2463 = issue_sel_10 & entries_ex_10_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2464 = issue_sel_11 & entries_ex_11_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2465 = issue_sel_12 & entries_ex_12_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2466 = issue_sel_13 & entries_ex_13_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2467 = issue_sel_14 & entries_ex_14_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2468 = issue_sel_15 & entries_ex_15_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_2469 = _issue_entry_T_2453 | _issue_entry_T_2454; // @[Mux.scala:30:73]
wire _issue_entry_T_2470 = _issue_entry_T_2469 | _issue_entry_T_2455; // @[Mux.scala:30:73]
wire _issue_entry_T_2471 = _issue_entry_T_2470 | _issue_entry_T_2456; // @[Mux.scala:30:73]
wire _issue_entry_T_2472 = _issue_entry_T_2471 | _issue_entry_T_2457; // @[Mux.scala:30:73]
wire _issue_entry_T_2473 = _issue_entry_T_2472 | _issue_entry_T_2458; // @[Mux.scala:30:73]
wire _issue_entry_T_2474 = _issue_entry_T_2473 | _issue_entry_T_2459; // @[Mux.scala:30:73]
wire _issue_entry_T_2475 = _issue_entry_T_2474 | _issue_entry_T_2460; // @[Mux.scala:30:73]
wire _issue_entry_T_2476 = _issue_entry_T_2475 | _issue_entry_T_2461; // @[Mux.scala:30:73]
wire _issue_entry_T_2477 = _issue_entry_T_2476 | _issue_entry_T_2462; // @[Mux.scala:30:73]
wire _issue_entry_T_2478 = _issue_entry_T_2477 | _issue_entry_T_2463; // @[Mux.scala:30:73]
wire _issue_entry_T_2479 = _issue_entry_T_2478 | _issue_entry_T_2464; // @[Mux.scala:30:73]
wire _issue_entry_T_2480 = _issue_entry_T_2479 | _issue_entry_T_2465; // @[Mux.scala:30:73]
wire _issue_entry_T_2481 = _issue_entry_T_2480 | _issue_entry_T_2466; // @[Mux.scala:30:73]
wire _issue_entry_T_2482 = _issue_entry_T_2481 | _issue_entry_T_2467; // @[Mux.scala:30:73]
wire _issue_entry_T_2483 = _issue_entry_T_2482 | _issue_entry_T_2468; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_168 = _issue_entry_T_2483; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_0 = _issue_entry_WIRE_168; // @[Mux.scala:30:73]
wire _issue_entry_T_2484 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2485 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2486 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2487 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2488 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2489 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2490 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2491 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2492 = issue_sel_8 & entries_ex_8_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2493 = issue_sel_9 & entries_ex_9_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2494 = issue_sel_10 & entries_ex_10_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2495 = issue_sel_11 & entries_ex_11_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2496 = issue_sel_12 & entries_ex_12_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2497 = issue_sel_13 & entries_ex_13_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2498 = issue_sel_14 & entries_ex_14_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2499 = issue_sel_15 & entries_ex_15_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_2500 = _issue_entry_T_2484 | _issue_entry_T_2485; // @[Mux.scala:30:73]
wire _issue_entry_T_2501 = _issue_entry_T_2500 | _issue_entry_T_2486; // @[Mux.scala:30:73]
wire _issue_entry_T_2502 = _issue_entry_T_2501 | _issue_entry_T_2487; // @[Mux.scala:30:73]
wire _issue_entry_T_2503 = _issue_entry_T_2502 | _issue_entry_T_2488; // @[Mux.scala:30:73]
wire _issue_entry_T_2504 = _issue_entry_T_2503 | _issue_entry_T_2489; // @[Mux.scala:30:73]
wire _issue_entry_T_2505 = _issue_entry_T_2504 | _issue_entry_T_2490; // @[Mux.scala:30:73]
wire _issue_entry_T_2506 = _issue_entry_T_2505 | _issue_entry_T_2491; // @[Mux.scala:30:73]
wire _issue_entry_T_2507 = _issue_entry_T_2506 | _issue_entry_T_2492; // @[Mux.scala:30:73]
wire _issue_entry_T_2508 = _issue_entry_T_2507 | _issue_entry_T_2493; // @[Mux.scala:30:73]
wire _issue_entry_T_2509 = _issue_entry_T_2508 | _issue_entry_T_2494; // @[Mux.scala:30:73]
wire _issue_entry_T_2510 = _issue_entry_T_2509 | _issue_entry_T_2495; // @[Mux.scala:30:73]
wire _issue_entry_T_2511 = _issue_entry_T_2510 | _issue_entry_T_2496; // @[Mux.scala:30:73]
wire _issue_entry_T_2512 = _issue_entry_T_2511 | _issue_entry_T_2497; // @[Mux.scala:30:73]
wire _issue_entry_T_2513 = _issue_entry_T_2512 | _issue_entry_T_2498; // @[Mux.scala:30:73]
wire _issue_entry_T_2514 = _issue_entry_T_2513 | _issue_entry_T_2499; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_169 = _issue_entry_T_2514; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_1 = _issue_entry_WIRE_169; // @[Mux.scala:30:73]
wire _issue_entry_T_2515 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2516 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2517 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2518 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2519 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2520 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2521 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2522 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2523 = issue_sel_8 & entries_ex_8_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2524 = issue_sel_9 & entries_ex_9_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2525 = issue_sel_10 & entries_ex_10_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2526 = issue_sel_11 & entries_ex_11_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2527 = issue_sel_12 & entries_ex_12_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2528 = issue_sel_13 & entries_ex_13_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2529 = issue_sel_14 & entries_ex_14_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2530 = issue_sel_15 & entries_ex_15_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_2531 = _issue_entry_T_2515 | _issue_entry_T_2516; // @[Mux.scala:30:73]
wire _issue_entry_T_2532 = _issue_entry_T_2531 | _issue_entry_T_2517; // @[Mux.scala:30:73]
wire _issue_entry_T_2533 = _issue_entry_T_2532 | _issue_entry_T_2518; // @[Mux.scala:30:73]
wire _issue_entry_T_2534 = _issue_entry_T_2533 | _issue_entry_T_2519; // @[Mux.scala:30:73]
wire _issue_entry_T_2535 = _issue_entry_T_2534 | _issue_entry_T_2520; // @[Mux.scala:30:73]
wire _issue_entry_T_2536 = _issue_entry_T_2535 | _issue_entry_T_2521; // @[Mux.scala:30:73]
wire _issue_entry_T_2537 = _issue_entry_T_2536 | _issue_entry_T_2522; // @[Mux.scala:30:73]
wire _issue_entry_T_2538 = _issue_entry_T_2537 | _issue_entry_T_2523; // @[Mux.scala:30:73]
wire _issue_entry_T_2539 = _issue_entry_T_2538 | _issue_entry_T_2524; // @[Mux.scala:30:73]
wire _issue_entry_T_2540 = _issue_entry_T_2539 | _issue_entry_T_2525; // @[Mux.scala:30:73]
wire _issue_entry_T_2541 = _issue_entry_T_2540 | _issue_entry_T_2526; // @[Mux.scala:30:73]
wire _issue_entry_T_2542 = _issue_entry_T_2541 | _issue_entry_T_2527; // @[Mux.scala:30:73]
wire _issue_entry_T_2543 = _issue_entry_T_2542 | _issue_entry_T_2528; // @[Mux.scala:30:73]
wire _issue_entry_T_2544 = _issue_entry_T_2543 | _issue_entry_T_2529; // @[Mux.scala:30:73]
wire _issue_entry_T_2545 = _issue_entry_T_2544 | _issue_entry_T_2530; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_170 = _issue_entry_T_2545; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_2 = _issue_entry_WIRE_170; // @[Mux.scala:30:73]
wire _issue_entry_T_2546 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2547 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2548 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2549 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2550 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2551 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2552 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2553 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2554 = issue_sel_8 & entries_ex_8_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2555 = issue_sel_9 & entries_ex_9_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2556 = issue_sel_10 & entries_ex_10_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2557 = issue_sel_11 & entries_ex_11_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2558 = issue_sel_12 & entries_ex_12_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2559 = issue_sel_13 & entries_ex_13_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2560 = issue_sel_14 & entries_ex_14_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2561 = issue_sel_15 & entries_ex_15_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_2562 = _issue_entry_T_2546 | _issue_entry_T_2547; // @[Mux.scala:30:73]
wire _issue_entry_T_2563 = _issue_entry_T_2562 | _issue_entry_T_2548; // @[Mux.scala:30:73]
wire _issue_entry_T_2564 = _issue_entry_T_2563 | _issue_entry_T_2549; // @[Mux.scala:30:73]
wire _issue_entry_T_2565 = _issue_entry_T_2564 | _issue_entry_T_2550; // @[Mux.scala:30:73]
wire _issue_entry_T_2566 = _issue_entry_T_2565 | _issue_entry_T_2551; // @[Mux.scala:30:73]
wire _issue_entry_T_2567 = _issue_entry_T_2566 | _issue_entry_T_2552; // @[Mux.scala:30:73]
wire _issue_entry_T_2568 = _issue_entry_T_2567 | _issue_entry_T_2553; // @[Mux.scala:30:73]
wire _issue_entry_T_2569 = _issue_entry_T_2568 | _issue_entry_T_2554; // @[Mux.scala:30:73]
wire _issue_entry_T_2570 = _issue_entry_T_2569 | _issue_entry_T_2555; // @[Mux.scala:30:73]
wire _issue_entry_T_2571 = _issue_entry_T_2570 | _issue_entry_T_2556; // @[Mux.scala:30:73]
wire _issue_entry_T_2572 = _issue_entry_T_2571 | _issue_entry_T_2557; // @[Mux.scala:30:73]
wire _issue_entry_T_2573 = _issue_entry_T_2572 | _issue_entry_T_2558; // @[Mux.scala:30:73]
wire _issue_entry_T_2574 = _issue_entry_T_2573 | _issue_entry_T_2559; // @[Mux.scala:30:73]
wire _issue_entry_T_2575 = _issue_entry_T_2574 | _issue_entry_T_2560; // @[Mux.scala:30:73]
wire _issue_entry_T_2576 = _issue_entry_T_2575 | _issue_entry_T_2561; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_171 = _issue_entry_T_2576; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_3 = _issue_entry_WIRE_171; // @[Mux.scala:30:73]
wire _issue_entry_T_2577 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2578 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2579 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2580 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2581 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2582 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2583 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2584 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2585 = issue_sel_8 & entries_ex_8_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2586 = issue_sel_9 & entries_ex_9_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2587 = issue_sel_10 & entries_ex_10_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2588 = issue_sel_11 & entries_ex_11_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2589 = issue_sel_12 & entries_ex_12_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2590 = issue_sel_13 & entries_ex_13_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2591 = issue_sel_14 & entries_ex_14_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2592 = issue_sel_15 & entries_ex_15_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_2593 = _issue_entry_T_2577 | _issue_entry_T_2578; // @[Mux.scala:30:73]
wire _issue_entry_T_2594 = _issue_entry_T_2593 | _issue_entry_T_2579; // @[Mux.scala:30:73]
wire _issue_entry_T_2595 = _issue_entry_T_2594 | _issue_entry_T_2580; // @[Mux.scala:30:73]
wire _issue_entry_T_2596 = _issue_entry_T_2595 | _issue_entry_T_2581; // @[Mux.scala:30:73]
wire _issue_entry_T_2597 = _issue_entry_T_2596 | _issue_entry_T_2582; // @[Mux.scala:30:73]
wire _issue_entry_T_2598 = _issue_entry_T_2597 | _issue_entry_T_2583; // @[Mux.scala:30:73]
wire _issue_entry_T_2599 = _issue_entry_T_2598 | _issue_entry_T_2584; // @[Mux.scala:30:73]
wire _issue_entry_T_2600 = _issue_entry_T_2599 | _issue_entry_T_2585; // @[Mux.scala:30:73]
wire _issue_entry_T_2601 = _issue_entry_T_2600 | _issue_entry_T_2586; // @[Mux.scala:30:73]
wire _issue_entry_T_2602 = _issue_entry_T_2601 | _issue_entry_T_2587; // @[Mux.scala:30:73]
wire _issue_entry_T_2603 = _issue_entry_T_2602 | _issue_entry_T_2588; // @[Mux.scala:30:73]
wire _issue_entry_T_2604 = _issue_entry_T_2603 | _issue_entry_T_2589; // @[Mux.scala:30:73]
wire _issue_entry_T_2605 = _issue_entry_T_2604 | _issue_entry_T_2590; // @[Mux.scala:30:73]
wire _issue_entry_T_2606 = _issue_entry_T_2605 | _issue_entry_T_2591; // @[Mux.scala:30:73]
wire _issue_entry_T_2607 = _issue_entry_T_2606 | _issue_entry_T_2592; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_172 = _issue_entry_T_2607; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_4 = _issue_entry_WIRE_172; // @[Mux.scala:30:73]
wire _issue_entry_T_2608 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2609 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2610 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2611 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2612 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2613 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2614 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2615 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2616 = issue_sel_8 & entries_ex_8_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2617 = issue_sel_9 & entries_ex_9_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2618 = issue_sel_10 & entries_ex_10_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2619 = issue_sel_11 & entries_ex_11_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2620 = issue_sel_12 & entries_ex_12_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2621 = issue_sel_13 & entries_ex_13_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2622 = issue_sel_14 & entries_ex_14_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2623 = issue_sel_15 & entries_ex_15_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_2624 = _issue_entry_T_2608 | _issue_entry_T_2609; // @[Mux.scala:30:73]
wire _issue_entry_T_2625 = _issue_entry_T_2624 | _issue_entry_T_2610; // @[Mux.scala:30:73]
wire _issue_entry_T_2626 = _issue_entry_T_2625 | _issue_entry_T_2611; // @[Mux.scala:30:73]
wire _issue_entry_T_2627 = _issue_entry_T_2626 | _issue_entry_T_2612; // @[Mux.scala:30:73]
wire _issue_entry_T_2628 = _issue_entry_T_2627 | _issue_entry_T_2613; // @[Mux.scala:30:73]
wire _issue_entry_T_2629 = _issue_entry_T_2628 | _issue_entry_T_2614; // @[Mux.scala:30:73]
wire _issue_entry_T_2630 = _issue_entry_T_2629 | _issue_entry_T_2615; // @[Mux.scala:30:73]
wire _issue_entry_T_2631 = _issue_entry_T_2630 | _issue_entry_T_2616; // @[Mux.scala:30:73]
wire _issue_entry_T_2632 = _issue_entry_T_2631 | _issue_entry_T_2617; // @[Mux.scala:30:73]
wire _issue_entry_T_2633 = _issue_entry_T_2632 | _issue_entry_T_2618; // @[Mux.scala:30:73]
wire _issue_entry_T_2634 = _issue_entry_T_2633 | _issue_entry_T_2619; // @[Mux.scala:30:73]
wire _issue_entry_T_2635 = _issue_entry_T_2634 | _issue_entry_T_2620; // @[Mux.scala:30:73]
wire _issue_entry_T_2636 = _issue_entry_T_2635 | _issue_entry_T_2621; // @[Mux.scala:30:73]
wire _issue_entry_T_2637 = _issue_entry_T_2636 | _issue_entry_T_2622; // @[Mux.scala:30:73]
wire _issue_entry_T_2638 = _issue_entry_T_2637 | _issue_entry_T_2623; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_173 = _issue_entry_T_2638; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_5 = _issue_entry_WIRE_173; // @[Mux.scala:30:73]
wire _issue_entry_T_2639 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2640 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2641 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2642 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2643 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2644 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2645 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2646 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2647 = issue_sel_8 & entries_ex_8_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2648 = issue_sel_9 & entries_ex_9_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2649 = issue_sel_10 & entries_ex_10_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2650 = issue_sel_11 & entries_ex_11_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2651 = issue_sel_12 & entries_ex_12_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2652 = issue_sel_13 & entries_ex_13_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2653 = issue_sel_14 & entries_ex_14_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2654 = issue_sel_15 & entries_ex_15_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_2655 = _issue_entry_T_2639 | _issue_entry_T_2640; // @[Mux.scala:30:73]
wire _issue_entry_T_2656 = _issue_entry_T_2655 | _issue_entry_T_2641; // @[Mux.scala:30:73]
wire _issue_entry_T_2657 = _issue_entry_T_2656 | _issue_entry_T_2642; // @[Mux.scala:30:73]
wire _issue_entry_T_2658 = _issue_entry_T_2657 | _issue_entry_T_2643; // @[Mux.scala:30:73]
wire _issue_entry_T_2659 = _issue_entry_T_2658 | _issue_entry_T_2644; // @[Mux.scala:30:73]
wire _issue_entry_T_2660 = _issue_entry_T_2659 | _issue_entry_T_2645; // @[Mux.scala:30:73]
wire _issue_entry_T_2661 = _issue_entry_T_2660 | _issue_entry_T_2646; // @[Mux.scala:30:73]
wire _issue_entry_T_2662 = _issue_entry_T_2661 | _issue_entry_T_2647; // @[Mux.scala:30:73]
wire _issue_entry_T_2663 = _issue_entry_T_2662 | _issue_entry_T_2648; // @[Mux.scala:30:73]
wire _issue_entry_T_2664 = _issue_entry_T_2663 | _issue_entry_T_2649; // @[Mux.scala:30:73]
wire _issue_entry_T_2665 = _issue_entry_T_2664 | _issue_entry_T_2650; // @[Mux.scala:30:73]
wire _issue_entry_T_2666 = _issue_entry_T_2665 | _issue_entry_T_2651; // @[Mux.scala:30:73]
wire _issue_entry_T_2667 = _issue_entry_T_2666 | _issue_entry_T_2652; // @[Mux.scala:30:73]
wire _issue_entry_T_2668 = _issue_entry_T_2667 | _issue_entry_T_2653; // @[Mux.scala:30:73]
wire _issue_entry_T_2669 = _issue_entry_T_2668 | _issue_entry_T_2654; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_174 = _issue_entry_T_2669; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_6 = _issue_entry_WIRE_174; // @[Mux.scala:30:73]
wire _issue_entry_T_2670 = issue_sel_0_1 & entries_ex_0_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2671 = issue_sel_1_1 & entries_ex_1_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2672 = issue_sel_2_1 & entries_ex_2_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2673 = issue_sel_3_1 & entries_ex_3_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2674 = issue_sel_4_1 & entries_ex_4_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2675 = issue_sel_5_1 & entries_ex_5_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2676 = issue_sel_6_1 & entries_ex_6_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2677 = issue_sel_7_1 & entries_ex_7_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2678 = issue_sel_8 & entries_ex_8_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2679 = issue_sel_9 & entries_ex_9_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2680 = issue_sel_10 & entries_ex_10_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2681 = issue_sel_11 & entries_ex_11_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2682 = issue_sel_12 & entries_ex_12_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2683 = issue_sel_13 & entries_ex_13_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2684 = issue_sel_14 & entries_ex_14_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2685 = issue_sel_15 & entries_ex_15_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_2686 = _issue_entry_T_2670 | _issue_entry_T_2671; // @[Mux.scala:30:73]
wire _issue_entry_T_2687 = _issue_entry_T_2686 | _issue_entry_T_2672; // @[Mux.scala:30:73]
wire _issue_entry_T_2688 = _issue_entry_T_2687 | _issue_entry_T_2673; // @[Mux.scala:30:73]
wire _issue_entry_T_2689 = _issue_entry_T_2688 | _issue_entry_T_2674; // @[Mux.scala:30:73]
wire _issue_entry_T_2690 = _issue_entry_T_2689 | _issue_entry_T_2675; // @[Mux.scala:30:73]
wire _issue_entry_T_2691 = _issue_entry_T_2690 | _issue_entry_T_2676; // @[Mux.scala:30:73]
wire _issue_entry_T_2692 = _issue_entry_T_2691 | _issue_entry_T_2677; // @[Mux.scala:30:73]
wire _issue_entry_T_2693 = _issue_entry_T_2692 | _issue_entry_T_2678; // @[Mux.scala:30:73]
wire _issue_entry_T_2694 = _issue_entry_T_2693 | _issue_entry_T_2679; // @[Mux.scala:30:73]
wire _issue_entry_T_2695 = _issue_entry_T_2694 | _issue_entry_T_2680; // @[Mux.scala:30:73]
wire _issue_entry_T_2696 = _issue_entry_T_2695 | _issue_entry_T_2681; // @[Mux.scala:30:73]
wire _issue_entry_T_2697 = _issue_entry_T_2696 | _issue_entry_T_2682; // @[Mux.scala:30:73]
wire _issue_entry_T_2698 = _issue_entry_T_2697 | _issue_entry_T_2683; // @[Mux.scala:30:73]
wire _issue_entry_T_2699 = _issue_entry_T_2698 | _issue_entry_T_2684; // @[Mux.scala:30:73]
wire _issue_entry_T_2700 = _issue_entry_T_2699 | _issue_entry_T_2685; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_175 = _issue_entry_T_2700; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_167_7 = _issue_entry_WIRE_175; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_182_inst_funct; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_funct = _issue_entry_WIRE_176_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_182_inst_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_rs2 = _issue_entry_WIRE_176_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_182_inst_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_rs1 = _issue_entry_WIRE_176_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_inst_xd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_xd = _issue_entry_WIRE_176_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_inst_xs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_xs1 = _issue_entry_WIRE_176_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_inst_xs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_xs2 = _issue_entry_WIRE_176_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_182_inst_rd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_rd = _issue_entry_WIRE_176_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_182_inst_opcode; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_inst_opcode = _issue_entry_WIRE_176_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_182_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_rs1 = _issue_entry_WIRE_176_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_182_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_rs2 = _issue_entry_WIRE_176_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_debug; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_debug = _issue_entry_WIRE_176_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_cease; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_cease = _issue_entry_WIRE_176_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_wfi; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_wfi = _issue_entry_WIRE_176_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_182_status_isa; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_isa = _issue_entry_WIRE_176_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_dprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_dprv = _issue_entry_WIRE_176_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_dv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_dv = _issue_entry_WIRE_176_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_prv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_prv = _issue_entry_WIRE_176_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_v; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_v = _issue_entry_WIRE_176_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_sd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_sd = _issue_entry_WIRE_176_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_182_status_zero2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_zero2 = _issue_entry_WIRE_176_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_mpv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_mpv = _issue_entry_WIRE_176_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_gva; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_gva = _issue_entry_WIRE_176_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_mbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_mbe = _issue_entry_WIRE_176_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_sbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_sbe = _issue_entry_WIRE_176_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_sxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_sxl = _issue_entry_WIRE_176_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_uxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_uxl = _issue_entry_WIRE_176_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_sd_rv32; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_176_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_182_status_zero1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_zero1 = _issue_entry_WIRE_176_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_tsr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_tsr = _issue_entry_WIRE_176_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_tw; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_tw = _issue_entry_WIRE_176_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_tvm; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_tvm = _issue_entry_WIRE_176_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_mxr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_mxr = _issue_entry_WIRE_176_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_sum; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_sum = _issue_entry_WIRE_176_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_mprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_mprv = _issue_entry_WIRE_176_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_xs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_xs = _issue_entry_WIRE_176_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_fs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_fs = _issue_entry_WIRE_176_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_mpp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_mpp = _issue_entry_WIRE_176_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_182_status_vs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_vs = _issue_entry_WIRE_176_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_spp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_spp = _issue_entry_WIRE_176_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_mpie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_mpie = _issue_entry_WIRE_176_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_ube; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_ube = _issue_entry_WIRE_176_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_spie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_spie = _issue_entry_WIRE_176_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_upie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_upie = _issue_entry_WIRE_176_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_mie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_mie = _issue_entry_WIRE_176_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_hie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_hie = _issue_entry_WIRE_176_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_sie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_sie = _issue_entry_WIRE_176_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_182_status_uie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_cmd_status_uie = _issue_entry_WIRE_176_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_179_valid; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_rob_id_valid = _issue_entry_WIRE_176_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_179_bits; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_rob_id_bits = _issue_entry_WIRE_176_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_178; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_from_matmul_fsm = _issue_entry_WIRE_176_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_177; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_cmd_from_conv_fsm = _issue_entry_WIRE_176_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_T_2701 = issue_sel_0_1 & entries_ex_0_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2702 = issue_sel_1_1 & entries_ex_1_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2703 = issue_sel_2_1 & entries_ex_2_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2704 = issue_sel_3_1 & entries_ex_3_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2705 = issue_sel_4_1 & entries_ex_4_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2706 = issue_sel_5_1 & entries_ex_5_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2707 = issue_sel_6_1 & entries_ex_6_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2708 = issue_sel_7_1 & entries_ex_7_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2709 = issue_sel_8 & entries_ex_8_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2710 = issue_sel_9 & entries_ex_9_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2711 = issue_sel_10 & entries_ex_10_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2712 = issue_sel_11 & entries_ex_11_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2713 = issue_sel_12 & entries_ex_12_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2714 = issue_sel_13 & entries_ex_13_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2715 = issue_sel_14 & entries_ex_14_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2716 = issue_sel_15 & entries_ex_15_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2717 = _issue_entry_T_2701 | _issue_entry_T_2702; // @[Mux.scala:30:73]
wire _issue_entry_T_2718 = _issue_entry_T_2717 | _issue_entry_T_2703; // @[Mux.scala:30:73]
wire _issue_entry_T_2719 = _issue_entry_T_2718 | _issue_entry_T_2704; // @[Mux.scala:30:73]
wire _issue_entry_T_2720 = _issue_entry_T_2719 | _issue_entry_T_2705; // @[Mux.scala:30:73]
wire _issue_entry_T_2721 = _issue_entry_T_2720 | _issue_entry_T_2706; // @[Mux.scala:30:73]
wire _issue_entry_T_2722 = _issue_entry_T_2721 | _issue_entry_T_2707; // @[Mux.scala:30:73]
wire _issue_entry_T_2723 = _issue_entry_T_2722 | _issue_entry_T_2708; // @[Mux.scala:30:73]
wire _issue_entry_T_2724 = _issue_entry_T_2723 | _issue_entry_T_2709; // @[Mux.scala:30:73]
wire _issue_entry_T_2725 = _issue_entry_T_2724 | _issue_entry_T_2710; // @[Mux.scala:30:73]
wire _issue_entry_T_2726 = _issue_entry_T_2725 | _issue_entry_T_2711; // @[Mux.scala:30:73]
wire _issue_entry_T_2727 = _issue_entry_T_2726 | _issue_entry_T_2712; // @[Mux.scala:30:73]
wire _issue_entry_T_2728 = _issue_entry_T_2727 | _issue_entry_T_2713; // @[Mux.scala:30:73]
wire _issue_entry_T_2729 = _issue_entry_T_2728 | _issue_entry_T_2714; // @[Mux.scala:30:73]
wire _issue_entry_T_2730 = _issue_entry_T_2729 | _issue_entry_T_2715; // @[Mux.scala:30:73]
wire _issue_entry_T_2731 = _issue_entry_T_2730 | _issue_entry_T_2716; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_177 = _issue_entry_T_2731; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_from_conv_fsm = _issue_entry_WIRE_177; // @[Mux.scala:30:73]
wire _issue_entry_T_2732 = issue_sel_0_1 & entries_ex_0_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2733 = issue_sel_1_1 & entries_ex_1_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2734 = issue_sel_2_1 & entries_ex_2_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2735 = issue_sel_3_1 & entries_ex_3_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2736 = issue_sel_4_1 & entries_ex_4_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2737 = issue_sel_5_1 & entries_ex_5_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2738 = issue_sel_6_1 & entries_ex_6_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2739 = issue_sel_7_1 & entries_ex_7_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2740 = issue_sel_8 & entries_ex_8_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2741 = issue_sel_9 & entries_ex_9_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2742 = issue_sel_10 & entries_ex_10_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2743 = issue_sel_11 & entries_ex_11_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2744 = issue_sel_12 & entries_ex_12_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2745 = issue_sel_13 & entries_ex_13_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2746 = issue_sel_14 & entries_ex_14_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2747 = issue_sel_15 & entries_ex_15_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_2748 = _issue_entry_T_2732 | _issue_entry_T_2733; // @[Mux.scala:30:73]
wire _issue_entry_T_2749 = _issue_entry_T_2748 | _issue_entry_T_2734; // @[Mux.scala:30:73]
wire _issue_entry_T_2750 = _issue_entry_T_2749 | _issue_entry_T_2735; // @[Mux.scala:30:73]
wire _issue_entry_T_2751 = _issue_entry_T_2750 | _issue_entry_T_2736; // @[Mux.scala:30:73]
wire _issue_entry_T_2752 = _issue_entry_T_2751 | _issue_entry_T_2737; // @[Mux.scala:30:73]
wire _issue_entry_T_2753 = _issue_entry_T_2752 | _issue_entry_T_2738; // @[Mux.scala:30:73]
wire _issue_entry_T_2754 = _issue_entry_T_2753 | _issue_entry_T_2739; // @[Mux.scala:30:73]
wire _issue_entry_T_2755 = _issue_entry_T_2754 | _issue_entry_T_2740; // @[Mux.scala:30:73]
wire _issue_entry_T_2756 = _issue_entry_T_2755 | _issue_entry_T_2741; // @[Mux.scala:30:73]
wire _issue_entry_T_2757 = _issue_entry_T_2756 | _issue_entry_T_2742; // @[Mux.scala:30:73]
wire _issue_entry_T_2758 = _issue_entry_T_2757 | _issue_entry_T_2743; // @[Mux.scala:30:73]
wire _issue_entry_T_2759 = _issue_entry_T_2758 | _issue_entry_T_2744; // @[Mux.scala:30:73]
wire _issue_entry_T_2760 = _issue_entry_T_2759 | _issue_entry_T_2745; // @[Mux.scala:30:73]
wire _issue_entry_T_2761 = _issue_entry_T_2760 | _issue_entry_T_2746; // @[Mux.scala:30:73]
wire _issue_entry_T_2762 = _issue_entry_T_2761 | _issue_entry_T_2747; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_178 = _issue_entry_T_2762; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_from_matmul_fsm = _issue_entry_WIRE_178; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_181; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_rob_id_valid = _issue_entry_WIRE_179_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_180; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_rob_id_bits = _issue_entry_WIRE_179_bits; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2763 = issue_sel_0_1 ? entries_ex_0_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2764 = issue_sel_1_1 ? entries_ex_1_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2765 = issue_sel_2_1 ? entries_ex_2_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2766 = issue_sel_3_1 ? entries_ex_3_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2767 = issue_sel_4_1 ? entries_ex_4_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2768 = issue_sel_5_1 ? entries_ex_5_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2769 = issue_sel_6_1 ? entries_ex_6_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2770 = issue_sel_7_1 ? entries_ex_7_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2771 = issue_sel_8 ? entries_ex_8_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2772 = issue_sel_9 ? entries_ex_9_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2773 = issue_sel_10 ? entries_ex_10_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2774 = issue_sel_11 ? entries_ex_11_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2775 = issue_sel_12 ? entries_ex_12_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2776 = issue_sel_13 ? entries_ex_13_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2777 = issue_sel_14 ? entries_ex_14_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2778 = issue_sel_15 ? entries_ex_15_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_2779 = _issue_entry_T_2763 | _issue_entry_T_2764; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2780 = _issue_entry_T_2779 | _issue_entry_T_2765; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2781 = _issue_entry_T_2780 | _issue_entry_T_2766; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2782 = _issue_entry_T_2781 | _issue_entry_T_2767; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2783 = _issue_entry_T_2782 | _issue_entry_T_2768; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2784 = _issue_entry_T_2783 | _issue_entry_T_2769; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2785 = _issue_entry_T_2784 | _issue_entry_T_2770; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2786 = _issue_entry_T_2785 | _issue_entry_T_2771; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2787 = _issue_entry_T_2786 | _issue_entry_T_2772; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2788 = _issue_entry_T_2787 | _issue_entry_T_2773; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2789 = _issue_entry_T_2788 | _issue_entry_T_2774; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2790 = _issue_entry_T_2789 | _issue_entry_T_2775; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2791 = _issue_entry_T_2790 | _issue_entry_T_2776; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2792 = _issue_entry_T_2791 | _issue_entry_T_2777; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_2793 = _issue_entry_T_2792 | _issue_entry_T_2778; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_180 = _issue_entry_T_2793; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_179_bits = _issue_entry_WIRE_180; // @[Mux.scala:30:73]
wire _issue_entry_T_2794 = issue_sel_0_1 & entries_ex_0_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2795 = issue_sel_1_1 & entries_ex_1_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2796 = issue_sel_2_1 & entries_ex_2_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2797 = issue_sel_3_1 & entries_ex_3_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2798 = issue_sel_4_1 & entries_ex_4_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2799 = issue_sel_5_1 & entries_ex_5_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2800 = issue_sel_6_1 & entries_ex_6_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2801 = issue_sel_7_1 & entries_ex_7_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2802 = issue_sel_8 & entries_ex_8_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2803 = issue_sel_9 & entries_ex_9_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2804 = issue_sel_10 & entries_ex_10_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2805 = issue_sel_11 & entries_ex_11_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2806 = issue_sel_12 & entries_ex_12_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2807 = issue_sel_13 & entries_ex_13_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2808 = issue_sel_14 & entries_ex_14_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2809 = issue_sel_15 & entries_ex_15_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_2810 = _issue_entry_T_2794 | _issue_entry_T_2795; // @[Mux.scala:30:73]
wire _issue_entry_T_2811 = _issue_entry_T_2810 | _issue_entry_T_2796; // @[Mux.scala:30:73]
wire _issue_entry_T_2812 = _issue_entry_T_2811 | _issue_entry_T_2797; // @[Mux.scala:30:73]
wire _issue_entry_T_2813 = _issue_entry_T_2812 | _issue_entry_T_2798; // @[Mux.scala:30:73]
wire _issue_entry_T_2814 = _issue_entry_T_2813 | _issue_entry_T_2799; // @[Mux.scala:30:73]
wire _issue_entry_T_2815 = _issue_entry_T_2814 | _issue_entry_T_2800; // @[Mux.scala:30:73]
wire _issue_entry_T_2816 = _issue_entry_T_2815 | _issue_entry_T_2801; // @[Mux.scala:30:73]
wire _issue_entry_T_2817 = _issue_entry_T_2816 | _issue_entry_T_2802; // @[Mux.scala:30:73]
wire _issue_entry_T_2818 = _issue_entry_T_2817 | _issue_entry_T_2803; // @[Mux.scala:30:73]
wire _issue_entry_T_2819 = _issue_entry_T_2818 | _issue_entry_T_2804; // @[Mux.scala:30:73]
wire _issue_entry_T_2820 = _issue_entry_T_2819 | _issue_entry_T_2805; // @[Mux.scala:30:73]
wire _issue_entry_T_2821 = _issue_entry_T_2820 | _issue_entry_T_2806; // @[Mux.scala:30:73]
wire _issue_entry_T_2822 = _issue_entry_T_2821 | _issue_entry_T_2807; // @[Mux.scala:30:73]
wire _issue_entry_T_2823 = _issue_entry_T_2822 | _issue_entry_T_2808; // @[Mux.scala:30:73]
wire _issue_entry_T_2824 = _issue_entry_T_2823 | _issue_entry_T_2809; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_181 = _issue_entry_T_2824; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_179_valid = _issue_entry_WIRE_181; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_223_funct; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_funct = _issue_entry_WIRE_182_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_223_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_rs2 = _issue_entry_WIRE_182_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_223_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_rs1 = _issue_entry_WIRE_182_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_223_xd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_xd = _issue_entry_WIRE_182_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_223_xs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_xs1 = _issue_entry_WIRE_182_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_223_xs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_xs2 = _issue_entry_WIRE_182_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_223_rd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_rd = _issue_entry_WIRE_182_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_223_opcode; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_inst_opcode = _issue_entry_WIRE_182_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_222; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_rs1 = _issue_entry_WIRE_182_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_221; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_rs2 = _issue_entry_WIRE_182_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_debug; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_debug = _issue_entry_WIRE_182_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_cease; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_cease = _issue_entry_WIRE_182_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_wfi; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_wfi = _issue_entry_WIRE_182_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_183_isa; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_isa = _issue_entry_WIRE_182_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_dprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_dprv = _issue_entry_WIRE_182_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_dv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_dv = _issue_entry_WIRE_182_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_prv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_prv = _issue_entry_WIRE_182_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_v; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_v = _issue_entry_WIRE_182_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_sd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_sd = _issue_entry_WIRE_182_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_183_zero2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_zero2 = _issue_entry_WIRE_182_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_mpv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_mpv = _issue_entry_WIRE_182_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_gva; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_gva = _issue_entry_WIRE_182_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_mbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_mbe = _issue_entry_WIRE_182_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_sbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_sbe = _issue_entry_WIRE_182_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_sxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_sxl = _issue_entry_WIRE_182_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_uxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_uxl = _issue_entry_WIRE_182_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_sd_rv32; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_sd_rv32 = _issue_entry_WIRE_182_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_183_zero1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_zero1 = _issue_entry_WIRE_182_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_tsr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_tsr = _issue_entry_WIRE_182_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_tw; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_tw = _issue_entry_WIRE_182_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_tvm; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_tvm = _issue_entry_WIRE_182_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_mxr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_mxr = _issue_entry_WIRE_182_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_sum; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_sum = _issue_entry_WIRE_182_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_mprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_mprv = _issue_entry_WIRE_182_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_xs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_xs = _issue_entry_WIRE_182_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_fs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_fs = _issue_entry_WIRE_182_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_mpp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_mpp = _issue_entry_WIRE_182_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_183_vs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_vs = _issue_entry_WIRE_182_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_spp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_spp = _issue_entry_WIRE_182_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_mpie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_mpie = _issue_entry_WIRE_182_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_ube; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_ube = _issue_entry_WIRE_182_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_spie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_spie = _issue_entry_WIRE_182_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_upie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_upie = _issue_entry_WIRE_182_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_mie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_mie = _issue_entry_WIRE_182_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_hie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_hie = _issue_entry_WIRE_182_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_sie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_sie = _issue_entry_WIRE_182_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_183_uie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_176_cmd_status_uie = _issue_entry_WIRE_182_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_220; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_debug = _issue_entry_WIRE_183_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_219; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_cease = _issue_entry_WIRE_183_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_218; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_wfi = _issue_entry_WIRE_183_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_217; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_isa = _issue_entry_WIRE_183_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_216; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_dprv = _issue_entry_WIRE_183_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_215; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_dv = _issue_entry_WIRE_183_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_214; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_prv = _issue_entry_WIRE_183_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_213; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_v = _issue_entry_WIRE_183_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_212; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_sd = _issue_entry_WIRE_183_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_211; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_zero2 = _issue_entry_WIRE_183_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_210; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_mpv = _issue_entry_WIRE_183_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_209; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_gva = _issue_entry_WIRE_183_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_208; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_mbe = _issue_entry_WIRE_183_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_207; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_sbe = _issue_entry_WIRE_183_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_206; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_sxl = _issue_entry_WIRE_183_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_205; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_uxl = _issue_entry_WIRE_183_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_204; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_sd_rv32 = _issue_entry_WIRE_183_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_203; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_zero1 = _issue_entry_WIRE_183_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_202; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_tsr = _issue_entry_WIRE_183_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_201; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_tw = _issue_entry_WIRE_183_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_200; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_tvm = _issue_entry_WIRE_183_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_199; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_mxr = _issue_entry_WIRE_183_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_198; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_sum = _issue_entry_WIRE_183_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_197; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_mprv = _issue_entry_WIRE_183_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_196; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_xs = _issue_entry_WIRE_183_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_195; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_fs = _issue_entry_WIRE_183_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_194; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_mpp = _issue_entry_WIRE_183_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_193; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_vs = _issue_entry_WIRE_183_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_192; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_spp = _issue_entry_WIRE_183_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_191; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_mpie = _issue_entry_WIRE_183_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_190; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_ube = _issue_entry_WIRE_183_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_189; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_spie = _issue_entry_WIRE_183_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_188; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_upie = _issue_entry_WIRE_183_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_187; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_mie = _issue_entry_WIRE_183_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_186; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_hie = _issue_entry_WIRE_183_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_185; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_sie = _issue_entry_WIRE_183_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_184; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_status_uie = _issue_entry_WIRE_183_uie; // @[Mux.scala:30:73]
wire _issue_entry_T_2825 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2826 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2827 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2828 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2829 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2830 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2831 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2832 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2833 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2834 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2835 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2836 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2837 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2838 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2839 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2840 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2841 = _issue_entry_T_2825 | _issue_entry_T_2826; // @[Mux.scala:30:73]
wire _issue_entry_T_2842 = _issue_entry_T_2841 | _issue_entry_T_2827; // @[Mux.scala:30:73]
wire _issue_entry_T_2843 = _issue_entry_T_2842 | _issue_entry_T_2828; // @[Mux.scala:30:73]
wire _issue_entry_T_2844 = _issue_entry_T_2843 | _issue_entry_T_2829; // @[Mux.scala:30:73]
wire _issue_entry_T_2845 = _issue_entry_T_2844 | _issue_entry_T_2830; // @[Mux.scala:30:73]
wire _issue_entry_T_2846 = _issue_entry_T_2845 | _issue_entry_T_2831; // @[Mux.scala:30:73]
wire _issue_entry_T_2847 = _issue_entry_T_2846 | _issue_entry_T_2832; // @[Mux.scala:30:73]
wire _issue_entry_T_2848 = _issue_entry_T_2847 | _issue_entry_T_2833; // @[Mux.scala:30:73]
wire _issue_entry_T_2849 = _issue_entry_T_2848 | _issue_entry_T_2834; // @[Mux.scala:30:73]
wire _issue_entry_T_2850 = _issue_entry_T_2849 | _issue_entry_T_2835; // @[Mux.scala:30:73]
wire _issue_entry_T_2851 = _issue_entry_T_2850 | _issue_entry_T_2836; // @[Mux.scala:30:73]
wire _issue_entry_T_2852 = _issue_entry_T_2851 | _issue_entry_T_2837; // @[Mux.scala:30:73]
wire _issue_entry_T_2853 = _issue_entry_T_2852 | _issue_entry_T_2838; // @[Mux.scala:30:73]
wire _issue_entry_T_2854 = _issue_entry_T_2853 | _issue_entry_T_2839; // @[Mux.scala:30:73]
wire _issue_entry_T_2855 = _issue_entry_T_2854 | _issue_entry_T_2840; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_184 = _issue_entry_T_2855; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_uie = _issue_entry_WIRE_184; // @[Mux.scala:30:73]
wire _issue_entry_T_2856 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2857 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2858 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2859 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2860 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2861 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2862 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2863 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2864 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2865 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2866 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2867 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2868 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2869 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2870 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2871 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2872 = _issue_entry_T_2856 | _issue_entry_T_2857; // @[Mux.scala:30:73]
wire _issue_entry_T_2873 = _issue_entry_T_2872 | _issue_entry_T_2858; // @[Mux.scala:30:73]
wire _issue_entry_T_2874 = _issue_entry_T_2873 | _issue_entry_T_2859; // @[Mux.scala:30:73]
wire _issue_entry_T_2875 = _issue_entry_T_2874 | _issue_entry_T_2860; // @[Mux.scala:30:73]
wire _issue_entry_T_2876 = _issue_entry_T_2875 | _issue_entry_T_2861; // @[Mux.scala:30:73]
wire _issue_entry_T_2877 = _issue_entry_T_2876 | _issue_entry_T_2862; // @[Mux.scala:30:73]
wire _issue_entry_T_2878 = _issue_entry_T_2877 | _issue_entry_T_2863; // @[Mux.scala:30:73]
wire _issue_entry_T_2879 = _issue_entry_T_2878 | _issue_entry_T_2864; // @[Mux.scala:30:73]
wire _issue_entry_T_2880 = _issue_entry_T_2879 | _issue_entry_T_2865; // @[Mux.scala:30:73]
wire _issue_entry_T_2881 = _issue_entry_T_2880 | _issue_entry_T_2866; // @[Mux.scala:30:73]
wire _issue_entry_T_2882 = _issue_entry_T_2881 | _issue_entry_T_2867; // @[Mux.scala:30:73]
wire _issue_entry_T_2883 = _issue_entry_T_2882 | _issue_entry_T_2868; // @[Mux.scala:30:73]
wire _issue_entry_T_2884 = _issue_entry_T_2883 | _issue_entry_T_2869; // @[Mux.scala:30:73]
wire _issue_entry_T_2885 = _issue_entry_T_2884 | _issue_entry_T_2870; // @[Mux.scala:30:73]
wire _issue_entry_T_2886 = _issue_entry_T_2885 | _issue_entry_T_2871; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_185 = _issue_entry_T_2886; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_sie = _issue_entry_WIRE_185; // @[Mux.scala:30:73]
wire _issue_entry_T_2887 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2888 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2889 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2890 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2891 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2892 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2893 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2894 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2895 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2896 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2897 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2898 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2899 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2900 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2901 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2902 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2903 = _issue_entry_T_2887 | _issue_entry_T_2888; // @[Mux.scala:30:73]
wire _issue_entry_T_2904 = _issue_entry_T_2903 | _issue_entry_T_2889; // @[Mux.scala:30:73]
wire _issue_entry_T_2905 = _issue_entry_T_2904 | _issue_entry_T_2890; // @[Mux.scala:30:73]
wire _issue_entry_T_2906 = _issue_entry_T_2905 | _issue_entry_T_2891; // @[Mux.scala:30:73]
wire _issue_entry_T_2907 = _issue_entry_T_2906 | _issue_entry_T_2892; // @[Mux.scala:30:73]
wire _issue_entry_T_2908 = _issue_entry_T_2907 | _issue_entry_T_2893; // @[Mux.scala:30:73]
wire _issue_entry_T_2909 = _issue_entry_T_2908 | _issue_entry_T_2894; // @[Mux.scala:30:73]
wire _issue_entry_T_2910 = _issue_entry_T_2909 | _issue_entry_T_2895; // @[Mux.scala:30:73]
wire _issue_entry_T_2911 = _issue_entry_T_2910 | _issue_entry_T_2896; // @[Mux.scala:30:73]
wire _issue_entry_T_2912 = _issue_entry_T_2911 | _issue_entry_T_2897; // @[Mux.scala:30:73]
wire _issue_entry_T_2913 = _issue_entry_T_2912 | _issue_entry_T_2898; // @[Mux.scala:30:73]
wire _issue_entry_T_2914 = _issue_entry_T_2913 | _issue_entry_T_2899; // @[Mux.scala:30:73]
wire _issue_entry_T_2915 = _issue_entry_T_2914 | _issue_entry_T_2900; // @[Mux.scala:30:73]
wire _issue_entry_T_2916 = _issue_entry_T_2915 | _issue_entry_T_2901; // @[Mux.scala:30:73]
wire _issue_entry_T_2917 = _issue_entry_T_2916 | _issue_entry_T_2902; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_186 = _issue_entry_T_2917; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_hie = _issue_entry_WIRE_186; // @[Mux.scala:30:73]
wire _issue_entry_T_2918 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2919 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2920 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2921 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2922 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2923 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2924 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2925 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2926 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2927 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2928 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2929 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2930 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2931 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2932 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2933 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2934 = _issue_entry_T_2918 | _issue_entry_T_2919; // @[Mux.scala:30:73]
wire _issue_entry_T_2935 = _issue_entry_T_2934 | _issue_entry_T_2920; // @[Mux.scala:30:73]
wire _issue_entry_T_2936 = _issue_entry_T_2935 | _issue_entry_T_2921; // @[Mux.scala:30:73]
wire _issue_entry_T_2937 = _issue_entry_T_2936 | _issue_entry_T_2922; // @[Mux.scala:30:73]
wire _issue_entry_T_2938 = _issue_entry_T_2937 | _issue_entry_T_2923; // @[Mux.scala:30:73]
wire _issue_entry_T_2939 = _issue_entry_T_2938 | _issue_entry_T_2924; // @[Mux.scala:30:73]
wire _issue_entry_T_2940 = _issue_entry_T_2939 | _issue_entry_T_2925; // @[Mux.scala:30:73]
wire _issue_entry_T_2941 = _issue_entry_T_2940 | _issue_entry_T_2926; // @[Mux.scala:30:73]
wire _issue_entry_T_2942 = _issue_entry_T_2941 | _issue_entry_T_2927; // @[Mux.scala:30:73]
wire _issue_entry_T_2943 = _issue_entry_T_2942 | _issue_entry_T_2928; // @[Mux.scala:30:73]
wire _issue_entry_T_2944 = _issue_entry_T_2943 | _issue_entry_T_2929; // @[Mux.scala:30:73]
wire _issue_entry_T_2945 = _issue_entry_T_2944 | _issue_entry_T_2930; // @[Mux.scala:30:73]
wire _issue_entry_T_2946 = _issue_entry_T_2945 | _issue_entry_T_2931; // @[Mux.scala:30:73]
wire _issue_entry_T_2947 = _issue_entry_T_2946 | _issue_entry_T_2932; // @[Mux.scala:30:73]
wire _issue_entry_T_2948 = _issue_entry_T_2947 | _issue_entry_T_2933; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_187 = _issue_entry_T_2948; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_mie = _issue_entry_WIRE_187; // @[Mux.scala:30:73]
wire _issue_entry_T_2949 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2950 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2951 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2952 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2953 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2954 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2955 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2956 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2957 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2958 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2959 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2960 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2961 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2962 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2963 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2964 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2965 = _issue_entry_T_2949 | _issue_entry_T_2950; // @[Mux.scala:30:73]
wire _issue_entry_T_2966 = _issue_entry_T_2965 | _issue_entry_T_2951; // @[Mux.scala:30:73]
wire _issue_entry_T_2967 = _issue_entry_T_2966 | _issue_entry_T_2952; // @[Mux.scala:30:73]
wire _issue_entry_T_2968 = _issue_entry_T_2967 | _issue_entry_T_2953; // @[Mux.scala:30:73]
wire _issue_entry_T_2969 = _issue_entry_T_2968 | _issue_entry_T_2954; // @[Mux.scala:30:73]
wire _issue_entry_T_2970 = _issue_entry_T_2969 | _issue_entry_T_2955; // @[Mux.scala:30:73]
wire _issue_entry_T_2971 = _issue_entry_T_2970 | _issue_entry_T_2956; // @[Mux.scala:30:73]
wire _issue_entry_T_2972 = _issue_entry_T_2971 | _issue_entry_T_2957; // @[Mux.scala:30:73]
wire _issue_entry_T_2973 = _issue_entry_T_2972 | _issue_entry_T_2958; // @[Mux.scala:30:73]
wire _issue_entry_T_2974 = _issue_entry_T_2973 | _issue_entry_T_2959; // @[Mux.scala:30:73]
wire _issue_entry_T_2975 = _issue_entry_T_2974 | _issue_entry_T_2960; // @[Mux.scala:30:73]
wire _issue_entry_T_2976 = _issue_entry_T_2975 | _issue_entry_T_2961; // @[Mux.scala:30:73]
wire _issue_entry_T_2977 = _issue_entry_T_2976 | _issue_entry_T_2962; // @[Mux.scala:30:73]
wire _issue_entry_T_2978 = _issue_entry_T_2977 | _issue_entry_T_2963; // @[Mux.scala:30:73]
wire _issue_entry_T_2979 = _issue_entry_T_2978 | _issue_entry_T_2964; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_188 = _issue_entry_T_2979; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_upie = _issue_entry_WIRE_188; // @[Mux.scala:30:73]
wire _issue_entry_T_2980 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2981 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2982 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2983 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2984 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2985 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2986 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2987 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2988 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2989 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2990 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2991 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2992 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2993 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2994 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2995 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_2996 = _issue_entry_T_2980 | _issue_entry_T_2981; // @[Mux.scala:30:73]
wire _issue_entry_T_2997 = _issue_entry_T_2996 | _issue_entry_T_2982; // @[Mux.scala:30:73]
wire _issue_entry_T_2998 = _issue_entry_T_2997 | _issue_entry_T_2983; // @[Mux.scala:30:73]
wire _issue_entry_T_2999 = _issue_entry_T_2998 | _issue_entry_T_2984; // @[Mux.scala:30:73]
wire _issue_entry_T_3000 = _issue_entry_T_2999 | _issue_entry_T_2985; // @[Mux.scala:30:73]
wire _issue_entry_T_3001 = _issue_entry_T_3000 | _issue_entry_T_2986; // @[Mux.scala:30:73]
wire _issue_entry_T_3002 = _issue_entry_T_3001 | _issue_entry_T_2987; // @[Mux.scala:30:73]
wire _issue_entry_T_3003 = _issue_entry_T_3002 | _issue_entry_T_2988; // @[Mux.scala:30:73]
wire _issue_entry_T_3004 = _issue_entry_T_3003 | _issue_entry_T_2989; // @[Mux.scala:30:73]
wire _issue_entry_T_3005 = _issue_entry_T_3004 | _issue_entry_T_2990; // @[Mux.scala:30:73]
wire _issue_entry_T_3006 = _issue_entry_T_3005 | _issue_entry_T_2991; // @[Mux.scala:30:73]
wire _issue_entry_T_3007 = _issue_entry_T_3006 | _issue_entry_T_2992; // @[Mux.scala:30:73]
wire _issue_entry_T_3008 = _issue_entry_T_3007 | _issue_entry_T_2993; // @[Mux.scala:30:73]
wire _issue_entry_T_3009 = _issue_entry_T_3008 | _issue_entry_T_2994; // @[Mux.scala:30:73]
wire _issue_entry_T_3010 = _issue_entry_T_3009 | _issue_entry_T_2995; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_189 = _issue_entry_T_3010; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_spie = _issue_entry_WIRE_189; // @[Mux.scala:30:73]
wire _issue_entry_T_3011 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3012 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3013 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3014 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3015 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3016 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3017 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3018 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3019 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3020 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3021 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3022 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3023 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3024 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3025 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3026 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_3027 = _issue_entry_T_3011 | _issue_entry_T_3012; // @[Mux.scala:30:73]
wire _issue_entry_T_3028 = _issue_entry_T_3027 | _issue_entry_T_3013; // @[Mux.scala:30:73]
wire _issue_entry_T_3029 = _issue_entry_T_3028 | _issue_entry_T_3014; // @[Mux.scala:30:73]
wire _issue_entry_T_3030 = _issue_entry_T_3029 | _issue_entry_T_3015; // @[Mux.scala:30:73]
wire _issue_entry_T_3031 = _issue_entry_T_3030 | _issue_entry_T_3016; // @[Mux.scala:30:73]
wire _issue_entry_T_3032 = _issue_entry_T_3031 | _issue_entry_T_3017; // @[Mux.scala:30:73]
wire _issue_entry_T_3033 = _issue_entry_T_3032 | _issue_entry_T_3018; // @[Mux.scala:30:73]
wire _issue_entry_T_3034 = _issue_entry_T_3033 | _issue_entry_T_3019; // @[Mux.scala:30:73]
wire _issue_entry_T_3035 = _issue_entry_T_3034 | _issue_entry_T_3020; // @[Mux.scala:30:73]
wire _issue_entry_T_3036 = _issue_entry_T_3035 | _issue_entry_T_3021; // @[Mux.scala:30:73]
wire _issue_entry_T_3037 = _issue_entry_T_3036 | _issue_entry_T_3022; // @[Mux.scala:30:73]
wire _issue_entry_T_3038 = _issue_entry_T_3037 | _issue_entry_T_3023; // @[Mux.scala:30:73]
wire _issue_entry_T_3039 = _issue_entry_T_3038 | _issue_entry_T_3024; // @[Mux.scala:30:73]
wire _issue_entry_T_3040 = _issue_entry_T_3039 | _issue_entry_T_3025; // @[Mux.scala:30:73]
wire _issue_entry_T_3041 = _issue_entry_T_3040 | _issue_entry_T_3026; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_190 = _issue_entry_T_3041; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_ube = _issue_entry_WIRE_190; // @[Mux.scala:30:73]
wire _issue_entry_T_3042 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3043 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3044 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3045 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3046 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3047 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3048 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3049 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3050 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3051 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3052 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3053 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3054 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3055 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3056 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3057 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_3058 = _issue_entry_T_3042 | _issue_entry_T_3043; // @[Mux.scala:30:73]
wire _issue_entry_T_3059 = _issue_entry_T_3058 | _issue_entry_T_3044; // @[Mux.scala:30:73]
wire _issue_entry_T_3060 = _issue_entry_T_3059 | _issue_entry_T_3045; // @[Mux.scala:30:73]
wire _issue_entry_T_3061 = _issue_entry_T_3060 | _issue_entry_T_3046; // @[Mux.scala:30:73]
wire _issue_entry_T_3062 = _issue_entry_T_3061 | _issue_entry_T_3047; // @[Mux.scala:30:73]
wire _issue_entry_T_3063 = _issue_entry_T_3062 | _issue_entry_T_3048; // @[Mux.scala:30:73]
wire _issue_entry_T_3064 = _issue_entry_T_3063 | _issue_entry_T_3049; // @[Mux.scala:30:73]
wire _issue_entry_T_3065 = _issue_entry_T_3064 | _issue_entry_T_3050; // @[Mux.scala:30:73]
wire _issue_entry_T_3066 = _issue_entry_T_3065 | _issue_entry_T_3051; // @[Mux.scala:30:73]
wire _issue_entry_T_3067 = _issue_entry_T_3066 | _issue_entry_T_3052; // @[Mux.scala:30:73]
wire _issue_entry_T_3068 = _issue_entry_T_3067 | _issue_entry_T_3053; // @[Mux.scala:30:73]
wire _issue_entry_T_3069 = _issue_entry_T_3068 | _issue_entry_T_3054; // @[Mux.scala:30:73]
wire _issue_entry_T_3070 = _issue_entry_T_3069 | _issue_entry_T_3055; // @[Mux.scala:30:73]
wire _issue_entry_T_3071 = _issue_entry_T_3070 | _issue_entry_T_3056; // @[Mux.scala:30:73]
wire _issue_entry_T_3072 = _issue_entry_T_3071 | _issue_entry_T_3057; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_191 = _issue_entry_T_3072; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_mpie = _issue_entry_WIRE_191; // @[Mux.scala:30:73]
wire _issue_entry_T_3073 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3074 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3075 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3076 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3077 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3078 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3079 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3080 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3081 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3082 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3083 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3084 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3085 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3086 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3087 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3088 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_3089 = _issue_entry_T_3073 | _issue_entry_T_3074; // @[Mux.scala:30:73]
wire _issue_entry_T_3090 = _issue_entry_T_3089 | _issue_entry_T_3075; // @[Mux.scala:30:73]
wire _issue_entry_T_3091 = _issue_entry_T_3090 | _issue_entry_T_3076; // @[Mux.scala:30:73]
wire _issue_entry_T_3092 = _issue_entry_T_3091 | _issue_entry_T_3077; // @[Mux.scala:30:73]
wire _issue_entry_T_3093 = _issue_entry_T_3092 | _issue_entry_T_3078; // @[Mux.scala:30:73]
wire _issue_entry_T_3094 = _issue_entry_T_3093 | _issue_entry_T_3079; // @[Mux.scala:30:73]
wire _issue_entry_T_3095 = _issue_entry_T_3094 | _issue_entry_T_3080; // @[Mux.scala:30:73]
wire _issue_entry_T_3096 = _issue_entry_T_3095 | _issue_entry_T_3081; // @[Mux.scala:30:73]
wire _issue_entry_T_3097 = _issue_entry_T_3096 | _issue_entry_T_3082; // @[Mux.scala:30:73]
wire _issue_entry_T_3098 = _issue_entry_T_3097 | _issue_entry_T_3083; // @[Mux.scala:30:73]
wire _issue_entry_T_3099 = _issue_entry_T_3098 | _issue_entry_T_3084; // @[Mux.scala:30:73]
wire _issue_entry_T_3100 = _issue_entry_T_3099 | _issue_entry_T_3085; // @[Mux.scala:30:73]
wire _issue_entry_T_3101 = _issue_entry_T_3100 | _issue_entry_T_3086; // @[Mux.scala:30:73]
wire _issue_entry_T_3102 = _issue_entry_T_3101 | _issue_entry_T_3087; // @[Mux.scala:30:73]
wire _issue_entry_T_3103 = _issue_entry_T_3102 | _issue_entry_T_3088; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_192 = _issue_entry_T_3103; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_spp = _issue_entry_WIRE_192; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3104 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3105 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3106 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3107 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3108 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3109 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3110 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3111 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3112 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3113 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3114 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3115 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3116 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3117 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3118 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3119 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3120 = _issue_entry_T_3104 | _issue_entry_T_3105; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3121 = _issue_entry_T_3120 | _issue_entry_T_3106; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3122 = _issue_entry_T_3121 | _issue_entry_T_3107; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3123 = _issue_entry_T_3122 | _issue_entry_T_3108; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3124 = _issue_entry_T_3123 | _issue_entry_T_3109; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3125 = _issue_entry_T_3124 | _issue_entry_T_3110; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3126 = _issue_entry_T_3125 | _issue_entry_T_3111; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3127 = _issue_entry_T_3126 | _issue_entry_T_3112; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3128 = _issue_entry_T_3127 | _issue_entry_T_3113; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3129 = _issue_entry_T_3128 | _issue_entry_T_3114; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3130 = _issue_entry_T_3129 | _issue_entry_T_3115; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3131 = _issue_entry_T_3130 | _issue_entry_T_3116; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3132 = _issue_entry_T_3131 | _issue_entry_T_3117; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3133 = _issue_entry_T_3132 | _issue_entry_T_3118; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3134 = _issue_entry_T_3133 | _issue_entry_T_3119; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_193 = _issue_entry_T_3134; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_vs = _issue_entry_WIRE_193; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3135 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3136 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3137 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3138 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3139 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3140 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3141 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3142 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3143 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3144 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3145 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3146 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3147 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3148 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3149 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3150 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3151 = _issue_entry_T_3135 | _issue_entry_T_3136; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3152 = _issue_entry_T_3151 | _issue_entry_T_3137; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3153 = _issue_entry_T_3152 | _issue_entry_T_3138; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3154 = _issue_entry_T_3153 | _issue_entry_T_3139; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3155 = _issue_entry_T_3154 | _issue_entry_T_3140; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3156 = _issue_entry_T_3155 | _issue_entry_T_3141; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3157 = _issue_entry_T_3156 | _issue_entry_T_3142; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3158 = _issue_entry_T_3157 | _issue_entry_T_3143; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3159 = _issue_entry_T_3158 | _issue_entry_T_3144; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3160 = _issue_entry_T_3159 | _issue_entry_T_3145; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3161 = _issue_entry_T_3160 | _issue_entry_T_3146; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3162 = _issue_entry_T_3161 | _issue_entry_T_3147; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3163 = _issue_entry_T_3162 | _issue_entry_T_3148; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3164 = _issue_entry_T_3163 | _issue_entry_T_3149; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3165 = _issue_entry_T_3164 | _issue_entry_T_3150; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_194 = _issue_entry_T_3165; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_mpp = _issue_entry_WIRE_194; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3166 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3167 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3168 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3169 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3170 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3171 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3172 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3173 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3174 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3175 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3176 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3177 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3178 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3179 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3180 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3181 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3182 = _issue_entry_T_3166 | _issue_entry_T_3167; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3183 = _issue_entry_T_3182 | _issue_entry_T_3168; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3184 = _issue_entry_T_3183 | _issue_entry_T_3169; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3185 = _issue_entry_T_3184 | _issue_entry_T_3170; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3186 = _issue_entry_T_3185 | _issue_entry_T_3171; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3187 = _issue_entry_T_3186 | _issue_entry_T_3172; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3188 = _issue_entry_T_3187 | _issue_entry_T_3173; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3189 = _issue_entry_T_3188 | _issue_entry_T_3174; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3190 = _issue_entry_T_3189 | _issue_entry_T_3175; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3191 = _issue_entry_T_3190 | _issue_entry_T_3176; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3192 = _issue_entry_T_3191 | _issue_entry_T_3177; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3193 = _issue_entry_T_3192 | _issue_entry_T_3178; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3194 = _issue_entry_T_3193 | _issue_entry_T_3179; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3195 = _issue_entry_T_3194 | _issue_entry_T_3180; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3196 = _issue_entry_T_3195 | _issue_entry_T_3181; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_195 = _issue_entry_T_3196; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_fs = _issue_entry_WIRE_195; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3197 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3198 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3199 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3200 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3201 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3202 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3203 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3204 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3205 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3206 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3207 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3208 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3209 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3210 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3211 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3212 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3213 = _issue_entry_T_3197 | _issue_entry_T_3198; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3214 = _issue_entry_T_3213 | _issue_entry_T_3199; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3215 = _issue_entry_T_3214 | _issue_entry_T_3200; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3216 = _issue_entry_T_3215 | _issue_entry_T_3201; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3217 = _issue_entry_T_3216 | _issue_entry_T_3202; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3218 = _issue_entry_T_3217 | _issue_entry_T_3203; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3219 = _issue_entry_T_3218 | _issue_entry_T_3204; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3220 = _issue_entry_T_3219 | _issue_entry_T_3205; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3221 = _issue_entry_T_3220 | _issue_entry_T_3206; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3222 = _issue_entry_T_3221 | _issue_entry_T_3207; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3223 = _issue_entry_T_3222 | _issue_entry_T_3208; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3224 = _issue_entry_T_3223 | _issue_entry_T_3209; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3225 = _issue_entry_T_3224 | _issue_entry_T_3210; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3226 = _issue_entry_T_3225 | _issue_entry_T_3211; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3227 = _issue_entry_T_3226 | _issue_entry_T_3212; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_196 = _issue_entry_T_3227; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_xs = _issue_entry_WIRE_196; // @[Mux.scala:30:73]
wire _issue_entry_T_3228 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3229 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3230 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3231 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3232 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3233 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3234 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3235 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3236 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3237 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3238 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3239 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3240 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3241 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3242 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3243 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3244 = _issue_entry_T_3228 | _issue_entry_T_3229; // @[Mux.scala:30:73]
wire _issue_entry_T_3245 = _issue_entry_T_3244 | _issue_entry_T_3230; // @[Mux.scala:30:73]
wire _issue_entry_T_3246 = _issue_entry_T_3245 | _issue_entry_T_3231; // @[Mux.scala:30:73]
wire _issue_entry_T_3247 = _issue_entry_T_3246 | _issue_entry_T_3232; // @[Mux.scala:30:73]
wire _issue_entry_T_3248 = _issue_entry_T_3247 | _issue_entry_T_3233; // @[Mux.scala:30:73]
wire _issue_entry_T_3249 = _issue_entry_T_3248 | _issue_entry_T_3234; // @[Mux.scala:30:73]
wire _issue_entry_T_3250 = _issue_entry_T_3249 | _issue_entry_T_3235; // @[Mux.scala:30:73]
wire _issue_entry_T_3251 = _issue_entry_T_3250 | _issue_entry_T_3236; // @[Mux.scala:30:73]
wire _issue_entry_T_3252 = _issue_entry_T_3251 | _issue_entry_T_3237; // @[Mux.scala:30:73]
wire _issue_entry_T_3253 = _issue_entry_T_3252 | _issue_entry_T_3238; // @[Mux.scala:30:73]
wire _issue_entry_T_3254 = _issue_entry_T_3253 | _issue_entry_T_3239; // @[Mux.scala:30:73]
wire _issue_entry_T_3255 = _issue_entry_T_3254 | _issue_entry_T_3240; // @[Mux.scala:30:73]
wire _issue_entry_T_3256 = _issue_entry_T_3255 | _issue_entry_T_3241; // @[Mux.scala:30:73]
wire _issue_entry_T_3257 = _issue_entry_T_3256 | _issue_entry_T_3242; // @[Mux.scala:30:73]
wire _issue_entry_T_3258 = _issue_entry_T_3257 | _issue_entry_T_3243; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_197 = _issue_entry_T_3258; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_mprv = _issue_entry_WIRE_197; // @[Mux.scala:30:73]
wire _issue_entry_T_3259 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3260 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3261 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3262 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3263 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3264 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3265 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3266 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3267 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3268 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3269 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3270 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3271 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3272 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3273 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3274 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_3275 = _issue_entry_T_3259 | _issue_entry_T_3260; // @[Mux.scala:30:73]
wire _issue_entry_T_3276 = _issue_entry_T_3275 | _issue_entry_T_3261; // @[Mux.scala:30:73]
wire _issue_entry_T_3277 = _issue_entry_T_3276 | _issue_entry_T_3262; // @[Mux.scala:30:73]
wire _issue_entry_T_3278 = _issue_entry_T_3277 | _issue_entry_T_3263; // @[Mux.scala:30:73]
wire _issue_entry_T_3279 = _issue_entry_T_3278 | _issue_entry_T_3264; // @[Mux.scala:30:73]
wire _issue_entry_T_3280 = _issue_entry_T_3279 | _issue_entry_T_3265; // @[Mux.scala:30:73]
wire _issue_entry_T_3281 = _issue_entry_T_3280 | _issue_entry_T_3266; // @[Mux.scala:30:73]
wire _issue_entry_T_3282 = _issue_entry_T_3281 | _issue_entry_T_3267; // @[Mux.scala:30:73]
wire _issue_entry_T_3283 = _issue_entry_T_3282 | _issue_entry_T_3268; // @[Mux.scala:30:73]
wire _issue_entry_T_3284 = _issue_entry_T_3283 | _issue_entry_T_3269; // @[Mux.scala:30:73]
wire _issue_entry_T_3285 = _issue_entry_T_3284 | _issue_entry_T_3270; // @[Mux.scala:30:73]
wire _issue_entry_T_3286 = _issue_entry_T_3285 | _issue_entry_T_3271; // @[Mux.scala:30:73]
wire _issue_entry_T_3287 = _issue_entry_T_3286 | _issue_entry_T_3272; // @[Mux.scala:30:73]
wire _issue_entry_T_3288 = _issue_entry_T_3287 | _issue_entry_T_3273; // @[Mux.scala:30:73]
wire _issue_entry_T_3289 = _issue_entry_T_3288 | _issue_entry_T_3274; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_198 = _issue_entry_T_3289; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_sum = _issue_entry_WIRE_198; // @[Mux.scala:30:73]
wire _issue_entry_T_3290 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3291 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3292 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3293 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3294 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3295 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3296 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3297 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3298 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3299 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3300 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3301 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3302 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3303 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3304 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3305 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3306 = _issue_entry_T_3290 | _issue_entry_T_3291; // @[Mux.scala:30:73]
wire _issue_entry_T_3307 = _issue_entry_T_3306 | _issue_entry_T_3292; // @[Mux.scala:30:73]
wire _issue_entry_T_3308 = _issue_entry_T_3307 | _issue_entry_T_3293; // @[Mux.scala:30:73]
wire _issue_entry_T_3309 = _issue_entry_T_3308 | _issue_entry_T_3294; // @[Mux.scala:30:73]
wire _issue_entry_T_3310 = _issue_entry_T_3309 | _issue_entry_T_3295; // @[Mux.scala:30:73]
wire _issue_entry_T_3311 = _issue_entry_T_3310 | _issue_entry_T_3296; // @[Mux.scala:30:73]
wire _issue_entry_T_3312 = _issue_entry_T_3311 | _issue_entry_T_3297; // @[Mux.scala:30:73]
wire _issue_entry_T_3313 = _issue_entry_T_3312 | _issue_entry_T_3298; // @[Mux.scala:30:73]
wire _issue_entry_T_3314 = _issue_entry_T_3313 | _issue_entry_T_3299; // @[Mux.scala:30:73]
wire _issue_entry_T_3315 = _issue_entry_T_3314 | _issue_entry_T_3300; // @[Mux.scala:30:73]
wire _issue_entry_T_3316 = _issue_entry_T_3315 | _issue_entry_T_3301; // @[Mux.scala:30:73]
wire _issue_entry_T_3317 = _issue_entry_T_3316 | _issue_entry_T_3302; // @[Mux.scala:30:73]
wire _issue_entry_T_3318 = _issue_entry_T_3317 | _issue_entry_T_3303; // @[Mux.scala:30:73]
wire _issue_entry_T_3319 = _issue_entry_T_3318 | _issue_entry_T_3304; // @[Mux.scala:30:73]
wire _issue_entry_T_3320 = _issue_entry_T_3319 | _issue_entry_T_3305; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_199 = _issue_entry_T_3320; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_mxr = _issue_entry_WIRE_199; // @[Mux.scala:30:73]
wire _issue_entry_T_3321 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3322 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3323 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3324 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3325 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3326 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3327 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3328 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3329 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3330 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3331 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3332 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3333 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3334 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3335 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3336 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_3337 = _issue_entry_T_3321 | _issue_entry_T_3322; // @[Mux.scala:30:73]
wire _issue_entry_T_3338 = _issue_entry_T_3337 | _issue_entry_T_3323; // @[Mux.scala:30:73]
wire _issue_entry_T_3339 = _issue_entry_T_3338 | _issue_entry_T_3324; // @[Mux.scala:30:73]
wire _issue_entry_T_3340 = _issue_entry_T_3339 | _issue_entry_T_3325; // @[Mux.scala:30:73]
wire _issue_entry_T_3341 = _issue_entry_T_3340 | _issue_entry_T_3326; // @[Mux.scala:30:73]
wire _issue_entry_T_3342 = _issue_entry_T_3341 | _issue_entry_T_3327; // @[Mux.scala:30:73]
wire _issue_entry_T_3343 = _issue_entry_T_3342 | _issue_entry_T_3328; // @[Mux.scala:30:73]
wire _issue_entry_T_3344 = _issue_entry_T_3343 | _issue_entry_T_3329; // @[Mux.scala:30:73]
wire _issue_entry_T_3345 = _issue_entry_T_3344 | _issue_entry_T_3330; // @[Mux.scala:30:73]
wire _issue_entry_T_3346 = _issue_entry_T_3345 | _issue_entry_T_3331; // @[Mux.scala:30:73]
wire _issue_entry_T_3347 = _issue_entry_T_3346 | _issue_entry_T_3332; // @[Mux.scala:30:73]
wire _issue_entry_T_3348 = _issue_entry_T_3347 | _issue_entry_T_3333; // @[Mux.scala:30:73]
wire _issue_entry_T_3349 = _issue_entry_T_3348 | _issue_entry_T_3334; // @[Mux.scala:30:73]
wire _issue_entry_T_3350 = _issue_entry_T_3349 | _issue_entry_T_3335; // @[Mux.scala:30:73]
wire _issue_entry_T_3351 = _issue_entry_T_3350 | _issue_entry_T_3336; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_200 = _issue_entry_T_3351; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_tvm = _issue_entry_WIRE_200; // @[Mux.scala:30:73]
wire _issue_entry_T_3352 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3353 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3354 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3355 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3356 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3357 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3358 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3359 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3360 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3361 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3362 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3363 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3364 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3365 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3366 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3367 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_3368 = _issue_entry_T_3352 | _issue_entry_T_3353; // @[Mux.scala:30:73]
wire _issue_entry_T_3369 = _issue_entry_T_3368 | _issue_entry_T_3354; // @[Mux.scala:30:73]
wire _issue_entry_T_3370 = _issue_entry_T_3369 | _issue_entry_T_3355; // @[Mux.scala:30:73]
wire _issue_entry_T_3371 = _issue_entry_T_3370 | _issue_entry_T_3356; // @[Mux.scala:30:73]
wire _issue_entry_T_3372 = _issue_entry_T_3371 | _issue_entry_T_3357; // @[Mux.scala:30:73]
wire _issue_entry_T_3373 = _issue_entry_T_3372 | _issue_entry_T_3358; // @[Mux.scala:30:73]
wire _issue_entry_T_3374 = _issue_entry_T_3373 | _issue_entry_T_3359; // @[Mux.scala:30:73]
wire _issue_entry_T_3375 = _issue_entry_T_3374 | _issue_entry_T_3360; // @[Mux.scala:30:73]
wire _issue_entry_T_3376 = _issue_entry_T_3375 | _issue_entry_T_3361; // @[Mux.scala:30:73]
wire _issue_entry_T_3377 = _issue_entry_T_3376 | _issue_entry_T_3362; // @[Mux.scala:30:73]
wire _issue_entry_T_3378 = _issue_entry_T_3377 | _issue_entry_T_3363; // @[Mux.scala:30:73]
wire _issue_entry_T_3379 = _issue_entry_T_3378 | _issue_entry_T_3364; // @[Mux.scala:30:73]
wire _issue_entry_T_3380 = _issue_entry_T_3379 | _issue_entry_T_3365; // @[Mux.scala:30:73]
wire _issue_entry_T_3381 = _issue_entry_T_3380 | _issue_entry_T_3366; // @[Mux.scala:30:73]
wire _issue_entry_T_3382 = _issue_entry_T_3381 | _issue_entry_T_3367; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_201 = _issue_entry_T_3382; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_tw = _issue_entry_WIRE_201; // @[Mux.scala:30:73]
wire _issue_entry_T_3383 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3384 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3385 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3386 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3387 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3388 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3389 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3390 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3391 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3392 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3393 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3394 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3395 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3396 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3397 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3398 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_3399 = _issue_entry_T_3383 | _issue_entry_T_3384; // @[Mux.scala:30:73]
wire _issue_entry_T_3400 = _issue_entry_T_3399 | _issue_entry_T_3385; // @[Mux.scala:30:73]
wire _issue_entry_T_3401 = _issue_entry_T_3400 | _issue_entry_T_3386; // @[Mux.scala:30:73]
wire _issue_entry_T_3402 = _issue_entry_T_3401 | _issue_entry_T_3387; // @[Mux.scala:30:73]
wire _issue_entry_T_3403 = _issue_entry_T_3402 | _issue_entry_T_3388; // @[Mux.scala:30:73]
wire _issue_entry_T_3404 = _issue_entry_T_3403 | _issue_entry_T_3389; // @[Mux.scala:30:73]
wire _issue_entry_T_3405 = _issue_entry_T_3404 | _issue_entry_T_3390; // @[Mux.scala:30:73]
wire _issue_entry_T_3406 = _issue_entry_T_3405 | _issue_entry_T_3391; // @[Mux.scala:30:73]
wire _issue_entry_T_3407 = _issue_entry_T_3406 | _issue_entry_T_3392; // @[Mux.scala:30:73]
wire _issue_entry_T_3408 = _issue_entry_T_3407 | _issue_entry_T_3393; // @[Mux.scala:30:73]
wire _issue_entry_T_3409 = _issue_entry_T_3408 | _issue_entry_T_3394; // @[Mux.scala:30:73]
wire _issue_entry_T_3410 = _issue_entry_T_3409 | _issue_entry_T_3395; // @[Mux.scala:30:73]
wire _issue_entry_T_3411 = _issue_entry_T_3410 | _issue_entry_T_3396; // @[Mux.scala:30:73]
wire _issue_entry_T_3412 = _issue_entry_T_3411 | _issue_entry_T_3397; // @[Mux.scala:30:73]
wire _issue_entry_T_3413 = _issue_entry_T_3412 | _issue_entry_T_3398; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_202 = _issue_entry_T_3413; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_tsr = _issue_entry_WIRE_202; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3414 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3415 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3416 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3417 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3418 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3419 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3420 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3421 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3422 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3423 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3424 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3425 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3426 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3427 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3428 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3429 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_3430 = _issue_entry_T_3414 | _issue_entry_T_3415; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3431 = _issue_entry_T_3430 | _issue_entry_T_3416; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3432 = _issue_entry_T_3431 | _issue_entry_T_3417; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3433 = _issue_entry_T_3432 | _issue_entry_T_3418; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3434 = _issue_entry_T_3433 | _issue_entry_T_3419; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3435 = _issue_entry_T_3434 | _issue_entry_T_3420; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3436 = _issue_entry_T_3435 | _issue_entry_T_3421; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3437 = _issue_entry_T_3436 | _issue_entry_T_3422; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3438 = _issue_entry_T_3437 | _issue_entry_T_3423; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3439 = _issue_entry_T_3438 | _issue_entry_T_3424; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3440 = _issue_entry_T_3439 | _issue_entry_T_3425; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3441 = _issue_entry_T_3440 | _issue_entry_T_3426; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3442 = _issue_entry_T_3441 | _issue_entry_T_3427; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3443 = _issue_entry_T_3442 | _issue_entry_T_3428; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_3444 = _issue_entry_T_3443 | _issue_entry_T_3429; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_203 = _issue_entry_T_3444; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_zero1 = _issue_entry_WIRE_203; // @[Mux.scala:30:73]
wire _issue_entry_T_3445 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3446 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3447 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3448 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3449 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3450 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3451 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3452 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3453 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3454 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3455 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3456 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3457 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3458 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3459 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3460 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_3461 = _issue_entry_T_3445 | _issue_entry_T_3446; // @[Mux.scala:30:73]
wire _issue_entry_T_3462 = _issue_entry_T_3461 | _issue_entry_T_3447; // @[Mux.scala:30:73]
wire _issue_entry_T_3463 = _issue_entry_T_3462 | _issue_entry_T_3448; // @[Mux.scala:30:73]
wire _issue_entry_T_3464 = _issue_entry_T_3463 | _issue_entry_T_3449; // @[Mux.scala:30:73]
wire _issue_entry_T_3465 = _issue_entry_T_3464 | _issue_entry_T_3450; // @[Mux.scala:30:73]
wire _issue_entry_T_3466 = _issue_entry_T_3465 | _issue_entry_T_3451; // @[Mux.scala:30:73]
wire _issue_entry_T_3467 = _issue_entry_T_3466 | _issue_entry_T_3452; // @[Mux.scala:30:73]
wire _issue_entry_T_3468 = _issue_entry_T_3467 | _issue_entry_T_3453; // @[Mux.scala:30:73]
wire _issue_entry_T_3469 = _issue_entry_T_3468 | _issue_entry_T_3454; // @[Mux.scala:30:73]
wire _issue_entry_T_3470 = _issue_entry_T_3469 | _issue_entry_T_3455; // @[Mux.scala:30:73]
wire _issue_entry_T_3471 = _issue_entry_T_3470 | _issue_entry_T_3456; // @[Mux.scala:30:73]
wire _issue_entry_T_3472 = _issue_entry_T_3471 | _issue_entry_T_3457; // @[Mux.scala:30:73]
wire _issue_entry_T_3473 = _issue_entry_T_3472 | _issue_entry_T_3458; // @[Mux.scala:30:73]
wire _issue_entry_T_3474 = _issue_entry_T_3473 | _issue_entry_T_3459; // @[Mux.scala:30:73]
wire _issue_entry_T_3475 = _issue_entry_T_3474 | _issue_entry_T_3460; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_204 = _issue_entry_T_3475; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_sd_rv32 = _issue_entry_WIRE_204; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3476 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3477 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3478 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3479 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3480 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3481 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3482 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3483 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3484 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3485 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3486 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3487 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3488 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3489 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3490 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3491 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3492 = _issue_entry_T_3476 | _issue_entry_T_3477; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3493 = _issue_entry_T_3492 | _issue_entry_T_3478; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3494 = _issue_entry_T_3493 | _issue_entry_T_3479; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3495 = _issue_entry_T_3494 | _issue_entry_T_3480; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3496 = _issue_entry_T_3495 | _issue_entry_T_3481; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3497 = _issue_entry_T_3496 | _issue_entry_T_3482; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3498 = _issue_entry_T_3497 | _issue_entry_T_3483; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3499 = _issue_entry_T_3498 | _issue_entry_T_3484; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3500 = _issue_entry_T_3499 | _issue_entry_T_3485; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3501 = _issue_entry_T_3500 | _issue_entry_T_3486; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3502 = _issue_entry_T_3501 | _issue_entry_T_3487; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3503 = _issue_entry_T_3502 | _issue_entry_T_3488; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3504 = _issue_entry_T_3503 | _issue_entry_T_3489; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3505 = _issue_entry_T_3504 | _issue_entry_T_3490; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3506 = _issue_entry_T_3505 | _issue_entry_T_3491; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_205 = _issue_entry_T_3506; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_uxl = _issue_entry_WIRE_205; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3507 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3508 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3509 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3510 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3511 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3512 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3513 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3514 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3515 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3516 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3517 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3518 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3519 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3520 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3521 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3522 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3523 = _issue_entry_T_3507 | _issue_entry_T_3508; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3524 = _issue_entry_T_3523 | _issue_entry_T_3509; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3525 = _issue_entry_T_3524 | _issue_entry_T_3510; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3526 = _issue_entry_T_3525 | _issue_entry_T_3511; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3527 = _issue_entry_T_3526 | _issue_entry_T_3512; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3528 = _issue_entry_T_3527 | _issue_entry_T_3513; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3529 = _issue_entry_T_3528 | _issue_entry_T_3514; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3530 = _issue_entry_T_3529 | _issue_entry_T_3515; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3531 = _issue_entry_T_3530 | _issue_entry_T_3516; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3532 = _issue_entry_T_3531 | _issue_entry_T_3517; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3533 = _issue_entry_T_3532 | _issue_entry_T_3518; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3534 = _issue_entry_T_3533 | _issue_entry_T_3519; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3535 = _issue_entry_T_3534 | _issue_entry_T_3520; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3536 = _issue_entry_T_3535 | _issue_entry_T_3521; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3537 = _issue_entry_T_3536 | _issue_entry_T_3522; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_206 = _issue_entry_T_3537; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_sxl = _issue_entry_WIRE_206; // @[Mux.scala:30:73]
wire _issue_entry_T_3538 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3539 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3540 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3541 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3542 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3543 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3544 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3545 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3546 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3547 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3548 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3549 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3550 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3551 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3552 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3553 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3554 = _issue_entry_T_3538 | _issue_entry_T_3539; // @[Mux.scala:30:73]
wire _issue_entry_T_3555 = _issue_entry_T_3554 | _issue_entry_T_3540; // @[Mux.scala:30:73]
wire _issue_entry_T_3556 = _issue_entry_T_3555 | _issue_entry_T_3541; // @[Mux.scala:30:73]
wire _issue_entry_T_3557 = _issue_entry_T_3556 | _issue_entry_T_3542; // @[Mux.scala:30:73]
wire _issue_entry_T_3558 = _issue_entry_T_3557 | _issue_entry_T_3543; // @[Mux.scala:30:73]
wire _issue_entry_T_3559 = _issue_entry_T_3558 | _issue_entry_T_3544; // @[Mux.scala:30:73]
wire _issue_entry_T_3560 = _issue_entry_T_3559 | _issue_entry_T_3545; // @[Mux.scala:30:73]
wire _issue_entry_T_3561 = _issue_entry_T_3560 | _issue_entry_T_3546; // @[Mux.scala:30:73]
wire _issue_entry_T_3562 = _issue_entry_T_3561 | _issue_entry_T_3547; // @[Mux.scala:30:73]
wire _issue_entry_T_3563 = _issue_entry_T_3562 | _issue_entry_T_3548; // @[Mux.scala:30:73]
wire _issue_entry_T_3564 = _issue_entry_T_3563 | _issue_entry_T_3549; // @[Mux.scala:30:73]
wire _issue_entry_T_3565 = _issue_entry_T_3564 | _issue_entry_T_3550; // @[Mux.scala:30:73]
wire _issue_entry_T_3566 = _issue_entry_T_3565 | _issue_entry_T_3551; // @[Mux.scala:30:73]
wire _issue_entry_T_3567 = _issue_entry_T_3566 | _issue_entry_T_3552; // @[Mux.scala:30:73]
wire _issue_entry_T_3568 = _issue_entry_T_3567 | _issue_entry_T_3553; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_207 = _issue_entry_T_3568; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_sbe = _issue_entry_WIRE_207; // @[Mux.scala:30:73]
wire _issue_entry_T_3569 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3570 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3571 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3572 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3573 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3574 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3575 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3576 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3577 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3578 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3579 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3580 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3581 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3582 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3583 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3584 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_3585 = _issue_entry_T_3569 | _issue_entry_T_3570; // @[Mux.scala:30:73]
wire _issue_entry_T_3586 = _issue_entry_T_3585 | _issue_entry_T_3571; // @[Mux.scala:30:73]
wire _issue_entry_T_3587 = _issue_entry_T_3586 | _issue_entry_T_3572; // @[Mux.scala:30:73]
wire _issue_entry_T_3588 = _issue_entry_T_3587 | _issue_entry_T_3573; // @[Mux.scala:30:73]
wire _issue_entry_T_3589 = _issue_entry_T_3588 | _issue_entry_T_3574; // @[Mux.scala:30:73]
wire _issue_entry_T_3590 = _issue_entry_T_3589 | _issue_entry_T_3575; // @[Mux.scala:30:73]
wire _issue_entry_T_3591 = _issue_entry_T_3590 | _issue_entry_T_3576; // @[Mux.scala:30:73]
wire _issue_entry_T_3592 = _issue_entry_T_3591 | _issue_entry_T_3577; // @[Mux.scala:30:73]
wire _issue_entry_T_3593 = _issue_entry_T_3592 | _issue_entry_T_3578; // @[Mux.scala:30:73]
wire _issue_entry_T_3594 = _issue_entry_T_3593 | _issue_entry_T_3579; // @[Mux.scala:30:73]
wire _issue_entry_T_3595 = _issue_entry_T_3594 | _issue_entry_T_3580; // @[Mux.scala:30:73]
wire _issue_entry_T_3596 = _issue_entry_T_3595 | _issue_entry_T_3581; // @[Mux.scala:30:73]
wire _issue_entry_T_3597 = _issue_entry_T_3596 | _issue_entry_T_3582; // @[Mux.scala:30:73]
wire _issue_entry_T_3598 = _issue_entry_T_3597 | _issue_entry_T_3583; // @[Mux.scala:30:73]
wire _issue_entry_T_3599 = _issue_entry_T_3598 | _issue_entry_T_3584; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_208 = _issue_entry_T_3599; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_mbe = _issue_entry_WIRE_208; // @[Mux.scala:30:73]
wire _issue_entry_T_3600 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3601 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3602 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3603 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3604 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3605 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3606 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3607 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3608 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3609 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3610 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3611 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3612 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3613 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3614 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3615 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_3616 = _issue_entry_T_3600 | _issue_entry_T_3601; // @[Mux.scala:30:73]
wire _issue_entry_T_3617 = _issue_entry_T_3616 | _issue_entry_T_3602; // @[Mux.scala:30:73]
wire _issue_entry_T_3618 = _issue_entry_T_3617 | _issue_entry_T_3603; // @[Mux.scala:30:73]
wire _issue_entry_T_3619 = _issue_entry_T_3618 | _issue_entry_T_3604; // @[Mux.scala:30:73]
wire _issue_entry_T_3620 = _issue_entry_T_3619 | _issue_entry_T_3605; // @[Mux.scala:30:73]
wire _issue_entry_T_3621 = _issue_entry_T_3620 | _issue_entry_T_3606; // @[Mux.scala:30:73]
wire _issue_entry_T_3622 = _issue_entry_T_3621 | _issue_entry_T_3607; // @[Mux.scala:30:73]
wire _issue_entry_T_3623 = _issue_entry_T_3622 | _issue_entry_T_3608; // @[Mux.scala:30:73]
wire _issue_entry_T_3624 = _issue_entry_T_3623 | _issue_entry_T_3609; // @[Mux.scala:30:73]
wire _issue_entry_T_3625 = _issue_entry_T_3624 | _issue_entry_T_3610; // @[Mux.scala:30:73]
wire _issue_entry_T_3626 = _issue_entry_T_3625 | _issue_entry_T_3611; // @[Mux.scala:30:73]
wire _issue_entry_T_3627 = _issue_entry_T_3626 | _issue_entry_T_3612; // @[Mux.scala:30:73]
wire _issue_entry_T_3628 = _issue_entry_T_3627 | _issue_entry_T_3613; // @[Mux.scala:30:73]
wire _issue_entry_T_3629 = _issue_entry_T_3628 | _issue_entry_T_3614; // @[Mux.scala:30:73]
wire _issue_entry_T_3630 = _issue_entry_T_3629 | _issue_entry_T_3615; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_209 = _issue_entry_T_3630; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_gva = _issue_entry_WIRE_209; // @[Mux.scala:30:73]
wire _issue_entry_T_3631 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3632 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3633 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3634 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3635 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3636 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3637 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3638 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3639 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3640 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3641 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3642 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3643 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3644 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3645 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3646 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3647 = _issue_entry_T_3631 | _issue_entry_T_3632; // @[Mux.scala:30:73]
wire _issue_entry_T_3648 = _issue_entry_T_3647 | _issue_entry_T_3633; // @[Mux.scala:30:73]
wire _issue_entry_T_3649 = _issue_entry_T_3648 | _issue_entry_T_3634; // @[Mux.scala:30:73]
wire _issue_entry_T_3650 = _issue_entry_T_3649 | _issue_entry_T_3635; // @[Mux.scala:30:73]
wire _issue_entry_T_3651 = _issue_entry_T_3650 | _issue_entry_T_3636; // @[Mux.scala:30:73]
wire _issue_entry_T_3652 = _issue_entry_T_3651 | _issue_entry_T_3637; // @[Mux.scala:30:73]
wire _issue_entry_T_3653 = _issue_entry_T_3652 | _issue_entry_T_3638; // @[Mux.scala:30:73]
wire _issue_entry_T_3654 = _issue_entry_T_3653 | _issue_entry_T_3639; // @[Mux.scala:30:73]
wire _issue_entry_T_3655 = _issue_entry_T_3654 | _issue_entry_T_3640; // @[Mux.scala:30:73]
wire _issue_entry_T_3656 = _issue_entry_T_3655 | _issue_entry_T_3641; // @[Mux.scala:30:73]
wire _issue_entry_T_3657 = _issue_entry_T_3656 | _issue_entry_T_3642; // @[Mux.scala:30:73]
wire _issue_entry_T_3658 = _issue_entry_T_3657 | _issue_entry_T_3643; // @[Mux.scala:30:73]
wire _issue_entry_T_3659 = _issue_entry_T_3658 | _issue_entry_T_3644; // @[Mux.scala:30:73]
wire _issue_entry_T_3660 = _issue_entry_T_3659 | _issue_entry_T_3645; // @[Mux.scala:30:73]
wire _issue_entry_T_3661 = _issue_entry_T_3660 | _issue_entry_T_3646; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_210 = _issue_entry_T_3661; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_mpv = _issue_entry_WIRE_210; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3662 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3663 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3664 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3665 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3666 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3667 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3668 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3669 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3670 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3671 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3672 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3673 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3674 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3675 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3676 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3677 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_3678 = _issue_entry_T_3662 | _issue_entry_T_3663; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3679 = _issue_entry_T_3678 | _issue_entry_T_3664; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3680 = _issue_entry_T_3679 | _issue_entry_T_3665; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3681 = _issue_entry_T_3680 | _issue_entry_T_3666; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3682 = _issue_entry_T_3681 | _issue_entry_T_3667; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3683 = _issue_entry_T_3682 | _issue_entry_T_3668; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3684 = _issue_entry_T_3683 | _issue_entry_T_3669; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3685 = _issue_entry_T_3684 | _issue_entry_T_3670; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3686 = _issue_entry_T_3685 | _issue_entry_T_3671; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3687 = _issue_entry_T_3686 | _issue_entry_T_3672; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3688 = _issue_entry_T_3687 | _issue_entry_T_3673; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3689 = _issue_entry_T_3688 | _issue_entry_T_3674; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3690 = _issue_entry_T_3689 | _issue_entry_T_3675; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3691 = _issue_entry_T_3690 | _issue_entry_T_3676; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_3692 = _issue_entry_T_3691 | _issue_entry_T_3677; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_211 = _issue_entry_T_3692; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_zero2 = _issue_entry_WIRE_211; // @[Mux.scala:30:73]
wire _issue_entry_T_3693 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3694 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3695 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3696 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3697 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3698 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3699 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3700 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3701 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3702 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3703 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3704 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3705 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3706 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3707 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3708 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_3709 = _issue_entry_T_3693 | _issue_entry_T_3694; // @[Mux.scala:30:73]
wire _issue_entry_T_3710 = _issue_entry_T_3709 | _issue_entry_T_3695; // @[Mux.scala:30:73]
wire _issue_entry_T_3711 = _issue_entry_T_3710 | _issue_entry_T_3696; // @[Mux.scala:30:73]
wire _issue_entry_T_3712 = _issue_entry_T_3711 | _issue_entry_T_3697; // @[Mux.scala:30:73]
wire _issue_entry_T_3713 = _issue_entry_T_3712 | _issue_entry_T_3698; // @[Mux.scala:30:73]
wire _issue_entry_T_3714 = _issue_entry_T_3713 | _issue_entry_T_3699; // @[Mux.scala:30:73]
wire _issue_entry_T_3715 = _issue_entry_T_3714 | _issue_entry_T_3700; // @[Mux.scala:30:73]
wire _issue_entry_T_3716 = _issue_entry_T_3715 | _issue_entry_T_3701; // @[Mux.scala:30:73]
wire _issue_entry_T_3717 = _issue_entry_T_3716 | _issue_entry_T_3702; // @[Mux.scala:30:73]
wire _issue_entry_T_3718 = _issue_entry_T_3717 | _issue_entry_T_3703; // @[Mux.scala:30:73]
wire _issue_entry_T_3719 = _issue_entry_T_3718 | _issue_entry_T_3704; // @[Mux.scala:30:73]
wire _issue_entry_T_3720 = _issue_entry_T_3719 | _issue_entry_T_3705; // @[Mux.scala:30:73]
wire _issue_entry_T_3721 = _issue_entry_T_3720 | _issue_entry_T_3706; // @[Mux.scala:30:73]
wire _issue_entry_T_3722 = _issue_entry_T_3721 | _issue_entry_T_3707; // @[Mux.scala:30:73]
wire _issue_entry_T_3723 = _issue_entry_T_3722 | _issue_entry_T_3708; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_212 = _issue_entry_T_3723; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_sd = _issue_entry_WIRE_212; // @[Mux.scala:30:73]
wire _issue_entry_T_3724 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3725 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3726 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3727 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3728 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3729 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3730 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3731 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3732 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3733 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3734 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3735 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3736 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3737 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3738 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3739 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_3740 = _issue_entry_T_3724 | _issue_entry_T_3725; // @[Mux.scala:30:73]
wire _issue_entry_T_3741 = _issue_entry_T_3740 | _issue_entry_T_3726; // @[Mux.scala:30:73]
wire _issue_entry_T_3742 = _issue_entry_T_3741 | _issue_entry_T_3727; // @[Mux.scala:30:73]
wire _issue_entry_T_3743 = _issue_entry_T_3742 | _issue_entry_T_3728; // @[Mux.scala:30:73]
wire _issue_entry_T_3744 = _issue_entry_T_3743 | _issue_entry_T_3729; // @[Mux.scala:30:73]
wire _issue_entry_T_3745 = _issue_entry_T_3744 | _issue_entry_T_3730; // @[Mux.scala:30:73]
wire _issue_entry_T_3746 = _issue_entry_T_3745 | _issue_entry_T_3731; // @[Mux.scala:30:73]
wire _issue_entry_T_3747 = _issue_entry_T_3746 | _issue_entry_T_3732; // @[Mux.scala:30:73]
wire _issue_entry_T_3748 = _issue_entry_T_3747 | _issue_entry_T_3733; // @[Mux.scala:30:73]
wire _issue_entry_T_3749 = _issue_entry_T_3748 | _issue_entry_T_3734; // @[Mux.scala:30:73]
wire _issue_entry_T_3750 = _issue_entry_T_3749 | _issue_entry_T_3735; // @[Mux.scala:30:73]
wire _issue_entry_T_3751 = _issue_entry_T_3750 | _issue_entry_T_3736; // @[Mux.scala:30:73]
wire _issue_entry_T_3752 = _issue_entry_T_3751 | _issue_entry_T_3737; // @[Mux.scala:30:73]
wire _issue_entry_T_3753 = _issue_entry_T_3752 | _issue_entry_T_3738; // @[Mux.scala:30:73]
wire _issue_entry_T_3754 = _issue_entry_T_3753 | _issue_entry_T_3739; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_213 = _issue_entry_T_3754; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_v = _issue_entry_WIRE_213; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3755 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3756 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3757 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3758 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3759 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3760 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3761 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3762 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3763 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3764 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3765 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3766 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3767 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3768 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3769 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3770 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3771 = _issue_entry_T_3755 | _issue_entry_T_3756; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3772 = _issue_entry_T_3771 | _issue_entry_T_3757; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3773 = _issue_entry_T_3772 | _issue_entry_T_3758; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3774 = _issue_entry_T_3773 | _issue_entry_T_3759; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3775 = _issue_entry_T_3774 | _issue_entry_T_3760; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3776 = _issue_entry_T_3775 | _issue_entry_T_3761; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3777 = _issue_entry_T_3776 | _issue_entry_T_3762; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3778 = _issue_entry_T_3777 | _issue_entry_T_3763; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3779 = _issue_entry_T_3778 | _issue_entry_T_3764; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3780 = _issue_entry_T_3779 | _issue_entry_T_3765; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3781 = _issue_entry_T_3780 | _issue_entry_T_3766; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3782 = _issue_entry_T_3781 | _issue_entry_T_3767; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3783 = _issue_entry_T_3782 | _issue_entry_T_3768; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3784 = _issue_entry_T_3783 | _issue_entry_T_3769; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3785 = _issue_entry_T_3784 | _issue_entry_T_3770; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_214 = _issue_entry_T_3785; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_prv = _issue_entry_WIRE_214; // @[Mux.scala:30:73]
wire _issue_entry_T_3786 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3787 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3788 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3789 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3790 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3791 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3792 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3793 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3794 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3795 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3796 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3797 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3798 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3799 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3800 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3801 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_3802 = _issue_entry_T_3786 | _issue_entry_T_3787; // @[Mux.scala:30:73]
wire _issue_entry_T_3803 = _issue_entry_T_3802 | _issue_entry_T_3788; // @[Mux.scala:30:73]
wire _issue_entry_T_3804 = _issue_entry_T_3803 | _issue_entry_T_3789; // @[Mux.scala:30:73]
wire _issue_entry_T_3805 = _issue_entry_T_3804 | _issue_entry_T_3790; // @[Mux.scala:30:73]
wire _issue_entry_T_3806 = _issue_entry_T_3805 | _issue_entry_T_3791; // @[Mux.scala:30:73]
wire _issue_entry_T_3807 = _issue_entry_T_3806 | _issue_entry_T_3792; // @[Mux.scala:30:73]
wire _issue_entry_T_3808 = _issue_entry_T_3807 | _issue_entry_T_3793; // @[Mux.scala:30:73]
wire _issue_entry_T_3809 = _issue_entry_T_3808 | _issue_entry_T_3794; // @[Mux.scala:30:73]
wire _issue_entry_T_3810 = _issue_entry_T_3809 | _issue_entry_T_3795; // @[Mux.scala:30:73]
wire _issue_entry_T_3811 = _issue_entry_T_3810 | _issue_entry_T_3796; // @[Mux.scala:30:73]
wire _issue_entry_T_3812 = _issue_entry_T_3811 | _issue_entry_T_3797; // @[Mux.scala:30:73]
wire _issue_entry_T_3813 = _issue_entry_T_3812 | _issue_entry_T_3798; // @[Mux.scala:30:73]
wire _issue_entry_T_3814 = _issue_entry_T_3813 | _issue_entry_T_3799; // @[Mux.scala:30:73]
wire _issue_entry_T_3815 = _issue_entry_T_3814 | _issue_entry_T_3800; // @[Mux.scala:30:73]
wire _issue_entry_T_3816 = _issue_entry_T_3815 | _issue_entry_T_3801; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_215 = _issue_entry_T_3816; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_dv = _issue_entry_WIRE_215; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3817 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3818 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3819 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3820 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3821 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3822 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3823 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3824 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3825 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3826 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3827 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3828 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3829 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3830 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3831 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3832 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_3833 = _issue_entry_T_3817 | _issue_entry_T_3818; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3834 = _issue_entry_T_3833 | _issue_entry_T_3819; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3835 = _issue_entry_T_3834 | _issue_entry_T_3820; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3836 = _issue_entry_T_3835 | _issue_entry_T_3821; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3837 = _issue_entry_T_3836 | _issue_entry_T_3822; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3838 = _issue_entry_T_3837 | _issue_entry_T_3823; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3839 = _issue_entry_T_3838 | _issue_entry_T_3824; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3840 = _issue_entry_T_3839 | _issue_entry_T_3825; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3841 = _issue_entry_T_3840 | _issue_entry_T_3826; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3842 = _issue_entry_T_3841 | _issue_entry_T_3827; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3843 = _issue_entry_T_3842 | _issue_entry_T_3828; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3844 = _issue_entry_T_3843 | _issue_entry_T_3829; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3845 = _issue_entry_T_3844 | _issue_entry_T_3830; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3846 = _issue_entry_T_3845 | _issue_entry_T_3831; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_3847 = _issue_entry_T_3846 | _issue_entry_T_3832; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_216 = _issue_entry_T_3847; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_dprv = _issue_entry_WIRE_216; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3848 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3849 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3850 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3851 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3852 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3853 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3854 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3855 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3856 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3857 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3858 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3859 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3860 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3861 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3862 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3863 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_3864 = _issue_entry_T_3848 | _issue_entry_T_3849; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3865 = _issue_entry_T_3864 | _issue_entry_T_3850; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3866 = _issue_entry_T_3865 | _issue_entry_T_3851; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3867 = _issue_entry_T_3866 | _issue_entry_T_3852; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3868 = _issue_entry_T_3867 | _issue_entry_T_3853; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3869 = _issue_entry_T_3868 | _issue_entry_T_3854; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3870 = _issue_entry_T_3869 | _issue_entry_T_3855; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3871 = _issue_entry_T_3870 | _issue_entry_T_3856; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3872 = _issue_entry_T_3871 | _issue_entry_T_3857; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3873 = _issue_entry_T_3872 | _issue_entry_T_3858; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3874 = _issue_entry_T_3873 | _issue_entry_T_3859; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3875 = _issue_entry_T_3874 | _issue_entry_T_3860; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3876 = _issue_entry_T_3875 | _issue_entry_T_3861; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3877 = _issue_entry_T_3876 | _issue_entry_T_3862; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_3878 = _issue_entry_T_3877 | _issue_entry_T_3863; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_217 = _issue_entry_T_3878; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_isa = _issue_entry_WIRE_217; // @[Mux.scala:30:73]
wire _issue_entry_T_3879 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3880 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3881 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3882 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3883 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3884 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3885 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3886 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3887 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3888 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3889 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3890 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3891 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3892 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3893 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3894 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_3895 = _issue_entry_T_3879 | _issue_entry_T_3880; // @[Mux.scala:30:73]
wire _issue_entry_T_3896 = _issue_entry_T_3895 | _issue_entry_T_3881; // @[Mux.scala:30:73]
wire _issue_entry_T_3897 = _issue_entry_T_3896 | _issue_entry_T_3882; // @[Mux.scala:30:73]
wire _issue_entry_T_3898 = _issue_entry_T_3897 | _issue_entry_T_3883; // @[Mux.scala:30:73]
wire _issue_entry_T_3899 = _issue_entry_T_3898 | _issue_entry_T_3884; // @[Mux.scala:30:73]
wire _issue_entry_T_3900 = _issue_entry_T_3899 | _issue_entry_T_3885; // @[Mux.scala:30:73]
wire _issue_entry_T_3901 = _issue_entry_T_3900 | _issue_entry_T_3886; // @[Mux.scala:30:73]
wire _issue_entry_T_3902 = _issue_entry_T_3901 | _issue_entry_T_3887; // @[Mux.scala:30:73]
wire _issue_entry_T_3903 = _issue_entry_T_3902 | _issue_entry_T_3888; // @[Mux.scala:30:73]
wire _issue_entry_T_3904 = _issue_entry_T_3903 | _issue_entry_T_3889; // @[Mux.scala:30:73]
wire _issue_entry_T_3905 = _issue_entry_T_3904 | _issue_entry_T_3890; // @[Mux.scala:30:73]
wire _issue_entry_T_3906 = _issue_entry_T_3905 | _issue_entry_T_3891; // @[Mux.scala:30:73]
wire _issue_entry_T_3907 = _issue_entry_T_3906 | _issue_entry_T_3892; // @[Mux.scala:30:73]
wire _issue_entry_T_3908 = _issue_entry_T_3907 | _issue_entry_T_3893; // @[Mux.scala:30:73]
wire _issue_entry_T_3909 = _issue_entry_T_3908 | _issue_entry_T_3894; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_218 = _issue_entry_T_3909; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_wfi = _issue_entry_WIRE_218; // @[Mux.scala:30:73]
wire _issue_entry_T_3910 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3911 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3912 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3913 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3914 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3915 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3916 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3917 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3918 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3919 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3920 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3921 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3922 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3923 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3924 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3925 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_3926 = _issue_entry_T_3910 | _issue_entry_T_3911; // @[Mux.scala:30:73]
wire _issue_entry_T_3927 = _issue_entry_T_3926 | _issue_entry_T_3912; // @[Mux.scala:30:73]
wire _issue_entry_T_3928 = _issue_entry_T_3927 | _issue_entry_T_3913; // @[Mux.scala:30:73]
wire _issue_entry_T_3929 = _issue_entry_T_3928 | _issue_entry_T_3914; // @[Mux.scala:30:73]
wire _issue_entry_T_3930 = _issue_entry_T_3929 | _issue_entry_T_3915; // @[Mux.scala:30:73]
wire _issue_entry_T_3931 = _issue_entry_T_3930 | _issue_entry_T_3916; // @[Mux.scala:30:73]
wire _issue_entry_T_3932 = _issue_entry_T_3931 | _issue_entry_T_3917; // @[Mux.scala:30:73]
wire _issue_entry_T_3933 = _issue_entry_T_3932 | _issue_entry_T_3918; // @[Mux.scala:30:73]
wire _issue_entry_T_3934 = _issue_entry_T_3933 | _issue_entry_T_3919; // @[Mux.scala:30:73]
wire _issue_entry_T_3935 = _issue_entry_T_3934 | _issue_entry_T_3920; // @[Mux.scala:30:73]
wire _issue_entry_T_3936 = _issue_entry_T_3935 | _issue_entry_T_3921; // @[Mux.scala:30:73]
wire _issue_entry_T_3937 = _issue_entry_T_3936 | _issue_entry_T_3922; // @[Mux.scala:30:73]
wire _issue_entry_T_3938 = _issue_entry_T_3937 | _issue_entry_T_3923; // @[Mux.scala:30:73]
wire _issue_entry_T_3939 = _issue_entry_T_3938 | _issue_entry_T_3924; // @[Mux.scala:30:73]
wire _issue_entry_T_3940 = _issue_entry_T_3939 | _issue_entry_T_3925; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_219 = _issue_entry_T_3940; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_cease = _issue_entry_WIRE_219; // @[Mux.scala:30:73]
wire _issue_entry_T_3941 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3942 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3943 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3944 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3945 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3946 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3947 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3948 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3949 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3950 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3951 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3952 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3953 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3954 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3955 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3956 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_3957 = _issue_entry_T_3941 | _issue_entry_T_3942; // @[Mux.scala:30:73]
wire _issue_entry_T_3958 = _issue_entry_T_3957 | _issue_entry_T_3943; // @[Mux.scala:30:73]
wire _issue_entry_T_3959 = _issue_entry_T_3958 | _issue_entry_T_3944; // @[Mux.scala:30:73]
wire _issue_entry_T_3960 = _issue_entry_T_3959 | _issue_entry_T_3945; // @[Mux.scala:30:73]
wire _issue_entry_T_3961 = _issue_entry_T_3960 | _issue_entry_T_3946; // @[Mux.scala:30:73]
wire _issue_entry_T_3962 = _issue_entry_T_3961 | _issue_entry_T_3947; // @[Mux.scala:30:73]
wire _issue_entry_T_3963 = _issue_entry_T_3962 | _issue_entry_T_3948; // @[Mux.scala:30:73]
wire _issue_entry_T_3964 = _issue_entry_T_3963 | _issue_entry_T_3949; // @[Mux.scala:30:73]
wire _issue_entry_T_3965 = _issue_entry_T_3964 | _issue_entry_T_3950; // @[Mux.scala:30:73]
wire _issue_entry_T_3966 = _issue_entry_T_3965 | _issue_entry_T_3951; // @[Mux.scala:30:73]
wire _issue_entry_T_3967 = _issue_entry_T_3966 | _issue_entry_T_3952; // @[Mux.scala:30:73]
wire _issue_entry_T_3968 = _issue_entry_T_3967 | _issue_entry_T_3953; // @[Mux.scala:30:73]
wire _issue_entry_T_3969 = _issue_entry_T_3968 | _issue_entry_T_3954; // @[Mux.scala:30:73]
wire _issue_entry_T_3970 = _issue_entry_T_3969 | _issue_entry_T_3955; // @[Mux.scala:30:73]
wire _issue_entry_T_3971 = _issue_entry_T_3970 | _issue_entry_T_3956; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_220 = _issue_entry_T_3971; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_183_debug = _issue_entry_WIRE_220; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3972 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3973 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3974 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3975 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3976 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3977 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3978 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3979 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3980 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3981 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3982 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3983 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3984 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3985 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3986 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3987 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_3988 = _issue_entry_T_3972 | _issue_entry_T_3973; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3989 = _issue_entry_T_3988 | _issue_entry_T_3974; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3990 = _issue_entry_T_3989 | _issue_entry_T_3975; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3991 = _issue_entry_T_3990 | _issue_entry_T_3976; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3992 = _issue_entry_T_3991 | _issue_entry_T_3977; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3993 = _issue_entry_T_3992 | _issue_entry_T_3978; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3994 = _issue_entry_T_3993 | _issue_entry_T_3979; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3995 = _issue_entry_T_3994 | _issue_entry_T_3980; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3996 = _issue_entry_T_3995 | _issue_entry_T_3981; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3997 = _issue_entry_T_3996 | _issue_entry_T_3982; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3998 = _issue_entry_T_3997 | _issue_entry_T_3983; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_3999 = _issue_entry_T_3998 | _issue_entry_T_3984; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4000 = _issue_entry_T_3999 | _issue_entry_T_3985; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4001 = _issue_entry_T_4000 | _issue_entry_T_3986; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4002 = _issue_entry_T_4001 | _issue_entry_T_3987; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_221 = _issue_entry_T_4002; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_rs2 = _issue_entry_WIRE_221; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4003 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4004 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4005 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4006 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4007 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4008 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4009 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4010 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4011 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4012 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4013 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4014 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4015 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4016 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4017 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4018 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_4019 = _issue_entry_T_4003 | _issue_entry_T_4004; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4020 = _issue_entry_T_4019 | _issue_entry_T_4005; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4021 = _issue_entry_T_4020 | _issue_entry_T_4006; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4022 = _issue_entry_T_4021 | _issue_entry_T_4007; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4023 = _issue_entry_T_4022 | _issue_entry_T_4008; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4024 = _issue_entry_T_4023 | _issue_entry_T_4009; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4025 = _issue_entry_T_4024 | _issue_entry_T_4010; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4026 = _issue_entry_T_4025 | _issue_entry_T_4011; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4027 = _issue_entry_T_4026 | _issue_entry_T_4012; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4028 = _issue_entry_T_4027 | _issue_entry_T_4013; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4029 = _issue_entry_T_4028 | _issue_entry_T_4014; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4030 = _issue_entry_T_4029 | _issue_entry_T_4015; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4031 = _issue_entry_T_4030 | _issue_entry_T_4016; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4032 = _issue_entry_T_4031 | _issue_entry_T_4017; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_4033 = _issue_entry_T_4032 | _issue_entry_T_4018; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_222 = _issue_entry_T_4033; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_rs1 = _issue_entry_WIRE_222; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_231; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_funct = _issue_entry_WIRE_223_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_230; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_rs2 = _issue_entry_WIRE_223_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_229; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_rs1 = _issue_entry_WIRE_223_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_228; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_xd = _issue_entry_WIRE_223_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_227; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_xs1 = _issue_entry_WIRE_223_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_226; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_xs2 = _issue_entry_WIRE_223_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_225; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_rd = _issue_entry_WIRE_223_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_224; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_182_inst_opcode = _issue_entry_WIRE_223_opcode; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4034 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4035 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4036 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4037 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4038 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4039 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4040 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4041 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4042 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4043 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4044 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4045 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4046 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4047 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4048 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4049 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4050 = _issue_entry_T_4034 | _issue_entry_T_4035; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4051 = _issue_entry_T_4050 | _issue_entry_T_4036; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4052 = _issue_entry_T_4051 | _issue_entry_T_4037; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4053 = _issue_entry_T_4052 | _issue_entry_T_4038; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4054 = _issue_entry_T_4053 | _issue_entry_T_4039; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4055 = _issue_entry_T_4054 | _issue_entry_T_4040; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4056 = _issue_entry_T_4055 | _issue_entry_T_4041; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4057 = _issue_entry_T_4056 | _issue_entry_T_4042; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4058 = _issue_entry_T_4057 | _issue_entry_T_4043; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4059 = _issue_entry_T_4058 | _issue_entry_T_4044; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4060 = _issue_entry_T_4059 | _issue_entry_T_4045; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4061 = _issue_entry_T_4060 | _issue_entry_T_4046; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4062 = _issue_entry_T_4061 | _issue_entry_T_4047; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4063 = _issue_entry_T_4062 | _issue_entry_T_4048; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4064 = _issue_entry_T_4063 | _issue_entry_T_4049; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_224 = _issue_entry_T_4064; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_opcode = _issue_entry_WIRE_224; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4065 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4066 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4067 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4068 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4069 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4070 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4071 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4072 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4073 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4074 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4075 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4076 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4077 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4078 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4079 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4080 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4081 = _issue_entry_T_4065 | _issue_entry_T_4066; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4082 = _issue_entry_T_4081 | _issue_entry_T_4067; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4083 = _issue_entry_T_4082 | _issue_entry_T_4068; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4084 = _issue_entry_T_4083 | _issue_entry_T_4069; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4085 = _issue_entry_T_4084 | _issue_entry_T_4070; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4086 = _issue_entry_T_4085 | _issue_entry_T_4071; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4087 = _issue_entry_T_4086 | _issue_entry_T_4072; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4088 = _issue_entry_T_4087 | _issue_entry_T_4073; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4089 = _issue_entry_T_4088 | _issue_entry_T_4074; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4090 = _issue_entry_T_4089 | _issue_entry_T_4075; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4091 = _issue_entry_T_4090 | _issue_entry_T_4076; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4092 = _issue_entry_T_4091 | _issue_entry_T_4077; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4093 = _issue_entry_T_4092 | _issue_entry_T_4078; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4094 = _issue_entry_T_4093 | _issue_entry_T_4079; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4095 = _issue_entry_T_4094 | _issue_entry_T_4080; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_225 = _issue_entry_T_4095; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_rd = _issue_entry_WIRE_225; // @[Mux.scala:30:73]
wire _issue_entry_T_4096 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4097 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4098 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4099 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4100 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4101 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4102 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4103 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4104 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4105 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4106 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4107 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4108 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4109 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4110 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4111 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_4112 = _issue_entry_T_4096 | _issue_entry_T_4097; // @[Mux.scala:30:73]
wire _issue_entry_T_4113 = _issue_entry_T_4112 | _issue_entry_T_4098; // @[Mux.scala:30:73]
wire _issue_entry_T_4114 = _issue_entry_T_4113 | _issue_entry_T_4099; // @[Mux.scala:30:73]
wire _issue_entry_T_4115 = _issue_entry_T_4114 | _issue_entry_T_4100; // @[Mux.scala:30:73]
wire _issue_entry_T_4116 = _issue_entry_T_4115 | _issue_entry_T_4101; // @[Mux.scala:30:73]
wire _issue_entry_T_4117 = _issue_entry_T_4116 | _issue_entry_T_4102; // @[Mux.scala:30:73]
wire _issue_entry_T_4118 = _issue_entry_T_4117 | _issue_entry_T_4103; // @[Mux.scala:30:73]
wire _issue_entry_T_4119 = _issue_entry_T_4118 | _issue_entry_T_4104; // @[Mux.scala:30:73]
wire _issue_entry_T_4120 = _issue_entry_T_4119 | _issue_entry_T_4105; // @[Mux.scala:30:73]
wire _issue_entry_T_4121 = _issue_entry_T_4120 | _issue_entry_T_4106; // @[Mux.scala:30:73]
wire _issue_entry_T_4122 = _issue_entry_T_4121 | _issue_entry_T_4107; // @[Mux.scala:30:73]
wire _issue_entry_T_4123 = _issue_entry_T_4122 | _issue_entry_T_4108; // @[Mux.scala:30:73]
wire _issue_entry_T_4124 = _issue_entry_T_4123 | _issue_entry_T_4109; // @[Mux.scala:30:73]
wire _issue_entry_T_4125 = _issue_entry_T_4124 | _issue_entry_T_4110; // @[Mux.scala:30:73]
wire _issue_entry_T_4126 = _issue_entry_T_4125 | _issue_entry_T_4111; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_226 = _issue_entry_T_4126; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_xs2 = _issue_entry_WIRE_226; // @[Mux.scala:30:73]
wire _issue_entry_T_4127 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4128 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4129 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4130 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4131 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4132 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4133 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4134 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4135 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4136 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4137 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4138 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4139 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4140 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4141 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4142 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_4143 = _issue_entry_T_4127 | _issue_entry_T_4128; // @[Mux.scala:30:73]
wire _issue_entry_T_4144 = _issue_entry_T_4143 | _issue_entry_T_4129; // @[Mux.scala:30:73]
wire _issue_entry_T_4145 = _issue_entry_T_4144 | _issue_entry_T_4130; // @[Mux.scala:30:73]
wire _issue_entry_T_4146 = _issue_entry_T_4145 | _issue_entry_T_4131; // @[Mux.scala:30:73]
wire _issue_entry_T_4147 = _issue_entry_T_4146 | _issue_entry_T_4132; // @[Mux.scala:30:73]
wire _issue_entry_T_4148 = _issue_entry_T_4147 | _issue_entry_T_4133; // @[Mux.scala:30:73]
wire _issue_entry_T_4149 = _issue_entry_T_4148 | _issue_entry_T_4134; // @[Mux.scala:30:73]
wire _issue_entry_T_4150 = _issue_entry_T_4149 | _issue_entry_T_4135; // @[Mux.scala:30:73]
wire _issue_entry_T_4151 = _issue_entry_T_4150 | _issue_entry_T_4136; // @[Mux.scala:30:73]
wire _issue_entry_T_4152 = _issue_entry_T_4151 | _issue_entry_T_4137; // @[Mux.scala:30:73]
wire _issue_entry_T_4153 = _issue_entry_T_4152 | _issue_entry_T_4138; // @[Mux.scala:30:73]
wire _issue_entry_T_4154 = _issue_entry_T_4153 | _issue_entry_T_4139; // @[Mux.scala:30:73]
wire _issue_entry_T_4155 = _issue_entry_T_4154 | _issue_entry_T_4140; // @[Mux.scala:30:73]
wire _issue_entry_T_4156 = _issue_entry_T_4155 | _issue_entry_T_4141; // @[Mux.scala:30:73]
wire _issue_entry_T_4157 = _issue_entry_T_4156 | _issue_entry_T_4142; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_227 = _issue_entry_T_4157; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_xs1 = _issue_entry_WIRE_227; // @[Mux.scala:30:73]
wire _issue_entry_T_4158 = issue_sel_0_1 & entries_ex_0_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4159 = issue_sel_1_1 & entries_ex_1_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4160 = issue_sel_2_1 & entries_ex_2_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4161 = issue_sel_3_1 & entries_ex_3_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4162 = issue_sel_4_1 & entries_ex_4_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4163 = issue_sel_5_1 & entries_ex_5_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4164 = issue_sel_6_1 & entries_ex_6_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4165 = issue_sel_7_1 & entries_ex_7_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4166 = issue_sel_8 & entries_ex_8_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4167 = issue_sel_9 & entries_ex_9_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4168 = issue_sel_10 & entries_ex_10_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4169 = issue_sel_11 & entries_ex_11_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4170 = issue_sel_12 & entries_ex_12_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4171 = issue_sel_13 & entries_ex_13_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4172 = issue_sel_14 & entries_ex_14_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4173 = issue_sel_15 & entries_ex_15_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_4174 = _issue_entry_T_4158 | _issue_entry_T_4159; // @[Mux.scala:30:73]
wire _issue_entry_T_4175 = _issue_entry_T_4174 | _issue_entry_T_4160; // @[Mux.scala:30:73]
wire _issue_entry_T_4176 = _issue_entry_T_4175 | _issue_entry_T_4161; // @[Mux.scala:30:73]
wire _issue_entry_T_4177 = _issue_entry_T_4176 | _issue_entry_T_4162; // @[Mux.scala:30:73]
wire _issue_entry_T_4178 = _issue_entry_T_4177 | _issue_entry_T_4163; // @[Mux.scala:30:73]
wire _issue_entry_T_4179 = _issue_entry_T_4178 | _issue_entry_T_4164; // @[Mux.scala:30:73]
wire _issue_entry_T_4180 = _issue_entry_T_4179 | _issue_entry_T_4165; // @[Mux.scala:30:73]
wire _issue_entry_T_4181 = _issue_entry_T_4180 | _issue_entry_T_4166; // @[Mux.scala:30:73]
wire _issue_entry_T_4182 = _issue_entry_T_4181 | _issue_entry_T_4167; // @[Mux.scala:30:73]
wire _issue_entry_T_4183 = _issue_entry_T_4182 | _issue_entry_T_4168; // @[Mux.scala:30:73]
wire _issue_entry_T_4184 = _issue_entry_T_4183 | _issue_entry_T_4169; // @[Mux.scala:30:73]
wire _issue_entry_T_4185 = _issue_entry_T_4184 | _issue_entry_T_4170; // @[Mux.scala:30:73]
wire _issue_entry_T_4186 = _issue_entry_T_4185 | _issue_entry_T_4171; // @[Mux.scala:30:73]
wire _issue_entry_T_4187 = _issue_entry_T_4186 | _issue_entry_T_4172; // @[Mux.scala:30:73]
wire _issue_entry_T_4188 = _issue_entry_T_4187 | _issue_entry_T_4173; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_228 = _issue_entry_T_4188; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_xd = _issue_entry_WIRE_228; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4189 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4190 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4191 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4192 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4193 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4194 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4195 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4196 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4197 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4198 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4199 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4200 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4201 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4202 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4203 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4204 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4205 = _issue_entry_T_4189 | _issue_entry_T_4190; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4206 = _issue_entry_T_4205 | _issue_entry_T_4191; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4207 = _issue_entry_T_4206 | _issue_entry_T_4192; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4208 = _issue_entry_T_4207 | _issue_entry_T_4193; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4209 = _issue_entry_T_4208 | _issue_entry_T_4194; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4210 = _issue_entry_T_4209 | _issue_entry_T_4195; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4211 = _issue_entry_T_4210 | _issue_entry_T_4196; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4212 = _issue_entry_T_4211 | _issue_entry_T_4197; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4213 = _issue_entry_T_4212 | _issue_entry_T_4198; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4214 = _issue_entry_T_4213 | _issue_entry_T_4199; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4215 = _issue_entry_T_4214 | _issue_entry_T_4200; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4216 = _issue_entry_T_4215 | _issue_entry_T_4201; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4217 = _issue_entry_T_4216 | _issue_entry_T_4202; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4218 = _issue_entry_T_4217 | _issue_entry_T_4203; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4219 = _issue_entry_T_4218 | _issue_entry_T_4204; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_229 = _issue_entry_T_4219; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_rs1 = _issue_entry_WIRE_229; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4220 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4221 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4222 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4223 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4224 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4225 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4226 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4227 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4228 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4229 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4230 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4231 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4232 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4233 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4234 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4235 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_4236 = _issue_entry_T_4220 | _issue_entry_T_4221; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4237 = _issue_entry_T_4236 | _issue_entry_T_4222; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4238 = _issue_entry_T_4237 | _issue_entry_T_4223; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4239 = _issue_entry_T_4238 | _issue_entry_T_4224; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4240 = _issue_entry_T_4239 | _issue_entry_T_4225; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4241 = _issue_entry_T_4240 | _issue_entry_T_4226; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4242 = _issue_entry_T_4241 | _issue_entry_T_4227; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4243 = _issue_entry_T_4242 | _issue_entry_T_4228; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4244 = _issue_entry_T_4243 | _issue_entry_T_4229; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4245 = _issue_entry_T_4244 | _issue_entry_T_4230; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4246 = _issue_entry_T_4245 | _issue_entry_T_4231; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4247 = _issue_entry_T_4246 | _issue_entry_T_4232; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4248 = _issue_entry_T_4247 | _issue_entry_T_4233; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4249 = _issue_entry_T_4248 | _issue_entry_T_4234; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_4250 = _issue_entry_T_4249 | _issue_entry_T_4235; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_230 = _issue_entry_T_4250; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_rs2 = _issue_entry_WIRE_230; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4251 = issue_sel_0_1 ? entries_ex_0_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4252 = issue_sel_1_1 ? entries_ex_1_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4253 = issue_sel_2_1 ? entries_ex_2_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4254 = issue_sel_3_1 ? entries_ex_3_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4255 = issue_sel_4_1 ? entries_ex_4_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4256 = issue_sel_5_1 ? entries_ex_5_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4257 = issue_sel_6_1 ? entries_ex_6_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4258 = issue_sel_7_1 ? entries_ex_7_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4259 = issue_sel_8 ? entries_ex_8_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4260 = issue_sel_9 ? entries_ex_9_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4261 = issue_sel_10 ? entries_ex_10_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4262 = issue_sel_11 ? entries_ex_11_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4263 = issue_sel_12 ? entries_ex_12_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4264 = issue_sel_13 ? entries_ex_13_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4265 = issue_sel_14 ? entries_ex_14_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4266 = issue_sel_15 ? entries_ex_15_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_4267 = _issue_entry_T_4251 | _issue_entry_T_4252; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4268 = _issue_entry_T_4267 | _issue_entry_T_4253; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4269 = _issue_entry_T_4268 | _issue_entry_T_4254; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4270 = _issue_entry_T_4269 | _issue_entry_T_4255; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4271 = _issue_entry_T_4270 | _issue_entry_T_4256; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4272 = _issue_entry_T_4271 | _issue_entry_T_4257; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4273 = _issue_entry_T_4272 | _issue_entry_T_4258; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4274 = _issue_entry_T_4273 | _issue_entry_T_4259; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4275 = _issue_entry_T_4274 | _issue_entry_T_4260; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4276 = _issue_entry_T_4275 | _issue_entry_T_4261; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4277 = _issue_entry_T_4276 | _issue_entry_T_4262; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4278 = _issue_entry_T_4277 | _issue_entry_T_4263; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4279 = _issue_entry_T_4278 | _issue_entry_T_4264; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4280 = _issue_entry_T_4279 | _issue_entry_T_4265; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_4281 = _issue_entry_T_4280 | _issue_entry_T_4266; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_231 = _issue_entry_T_4281; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_223_funct = _issue_entry_WIRE_231; // @[Mux.scala:30:73]
wire _issue_entry_T_4282 = issue_sel_0_1 & entries_ex_0_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4283 = issue_sel_1_1 & entries_ex_1_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4284 = issue_sel_2_1 & entries_ex_2_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4285 = issue_sel_3_1 & entries_ex_3_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4286 = issue_sel_4_1 & entries_ex_4_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4287 = issue_sel_5_1 & entries_ex_5_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4288 = issue_sel_6_1 & entries_ex_6_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4289 = issue_sel_7_1 & entries_ex_7_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4290 = issue_sel_8 & entries_ex_8_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4291 = issue_sel_9 & entries_ex_9_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4292 = issue_sel_10 & entries_ex_10_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4293 = issue_sel_11 & entries_ex_11_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4294 = issue_sel_12 & entries_ex_12_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4295 = issue_sel_13 & entries_ex_13_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4296 = issue_sel_14 & entries_ex_14_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4297 = issue_sel_15 & entries_ex_15_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_4298 = _issue_entry_T_4282 | _issue_entry_T_4283; // @[Mux.scala:30:73]
wire _issue_entry_T_4299 = _issue_entry_T_4298 | _issue_entry_T_4284; // @[Mux.scala:30:73]
wire _issue_entry_T_4300 = _issue_entry_T_4299 | _issue_entry_T_4285; // @[Mux.scala:30:73]
wire _issue_entry_T_4301 = _issue_entry_T_4300 | _issue_entry_T_4286; // @[Mux.scala:30:73]
wire _issue_entry_T_4302 = _issue_entry_T_4301 | _issue_entry_T_4287; // @[Mux.scala:30:73]
wire _issue_entry_T_4303 = _issue_entry_T_4302 | _issue_entry_T_4288; // @[Mux.scala:30:73]
wire _issue_entry_T_4304 = _issue_entry_T_4303 | _issue_entry_T_4289; // @[Mux.scala:30:73]
wire _issue_entry_T_4305 = _issue_entry_T_4304 | _issue_entry_T_4290; // @[Mux.scala:30:73]
wire _issue_entry_T_4306 = _issue_entry_T_4305 | _issue_entry_T_4291; // @[Mux.scala:30:73]
wire _issue_entry_T_4307 = _issue_entry_T_4306 | _issue_entry_T_4292; // @[Mux.scala:30:73]
wire _issue_entry_T_4308 = _issue_entry_T_4307 | _issue_entry_T_4293; // @[Mux.scala:30:73]
wire _issue_entry_T_4309 = _issue_entry_T_4308 | _issue_entry_T_4294; // @[Mux.scala:30:73]
wire _issue_entry_T_4310 = _issue_entry_T_4309 | _issue_entry_T_4295; // @[Mux.scala:30:73]
wire _issue_entry_T_4311 = _issue_entry_T_4310 | _issue_entry_T_4296; // @[Mux.scala:30:73]
wire _issue_entry_T_4312 = _issue_entry_T_4311 | _issue_entry_T_4297; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_232 = _issue_entry_T_4312; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_complete_on_issue = _issue_entry_WIRE_232; // @[Mux.scala:30:73]
wire _issue_entry_T_4313 = issue_sel_0_1 & entries_ex_0_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4314 = issue_sel_1_1 & entries_ex_1_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4315 = issue_sel_2_1 & entries_ex_2_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4316 = issue_sel_3_1 & entries_ex_3_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4317 = issue_sel_4_1 & entries_ex_4_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4318 = issue_sel_5_1 & entries_ex_5_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4319 = issue_sel_6_1 & entries_ex_6_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4320 = issue_sel_7_1 & entries_ex_7_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4321 = issue_sel_8 & entries_ex_8_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4322 = issue_sel_9 & entries_ex_9_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4323 = issue_sel_10 & entries_ex_10_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4324 = issue_sel_11 & entries_ex_11_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4325 = issue_sel_12 & entries_ex_12_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4326 = issue_sel_13 & entries_ex_13_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4327 = issue_sel_14 & entries_ex_14_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4328 = issue_sel_15 & entries_ex_15_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_4329 = _issue_entry_T_4313 | _issue_entry_T_4314; // @[Mux.scala:30:73]
wire _issue_entry_T_4330 = _issue_entry_T_4329 | _issue_entry_T_4315; // @[Mux.scala:30:73]
wire _issue_entry_T_4331 = _issue_entry_T_4330 | _issue_entry_T_4316; // @[Mux.scala:30:73]
wire _issue_entry_T_4332 = _issue_entry_T_4331 | _issue_entry_T_4317; // @[Mux.scala:30:73]
wire _issue_entry_T_4333 = _issue_entry_T_4332 | _issue_entry_T_4318; // @[Mux.scala:30:73]
wire _issue_entry_T_4334 = _issue_entry_T_4333 | _issue_entry_T_4319; // @[Mux.scala:30:73]
wire _issue_entry_T_4335 = _issue_entry_T_4334 | _issue_entry_T_4320; // @[Mux.scala:30:73]
wire _issue_entry_T_4336 = _issue_entry_T_4335 | _issue_entry_T_4321; // @[Mux.scala:30:73]
wire _issue_entry_T_4337 = _issue_entry_T_4336 | _issue_entry_T_4322; // @[Mux.scala:30:73]
wire _issue_entry_T_4338 = _issue_entry_T_4337 | _issue_entry_T_4323; // @[Mux.scala:30:73]
wire _issue_entry_T_4339 = _issue_entry_T_4338 | _issue_entry_T_4324; // @[Mux.scala:30:73]
wire _issue_entry_T_4340 = _issue_entry_T_4339 | _issue_entry_T_4325; // @[Mux.scala:30:73]
wire _issue_entry_T_4341 = _issue_entry_T_4340 | _issue_entry_T_4326; // @[Mux.scala:30:73]
wire _issue_entry_T_4342 = _issue_entry_T_4341 | _issue_entry_T_4327; // @[Mux.scala:30:73]
wire _issue_entry_T_4343 = _issue_entry_T_4342 | _issue_entry_T_4328; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_233 = _issue_entry_T_4343; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_issued = _issue_entry_WIRE_233; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_257; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_valid = _issue_entry_WIRE_234_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_start_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_start_is_acc_addr = _issue_entry_WIRE_234_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_start_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_start_accumulate = _issue_entry_WIRE_234_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_start_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_start_read_full_acc_row = _issue_entry_WIRE_234_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_235_start_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_start_norm_cmd = _issue_entry_WIRE_234_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_235_start_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_start_garbage = _issue_entry_WIRE_234_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_start_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_start_garbage_bit = _issue_entry_WIRE_234_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_235_start_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_start_data = _issue_entry_WIRE_234_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_end_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_end_is_acc_addr = _issue_entry_WIRE_234_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_end_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_end_accumulate = _issue_entry_WIRE_234_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_end_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_end_read_full_acc_row = _issue_entry_WIRE_234_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_235_end_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_end_norm_cmd = _issue_entry_WIRE_234_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_235_end_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_end_garbage = _issue_entry_WIRE_234_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_end_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_end_garbage_bit = _issue_entry_WIRE_234_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_235_end_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_end_data = _issue_entry_WIRE_234_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_235_wraps_around; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opb_bits_wraps_around = _issue_entry_WIRE_234_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_247_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_start_is_acc_addr = _issue_entry_WIRE_235_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_247_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_start_accumulate = _issue_entry_WIRE_235_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_247_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_start_read_full_acc_row = _issue_entry_WIRE_235_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_247_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_start_norm_cmd = _issue_entry_WIRE_235_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_247_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_start_garbage = _issue_entry_WIRE_235_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_247_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_start_garbage_bit = _issue_entry_WIRE_235_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_247_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_start_data = _issue_entry_WIRE_235_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_237_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_end_is_acc_addr = _issue_entry_WIRE_235_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_237_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_end_accumulate = _issue_entry_WIRE_235_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_237_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_end_read_full_acc_row = _issue_entry_WIRE_235_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_237_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_end_norm_cmd = _issue_entry_WIRE_235_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_237_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_end_garbage = _issue_entry_WIRE_235_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_237_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_end_garbage_bit = _issue_entry_WIRE_235_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_237_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_end_data = _issue_entry_WIRE_235_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_236; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_bits_wraps_around = _issue_entry_WIRE_235_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_T_4344 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4345 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4346 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4347 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4348 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4349 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4350 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4351 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4352 = issue_sel_8 & entries_ex_8_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4353 = issue_sel_9 & entries_ex_9_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4354 = issue_sel_10 & entries_ex_10_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4355 = issue_sel_11 & entries_ex_11_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4356 = issue_sel_12 & entries_ex_12_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4357 = issue_sel_13 & entries_ex_13_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4358 = issue_sel_14 & entries_ex_14_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4359 = issue_sel_15 & entries_ex_15_bits_opb_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4360 = _issue_entry_T_4344 | _issue_entry_T_4345; // @[Mux.scala:30:73]
wire _issue_entry_T_4361 = _issue_entry_T_4360 | _issue_entry_T_4346; // @[Mux.scala:30:73]
wire _issue_entry_T_4362 = _issue_entry_T_4361 | _issue_entry_T_4347; // @[Mux.scala:30:73]
wire _issue_entry_T_4363 = _issue_entry_T_4362 | _issue_entry_T_4348; // @[Mux.scala:30:73]
wire _issue_entry_T_4364 = _issue_entry_T_4363 | _issue_entry_T_4349; // @[Mux.scala:30:73]
wire _issue_entry_T_4365 = _issue_entry_T_4364 | _issue_entry_T_4350; // @[Mux.scala:30:73]
wire _issue_entry_T_4366 = _issue_entry_T_4365 | _issue_entry_T_4351; // @[Mux.scala:30:73]
wire _issue_entry_T_4367 = _issue_entry_T_4366 | _issue_entry_T_4352; // @[Mux.scala:30:73]
wire _issue_entry_T_4368 = _issue_entry_T_4367 | _issue_entry_T_4353; // @[Mux.scala:30:73]
wire _issue_entry_T_4369 = _issue_entry_T_4368 | _issue_entry_T_4354; // @[Mux.scala:30:73]
wire _issue_entry_T_4370 = _issue_entry_T_4369 | _issue_entry_T_4355; // @[Mux.scala:30:73]
wire _issue_entry_T_4371 = _issue_entry_T_4370 | _issue_entry_T_4356; // @[Mux.scala:30:73]
wire _issue_entry_T_4372 = _issue_entry_T_4371 | _issue_entry_T_4357; // @[Mux.scala:30:73]
wire _issue_entry_T_4373 = _issue_entry_T_4372 | _issue_entry_T_4358; // @[Mux.scala:30:73]
wire _issue_entry_T_4374 = _issue_entry_T_4373 | _issue_entry_T_4359; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_236 = _issue_entry_T_4374; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_wraps_around = _issue_entry_WIRE_236; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_246; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_end_is_acc_addr = _issue_entry_WIRE_237_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_245; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_end_accumulate = _issue_entry_WIRE_237_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_244; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_end_read_full_acc_row = _issue_entry_WIRE_237_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_241; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_end_norm_cmd = _issue_entry_WIRE_237_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_240; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_end_garbage = _issue_entry_WIRE_237_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_239; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_end_garbage_bit = _issue_entry_WIRE_237_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_238; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_end_data = _issue_entry_WIRE_237_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4375 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4376 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4377 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4378 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4379 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4380 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4381 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4382 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4383 = issue_sel_8 ? entries_ex_8_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4384 = issue_sel_9 ? entries_ex_9_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4385 = issue_sel_10 ? entries_ex_10_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4386 = issue_sel_11 ? entries_ex_11_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4387 = issue_sel_12 ? entries_ex_12_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4388 = issue_sel_13 ? entries_ex_13_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4389 = issue_sel_14 ? entries_ex_14_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4390 = issue_sel_15 ? entries_ex_15_bits_opb_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4391 = _issue_entry_T_4375 | _issue_entry_T_4376; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4392 = _issue_entry_T_4391 | _issue_entry_T_4377; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4393 = _issue_entry_T_4392 | _issue_entry_T_4378; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4394 = _issue_entry_T_4393 | _issue_entry_T_4379; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4395 = _issue_entry_T_4394 | _issue_entry_T_4380; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4396 = _issue_entry_T_4395 | _issue_entry_T_4381; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4397 = _issue_entry_T_4396 | _issue_entry_T_4382; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4398 = _issue_entry_T_4397 | _issue_entry_T_4383; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4399 = _issue_entry_T_4398 | _issue_entry_T_4384; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4400 = _issue_entry_T_4399 | _issue_entry_T_4385; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4401 = _issue_entry_T_4400 | _issue_entry_T_4386; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4402 = _issue_entry_T_4401 | _issue_entry_T_4387; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4403 = _issue_entry_T_4402 | _issue_entry_T_4388; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4404 = _issue_entry_T_4403 | _issue_entry_T_4389; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4405 = _issue_entry_T_4404 | _issue_entry_T_4390; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_238 = _issue_entry_T_4405; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_237_data = _issue_entry_WIRE_238; // @[Mux.scala:30:73]
wire _issue_entry_T_4406 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4407 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4408 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4409 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4410 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4411 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4412 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4413 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4414 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4415 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4416 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4417 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4418 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4419 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4420 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4421 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4422 = _issue_entry_T_4406 | _issue_entry_T_4407; // @[Mux.scala:30:73]
wire _issue_entry_T_4423 = _issue_entry_T_4422 | _issue_entry_T_4408; // @[Mux.scala:30:73]
wire _issue_entry_T_4424 = _issue_entry_T_4423 | _issue_entry_T_4409; // @[Mux.scala:30:73]
wire _issue_entry_T_4425 = _issue_entry_T_4424 | _issue_entry_T_4410; // @[Mux.scala:30:73]
wire _issue_entry_T_4426 = _issue_entry_T_4425 | _issue_entry_T_4411; // @[Mux.scala:30:73]
wire _issue_entry_T_4427 = _issue_entry_T_4426 | _issue_entry_T_4412; // @[Mux.scala:30:73]
wire _issue_entry_T_4428 = _issue_entry_T_4427 | _issue_entry_T_4413; // @[Mux.scala:30:73]
wire _issue_entry_T_4429 = _issue_entry_T_4428 | _issue_entry_T_4414; // @[Mux.scala:30:73]
wire _issue_entry_T_4430 = _issue_entry_T_4429 | _issue_entry_T_4415; // @[Mux.scala:30:73]
wire _issue_entry_T_4431 = _issue_entry_T_4430 | _issue_entry_T_4416; // @[Mux.scala:30:73]
wire _issue_entry_T_4432 = _issue_entry_T_4431 | _issue_entry_T_4417; // @[Mux.scala:30:73]
wire _issue_entry_T_4433 = _issue_entry_T_4432 | _issue_entry_T_4418; // @[Mux.scala:30:73]
wire _issue_entry_T_4434 = _issue_entry_T_4433 | _issue_entry_T_4419; // @[Mux.scala:30:73]
wire _issue_entry_T_4435 = _issue_entry_T_4434 | _issue_entry_T_4420; // @[Mux.scala:30:73]
wire _issue_entry_T_4436 = _issue_entry_T_4435 | _issue_entry_T_4421; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_239 = _issue_entry_T_4436; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_237_garbage_bit = _issue_entry_WIRE_239; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4437 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4438 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4439 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4440 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4441 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4442 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4443 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4444 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4445 = issue_sel_8 ? entries_ex_8_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4446 = issue_sel_9 ? entries_ex_9_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4447 = issue_sel_10 ? entries_ex_10_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4448 = issue_sel_11 ? entries_ex_11_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4449 = issue_sel_12 ? entries_ex_12_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4450 = issue_sel_13 ? entries_ex_13_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4451 = issue_sel_14 ? entries_ex_14_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4452 = issue_sel_15 ? entries_ex_15_bits_opb_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4453 = _issue_entry_T_4437 | _issue_entry_T_4438; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4454 = _issue_entry_T_4453 | _issue_entry_T_4439; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4455 = _issue_entry_T_4454 | _issue_entry_T_4440; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4456 = _issue_entry_T_4455 | _issue_entry_T_4441; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4457 = _issue_entry_T_4456 | _issue_entry_T_4442; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4458 = _issue_entry_T_4457 | _issue_entry_T_4443; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4459 = _issue_entry_T_4458 | _issue_entry_T_4444; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4460 = _issue_entry_T_4459 | _issue_entry_T_4445; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4461 = _issue_entry_T_4460 | _issue_entry_T_4446; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4462 = _issue_entry_T_4461 | _issue_entry_T_4447; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4463 = _issue_entry_T_4462 | _issue_entry_T_4448; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4464 = _issue_entry_T_4463 | _issue_entry_T_4449; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4465 = _issue_entry_T_4464 | _issue_entry_T_4450; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4466 = _issue_entry_T_4465 | _issue_entry_T_4451; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4467 = _issue_entry_T_4466 | _issue_entry_T_4452; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_240 = _issue_entry_T_4467; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_237_garbage = _issue_entry_WIRE_240; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4469 = issue_sel_0_1 ? _issue_entry_T_4468 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4471 = issue_sel_1_1 ? _issue_entry_T_4470 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4473 = issue_sel_2_1 ? _issue_entry_T_4472 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4475 = issue_sel_3_1 ? _issue_entry_T_4474 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4477 = issue_sel_4_1 ? _issue_entry_T_4476 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4479 = issue_sel_5_1 ? _issue_entry_T_4478 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4481 = issue_sel_6_1 ? _issue_entry_T_4480 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4483 = issue_sel_7_1 ? _issue_entry_T_4482 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4485 = issue_sel_8 ? _issue_entry_T_4484 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4487 = issue_sel_9 ? _issue_entry_T_4486 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4489 = issue_sel_10 ? _issue_entry_T_4488 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4491 = issue_sel_11 ? _issue_entry_T_4490 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4493 = issue_sel_12 ? _issue_entry_T_4492 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4495 = issue_sel_13 ? _issue_entry_T_4494 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4497 = issue_sel_14 ? _issue_entry_T_4496 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4499 = issue_sel_15 ? _issue_entry_T_4498 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4500 = _issue_entry_T_4469 | _issue_entry_T_4471; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4501 = _issue_entry_T_4500 | _issue_entry_T_4473; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4502 = _issue_entry_T_4501 | _issue_entry_T_4475; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4503 = _issue_entry_T_4502 | _issue_entry_T_4477; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4504 = _issue_entry_T_4503 | _issue_entry_T_4479; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4505 = _issue_entry_T_4504 | _issue_entry_T_4481; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4506 = _issue_entry_T_4505 | _issue_entry_T_4483; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4507 = _issue_entry_T_4506 | _issue_entry_T_4485; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4508 = _issue_entry_T_4507 | _issue_entry_T_4487; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4509 = _issue_entry_T_4508 | _issue_entry_T_4489; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4510 = _issue_entry_T_4509 | _issue_entry_T_4491; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4511 = _issue_entry_T_4510 | _issue_entry_T_4493; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4512 = _issue_entry_T_4511 | _issue_entry_T_4495; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4513 = _issue_entry_T_4512 | _issue_entry_T_4497; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4514 = _issue_entry_T_4513 | _issue_entry_T_4499; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_242 = _issue_entry_T_4514; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_243; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_237_norm_cmd = _issue_entry_WIRE_241; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_243 = _issue_entry_WIRE_242; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_241 = _issue_entry_WIRE_243; // @[Mux.scala:30:73]
wire _issue_entry_T_4515 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4516 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4517 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4518 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4519 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4520 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4521 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4522 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4523 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4524 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4525 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4526 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4527 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4528 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4529 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4530 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4531 = _issue_entry_T_4515 | _issue_entry_T_4516; // @[Mux.scala:30:73]
wire _issue_entry_T_4532 = _issue_entry_T_4531 | _issue_entry_T_4517; // @[Mux.scala:30:73]
wire _issue_entry_T_4533 = _issue_entry_T_4532 | _issue_entry_T_4518; // @[Mux.scala:30:73]
wire _issue_entry_T_4534 = _issue_entry_T_4533 | _issue_entry_T_4519; // @[Mux.scala:30:73]
wire _issue_entry_T_4535 = _issue_entry_T_4534 | _issue_entry_T_4520; // @[Mux.scala:30:73]
wire _issue_entry_T_4536 = _issue_entry_T_4535 | _issue_entry_T_4521; // @[Mux.scala:30:73]
wire _issue_entry_T_4537 = _issue_entry_T_4536 | _issue_entry_T_4522; // @[Mux.scala:30:73]
wire _issue_entry_T_4538 = _issue_entry_T_4537 | _issue_entry_T_4523; // @[Mux.scala:30:73]
wire _issue_entry_T_4539 = _issue_entry_T_4538 | _issue_entry_T_4524; // @[Mux.scala:30:73]
wire _issue_entry_T_4540 = _issue_entry_T_4539 | _issue_entry_T_4525; // @[Mux.scala:30:73]
wire _issue_entry_T_4541 = _issue_entry_T_4540 | _issue_entry_T_4526; // @[Mux.scala:30:73]
wire _issue_entry_T_4542 = _issue_entry_T_4541 | _issue_entry_T_4527; // @[Mux.scala:30:73]
wire _issue_entry_T_4543 = _issue_entry_T_4542 | _issue_entry_T_4528; // @[Mux.scala:30:73]
wire _issue_entry_T_4544 = _issue_entry_T_4543 | _issue_entry_T_4529; // @[Mux.scala:30:73]
wire _issue_entry_T_4545 = _issue_entry_T_4544 | _issue_entry_T_4530; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_244 = _issue_entry_T_4545; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_237_read_full_acc_row = _issue_entry_WIRE_244; // @[Mux.scala:30:73]
wire _issue_entry_T_4546 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4547 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4548 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4549 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4550 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4551 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4552 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4553 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4554 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4555 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4556 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4557 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4558 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4559 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4560 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4561 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4562 = _issue_entry_T_4546 | _issue_entry_T_4547; // @[Mux.scala:30:73]
wire _issue_entry_T_4563 = _issue_entry_T_4562 | _issue_entry_T_4548; // @[Mux.scala:30:73]
wire _issue_entry_T_4564 = _issue_entry_T_4563 | _issue_entry_T_4549; // @[Mux.scala:30:73]
wire _issue_entry_T_4565 = _issue_entry_T_4564 | _issue_entry_T_4550; // @[Mux.scala:30:73]
wire _issue_entry_T_4566 = _issue_entry_T_4565 | _issue_entry_T_4551; // @[Mux.scala:30:73]
wire _issue_entry_T_4567 = _issue_entry_T_4566 | _issue_entry_T_4552; // @[Mux.scala:30:73]
wire _issue_entry_T_4568 = _issue_entry_T_4567 | _issue_entry_T_4553; // @[Mux.scala:30:73]
wire _issue_entry_T_4569 = _issue_entry_T_4568 | _issue_entry_T_4554; // @[Mux.scala:30:73]
wire _issue_entry_T_4570 = _issue_entry_T_4569 | _issue_entry_T_4555; // @[Mux.scala:30:73]
wire _issue_entry_T_4571 = _issue_entry_T_4570 | _issue_entry_T_4556; // @[Mux.scala:30:73]
wire _issue_entry_T_4572 = _issue_entry_T_4571 | _issue_entry_T_4557; // @[Mux.scala:30:73]
wire _issue_entry_T_4573 = _issue_entry_T_4572 | _issue_entry_T_4558; // @[Mux.scala:30:73]
wire _issue_entry_T_4574 = _issue_entry_T_4573 | _issue_entry_T_4559; // @[Mux.scala:30:73]
wire _issue_entry_T_4575 = _issue_entry_T_4574 | _issue_entry_T_4560; // @[Mux.scala:30:73]
wire _issue_entry_T_4576 = _issue_entry_T_4575 | _issue_entry_T_4561; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_245 = _issue_entry_T_4576; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_237_accumulate = _issue_entry_WIRE_245; // @[Mux.scala:30:73]
wire _issue_entry_T_4577 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4578 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4579 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4580 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4581 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4582 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4583 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4584 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4585 = issue_sel_8 & entries_ex_8_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4586 = issue_sel_9 & entries_ex_9_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4587 = issue_sel_10 & entries_ex_10_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4588 = issue_sel_11 & entries_ex_11_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4589 = issue_sel_12 & entries_ex_12_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4590 = issue_sel_13 & entries_ex_13_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4591 = issue_sel_14 & entries_ex_14_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4592 = issue_sel_15 & entries_ex_15_bits_opb_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4593 = _issue_entry_T_4577 | _issue_entry_T_4578; // @[Mux.scala:30:73]
wire _issue_entry_T_4594 = _issue_entry_T_4593 | _issue_entry_T_4579; // @[Mux.scala:30:73]
wire _issue_entry_T_4595 = _issue_entry_T_4594 | _issue_entry_T_4580; // @[Mux.scala:30:73]
wire _issue_entry_T_4596 = _issue_entry_T_4595 | _issue_entry_T_4581; // @[Mux.scala:30:73]
wire _issue_entry_T_4597 = _issue_entry_T_4596 | _issue_entry_T_4582; // @[Mux.scala:30:73]
wire _issue_entry_T_4598 = _issue_entry_T_4597 | _issue_entry_T_4583; // @[Mux.scala:30:73]
wire _issue_entry_T_4599 = _issue_entry_T_4598 | _issue_entry_T_4584; // @[Mux.scala:30:73]
wire _issue_entry_T_4600 = _issue_entry_T_4599 | _issue_entry_T_4585; // @[Mux.scala:30:73]
wire _issue_entry_T_4601 = _issue_entry_T_4600 | _issue_entry_T_4586; // @[Mux.scala:30:73]
wire _issue_entry_T_4602 = _issue_entry_T_4601 | _issue_entry_T_4587; // @[Mux.scala:30:73]
wire _issue_entry_T_4603 = _issue_entry_T_4602 | _issue_entry_T_4588; // @[Mux.scala:30:73]
wire _issue_entry_T_4604 = _issue_entry_T_4603 | _issue_entry_T_4589; // @[Mux.scala:30:73]
wire _issue_entry_T_4605 = _issue_entry_T_4604 | _issue_entry_T_4590; // @[Mux.scala:30:73]
wire _issue_entry_T_4606 = _issue_entry_T_4605 | _issue_entry_T_4591; // @[Mux.scala:30:73]
wire _issue_entry_T_4607 = _issue_entry_T_4606 | _issue_entry_T_4592; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_246 = _issue_entry_T_4607; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_237_is_acc_addr = _issue_entry_WIRE_246; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_256; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_start_is_acc_addr = _issue_entry_WIRE_247_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_255; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_start_accumulate = _issue_entry_WIRE_247_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_254; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_start_read_full_acc_row = _issue_entry_WIRE_247_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_251; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_start_norm_cmd = _issue_entry_WIRE_247_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_250; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_start_garbage = _issue_entry_WIRE_247_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_249; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_start_garbage_bit = _issue_entry_WIRE_247_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_248; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_235_start_data = _issue_entry_WIRE_247_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4608 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4609 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4610 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4611 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4612 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4613 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4614 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4615 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4616 = issue_sel_8 ? entries_ex_8_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4617 = issue_sel_9 ? entries_ex_9_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4618 = issue_sel_10 ? entries_ex_10_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4619 = issue_sel_11 ? entries_ex_11_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4620 = issue_sel_12 ? entries_ex_12_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4621 = issue_sel_13 ? entries_ex_13_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4622 = issue_sel_14 ? entries_ex_14_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4623 = issue_sel_15 ? entries_ex_15_bits_opb_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4624 = _issue_entry_T_4608 | _issue_entry_T_4609; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4625 = _issue_entry_T_4624 | _issue_entry_T_4610; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4626 = _issue_entry_T_4625 | _issue_entry_T_4611; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4627 = _issue_entry_T_4626 | _issue_entry_T_4612; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4628 = _issue_entry_T_4627 | _issue_entry_T_4613; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4629 = _issue_entry_T_4628 | _issue_entry_T_4614; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4630 = _issue_entry_T_4629 | _issue_entry_T_4615; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4631 = _issue_entry_T_4630 | _issue_entry_T_4616; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4632 = _issue_entry_T_4631 | _issue_entry_T_4617; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4633 = _issue_entry_T_4632 | _issue_entry_T_4618; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4634 = _issue_entry_T_4633 | _issue_entry_T_4619; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4635 = _issue_entry_T_4634 | _issue_entry_T_4620; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4636 = _issue_entry_T_4635 | _issue_entry_T_4621; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4637 = _issue_entry_T_4636 | _issue_entry_T_4622; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4638 = _issue_entry_T_4637 | _issue_entry_T_4623; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_248 = _issue_entry_T_4638; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_247_data = _issue_entry_WIRE_248; // @[Mux.scala:30:73]
wire _issue_entry_T_4639 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4640 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4641 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4642 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4643 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4644 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4645 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4646 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4647 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4648 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4649 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4650 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4651 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4652 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4653 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4654 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4655 = _issue_entry_T_4639 | _issue_entry_T_4640; // @[Mux.scala:30:73]
wire _issue_entry_T_4656 = _issue_entry_T_4655 | _issue_entry_T_4641; // @[Mux.scala:30:73]
wire _issue_entry_T_4657 = _issue_entry_T_4656 | _issue_entry_T_4642; // @[Mux.scala:30:73]
wire _issue_entry_T_4658 = _issue_entry_T_4657 | _issue_entry_T_4643; // @[Mux.scala:30:73]
wire _issue_entry_T_4659 = _issue_entry_T_4658 | _issue_entry_T_4644; // @[Mux.scala:30:73]
wire _issue_entry_T_4660 = _issue_entry_T_4659 | _issue_entry_T_4645; // @[Mux.scala:30:73]
wire _issue_entry_T_4661 = _issue_entry_T_4660 | _issue_entry_T_4646; // @[Mux.scala:30:73]
wire _issue_entry_T_4662 = _issue_entry_T_4661 | _issue_entry_T_4647; // @[Mux.scala:30:73]
wire _issue_entry_T_4663 = _issue_entry_T_4662 | _issue_entry_T_4648; // @[Mux.scala:30:73]
wire _issue_entry_T_4664 = _issue_entry_T_4663 | _issue_entry_T_4649; // @[Mux.scala:30:73]
wire _issue_entry_T_4665 = _issue_entry_T_4664 | _issue_entry_T_4650; // @[Mux.scala:30:73]
wire _issue_entry_T_4666 = _issue_entry_T_4665 | _issue_entry_T_4651; // @[Mux.scala:30:73]
wire _issue_entry_T_4667 = _issue_entry_T_4666 | _issue_entry_T_4652; // @[Mux.scala:30:73]
wire _issue_entry_T_4668 = _issue_entry_T_4667 | _issue_entry_T_4653; // @[Mux.scala:30:73]
wire _issue_entry_T_4669 = _issue_entry_T_4668 | _issue_entry_T_4654; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_249 = _issue_entry_T_4669; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_247_garbage_bit = _issue_entry_WIRE_249; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4670 = issue_sel_0_1 ? entries_ex_0_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4671 = issue_sel_1_1 ? entries_ex_1_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4672 = issue_sel_2_1 ? entries_ex_2_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4673 = issue_sel_3_1 ? entries_ex_3_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4674 = issue_sel_4_1 ? entries_ex_4_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4675 = issue_sel_5_1 ? entries_ex_5_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4676 = issue_sel_6_1 ? entries_ex_6_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4677 = issue_sel_7_1 ? entries_ex_7_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4678 = issue_sel_8 ? entries_ex_8_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4679 = issue_sel_9 ? entries_ex_9_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4680 = issue_sel_10 ? entries_ex_10_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4681 = issue_sel_11 ? entries_ex_11_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4682 = issue_sel_12 ? entries_ex_12_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4683 = issue_sel_13 ? entries_ex_13_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4684 = issue_sel_14 ? entries_ex_14_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4685 = issue_sel_15 ? entries_ex_15_bits_opb_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4686 = _issue_entry_T_4670 | _issue_entry_T_4671; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4687 = _issue_entry_T_4686 | _issue_entry_T_4672; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4688 = _issue_entry_T_4687 | _issue_entry_T_4673; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4689 = _issue_entry_T_4688 | _issue_entry_T_4674; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4690 = _issue_entry_T_4689 | _issue_entry_T_4675; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4691 = _issue_entry_T_4690 | _issue_entry_T_4676; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4692 = _issue_entry_T_4691 | _issue_entry_T_4677; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4693 = _issue_entry_T_4692 | _issue_entry_T_4678; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4694 = _issue_entry_T_4693 | _issue_entry_T_4679; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4695 = _issue_entry_T_4694 | _issue_entry_T_4680; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4696 = _issue_entry_T_4695 | _issue_entry_T_4681; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4697 = _issue_entry_T_4696 | _issue_entry_T_4682; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4698 = _issue_entry_T_4697 | _issue_entry_T_4683; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4699 = _issue_entry_T_4698 | _issue_entry_T_4684; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4700 = _issue_entry_T_4699 | _issue_entry_T_4685; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_250 = _issue_entry_T_4700; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_247_garbage = _issue_entry_WIRE_250; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4702 = issue_sel_0_1 ? _issue_entry_T_4701 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4704 = issue_sel_1_1 ? _issue_entry_T_4703 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4706 = issue_sel_2_1 ? _issue_entry_T_4705 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4708 = issue_sel_3_1 ? _issue_entry_T_4707 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4710 = issue_sel_4_1 ? _issue_entry_T_4709 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4712 = issue_sel_5_1 ? _issue_entry_T_4711 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4714 = issue_sel_6_1 ? _issue_entry_T_4713 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4716 = issue_sel_7_1 ? _issue_entry_T_4715 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4718 = issue_sel_8 ? _issue_entry_T_4717 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4720 = issue_sel_9 ? _issue_entry_T_4719 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4722 = issue_sel_10 ? _issue_entry_T_4721 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4724 = issue_sel_11 ? _issue_entry_T_4723 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4726 = issue_sel_12 ? _issue_entry_T_4725 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4728 = issue_sel_13 ? _issue_entry_T_4727 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4730 = issue_sel_14 ? _issue_entry_T_4729 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4732 = issue_sel_15 ? _issue_entry_T_4731 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_4733 = _issue_entry_T_4702 | _issue_entry_T_4704; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4734 = _issue_entry_T_4733 | _issue_entry_T_4706; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4735 = _issue_entry_T_4734 | _issue_entry_T_4708; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4736 = _issue_entry_T_4735 | _issue_entry_T_4710; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4737 = _issue_entry_T_4736 | _issue_entry_T_4712; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4738 = _issue_entry_T_4737 | _issue_entry_T_4714; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4739 = _issue_entry_T_4738 | _issue_entry_T_4716; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4740 = _issue_entry_T_4739 | _issue_entry_T_4718; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4741 = _issue_entry_T_4740 | _issue_entry_T_4720; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4742 = _issue_entry_T_4741 | _issue_entry_T_4722; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4743 = _issue_entry_T_4742 | _issue_entry_T_4724; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4744 = _issue_entry_T_4743 | _issue_entry_T_4726; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4745 = _issue_entry_T_4744 | _issue_entry_T_4728; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4746 = _issue_entry_T_4745 | _issue_entry_T_4730; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_4747 = _issue_entry_T_4746 | _issue_entry_T_4732; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_252 = _issue_entry_T_4747; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_253; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_247_norm_cmd = _issue_entry_WIRE_251; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_253 = _issue_entry_WIRE_252; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_251 = _issue_entry_WIRE_253; // @[Mux.scala:30:73]
wire _issue_entry_T_4748 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4749 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4750 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4751 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4752 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4753 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4754 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4755 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4756 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4757 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4758 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4759 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4760 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4761 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4762 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4763 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_4764 = _issue_entry_T_4748 | _issue_entry_T_4749; // @[Mux.scala:30:73]
wire _issue_entry_T_4765 = _issue_entry_T_4764 | _issue_entry_T_4750; // @[Mux.scala:30:73]
wire _issue_entry_T_4766 = _issue_entry_T_4765 | _issue_entry_T_4751; // @[Mux.scala:30:73]
wire _issue_entry_T_4767 = _issue_entry_T_4766 | _issue_entry_T_4752; // @[Mux.scala:30:73]
wire _issue_entry_T_4768 = _issue_entry_T_4767 | _issue_entry_T_4753; // @[Mux.scala:30:73]
wire _issue_entry_T_4769 = _issue_entry_T_4768 | _issue_entry_T_4754; // @[Mux.scala:30:73]
wire _issue_entry_T_4770 = _issue_entry_T_4769 | _issue_entry_T_4755; // @[Mux.scala:30:73]
wire _issue_entry_T_4771 = _issue_entry_T_4770 | _issue_entry_T_4756; // @[Mux.scala:30:73]
wire _issue_entry_T_4772 = _issue_entry_T_4771 | _issue_entry_T_4757; // @[Mux.scala:30:73]
wire _issue_entry_T_4773 = _issue_entry_T_4772 | _issue_entry_T_4758; // @[Mux.scala:30:73]
wire _issue_entry_T_4774 = _issue_entry_T_4773 | _issue_entry_T_4759; // @[Mux.scala:30:73]
wire _issue_entry_T_4775 = _issue_entry_T_4774 | _issue_entry_T_4760; // @[Mux.scala:30:73]
wire _issue_entry_T_4776 = _issue_entry_T_4775 | _issue_entry_T_4761; // @[Mux.scala:30:73]
wire _issue_entry_T_4777 = _issue_entry_T_4776 | _issue_entry_T_4762; // @[Mux.scala:30:73]
wire _issue_entry_T_4778 = _issue_entry_T_4777 | _issue_entry_T_4763; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_254 = _issue_entry_T_4778; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_247_read_full_acc_row = _issue_entry_WIRE_254; // @[Mux.scala:30:73]
wire _issue_entry_T_4779 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4780 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4781 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4782 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4783 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4784 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4785 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4786 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4787 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4788 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4789 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4790 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4791 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4792 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4793 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4794 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_4795 = _issue_entry_T_4779 | _issue_entry_T_4780; // @[Mux.scala:30:73]
wire _issue_entry_T_4796 = _issue_entry_T_4795 | _issue_entry_T_4781; // @[Mux.scala:30:73]
wire _issue_entry_T_4797 = _issue_entry_T_4796 | _issue_entry_T_4782; // @[Mux.scala:30:73]
wire _issue_entry_T_4798 = _issue_entry_T_4797 | _issue_entry_T_4783; // @[Mux.scala:30:73]
wire _issue_entry_T_4799 = _issue_entry_T_4798 | _issue_entry_T_4784; // @[Mux.scala:30:73]
wire _issue_entry_T_4800 = _issue_entry_T_4799 | _issue_entry_T_4785; // @[Mux.scala:30:73]
wire _issue_entry_T_4801 = _issue_entry_T_4800 | _issue_entry_T_4786; // @[Mux.scala:30:73]
wire _issue_entry_T_4802 = _issue_entry_T_4801 | _issue_entry_T_4787; // @[Mux.scala:30:73]
wire _issue_entry_T_4803 = _issue_entry_T_4802 | _issue_entry_T_4788; // @[Mux.scala:30:73]
wire _issue_entry_T_4804 = _issue_entry_T_4803 | _issue_entry_T_4789; // @[Mux.scala:30:73]
wire _issue_entry_T_4805 = _issue_entry_T_4804 | _issue_entry_T_4790; // @[Mux.scala:30:73]
wire _issue_entry_T_4806 = _issue_entry_T_4805 | _issue_entry_T_4791; // @[Mux.scala:30:73]
wire _issue_entry_T_4807 = _issue_entry_T_4806 | _issue_entry_T_4792; // @[Mux.scala:30:73]
wire _issue_entry_T_4808 = _issue_entry_T_4807 | _issue_entry_T_4793; // @[Mux.scala:30:73]
wire _issue_entry_T_4809 = _issue_entry_T_4808 | _issue_entry_T_4794; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_255 = _issue_entry_T_4809; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_247_accumulate = _issue_entry_WIRE_255; // @[Mux.scala:30:73]
wire _issue_entry_T_4810 = issue_sel_0_1 & entries_ex_0_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4811 = issue_sel_1_1 & entries_ex_1_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4812 = issue_sel_2_1 & entries_ex_2_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4813 = issue_sel_3_1 & entries_ex_3_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4814 = issue_sel_4_1 & entries_ex_4_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4815 = issue_sel_5_1 & entries_ex_5_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4816 = issue_sel_6_1 & entries_ex_6_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4817 = issue_sel_7_1 & entries_ex_7_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4818 = issue_sel_8 & entries_ex_8_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4819 = issue_sel_9 & entries_ex_9_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4820 = issue_sel_10 & entries_ex_10_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4821 = issue_sel_11 & entries_ex_11_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4822 = issue_sel_12 & entries_ex_12_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4823 = issue_sel_13 & entries_ex_13_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4824 = issue_sel_14 & entries_ex_14_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4825 = issue_sel_15 & entries_ex_15_bits_opb_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_4826 = _issue_entry_T_4810 | _issue_entry_T_4811; // @[Mux.scala:30:73]
wire _issue_entry_T_4827 = _issue_entry_T_4826 | _issue_entry_T_4812; // @[Mux.scala:30:73]
wire _issue_entry_T_4828 = _issue_entry_T_4827 | _issue_entry_T_4813; // @[Mux.scala:30:73]
wire _issue_entry_T_4829 = _issue_entry_T_4828 | _issue_entry_T_4814; // @[Mux.scala:30:73]
wire _issue_entry_T_4830 = _issue_entry_T_4829 | _issue_entry_T_4815; // @[Mux.scala:30:73]
wire _issue_entry_T_4831 = _issue_entry_T_4830 | _issue_entry_T_4816; // @[Mux.scala:30:73]
wire _issue_entry_T_4832 = _issue_entry_T_4831 | _issue_entry_T_4817; // @[Mux.scala:30:73]
wire _issue_entry_T_4833 = _issue_entry_T_4832 | _issue_entry_T_4818; // @[Mux.scala:30:73]
wire _issue_entry_T_4834 = _issue_entry_T_4833 | _issue_entry_T_4819; // @[Mux.scala:30:73]
wire _issue_entry_T_4835 = _issue_entry_T_4834 | _issue_entry_T_4820; // @[Mux.scala:30:73]
wire _issue_entry_T_4836 = _issue_entry_T_4835 | _issue_entry_T_4821; // @[Mux.scala:30:73]
wire _issue_entry_T_4837 = _issue_entry_T_4836 | _issue_entry_T_4822; // @[Mux.scala:30:73]
wire _issue_entry_T_4838 = _issue_entry_T_4837 | _issue_entry_T_4823; // @[Mux.scala:30:73]
wire _issue_entry_T_4839 = _issue_entry_T_4838 | _issue_entry_T_4824; // @[Mux.scala:30:73]
wire _issue_entry_T_4840 = _issue_entry_T_4839 | _issue_entry_T_4825; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_256 = _issue_entry_T_4840; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_247_is_acc_addr = _issue_entry_WIRE_256; // @[Mux.scala:30:73]
wire _issue_entry_T_4841 = issue_sel_0_1 & entries_ex_0_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4842 = issue_sel_1_1 & entries_ex_1_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4843 = issue_sel_2_1 & entries_ex_2_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4844 = issue_sel_3_1 & entries_ex_3_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4845 = issue_sel_4_1 & entries_ex_4_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4846 = issue_sel_5_1 & entries_ex_5_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4847 = issue_sel_6_1 & entries_ex_6_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4848 = issue_sel_7_1 & entries_ex_7_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4849 = issue_sel_8 & entries_ex_8_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4850 = issue_sel_9 & entries_ex_9_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4851 = issue_sel_10 & entries_ex_10_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4852 = issue_sel_11 & entries_ex_11_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4853 = issue_sel_12 & entries_ex_12_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4854 = issue_sel_13 & entries_ex_13_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4855 = issue_sel_14 & entries_ex_14_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4856 = issue_sel_15 & entries_ex_15_bits_opb_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_4857 = _issue_entry_T_4841 | _issue_entry_T_4842; // @[Mux.scala:30:73]
wire _issue_entry_T_4858 = _issue_entry_T_4857 | _issue_entry_T_4843; // @[Mux.scala:30:73]
wire _issue_entry_T_4859 = _issue_entry_T_4858 | _issue_entry_T_4844; // @[Mux.scala:30:73]
wire _issue_entry_T_4860 = _issue_entry_T_4859 | _issue_entry_T_4845; // @[Mux.scala:30:73]
wire _issue_entry_T_4861 = _issue_entry_T_4860 | _issue_entry_T_4846; // @[Mux.scala:30:73]
wire _issue_entry_T_4862 = _issue_entry_T_4861 | _issue_entry_T_4847; // @[Mux.scala:30:73]
wire _issue_entry_T_4863 = _issue_entry_T_4862 | _issue_entry_T_4848; // @[Mux.scala:30:73]
wire _issue_entry_T_4864 = _issue_entry_T_4863 | _issue_entry_T_4849; // @[Mux.scala:30:73]
wire _issue_entry_T_4865 = _issue_entry_T_4864 | _issue_entry_T_4850; // @[Mux.scala:30:73]
wire _issue_entry_T_4866 = _issue_entry_T_4865 | _issue_entry_T_4851; // @[Mux.scala:30:73]
wire _issue_entry_T_4867 = _issue_entry_T_4866 | _issue_entry_T_4852; // @[Mux.scala:30:73]
wire _issue_entry_T_4868 = _issue_entry_T_4867 | _issue_entry_T_4853; // @[Mux.scala:30:73]
wire _issue_entry_T_4869 = _issue_entry_T_4868 | _issue_entry_T_4854; // @[Mux.scala:30:73]
wire _issue_entry_T_4870 = _issue_entry_T_4869 | _issue_entry_T_4855; // @[Mux.scala:30:73]
wire _issue_entry_T_4871 = _issue_entry_T_4870 | _issue_entry_T_4856; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_257 = _issue_entry_T_4871; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_234_valid = _issue_entry_WIRE_257; // @[Mux.scala:30:73]
wire _issue_entry_T_4872 = issue_sel_0_1 & entries_ex_0_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4873 = issue_sel_1_1 & entries_ex_1_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4874 = issue_sel_2_1 & entries_ex_2_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4875 = issue_sel_3_1 & entries_ex_3_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4876 = issue_sel_4_1 & entries_ex_4_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4877 = issue_sel_5_1 & entries_ex_5_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4878 = issue_sel_6_1 & entries_ex_6_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4879 = issue_sel_7_1 & entries_ex_7_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4880 = issue_sel_8 & entries_ex_8_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4881 = issue_sel_9 & entries_ex_9_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4882 = issue_sel_10 & entries_ex_10_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4883 = issue_sel_11 & entries_ex_11_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4884 = issue_sel_12 & entries_ex_12_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4885 = issue_sel_13 & entries_ex_13_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4886 = issue_sel_14 & entries_ex_14_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4887 = issue_sel_15 & entries_ex_15_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_4888 = _issue_entry_T_4872 | _issue_entry_T_4873; // @[Mux.scala:30:73]
wire _issue_entry_T_4889 = _issue_entry_T_4888 | _issue_entry_T_4874; // @[Mux.scala:30:73]
wire _issue_entry_T_4890 = _issue_entry_T_4889 | _issue_entry_T_4875; // @[Mux.scala:30:73]
wire _issue_entry_T_4891 = _issue_entry_T_4890 | _issue_entry_T_4876; // @[Mux.scala:30:73]
wire _issue_entry_T_4892 = _issue_entry_T_4891 | _issue_entry_T_4877; // @[Mux.scala:30:73]
wire _issue_entry_T_4893 = _issue_entry_T_4892 | _issue_entry_T_4878; // @[Mux.scala:30:73]
wire _issue_entry_T_4894 = _issue_entry_T_4893 | _issue_entry_T_4879; // @[Mux.scala:30:73]
wire _issue_entry_T_4895 = _issue_entry_T_4894 | _issue_entry_T_4880; // @[Mux.scala:30:73]
wire _issue_entry_T_4896 = _issue_entry_T_4895 | _issue_entry_T_4881; // @[Mux.scala:30:73]
wire _issue_entry_T_4897 = _issue_entry_T_4896 | _issue_entry_T_4882; // @[Mux.scala:30:73]
wire _issue_entry_T_4898 = _issue_entry_T_4897 | _issue_entry_T_4883; // @[Mux.scala:30:73]
wire _issue_entry_T_4899 = _issue_entry_T_4898 | _issue_entry_T_4884; // @[Mux.scala:30:73]
wire _issue_entry_T_4900 = _issue_entry_T_4899 | _issue_entry_T_4885; // @[Mux.scala:30:73]
wire _issue_entry_T_4901 = _issue_entry_T_4900 | _issue_entry_T_4886; // @[Mux.scala:30:73]
wire _issue_entry_T_4902 = _issue_entry_T_4901 | _issue_entry_T_4887; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_258 = _issue_entry_T_4902; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_is_dst = _issue_entry_WIRE_258; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_282; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_valid = _issue_entry_WIRE_259_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_start_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_start_is_acc_addr = _issue_entry_WIRE_259_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_start_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_start_accumulate = _issue_entry_WIRE_259_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_start_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_259_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_260_start_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_start_norm_cmd = _issue_entry_WIRE_259_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_260_start_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_start_garbage = _issue_entry_WIRE_259_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_start_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_start_garbage_bit = _issue_entry_WIRE_259_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_260_start_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_start_data = _issue_entry_WIRE_259_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_end_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_end_is_acc_addr = _issue_entry_WIRE_259_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_end_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_end_accumulate = _issue_entry_WIRE_259_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_end_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_259_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_260_end_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_end_norm_cmd = _issue_entry_WIRE_259_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_260_end_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_end_garbage = _issue_entry_WIRE_259_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_end_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_end_garbage_bit = _issue_entry_WIRE_259_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_260_end_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_end_data = _issue_entry_WIRE_259_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_260_wraps_around; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_opa_bits_wraps_around = _issue_entry_WIRE_259_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_272_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_start_is_acc_addr = _issue_entry_WIRE_260_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_272_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_start_accumulate = _issue_entry_WIRE_260_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_272_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_start_read_full_acc_row = _issue_entry_WIRE_260_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_272_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_start_norm_cmd = _issue_entry_WIRE_260_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_272_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_start_garbage = _issue_entry_WIRE_260_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_272_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_start_garbage_bit = _issue_entry_WIRE_260_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_272_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_start_data = _issue_entry_WIRE_260_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_262_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_end_is_acc_addr = _issue_entry_WIRE_260_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_262_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_end_accumulate = _issue_entry_WIRE_260_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_262_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_end_read_full_acc_row = _issue_entry_WIRE_260_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_262_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_end_norm_cmd = _issue_entry_WIRE_260_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_262_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_end_garbage = _issue_entry_WIRE_260_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_262_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_end_garbage_bit = _issue_entry_WIRE_260_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_262_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_end_data = _issue_entry_WIRE_260_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_261; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_bits_wraps_around = _issue_entry_WIRE_260_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_T_4903 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4904 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4905 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4906 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4907 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4908 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4909 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4910 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4911 = issue_sel_8 & entries_ex_8_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4912 = issue_sel_9 & entries_ex_9_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4913 = issue_sel_10 & entries_ex_10_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4914 = issue_sel_11 & entries_ex_11_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4915 = issue_sel_12 & entries_ex_12_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4916 = issue_sel_13 & entries_ex_13_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4917 = issue_sel_14 & entries_ex_14_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4918 = issue_sel_15 & entries_ex_15_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_4919 = _issue_entry_T_4903 | _issue_entry_T_4904; // @[Mux.scala:30:73]
wire _issue_entry_T_4920 = _issue_entry_T_4919 | _issue_entry_T_4905; // @[Mux.scala:30:73]
wire _issue_entry_T_4921 = _issue_entry_T_4920 | _issue_entry_T_4906; // @[Mux.scala:30:73]
wire _issue_entry_T_4922 = _issue_entry_T_4921 | _issue_entry_T_4907; // @[Mux.scala:30:73]
wire _issue_entry_T_4923 = _issue_entry_T_4922 | _issue_entry_T_4908; // @[Mux.scala:30:73]
wire _issue_entry_T_4924 = _issue_entry_T_4923 | _issue_entry_T_4909; // @[Mux.scala:30:73]
wire _issue_entry_T_4925 = _issue_entry_T_4924 | _issue_entry_T_4910; // @[Mux.scala:30:73]
wire _issue_entry_T_4926 = _issue_entry_T_4925 | _issue_entry_T_4911; // @[Mux.scala:30:73]
wire _issue_entry_T_4927 = _issue_entry_T_4926 | _issue_entry_T_4912; // @[Mux.scala:30:73]
wire _issue_entry_T_4928 = _issue_entry_T_4927 | _issue_entry_T_4913; // @[Mux.scala:30:73]
wire _issue_entry_T_4929 = _issue_entry_T_4928 | _issue_entry_T_4914; // @[Mux.scala:30:73]
wire _issue_entry_T_4930 = _issue_entry_T_4929 | _issue_entry_T_4915; // @[Mux.scala:30:73]
wire _issue_entry_T_4931 = _issue_entry_T_4930 | _issue_entry_T_4916; // @[Mux.scala:30:73]
wire _issue_entry_T_4932 = _issue_entry_T_4931 | _issue_entry_T_4917; // @[Mux.scala:30:73]
wire _issue_entry_T_4933 = _issue_entry_T_4932 | _issue_entry_T_4918; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_261 = _issue_entry_T_4933; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_wraps_around = _issue_entry_WIRE_261; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_271; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_end_is_acc_addr = _issue_entry_WIRE_262_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_270; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_end_accumulate = _issue_entry_WIRE_262_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_269; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_end_read_full_acc_row = _issue_entry_WIRE_262_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_266; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_end_norm_cmd = _issue_entry_WIRE_262_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_265; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_end_garbage = _issue_entry_WIRE_262_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_264; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_end_garbage_bit = _issue_entry_WIRE_262_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_263; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_end_data = _issue_entry_WIRE_262_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4934 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4935 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4936 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4937 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4938 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4939 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4940 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4941 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4942 = issue_sel_8 ? entries_ex_8_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4943 = issue_sel_9 ? entries_ex_9_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4944 = issue_sel_10 ? entries_ex_10_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4945 = issue_sel_11 ? entries_ex_11_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4946 = issue_sel_12 ? entries_ex_12_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4947 = issue_sel_13 ? entries_ex_13_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4948 = issue_sel_14 ? entries_ex_14_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4949 = issue_sel_15 ? entries_ex_15_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_4950 = _issue_entry_T_4934 | _issue_entry_T_4935; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4951 = _issue_entry_T_4950 | _issue_entry_T_4936; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4952 = _issue_entry_T_4951 | _issue_entry_T_4937; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4953 = _issue_entry_T_4952 | _issue_entry_T_4938; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4954 = _issue_entry_T_4953 | _issue_entry_T_4939; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4955 = _issue_entry_T_4954 | _issue_entry_T_4940; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4956 = _issue_entry_T_4955 | _issue_entry_T_4941; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4957 = _issue_entry_T_4956 | _issue_entry_T_4942; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4958 = _issue_entry_T_4957 | _issue_entry_T_4943; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4959 = _issue_entry_T_4958 | _issue_entry_T_4944; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4960 = _issue_entry_T_4959 | _issue_entry_T_4945; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4961 = _issue_entry_T_4960 | _issue_entry_T_4946; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4962 = _issue_entry_T_4961 | _issue_entry_T_4947; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4963 = _issue_entry_T_4962 | _issue_entry_T_4948; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_4964 = _issue_entry_T_4963 | _issue_entry_T_4949; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_263 = _issue_entry_T_4964; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_262_data = _issue_entry_WIRE_263; // @[Mux.scala:30:73]
wire _issue_entry_T_4965 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4966 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4967 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4968 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4969 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4970 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4971 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4972 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4973 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4974 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4975 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4976 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4977 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4978 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4979 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4980 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_4981 = _issue_entry_T_4965 | _issue_entry_T_4966; // @[Mux.scala:30:73]
wire _issue_entry_T_4982 = _issue_entry_T_4981 | _issue_entry_T_4967; // @[Mux.scala:30:73]
wire _issue_entry_T_4983 = _issue_entry_T_4982 | _issue_entry_T_4968; // @[Mux.scala:30:73]
wire _issue_entry_T_4984 = _issue_entry_T_4983 | _issue_entry_T_4969; // @[Mux.scala:30:73]
wire _issue_entry_T_4985 = _issue_entry_T_4984 | _issue_entry_T_4970; // @[Mux.scala:30:73]
wire _issue_entry_T_4986 = _issue_entry_T_4985 | _issue_entry_T_4971; // @[Mux.scala:30:73]
wire _issue_entry_T_4987 = _issue_entry_T_4986 | _issue_entry_T_4972; // @[Mux.scala:30:73]
wire _issue_entry_T_4988 = _issue_entry_T_4987 | _issue_entry_T_4973; // @[Mux.scala:30:73]
wire _issue_entry_T_4989 = _issue_entry_T_4988 | _issue_entry_T_4974; // @[Mux.scala:30:73]
wire _issue_entry_T_4990 = _issue_entry_T_4989 | _issue_entry_T_4975; // @[Mux.scala:30:73]
wire _issue_entry_T_4991 = _issue_entry_T_4990 | _issue_entry_T_4976; // @[Mux.scala:30:73]
wire _issue_entry_T_4992 = _issue_entry_T_4991 | _issue_entry_T_4977; // @[Mux.scala:30:73]
wire _issue_entry_T_4993 = _issue_entry_T_4992 | _issue_entry_T_4978; // @[Mux.scala:30:73]
wire _issue_entry_T_4994 = _issue_entry_T_4993 | _issue_entry_T_4979; // @[Mux.scala:30:73]
wire _issue_entry_T_4995 = _issue_entry_T_4994 | _issue_entry_T_4980; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_264 = _issue_entry_T_4995; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_262_garbage_bit = _issue_entry_WIRE_264; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_4996 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4997 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4998 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_4999 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5000 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5001 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5002 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5003 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5004 = issue_sel_8 ? entries_ex_8_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5005 = issue_sel_9 ? entries_ex_9_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5006 = issue_sel_10 ? entries_ex_10_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5007 = issue_sel_11 ? entries_ex_11_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5008 = issue_sel_12 ? entries_ex_12_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5009 = issue_sel_13 ? entries_ex_13_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5010 = issue_sel_14 ? entries_ex_14_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5011 = issue_sel_15 ? entries_ex_15_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5012 = _issue_entry_T_4996 | _issue_entry_T_4997; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5013 = _issue_entry_T_5012 | _issue_entry_T_4998; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5014 = _issue_entry_T_5013 | _issue_entry_T_4999; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5015 = _issue_entry_T_5014 | _issue_entry_T_5000; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5016 = _issue_entry_T_5015 | _issue_entry_T_5001; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5017 = _issue_entry_T_5016 | _issue_entry_T_5002; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5018 = _issue_entry_T_5017 | _issue_entry_T_5003; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5019 = _issue_entry_T_5018 | _issue_entry_T_5004; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5020 = _issue_entry_T_5019 | _issue_entry_T_5005; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5021 = _issue_entry_T_5020 | _issue_entry_T_5006; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5022 = _issue_entry_T_5021 | _issue_entry_T_5007; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5023 = _issue_entry_T_5022 | _issue_entry_T_5008; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5024 = _issue_entry_T_5023 | _issue_entry_T_5009; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5025 = _issue_entry_T_5024 | _issue_entry_T_5010; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5026 = _issue_entry_T_5025 | _issue_entry_T_5011; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_265 = _issue_entry_T_5026; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_262_garbage = _issue_entry_WIRE_265; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5028 = issue_sel_0_1 ? _issue_entry_T_5027 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5030 = issue_sel_1_1 ? _issue_entry_T_5029 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5032 = issue_sel_2_1 ? _issue_entry_T_5031 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5034 = issue_sel_3_1 ? _issue_entry_T_5033 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5036 = issue_sel_4_1 ? _issue_entry_T_5035 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5038 = issue_sel_5_1 ? _issue_entry_T_5037 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5040 = issue_sel_6_1 ? _issue_entry_T_5039 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5042 = issue_sel_7_1 ? _issue_entry_T_5041 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5044 = issue_sel_8 ? _issue_entry_T_5043 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5046 = issue_sel_9 ? _issue_entry_T_5045 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5048 = issue_sel_10 ? _issue_entry_T_5047 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5050 = issue_sel_11 ? _issue_entry_T_5049 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5052 = issue_sel_12 ? _issue_entry_T_5051 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5054 = issue_sel_13 ? _issue_entry_T_5053 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5056 = issue_sel_14 ? _issue_entry_T_5055 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5058 = issue_sel_15 ? _issue_entry_T_5057 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5059 = _issue_entry_T_5028 | _issue_entry_T_5030; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5060 = _issue_entry_T_5059 | _issue_entry_T_5032; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5061 = _issue_entry_T_5060 | _issue_entry_T_5034; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5062 = _issue_entry_T_5061 | _issue_entry_T_5036; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5063 = _issue_entry_T_5062 | _issue_entry_T_5038; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5064 = _issue_entry_T_5063 | _issue_entry_T_5040; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5065 = _issue_entry_T_5064 | _issue_entry_T_5042; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5066 = _issue_entry_T_5065 | _issue_entry_T_5044; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5067 = _issue_entry_T_5066 | _issue_entry_T_5046; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5068 = _issue_entry_T_5067 | _issue_entry_T_5048; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5069 = _issue_entry_T_5068 | _issue_entry_T_5050; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5070 = _issue_entry_T_5069 | _issue_entry_T_5052; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5071 = _issue_entry_T_5070 | _issue_entry_T_5054; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5072 = _issue_entry_T_5071 | _issue_entry_T_5056; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5073 = _issue_entry_T_5072 | _issue_entry_T_5058; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_267 = _issue_entry_T_5073; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_268; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_262_norm_cmd = _issue_entry_WIRE_266; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_268 = _issue_entry_WIRE_267; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_266 = _issue_entry_WIRE_268; // @[Mux.scala:30:73]
wire _issue_entry_T_5074 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5075 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5076 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5077 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5078 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5079 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5080 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5081 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5082 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5083 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5084 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5085 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5086 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5087 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5088 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5089 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5090 = _issue_entry_T_5074 | _issue_entry_T_5075; // @[Mux.scala:30:73]
wire _issue_entry_T_5091 = _issue_entry_T_5090 | _issue_entry_T_5076; // @[Mux.scala:30:73]
wire _issue_entry_T_5092 = _issue_entry_T_5091 | _issue_entry_T_5077; // @[Mux.scala:30:73]
wire _issue_entry_T_5093 = _issue_entry_T_5092 | _issue_entry_T_5078; // @[Mux.scala:30:73]
wire _issue_entry_T_5094 = _issue_entry_T_5093 | _issue_entry_T_5079; // @[Mux.scala:30:73]
wire _issue_entry_T_5095 = _issue_entry_T_5094 | _issue_entry_T_5080; // @[Mux.scala:30:73]
wire _issue_entry_T_5096 = _issue_entry_T_5095 | _issue_entry_T_5081; // @[Mux.scala:30:73]
wire _issue_entry_T_5097 = _issue_entry_T_5096 | _issue_entry_T_5082; // @[Mux.scala:30:73]
wire _issue_entry_T_5098 = _issue_entry_T_5097 | _issue_entry_T_5083; // @[Mux.scala:30:73]
wire _issue_entry_T_5099 = _issue_entry_T_5098 | _issue_entry_T_5084; // @[Mux.scala:30:73]
wire _issue_entry_T_5100 = _issue_entry_T_5099 | _issue_entry_T_5085; // @[Mux.scala:30:73]
wire _issue_entry_T_5101 = _issue_entry_T_5100 | _issue_entry_T_5086; // @[Mux.scala:30:73]
wire _issue_entry_T_5102 = _issue_entry_T_5101 | _issue_entry_T_5087; // @[Mux.scala:30:73]
wire _issue_entry_T_5103 = _issue_entry_T_5102 | _issue_entry_T_5088; // @[Mux.scala:30:73]
wire _issue_entry_T_5104 = _issue_entry_T_5103 | _issue_entry_T_5089; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_269 = _issue_entry_T_5104; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_262_read_full_acc_row = _issue_entry_WIRE_269; // @[Mux.scala:30:73]
wire _issue_entry_T_5105 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5106 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5107 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5108 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5109 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5110 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5111 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5112 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5113 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5114 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5115 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5116 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5117 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5118 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5119 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5120 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5121 = _issue_entry_T_5105 | _issue_entry_T_5106; // @[Mux.scala:30:73]
wire _issue_entry_T_5122 = _issue_entry_T_5121 | _issue_entry_T_5107; // @[Mux.scala:30:73]
wire _issue_entry_T_5123 = _issue_entry_T_5122 | _issue_entry_T_5108; // @[Mux.scala:30:73]
wire _issue_entry_T_5124 = _issue_entry_T_5123 | _issue_entry_T_5109; // @[Mux.scala:30:73]
wire _issue_entry_T_5125 = _issue_entry_T_5124 | _issue_entry_T_5110; // @[Mux.scala:30:73]
wire _issue_entry_T_5126 = _issue_entry_T_5125 | _issue_entry_T_5111; // @[Mux.scala:30:73]
wire _issue_entry_T_5127 = _issue_entry_T_5126 | _issue_entry_T_5112; // @[Mux.scala:30:73]
wire _issue_entry_T_5128 = _issue_entry_T_5127 | _issue_entry_T_5113; // @[Mux.scala:30:73]
wire _issue_entry_T_5129 = _issue_entry_T_5128 | _issue_entry_T_5114; // @[Mux.scala:30:73]
wire _issue_entry_T_5130 = _issue_entry_T_5129 | _issue_entry_T_5115; // @[Mux.scala:30:73]
wire _issue_entry_T_5131 = _issue_entry_T_5130 | _issue_entry_T_5116; // @[Mux.scala:30:73]
wire _issue_entry_T_5132 = _issue_entry_T_5131 | _issue_entry_T_5117; // @[Mux.scala:30:73]
wire _issue_entry_T_5133 = _issue_entry_T_5132 | _issue_entry_T_5118; // @[Mux.scala:30:73]
wire _issue_entry_T_5134 = _issue_entry_T_5133 | _issue_entry_T_5119; // @[Mux.scala:30:73]
wire _issue_entry_T_5135 = _issue_entry_T_5134 | _issue_entry_T_5120; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_270 = _issue_entry_T_5135; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_262_accumulate = _issue_entry_WIRE_270; // @[Mux.scala:30:73]
wire _issue_entry_T_5136 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5137 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5138 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5139 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5140 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5141 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5142 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5143 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5144 = issue_sel_8 & entries_ex_8_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5145 = issue_sel_9 & entries_ex_9_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5146 = issue_sel_10 & entries_ex_10_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5147 = issue_sel_11 & entries_ex_11_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5148 = issue_sel_12 & entries_ex_12_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5149 = issue_sel_13 & entries_ex_13_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5150 = issue_sel_14 & entries_ex_14_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5151 = issue_sel_15 & entries_ex_15_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5152 = _issue_entry_T_5136 | _issue_entry_T_5137; // @[Mux.scala:30:73]
wire _issue_entry_T_5153 = _issue_entry_T_5152 | _issue_entry_T_5138; // @[Mux.scala:30:73]
wire _issue_entry_T_5154 = _issue_entry_T_5153 | _issue_entry_T_5139; // @[Mux.scala:30:73]
wire _issue_entry_T_5155 = _issue_entry_T_5154 | _issue_entry_T_5140; // @[Mux.scala:30:73]
wire _issue_entry_T_5156 = _issue_entry_T_5155 | _issue_entry_T_5141; // @[Mux.scala:30:73]
wire _issue_entry_T_5157 = _issue_entry_T_5156 | _issue_entry_T_5142; // @[Mux.scala:30:73]
wire _issue_entry_T_5158 = _issue_entry_T_5157 | _issue_entry_T_5143; // @[Mux.scala:30:73]
wire _issue_entry_T_5159 = _issue_entry_T_5158 | _issue_entry_T_5144; // @[Mux.scala:30:73]
wire _issue_entry_T_5160 = _issue_entry_T_5159 | _issue_entry_T_5145; // @[Mux.scala:30:73]
wire _issue_entry_T_5161 = _issue_entry_T_5160 | _issue_entry_T_5146; // @[Mux.scala:30:73]
wire _issue_entry_T_5162 = _issue_entry_T_5161 | _issue_entry_T_5147; // @[Mux.scala:30:73]
wire _issue_entry_T_5163 = _issue_entry_T_5162 | _issue_entry_T_5148; // @[Mux.scala:30:73]
wire _issue_entry_T_5164 = _issue_entry_T_5163 | _issue_entry_T_5149; // @[Mux.scala:30:73]
wire _issue_entry_T_5165 = _issue_entry_T_5164 | _issue_entry_T_5150; // @[Mux.scala:30:73]
wire _issue_entry_T_5166 = _issue_entry_T_5165 | _issue_entry_T_5151; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_271 = _issue_entry_T_5166; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_262_is_acc_addr = _issue_entry_WIRE_271; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_281; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_start_is_acc_addr = _issue_entry_WIRE_272_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_280; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_start_accumulate = _issue_entry_WIRE_272_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_279; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_start_read_full_acc_row = _issue_entry_WIRE_272_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_276; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_start_norm_cmd = _issue_entry_WIRE_272_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_275; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_start_garbage = _issue_entry_WIRE_272_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_274; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_start_garbage_bit = _issue_entry_WIRE_272_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_273; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_260_start_data = _issue_entry_WIRE_272_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5167 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5168 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5169 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5170 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5171 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5172 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5173 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5174 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5175 = issue_sel_8 ? entries_ex_8_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5176 = issue_sel_9 ? entries_ex_9_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5177 = issue_sel_10 ? entries_ex_10_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5178 = issue_sel_11 ? entries_ex_11_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5179 = issue_sel_12 ? entries_ex_12_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5180 = issue_sel_13 ? entries_ex_13_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5181 = issue_sel_14 ? entries_ex_14_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5182 = issue_sel_15 ? entries_ex_15_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_5183 = _issue_entry_T_5167 | _issue_entry_T_5168; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5184 = _issue_entry_T_5183 | _issue_entry_T_5169; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5185 = _issue_entry_T_5184 | _issue_entry_T_5170; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5186 = _issue_entry_T_5185 | _issue_entry_T_5171; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5187 = _issue_entry_T_5186 | _issue_entry_T_5172; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5188 = _issue_entry_T_5187 | _issue_entry_T_5173; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5189 = _issue_entry_T_5188 | _issue_entry_T_5174; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5190 = _issue_entry_T_5189 | _issue_entry_T_5175; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5191 = _issue_entry_T_5190 | _issue_entry_T_5176; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5192 = _issue_entry_T_5191 | _issue_entry_T_5177; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5193 = _issue_entry_T_5192 | _issue_entry_T_5178; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5194 = _issue_entry_T_5193 | _issue_entry_T_5179; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5195 = _issue_entry_T_5194 | _issue_entry_T_5180; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5196 = _issue_entry_T_5195 | _issue_entry_T_5181; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_5197 = _issue_entry_T_5196 | _issue_entry_T_5182; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_273 = _issue_entry_T_5197; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_272_data = _issue_entry_WIRE_273; // @[Mux.scala:30:73]
wire _issue_entry_T_5198 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5199 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5200 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5201 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5202 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5203 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5204 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5205 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5206 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5207 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5208 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5209 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5210 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5211 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5212 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5213 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_5214 = _issue_entry_T_5198 | _issue_entry_T_5199; // @[Mux.scala:30:73]
wire _issue_entry_T_5215 = _issue_entry_T_5214 | _issue_entry_T_5200; // @[Mux.scala:30:73]
wire _issue_entry_T_5216 = _issue_entry_T_5215 | _issue_entry_T_5201; // @[Mux.scala:30:73]
wire _issue_entry_T_5217 = _issue_entry_T_5216 | _issue_entry_T_5202; // @[Mux.scala:30:73]
wire _issue_entry_T_5218 = _issue_entry_T_5217 | _issue_entry_T_5203; // @[Mux.scala:30:73]
wire _issue_entry_T_5219 = _issue_entry_T_5218 | _issue_entry_T_5204; // @[Mux.scala:30:73]
wire _issue_entry_T_5220 = _issue_entry_T_5219 | _issue_entry_T_5205; // @[Mux.scala:30:73]
wire _issue_entry_T_5221 = _issue_entry_T_5220 | _issue_entry_T_5206; // @[Mux.scala:30:73]
wire _issue_entry_T_5222 = _issue_entry_T_5221 | _issue_entry_T_5207; // @[Mux.scala:30:73]
wire _issue_entry_T_5223 = _issue_entry_T_5222 | _issue_entry_T_5208; // @[Mux.scala:30:73]
wire _issue_entry_T_5224 = _issue_entry_T_5223 | _issue_entry_T_5209; // @[Mux.scala:30:73]
wire _issue_entry_T_5225 = _issue_entry_T_5224 | _issue_entry_T_5210; // @[Mux.scala:30:73]
wire _issue_entry_T_5226 = _issue_entry_T_5225 | _issue_entry_T_5211; // @[Mux.scala:30:73]
wire _issue_entry_T_5227 = _issue_entry_T_5226 | _issue_entry_T_5212; // @[Mux.scala:30:73]
wire _issue_entry_T_5228 = _issue_entry_T_5227 | _issue_entry_T_5213; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_274 = _issue_entry_T_5228; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_272_garbage_bit = _issue_entry_WIRE_274; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5229 = issue_sel_0_1 ? entries_ex_0_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5230 = issue_sel_1_1 ? entries_ex_1_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5231 = issue_sel_2_1 ? entries_ex_2_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5232 = issue_sel_3_1 ? entries_ex_3_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5233 = issue_sel_4_1 ? entries_ex_4_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5234 = issue_sel_5_1 ? entries_ex_5_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5235 = issue_sel_6_1 ? entries_ex_6_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5236 = issue_sel_7_1 ? entries_ex_7_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5237 = issue_sel_8 ? entries_ex_8_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5238 = issue_sel_9 ? entries_ex_9_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5239 = issue_sel_10 ? entries_ex_10_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5240 = issue_sel_11 ? entries_ex_11_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5241 = issue_sel_12 ? entries_ex_12_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5242 = issue_sel_13 ? entries_ex_13_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5243 = issue_sel_14 ? entries_ex_14_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5244 = issue_sel_15 ? entries_ex_15_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_5245 = _issue_entry_T_5229 | _issue_entry_T_5230; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5246 = _issue_entry_T_5245 | _issue_entry_T_5231; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5247 = _issue_entry_T_5246 | _issue_entry_T_5232; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5248 = _issue_entry_T_5247 | _issue_entry_T_5233; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5249 = _issue_entry_T_5248 | _issue_entry_T_5234; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5250 = _issue_entry_T_5249 | _issue_entry_T_5235; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5251 = _issue_entry_T_5250 | _issue_entry_T_5236; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5252 = _issue_entry_T_5251 | _issue_entry_T_5237; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5253 = _issue_entry_T_5252 | _issue_entry_T_5238; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5254 = _issue_entry_T_5253 | _issue_entry_T_5239; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5255 = _issue_entry_T_5254 | _issue_entry_T_5240; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5256 = _issue_entry_T_5255 | _issue_entry_T_5241; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5257 = _issue_entry_T_5256 | _issue_entry_T_5242; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5258 = _issue_entry_T_5257 | _issue_entry_T_5243; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_5259 = _issue_entry_T_5258 | _issue_entry_T_5244; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_275 = _issue_entry_T_5259; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_272_garbage = _issue_entry_WIRE_275; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5261 = issue_sel_0_1 ? _issue_entry_T_5260 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5263 = issue_sel_1_1 ? _issue_entry_T_5262 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5265 = issue_sel_2_1 ? _issue_entry_T_5264 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5267 = issue_sel_3_1 ? _issue_entry_T_5266 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5269 = issue_sel_4_1 ? _issue_entry_T_5268 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5271 = issue_sel_5_1 ? _issue_entry_T_5270 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5273 = issue_sel_6_1 ? _issue_entry_T_5272 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5275 = issue_sel_7_1 ? _issue_entry_T_5274 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5277 = issue_sel_8 ? _issue_entry_T_5276 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5279 = issue_sel_9 ? _issue_entry_T_5278 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5281 = issue_sel_10 ? _issue_entry_T_5280 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5283 = issue_sel_11 ? _issue_entry_T_5282 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5285 = issue_sel_12 ? _issue_entry_T_5284 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5287 = issue_sel_13 ? _issue_entry_T_5286 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5289 = issue_sel_14 ? _issue_entry_T_5288 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5291 = issue_sel_15 ? _issue_entry_T_5290 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_5292 = _issue_entry_T_5261 | _issue_entry_T_5263; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5293 = _issue_entry_T_5292 | _issue_entry_T_5265; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5294 = _issue_entry_T_5293 | _issue_entry_T_5267; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5295 = _issue_entry_T_5294 | _issue_entry_T_5269; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5296 = _issue_entry_T_5295 | _issue_entry_T_5271; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5297 = _issue_entry_T_5296 | _issue_entry_T_5273; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5298 = _issue_entry_T_5297 | _issue_entry_T_5275; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5299 = _issue_entry_T_5298 | _issue_entry_T_5277; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5300 = _issue_entry_T_5299 | _issue_entry_T_5279; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5301 = _issue_entry_T_5300 | _issue_entry_T_5281; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5302 = _issue_entry_T_5301 | _issue_entry_T_5283; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5303 = _issue_entry_T_5302 | _issue_entry_T_5285; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5304 = _issue_entry_T_5303 | _issue_entry_T_5287; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5305 = _issue_entry_T_5304 | _issue_entry_T_5289; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_5306 = _issue_entry_T_5305 | _issue_entry_T_5291; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_277 = _issue_entry_T_5306; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_278; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_272_norm_cmd = _issue_entry_WIRE_276; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_278 = _issue_entry_WIRE_277; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_276 = _issue_entry_WIRE_278; // @[Mux.scala:30:73]
wire _issue_entry_T_5307 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5308 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5309 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5310 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5311 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5312 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5313 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5314 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5315 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5316 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5317 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5318 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5319 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5320 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5321 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5322 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_5323 = _issue_entry_T_5307 | _issue_entry_T_5308; // @[Mux.scala:30:73]
wire _issue_entry_T_5324 = _issue_entry_T_5323 | _issue_entry_T_5309; // @[Mux.scala:30:73]
wire _issue_entry_T_5325 = _issue_entry_T_5324 | _issue_entry_T_5310; // @[Mux.scala:30:73]
wire _issue_entry_T_5326 = _issue_entry_T_5325 | _issue_entry_T_5311; // @[Mux.scala:30:73]
wire _issue_entry_T_5327 = _issue_entry_T_5326 | _issue_entry_T_5312; // @[Mux.scala:30:73]
wire _issue_entry_T_5328 = _issue_entry_T_5327 | _issue_entry_T_5313; // @[Mux.scala:30:73]
wire _issue_entry_T_5329 = _issue_entry_T_5328 | _issue_entry_T_5314; // @[Mux.scala:30:73]
wire _issue_entry_T_5330 = _issue_entry_T_5329 | _issue_entry_T_5315; // @[Mux.scala:30:73]
wire _issue_entry_T_5331 = _issue_entry_T_5330 | _issue_entry_T_5316; // @[Mux.scala:30:73]
wire _issue_entry_T_5332 = _issue_entry_T_5331 | _issue_entry_T_5317; // @[Mux.scala:30:73]
wire _issue_entry_T_5333 = _issue_entry_T_5332 | _issue_entry_T_5318; // @[Mux.scala:30:73]
wire _issue_entry_T_5334 = _issue_entry_T_5333 | _issue_entry_T_5319; // @[Mux.scala:30:73]
wire _issue_entry_T_5335 = _issue_entry_T_5334 | _issue_entry_T_5320; // @[Mux.scala:30:73]
wire _issue_entry_T_5336 = _issue_entry_T_5335 | _issue_entry_T_5321; // @[Mux.scala:30:73]
wire _issue_entry_T_5337 = _issue_entry_T_5336 | _issue_entry_T_5322; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_279 = _issue_entry_T_5337; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_272_read_full_acc_row = _issue_entry_WIRE_279; // @[Mux.scala:30:73]
wire _issue_entry_T_5338 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5339 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5340 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5341 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5342 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5343 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5344 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5345 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5346 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5347 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5348 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5349 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5350 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5351 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5352 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5353 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_5354 = _issue_entry_T_5338 | _issue_entry_T_5339; // @[Mux.scala:30:73]
wire _issue_entry_T_5355 = _issue_entry_T_5354 | _issue_entry_T_5340; // @[Mux.scala:30:73]
wire _issue_entry_T_5356 = _issue_entry_T_5355 | _issue_entry_T_5341; // @[Mux.scala:30:73]
wire _issue_entry_T_5357 = _issue_entry_T_5356 | _issue_entry_T_5342; // @[Mux.scala:30:73]
wire _issue_entry_T_5358 = _issue_entry_T_5357 | _issue_entry_T_5343; // @[Mux.scala:30:73]
wire _issue_entry_T_5359 = _issue_entry_T_5358 | _issue_entry_T_5344; // @[Mux.scala:30:73]
wire _issue_entry_T_5360 = _issue_entry_T_5359 | _issue_entry_T_5345; // @[Mux.scala:30:73]
wire _issue_entry_T_5361 = _issue_entry_T_5360 | _issue_entry_T_5346; // @[Mux.scala:30:73]
wire _issue_entry_T_5362 = _issue_entry_T_5361 | _issue_entry_T_5347; // @[Mux.scala:30:73]
wire _issue_entry_T_5363 = _issue_entry_T_5362 | _issue_entry_T_5348; // @[Mux.scala:30:73]
wire _issue_entry_T_5364 = _issue_entry_T_5363 | _issue_entry_T_5349; // @[Mux.scala:30:73]
wire _issue_entry_T_5365 = _issue_entry_T_5364 | _issue_entry_T_5350; // @[Mux.scala:30:73]
wire _issue_entry_T_5366 = _issue_entry_T_5365 | _issue_entry_T_5351; // @[Mux.scala:30:73]
wire _issue_entry_T_5367 = _issue_entry_T_5366 | _issue_entry_T_5352; // @[Mux.scala:30:73]
wire _issue_entry_T_5368 = _issue_entry_T_5367 | _issue_entry_T_5353; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_280 = _issue_entry_T_5368; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_272_accumulate = _issue_entry_WIRE_280; // @[Mux.scala:30:73]
wire _issue_entry_T_5369 = issue_sel_0_1 & entries_ex_0_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5370 = issue_sel_1_1 & entries_ex_1_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5371 = issue_sel_2_1 & entries_ex_2_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5372 = issue_sel_3_1 & entries_ex_3_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5373 = issue_sel_4_1 & entries_ex_4_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5374 = issue_sel_5_1 & entries_ex_5_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5375 = issue_sel_6_1 & entries_ex_6_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5376 = issue_sel_7_1 & entries_ex_7_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5377 = issue_sel_8 & entries_ex_8_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5378 = issue_sel_9 & entries_ex_9_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5379 = issue_sel_10 & entries_ex_10_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5380 = issue_sel_11 & entries_ex_11_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5381 = issue_sel_12 & entries_ex_12_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5382 = issue_sel_13 & entries_ex_13_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5383 = issue_sel_14 & entries_ex_14_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5384 = issue_sel_15 & entries_ex_15_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5385 = _issue_entry_T_5369 | _issue_entry_T_5370; // @[Mux.scala:30:73]
wire _issue_entry_T_5386 = _issue_entry_T_5385 | _issue_entry_T_5371; // @[Mux.scala:30:73]
wire _issue_entry_T_5387 = _issue_entry_T_5386 | _issue_entry_T_5372; // @[Mux.scala:30:73]
wire _issue_entry_T_5388 = _issue_entry_T_5387 | _issue_entry_T_5373; // @[Mux.scala:30:73]
wire _issue_entry_T_5389 = _issue_entry_T_5388 | _issue_entry_T_5374; // @[Mux.scala:30:73]
wire _issue_entry_T_5390 = _issue_entry_T_5389 | _issue_entry_T_5375; // @[Mux.scala:30:73]
wire _issue_entry_T_5391 = _issue_entry_T_5390 | _issue_entry_T_5376; // @[Mux.scala:30:73]
wire _issue_entry_T_5392 = _issue_entry_T_5391 | _issue_entry_T_5377; // @[Mux.scala:30:73]
wire _issue_entry_T_5393 = _issue_entry_T_5392 | _issue_entry_T_5378; // @[Mux.scala:30:73]
wire _issue_entry_T_5394 = _issue_entry_T_5393 | _issue_entry_T_5379; // @[Mux.scala:30:73]
wire _issue_entry_T_5395 = _issue_entry_T_5394 | _issue_entry_T_5380; // @[Mux.scala:30:73]
wire _issue_entry_T_5396 = _issue_entry_T_5395 | _issue_entry_T_5381; // @[Mux.scala:30:73]
wire _issue_entry_T_5397 = _issue_entry_T_5396 | _issue_entry_T_5382; // @[Mux.scala:30:73]
wire _issue_entry_T_5398 = _issue_entry_T_5397 | _issue_entry_T_5383; // @[Mux.scala:30:73]
wire _issue_entry_T_5399 = _issue_entry_T_5398 | _issue_entry_T_5384; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_281 = _issue_entry_T_5399; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_272_is_acc_addr = _issue_entry_WIRE_281; // @[Mux.scala:30:73]
wire _issue_entry_T_5400 = issue_sel_0_1 & entries_ex_0_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5401 = issue_sel_1_1 & entries_ex_1_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5402 = issue_sel_2_1 & entries_ex_2_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5403 = issue_sel_3_1 & entries_ex_3_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5404 = issue_sel_4_1 & entries_ex_4_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5405 = issue_sel_5_1 & entries_ex_5_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5406 = issue_sel_6_1 & entries_ex_6_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5407 = issue_sel_7_1 & entries_ex_7_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5408 = issue_sel_8 & entries_ex_8_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5409 = issue_sel_9 & entries_ex_9_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5410 = issue_sel_10 & entries_ex_10_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5411 = issue_sel_11 & entries_ex_11_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5412 = issue_sel_12 & entries_ex_12_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5413 = issue_sel_13 & entries_ex_13_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5414 = issue_sel_14 & entries_ex_14_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5415 = issue_sel_15 & entries_ex_15_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5416 = _issue_entry_T_5400 | _issue_entry_T_5401; // @[Mux.scala:30:73]
wire _issue_entry_T_5417 = _issue_entry_T_5416 | _issue_entry_T_5402; // @[Mux.scala:30:73]
wire _issue_entry_T_5418 = _issue_entry_T_5417 | _issue_entry_T_5403; // @[Mux.scala:30:73]
wire _issue_entry_T_5419 = _issue_entry_T_5418 | _issue_entry_T_5404; // @[Mux.scala:30:73]
wire _issue_entry_T_5420 = _issue_entry_T_5419 | _issue_entry_T_5405; // @[Mux.scala:30:73]
wire _issue_entry_T_5421 = _issue_entry_T_5420 | _issue_entry_T_5406; // @[Mux.scala:30:73]
wire _issue_entry_T_5422 = _issue_entry_T_5421 | _issue_entry_T_5407; // @[Mux.scala:30:73]
wire _issue_entry_T_5423 = _issue_entry_T_5422 | _issue_entry_T_5408; // @[Mux.scala:30:73]
wire _issue_entry_T_5424 = _issue_entry_T_5423 | _issue_entry_T_5409; // @[Mux.scala:30:73]
wire _issue_entry_T_5425 = _issue_entry_T_5424 | _issue_entry_T_5410; // @[Mux.scala:30:73]
wire _issue_entry_T_5426 = _issue_entry_T_5425 | _issue_entry_T_5411; // @[Mux.scala:30:73]
wire _issue_entry_T_5427 = _issue_entry_T_5426 | _issue_entry_T_5412; // @[Mux.scala:30:73]
wire _issue_entry_T_5428 = _issue_entry_T_5427 | _issue_entry_T_5413; // @[Mux.scala:30:73]
wire _issue_entry_T_5429 = _issue_entry_T_5428 | _issue_entry_T_5414; // @[Mux.scala:30:73]
wire _issue_entry_T_5430 = _issue_entry_T_5429 | _issue_entry_T_5415; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_282 = _issue_entry_T_5430; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_259_valid = _issue_entry_WIRE_282; // @[Mux.scala:30:73]
wire _issue_entry_T_5431 = issue_sel_0_1 & entries_ex_0_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5432 = issue_sel_1_1 & entries_ex_1_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5433 = issue_sel_2_1 & entries_ex_2_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5434 = issue_sel_3_1 & entries_ex_3_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5435 = issue_sel_4_1 & entries_ex_4_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5436 = issue_sel_5_1 & entries_ex_5_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5437 = issue_sel_6_1 & entries_ex_6_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5438 = issue_sel_7_1 & entries_ex_7_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5439 = issue_sel_8 & entries_ex_8_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5440 = issue_sel_9 & entries_ex_9_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5441 = issue_sel_10 & entries_ex_10_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5442 = issue_sel_11 & entries_ex_11_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5443 = issue_sel_12 & entries_ex_12_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5444 = issue_sel_13 & entries_ex_13_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5445 = issue_sel_14 & entries_ex_14_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5446 = issue_sel_15 & entries_ex_15_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_5447 = _issue_entry_T_5431 | _issue_entry_T_5432; // @[Mux.scala:30:73]
wire _issue_entry_T_5448 = _issue_entry_T_5447 | _issue_entry_T_5433; // @[Mux.scala:30:73]
wire _issue_entry_T_5449 = _issue_entry_T_5448 | _issue_entry_T_5434; // @[Mux.scala:30:73]
wire _issue_entry_T_5450 = _issue_entry_T_5449 | _issue_entry_T_5435; // @[Mux.scala:30:73]
wire _issue_entry_T_5451 = _issue_entry_T_5450 | _issue_entry_T_5436; // @[Mux.scala:30:73]
wire _issue_entry_T_5452 = _issue_entry_T_5451 | _issue_entry_T_5437; // @[Mux.scala:30:73]
wire _issue_entry_T_5453 = _issue_entry_T_5452 | _issue_entry_T_5438; // @[Mux.scala:30:73]
wire _issue_entry_T_5454 = _issue_entry_T_5453 | _issue_entry_T_5439; // @[Mux.scala:30:73]
wire _issue_entry_T_5455 = _issue_entry_T_5454 | _issue_entry_T_5440; // @[Mux.scala:30:73]
wire _issue_entry_T_5456 = _issue_entry_T_5455 | _issue_entry_T_5441; // @[Mux.scala:30:73]
wire _issue_entry_T_5457 = _issue_entry_T_5456 | _issue_entry_T_5442; // @[Mux.scala:30:73]
wire _issue_entry_T_5458 = _issue_entry_T_5457 | _issue_entry_T_5443; // @[Mux.scala:30:73]
wire _issue_entry_T_5459 = _issue_entry_T_5458 | _issue_entry_T_5444; // @[Mux.scala:30:73]
wire _issue_entry_T_5460 = _issue_entry_T_5459 | _issue_entry_T_5445; // @[Mux.scala:30:73]
wire _issue_entry_T_5461 = _issue_entry_T_5460 | _issue_entry_T_5446; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_283 = _issue_entry_T_5461; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_is_config = _issue_entry_WIRE_283; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5462 = issue_sel_0_1 ? entries_ex_0_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5463 = issue_sel_1_1 ? entries_ex_1_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5464 = issue_sel_2_1 ? entries_ex_2_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5465 = issue_sel_3_1 ? entries_ex_3_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5466 = issue_sel_4_1 ? entries_ex_4_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5467 = issue_sel_5_1 ? entries_ex_5_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5468 = issue_sel_6_1 ? entries_ex_6_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5469 = issue_sel_7_1 ? entries_ex_7_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5470 = issue_sel_8 ? entries_ex_8_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5471 = issue_sel_9 ? entries_ex_9_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5472 = issue_sel_10 ? entries_ex_10_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5473 = issue_sel_11 ? entries_ex_11_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5474 = issue_sel_12 ? entries_ex_12_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5475 = issue_sel_13 ? entries_ex_13_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5476 = issue_sel_14 ? entries_ex_14_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5477 = issue_sel_15 ? entries_ex_15_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5478 = _issue_entry_T_5462 | _issue_entry_T_5463; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5479 = _issue_entry_T_5478 | _issue_entry_T_5464; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5480 = _issue_entry_T_5479 | _issue_entry_T_5465; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5481 = _issue_entry_T_5480 | _issue_entry_T_5466; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5482 = _issue_entry_T_5481 | _issue_entry_T_5467; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5483 = _issue_entry_T_5482 | _issue_entry_T_5468; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5484 = _issue_entry_T_5483 | _issue_entry_T_5469; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5485 = _issue_entry_T_5484 | _issue_entry_T_5470; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5486 = _issue_entry_T_5485 | _issue_entry_T_5471; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5487 = _issue_entry_T_5486 | _issue_entry_T_5472; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5488 = _issue_entry_T_5487 | _issue_entry_T_5473; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5489 = _issue_entry_T_5488 | _issue_entry_T_5474; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5490 = _issue_entry_T_5489 | _issue_entry_T_5475; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5491 = _issue_entry_T_5490 | _issue_entry_T_5476; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5492 = _issue_entry_T_5491 | _issue_entry_T_5477; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_284 = _issue_entry_T_5492; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_143_q = _issue_entry_WIRE_284; // @[Mux.scala:30:73]
wire _issue_entry_T_5493 = issue_sel_0_1 & entries_ex_0_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5494 = issue_sel_1_1 & entries_ex_1_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5495 = issue_sel_2_1 & entries_ex_2_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5496 = issue_sel_3_1 & entries_ex_3_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5497 = issue_sel_4_1 & entries_ex_4_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5498 = issue_sel_5_1 & entries_ex_5_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5499 = issue_sel_6_1 & entries_ex_6_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5500 = issue_sel_7_1 & entries_ex_7_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5501 = issue_sel_8 & entries_ex_8_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5502 = issue_sel_9 & entries_ex_9_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5503 = issue_sel_10 & entries_ex_10_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5504 = issue_sel_11 & entries_ex_11_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5505 = issue_sel_12 & entries_ex_12_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5506 = issue_sel_13 & entries_ex_13_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5507 = issue_sel_14 & entries_ex_14_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5508 = issue_sel_15 & entries_ex_15_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5509 = _issue_entry_T_5493 | _issue_entry_T_5494; // @[Mux.scala:30:73]
wire _issue_entry_T_5510 = _issue_entry_T_5509 | _issue_entry_T_5495; // @[Mux.scala:30:73]
wire _issue_entry_T_5511 = _issue_entry_T_5510 | _issue_entry_T_5496; // @[Mux.scala:30:73]
wire _issue_entry_T_5512 = _issue_entry_T_5511 | _issue_entry_T_5497; // @[Mux.scala:30:73]
wire _issue_entry_T_5513 = _issue_entry_T_5512 | _issue_entry_T_5498; // @[Mux.scala:30:73]
wire _issue_entry_T_5514 = _issue_entry_T_5513 | _issue_entry_T_5499; // @[Mux.scala:30:73]
wire _issue_entry_T_5515 = _issue_entry_T_5514 | _issue_entry_T_5500; // @[Mux.scala:30:73]
wire _issue_entry_T_5516 = _issue_entry_T_5515 | _issue_entry_T_5501; // @[Mux.scala:30:73]
wire _issue_entry_T_5517 = _issue_entry_T_5516 | _issue_entry_T_5502; // @[Mux.scala:30:73]
wire _issue_entry_T_5518 = _issue_entry_T_5517 | _issue_entry_T_5503; // @[Mux.scala:30:73]
wire _issue_entry_T_5519 = _issue_entry_T_5518 | _issue_entry_T_5504; // @[Mux.scala:30:73]
wire _issue_entry_T_5520 = _issue_entry_T_5519 | _issue_entry_T_5505; // @[Mux.scala:30:73]
wire _issue_entry_T_5521 = _issue_entry_T_5520 | _issue_entry_T_5506; // @[Mux.scala:30:73]
wire _issue_entry_T_5522 = _issue_entry_T_5521 | _issue_entry_T_5507; // @[Mux.scala:30:73]
wire _issue_entry_T_5523 = _issue_entry_T_5522 | _issue_entry_T_5508; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_285 = _issue_entry_T_5523; // @[Mux.scala:30:73]
assign issue_entry_1_valid = _issue_entry_WIRE_285; // @[Mux.scala:30:73]
wire _io_issue_ex_valid_T = issue_valids_0_1 | issue_valids_1_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_1 = _io_issue_ex_valid_T | issue_valids_2_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_2 = _io_issue_ex_valid_T_1 | issue_valids_3_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_3 = _io_issue_ex_valid_T_2 | issue_valids_4_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_4 = _io_issue_ex_valid_T_3 | issue_valids_5_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_5 = _io_issue_ex_valid_T_4 | issue_valids_6_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_6 = _io_issue_ex_valid_T_5 | issue_valids_7_1; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_7 = _io_issue_ex_valid_T_6 | issue_valids_8; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_8 = _io_issue_ex_valid_T_7 | issue_valids_9; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_9 = _io_issue_ex_valid_T_8 | issue_valids_10; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_10 = _io_issue_ex_valid_T_9 | issue_valids_11; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_11 = _io_issue_ex_valid_T_10 | issue_valids_12; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_12 = _io_issue_ex_valid_T_11 | issue_valids_13; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_ex_valid_T_13 = _io_issue_ex_valid_T_12 | issue_valids_14; // @[ReservationStation.scala:395:72, :404:38]
assign _io_issue_ex_valid_T_14 = _io_issue_ex_valid_T_13 | issue_valids_15; // @[ReservationStation.scala:395:72, :404:38]
assign io_issue_ex_valid_0 = _io_issue_ex_valid_T_14; // @[ReservationStation.scala:26:7, :404:38]
wire _T_5016 = io_issue_ex_valid_0 & io_issue_ex_ready_0; // @[ReservationStation.scala:22:20, :26:7]
wire _entries_ex_0_valid_T = ~entries_ex_0_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_1_valid_T = ~entries_ex_1_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_2_valid_T = ~entries_ex_2_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_3_valid_T = ~entries_ex_3_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_4_valid_T = ~entries_ex_4_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_5_valid_T = ~entries_ex_5_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_6_valid_T = ~entries_ex_6_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_7_valid_T = ~entries_ex_7_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_8_valid_T = ~entries_ex_8_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_9_valid_T = ~entries_ex_9_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_10_valid_T = ~entries_ex_10_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_11_valid_T = ~entries_ex_11_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_12_valid_T = ~entries_ex_12_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_13_valid_T = ~entries_ex_13_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_14_valid_T = ~entries_ex_14_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire _entries_ex_15_valid_T = ~entries_ex_15_bits_complete_on_issue; // @[ReservationStation.scala:118:23, :417:22]
wire [15:0] _GEN_94 = {{entries_ex_15_bits_complete_on_issue}, {entries_ex_14_bits_complete_on_issue}, {entries_ex_13_bits_complete_on_issue}, {entries_ex_12_bits_complete_on_issue}, {entries_ex_11_bits_complete_on_issue}, {entries_ex_10_bits_complete_on_issue}, {entries_ex_9_bits_complete_on_issue}, {entries_ex_8_bits_complete_on_issue}, {entries_ex_7_bits_complete_on_issue}, {entries_ex_6_bits_complete_on_issue}, {entries_ex_5_bits_complete_on_issue}, {entries_ex_4_bits_complete_on_issue}, {entries_ex_3_bits_complete_on_issue}, {entries_ex_2_bits_complete_on_issue}, {entries_ex_1_bits_complete_on_issue}, {entries_ex_0_bits_complete_on_issue}}; // @[ReservationStation.scala:118:23, :440:71]
wire [15:0] _GEN_95 = {{entries_ex_15_bits_cmd_from_conv_fsm}, {entries_ex_14_bits_cmd_from_conv_fsm}, {entries_ex_13_bits_cmd_from_conv_fsm}, {entries_ex_12_bits_cmd_from_conv_fsm}, {entries_ex_11_bits_cmd_from_conv_fsm}, {entries_ex_10_bits_cmd_from_conv_fsm}, {entries_ex_9_bits_cmd_from_conv_fsm}, {entries_ex_8_bits_cmd_from_conv_fsm}, {entries_ex_7_bits_cmd_from_conv_fsm}, {entries_ex_6_bits_cmd_from_conv_fsm}, {entries_ex_5_bits_cmd_from_conv_fsm}, {entries_ex_4_bits_cmd_from_conv_fsm}, {entries_ex_3_bits_cmd_from_conv_fsm}, {entries_ex_2_bits_cmd_from_conv_fsm}, {entries_ex_1_bits_cmd_from_conv_fsm}, {entries_ex_0_bits_cmd_from_conv_fsm}}; // @[ReservationStation.scala:118:23, :440:71]
wire _GEN_96 = _GEN_94[issue_id_1] & _GEN_95[issue_id_1]; // @[OneHot.scala:32:10]
wire _conv_ld_issue_completed_T_1; // @[ReservationStation.scala:440:71]
assign _conv_ld_issue_completed_T_1 = _GEN_96; // @[ReservationStation.scala:440:71]
wire _conv_st_issue_completed_T_1; // @[ReservationStation.scala:441:71]
assign _conv_st_issue_completed_T_1 = _GEN_96; // @[ReservationStation.scala:440:71, :441:71]
wire _conv_ex_issue_completed_T_1; // @[ReservationStation.scala:442:71]
assign _conv_ex_issue_completed_T_1 = _GEN_96; // @[ReservationStation.scala:440:71, :442:71]
assign conv_ex_issue_completed = _T_5016 & _conv_ex_issue_completed_T_1; // @[ReservationStation.scala:22:20, :140:41, :413:20, :442:{24,71}]
wire [15:0] _GEN_97 = {{entries_ex_15_bits_cmd_from_matmul_fsm}, {entries_ex_14_bits_cmd_from_matmul_fsm}, {entries_ex_13_bits_cmd_from_matmul_fsm}, {entries_ex_12_bits_cmd_from_matmul_fsm}, {entries_ex_11_bits_cmd_from_matmul_fsm}, {entries_ex_10_bits_cmd_from_matmul_fsm}, {entries_ex_9_bits_cmd_from_matmul_fsm}, {entries_ex_8_bits_cmd_from_matmul_fsm}, {entries_ex_7_bits_cmd_from_matmul_fsm}, {entries_ex_6_bits_cmd_from_matmul_fsm}, {entries_ex_5_bits_cmd_from_matmul_fsm}, {entries_ex_4_bits_cmd_from_matmul_fsm}, {entries_ex_3_bits_cmd_from_matmul_fsm}, {entries_ex_2_bits_cmd_from_matmul_fsm}, {entries_ex_1_bits_cmd_from_matmul_fsm}, {entries_ex_0_bits_cmd_from_matmul_fsm}}; // @[ReservationStation.scala:118:23, :444:73]
wire _GEN_98 = _GEN_94[issue_id_1] & _GEN_97[issue_id_1]; // @[OneHot.scala:32:10]
wire _matmul_ld_issue_completed_T_1; // @[ReservationStation.scala:444:73]
assign _matmul_ld_issue_completed_T_1 = _GEN_98; // @[ReservationStation.scala:444:73]
wire _matmul_st_issue_completed_T_1; // @[ReservationStation.scala:445:73]
assign _matmul_st_issue_completed_T_1 = _GEN_98; // @[ReservationStation.scala:444:73, :445:73]
wire _matmul_ex_issue_completed_T_1; // @[ReservationStation.scala:446:73]
assign _matmul_ex_issue_completed_T_1 = _GEN_98; // @[ReservationStation.scala:444:73, :446:73]
assign matmul_ex_issue_completed = _T_5016 & _matmul_ex_issue_completed_T_1; // @[ReservationStation.scala:22:20, :148:43, :413:20, :446:{24,73}]
wire _issue_valids_T_720 = entries_st_0_bits_deps_ld_0 | entries_st_0_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_721 = _issue_valids_T_720 | entries_st_0_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_722 = _issue_valids_T_721 | entries_st_0_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_723 = _issue_valids_T_722 | entries_st_0_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_724 = _issue_valids_T_723 | entries_st_0_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_725 = _issue_valids_T_724 | entries_st_0_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_726 = _issue_valids_T_725 | entries_st_0_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_727 = entries_st_0_bits_deps_ex_0 | entries_st_0_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_728 = _issue_valids_T_727 | entries_st_0_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_729 = _issue_valids_T_728 | entries_st_0_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_730 = _issue_valids_T_729 | entries_st_0_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_731 = _issue_valids_T_730 | entries_st_0_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_732 = _issue_valids_T_731 | entries_st_0_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_733 = _issue_valids_T_732 | entries_st_0_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_734 = _issue_valids_T_733 | entries_st_0_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_735 = _issue_valids_T_734 | entries_st_0_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_736 = _issue_valids_T_735 | entries_st_0_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_737 = _issue_valids_T_736 | entries_st_0_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_738 = _issue_valids_T_737 | entries_st_0_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_739 = _issue_valids_T_738 | entries_st_0_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_740 = _issue_valids_T_739 | entries_st_0_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_741 = _issue_valids_T_740 | entries_st_0_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_742 = _issue_valids_T_726 | _issue_valids_T_741; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_743 = entries_st_0_bits_deps_st_0 | entries_st_0_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_744 = _issue_valids_T_743 | entries_st_0_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_745 = _issue_valids_T_744 | entries_st_0_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_746 = _issue_valids_T_742 | _issue_valids_T_745; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_747 = ~_issue_valids_T_746; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_748 = entries_st_0_valid & _issue_valids_T_747; // @[ReservationStation.scala:107:39, :119:23, :395:54]
wire _issue_valids_T_749 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75]
wire issue_valids_0_2 = _issue_valids_T_748 & _issue_valids_T_749; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_750 = entries_st_1_bits_deps_ld_0 | entries_st_1_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_751 = _issue_valids_T_750 | entries_st_1_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_752 = _issue_valids_T_751 | entries_st_1_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_753 = _issue_valids_T_752 | entries_st_1_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_754 = _issue_valids_T_753 | entries_st_1_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_755 = _issue_valids_T_754 | entries_st_1_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_756 = _issue_valids_T_755 | entries_st_1_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_757 = entries_st_1_bits_deps_ex_0 | entries_st_1_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_758 = _issue_valids_T_757 | entries_st_1_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_759 = _issue_valids_T_758 | entries_st_1_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_760 = _issue_valids_T_759 | entries_st_1_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_761 = _issue_valids_T_760 | entries_st_1_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_762 = _issue_valids_T_761 | entries_st_1_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_763 = _issue_valids_T_762 | entries_st_1_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_764 = _issue_valids_T_763 | entries_st_1_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_765 = _issue_valids_T_764 | entries_st_1_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_766 = _issue_valids_T_765 | entries_st_1_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_767 = _issue_valids_T_766 | entries_st_1_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_768 = _issue_valids_T_767 | entries_st_1_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_769 = _issue_valids_T_768 | entries_st_1_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_770 = _issue_valids_T_769 | entries_st_1_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_771 = _issue_valids_T_770 | entries_st_1_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_772 = _issue_valids_T_756 | _issue_valids_T_771; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_773 = entries_st_1_bits_deps_st_0 | entries_st_1_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_774 = _issue_valids_T_773 | entries_st_1_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_775 = _issue_valids_T_774 | entries_st_1_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_776 = _issue_valids_T_772 | _issue_valids_T_775; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_777 = ~_issue_valids_T_776; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_778 = entries_st_1_valid & _issue_valids_T_777; // @[ReservationStation.scala:107:39, :119:23, :395:54]
wire _issue_valids_T_779 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75]
wire issue_valids_1_2 = _issue_valids_T_778 & _issue_valids_T_779; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_780 = entries_st_2_bits_deps_ld_0 | entries_st_2_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_781 = _issue_valids_T_780 | entries_st_2_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_782 = _issue_valids_T_781 | entries_st_2_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_783 = _issue_valids_T_782 | entries_st_2_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_784 = _issue_valids_T_783 | entries_st_2_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_785 = _issue_valids_T_784 | entries_st_2_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_786 = _issue_valids_T_785 | entries_st_2_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_787 = entries_st_2_bits_deps_ex_0 | entries_st_2_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_788 = _issue_valids_T_787 | entries_st_2_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_789 = _issue_valids_T_788 | entries_st_2_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_790 = _issue_valids_T_789 | entries_st_2_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_791 = _issue_valids_T_790 | entries_st_2_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_792 = _issue_valids_T_791 | entries_st_2_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_793 = _issue_valids_T_792 | entries_st_2_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_794 = _issue_valids_T_793 | entries_st_2_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_795 = _issue_valids_T_794 | entries_st_2_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_796 = _issue_valids_T_795 | entries_st_2_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_797 = _issue_valids_T_796 | entries_st_2_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_798 = _issue_valids_T_797 | entries_st_2_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_799 = _issue_valids_T_798 | entries_st_2_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_800 = _issue_valids_T_799 | entries_st_2_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_801 = _issue_valids_T_800 | entries_st_2_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_802 = _issue_valids_T_786 | _issue_valids_T_801; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_803 = entries_st_2_bits_deps_st_0 | entries_st_2_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_804 = _issue_valids_T_803 | entries_st_2_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_805 = _issue_valids_T_804 | entries_st_2_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_806 = _issue_valids_T_802 | _issue_valids_T_805; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_807 = ~_issue_valids_T_806; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_808 = entries_st_2_valid & _issue_valids_T_807; // @[ReservationStation.scala:107:39, :119:23, :395:54]
wire _issue_valids_T_809 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75]
wire issue_valids_2_2 = _issue_valids_T_808 & _issue_valids_T_809; // @[ReservationStation.scala:395:{54,72,75}]
wire _issue_valids_T_810 = entries_st_3_bits_deps_ld_0 | entries_st_3_bits_deps_ld_1; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_811 = _issue_valids_T_810 | entries_st_3_bits_deps_ld_2; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_812 = _issue_valids_T_811 | entries_st_3_bits_deps_ld_3; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_813 = _issue_valids_T_812 | entries_st_3_bits_deps_ld_4; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_814 = _issue_valids_T_813 | entries_st_3_bits_deps_ld_5; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_815 = _issue_valids_T_814 | entries_st_3_bits_deps_ld_6; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_816 = _issue_valids_T_815 | entries_st_3_bits_deps_ld_7; // @[ReservationStation.scala:107:58, :119:23]
wire _issue_valids_T_817 = entries_st_3_bits_deps_ex_0 | entries_st_3_bits_deps_ex_1; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_818 = _issue_valids_T_817 | entries_st_3_bits_deps_ex_2; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_819 = _issue_valids_T_818 | entries_st_3_bits_deps_ex_3; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_820 = _issue_valids_T_819 | entries_st_3_bits_deps_ex_4; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_821 = _issue_valids_T_820 | entries_st_3_bits_deps_ex_5; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_822 = _issue_valids_T_821 | entries_st_3_bits_deps_ex_6; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_823 = _issue_valids_T_822 | entries_st_3_bits_deps_ex_7; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_824 = _issue_valids_T_823 | entries_st_3_bits_deps_ex_8; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_825 = _issue_valids_T_824 | entries_st_3_bits_deps_ex_9; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_826 = _issue_valids_T_825 | entries_st_3_bits_deps_ex_10; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_827 = _issue_valids_T_826 | entries_st_3_bits_deps_ex_11; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_828 = _issue_valids_T_827 | entries_st_3_bits_deps_ex_12; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_829 = _issue_valids_T_828 | entries_st_3_bits_deps_ex_13; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_830 = _issue_valids_T_829 | entries_st_3_bits_deps_ex_14; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_831 = _issue_valids_T_830 | entries_st_3_bits_deps_ex_15; // @[ReservationStation.scala:107:84, :119:23]
wire _issue_valids_T_832 = _issue_valids_T_816 | _issue_valids_T_831; // @[ReservationStation.scala:107:{58,64,84}]
wire _issue_valids_T_833 = entries_st_3_bits_deps_st_0 | entries_st_3_bits_deps_st_1; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_834 = _issue_valids_T_833 | entries_st_3_bits_deps_st_2; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_835 = _issue_valids_T_834 | entries_st_3_bits_deps_st_3; // @[ReservationStation.scala:107:110, :119:23]
wire _issue_valids_T_836 = _issue_valids_T_832 | _issue_valids_T_835; // @[ReservationStation.scala:107:{64,90,110}]
wire _issue_valids_T_837 = ~_issue_valids_T_836; // @[ReservationStation.scala:107:{39,90}]
wire _issue_valids_T_838 = entries_st_3_valid & _issue_valids_T_837; // @[ReservationStation.scala:107:39, :119:23, :395:54]
wire _issue_valids_T_839 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75]
wire issue_valids_3_2 = _issue_valids_T_838 & _issue_valids_T_839; // @[ReservationStation.scala:395:{54,72,75}]
wire [3:0] _issue_sel_enc_T_22 = {issue_valids_3_2, 3'h0}; // @[Mux.scala:50:70]
wire [3:0] _issue_sel_enc_T_23 = issue_valids_2_2 ? 4'h4 : _issue_sel_enc_T_22; // @[Mux.scala:50:70]
wire [3:0] _issue_sel_enc_T_24 = issue_valids_1_2 ? 4'h2 : _issue_sel_enc_T_23; // @[Mux.scala:50:70]
wire [3:0] issue_sel_enc_2 = issue_valids_0_2 ? 4'h1 : _issue_sel_enc_T_24; // @[Mux.scala:50:70]
wire issue_sel_0_2 = issue_sel_enc_2[0]; // @[OneHot.scala:83:30]
wire issue_sel_1_2 = issue_sel_enc_2[1]; // @[OneHot.scala:83:30]
wire issue_sel_2_2 = issue_sel_enc_2[2]; // @[OneHot.scala:83:30]
wire issue_sel_3_2 = issue_sel_enc_2[3]; // @[OneHot.scala:83:30]
wire [1:0] issue_id_lo_7 = {issue_sel_1_2, issue_sel_0_2}; // @[OneHot.scala:21:45, :83:30]
wire [1:0] issue_id_hi_7 = {issue_sel_3_2, issue_sel_2_2}; // @[OneHot.scala:21:45, :83:30]
wire [3:0] _issue_id_T_17 = {issue_id_hi_7, issue_id_lo_7}; // @[OneHot.scala:21:45]
wire [1:0] issue_id_hi_8 = _issue_id_T_17[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] issue_id_lo_8 = _issue_id_T_17[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _issue_id_T_18 = |issue_id_hi_8; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _issue_id_T_19 = issue_id_hi_8 | issue_id_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _issue_id_T_20 = _issue_id_T_19[1]; // @[OneHot.scala:32:28]
wire [1:0] issue_id_2 = {_issue_id_T_18, _issue_id_T_20}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _global_issue_id_T_1 = {2'h0, issue_id_2}; // @[OneHot.scala:32:10]
assign global_issue_id_2 = {2'h2, _global_issue_id_T_1}; // @[ReservationStation.scala:398:{30,53}]
assign io_issue_st_rob_id_0 = global_issue_id_2; // @[ReservationStation.scala:26:7, :398:30]
wire _issue_entry_WIRE_428; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_q; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_is_config; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_286_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_286_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_286_opa_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_286_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_286_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_286_opa_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_opa_is_dst; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_issued; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_complete_on_issue; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_286_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_funct_0 = issue_entry_2_bits_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_286_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_rs2_0 = issue_entry_2_bits_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_286_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_rs1_0 = issue_entry_2_bits_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_xd_0 = issue_entry_2_bits_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_xs1_0 = issue_entry_2_bits_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_xs2_0 = issue_entry_2_bits_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_286_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_rd_0 = issue_entry_2_bits_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_286_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_inst_opcode_0 = issue_entry_2_bits_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_286_cmd_cmd_rs1; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_rs1_0 = issue_entry_2_bits_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_286_cmd_cmd_rs2; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_rs2_0 = issue_entry_2_bits_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_debug; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_debug_0 = issue_entry_2_bits_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_cease; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_cease_0 = issue_entry_2_bits_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_wfi_0 = issue_entry_2_bits_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_286_cmd_cmd_status_isa; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_isa_0 = issue_entry_2_bits_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_dprv_0 = issue_entry_2_bits_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_dv; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_dv_0 = issue_entry_2_bits_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_prv; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_prv_0 = issue_entry_2_bits_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_v; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_v_0 = issue_entry_2_bits_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_sd; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_sd_0 = issue_entry_2_bits_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_286_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_zero2_0 = issue_entry_2_bits_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_mpv_0 = issue_entry_2_bits_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_gva; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_gva_0 = issue_entry_2_bits_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_mbe_0 = issue_entry_2_bits_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_sbe_0 = issue_entry_2_bits_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_sxl_0 = issue_entry_2_bits_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_uxl_0 = issue_entry_2_bits_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_sd_rv32_0 = issue_entry_2_bits_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_286_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_zero1_0 = issue_entry_2_bits_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_tsr_0 = issue_entry_2_bits_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_tw; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_tw_0 = issue_entry_2_bits_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_tvm_0 = issue_entry_2_bits_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_mxr_0 = issue_entry_2_bits_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_sum; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_sum_0 = issue_entry_2_bits_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_mprv_0 = issue_entry_2_bits_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_xs; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_xs_0 = issue_entry_2_bits_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_fs; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_fs_0 = issue_entry_2_bits_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_mpp_0 = issue_entry_2_bits_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_286_cmd_cmd_status_vs; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_vs_0 = issue_entry_2_bits_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_spp; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_spp_0 = issue_entry_2_bits_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_mpie_0 = issue_entry_2_bits_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_ube; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_ube_0 = issue_entry_2_bits_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_spie; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_spie_0 = issue_entry_2_bits_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_upie; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_upie_0 = issue_entry_2_bits_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_mie; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_mie_0 = issue_entry_2_bits_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_hie; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_hie_0 = issue_entry_2_bits_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_sie; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_sie_0 = issue_entry_2_bits_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_cmd_status_uie; // @[Mux.scala:30:73]
assign io_issue_st_cmd_cmd_status_uie_0 = issue_entry_2_bits_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_rob_id_valid; // @[Mux.scala:30:73]
assign io_issue_st_cmd_rob_id_valid = issue_entry_2_bits_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_286_cmd_rob_id_bits; // @[Mux.scala:30:73]
assign io_issue_st_cmd_rob_id_bits = issue_entry_2_bits_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
assign io_issue_st_cmd_from_matmul_fsm_0 = issue_entry_2_bits_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_cmd_from_conv_fsm; // @[Mux.scala:30:73]
assign io_issue_st_cmd_from_conv_fsm_0 = issue_entry_2_bits_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ld_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_ex_15; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_st_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_st_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_st_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_286_deps_st_3; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_286_allocated_at; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_2_bits_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_2_bits_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_2_bits_opa_bits_start_data; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] issue_entry_2_bits_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] issue_entry_2_bits_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] issue_entry_2_bits_opa_bits_end_data; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_valid; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_1; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_2; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_3; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_4; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_5; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_6; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ld_7; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_1; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_2; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_3; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_4; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_5; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_6; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_7; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_8; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_9; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_10; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_11; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_12; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_13; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_14; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_ex_15; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_st_0; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_st_1; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_st_2; // @[Mux.scala:30:73]
wire issue_entry_2_bits_deps_st_3; // @[Mux.scala:30:73]
wire [1:0] issue_entry_2_bits_q; // @[Mux.scala:30:73]
wire issue_entry_2_bits_is_config; // @[Mux.scala:30:73]
wire issue_entry_2_bits_opa_is_dst; // @[Mux.scala:30:73]
wire issue_entry_2_bits_issued; // @[Mux.scala:30:73]
wire issue_entry_2_bits_complete_on_issue; // @[Mux.scala:30:73]
wire [31:0] issue_entry_2_bits_allocated_at; // @[Mux.scala:30:73]
wire issue_entry_2_valid; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_427; // @[Mux.scala:30:73]
assign issue_entry_2_bits_q = _issue_entry_WIRE_286_q; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_426; // @[Mux.scala:30:73]
assign issue_entry_2_bits_is_config = _issue_entry_WIRE_286_is_config; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_valid; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_valid = _issue_entry_WIRE_286_opa_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_start_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_start_is_acc_addr = _issue_entry_WIRE_286_opa_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_start_accumulate; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_start_accumulate = _issue_entry_WIRE_286_opa_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_286_opa_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_402_bits_start_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_start_norm_cmd = _issue_entry_WIRE_286_opa_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_402_bits_start_garbage; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_start_garbage = _issue_entry_WIRE_286_opa_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_start_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_start_garbage_bit = _issue_entry_WIRE_286_opa_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_402_bits_start_data; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_start_data = _issue_entry_WIRE_286_opa_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_end_is_acc_addr; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_end_is_acc_addr = _issue_entry_WIRE_286_opa_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_end_accumulate; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_end_accumulate = _issue_entry_WIRE_286_opa_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_286_opa_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_402_bits_end_norm_cmd; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_end_norm_cmd = _issue_entry_WIRE_286_opa_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_402_bits_end_garbage; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_end_garbage = _issue_entry_WIRE_286_opa_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_end_garbage_bit; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_end_garbage_bit = _issue_entry_WIRE_286_opa_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_402_bits_end_data; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_end_data = _issue_entry_WIRE_286_opa_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_402_bits_wraps_around; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_bits_wraps_around = _issue_entry_WIRE_286_opa_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_401; // @[Mux.scala:30:73]
assign issue_entry_2_bits_opa_is_dst = _issue_entry_WIRE_286_opa_is_dst; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_376; // @[Mux.scala:30:73]
assign issue_entry_2_bits_issued = _issue_entry_WIRE_286_issued; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_375; // @[Mux.scala:30:73]
assign issue_entry_2_bits_complete_on_issue = _issue_entry_WIRE_286_complete_on_issue; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_319_cmd_inst_funct; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_funct = _issue_entry_WIRE_286_cmd_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_319_cmd_inst_rs2; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_rs2 = _issue_entry_WIRE_286_cmd_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_319_cmd_inst_rs1; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_rs1 = _issue_entry_WIRE_286_cmd_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_inst_xd; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_xd = _issue_entry_WIRE_286_cmd_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_inst_xs1; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_xs1 = _issue_entry_WIRE_286_cmd_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_inst_xs2; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_xs2 = _issue_entry_WIRE_286_cmd_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_319_cmd_inst_rd; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_rd = _issue_entry_WIRE_286_cmd_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_319_cmd_inst_opcode; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_inst_opcode = _issue_entry_WIRE_286_cmd_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_319_cmd_rs1; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_rs1 = _issue_entry_WIRE_286_cmd_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_319_cmd_rs2; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_rs2 = _issue_entry_WIRE_286_cmd_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_debug; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_debug = _issue_entry_WIRE_286_cmd_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_cease; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_cease = _issue_entry_WIRE_286_cmd_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_wfi; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_wfi = _issue_entry_WIRE_286_cmd_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_319_cmd_status_isa; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_isa = _issue_entry_WIRE_286_cmd_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_dprv; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_dprv = _issue_entry_WIRE_286_cmd_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_dv; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_dv = _issue_entry_WIRE_286_cmd_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_prv; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_prv = _issue_entry_WIRE_286_cmd_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_v; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_v = _issue_entry_WIRE_286_cmd_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_sd; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_sd = _issue_entry_WIRE_286_cmd_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_319_cmd_status_zero2; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_zero2 = _issue_entry_WIRE_286_cmd_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_mpv; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_mpv = _issue_entry_WIRE_286_cmd_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_gva; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_gva = _issue_entry_WIRE_286_cmd_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_mbe; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_mbe = _issue_entry_WIRE_286_cmd_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_sbe; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_sbe = _issue_entry_WIRE_286_cmd_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_sxl; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_sxl = _issue_entry_WIRE_286_cmd_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_uxl; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_uxl = _issue_entry_WIRE_286_cmd_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_sd_rv32; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_286_cmd_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_319_cmd_status_zero1; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_zero1 = _issue_entry_WIRE_286_cmd_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_tsr; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_tsr = _issue_entry_WIRE_286_cmd_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_tw; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_tw = _issue_entry_WIRE_286_cmd_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_tvm; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_tvm = _issue_entry_WIRE_286_cmd_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_mxr; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_mxr = _issue_entry_WIRE_286_cmd_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_sum; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_sum = _issue_entry_WIRE_286_cmd_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_mprv; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_mprv = _issue_entry_WIRE_286_cmd_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_xs; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_xs = _issue_entry_WIRE_286_cmd_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_fs; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_fs = _issue_entry_WIRE_286_cmd_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_mpp; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_mpp = _issue_entry_WIRE_286_cmd_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_319_cmd_status_vs; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_vs = _issue_entry_WIRE_286_cmd_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_spp; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_spp = _issue_entry_WIRE_286_cmd_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_mpie; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_mpie = _issue_entry_WIRE_286_cmd_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_ube; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_ube = _issue_entry_WIRE_286_cmd_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_spie; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_spie = _issue_entry_WIRE_286_cmd_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_upie; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_upie = _issue_entry_WIRE_286_cmd_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_mie; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_mie = _issue_entry_WIRE_286_cmd_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_hie; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_hie = _issue_entry_WIRE_286_cmd_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_sie; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_sie = _issue_entry_WIRE_286_cmd_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_cmd_status_uie; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_cmd_status_uie = _issue_entry_WIRE_286_cmd_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_rob_id_valid; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_rob_id_valid = _issue_entry_WIRE_286_cmd_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_319_rob_id_bits; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_rob_id_bits = _issue_entry_WIRE_286_cmd_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_from_matmul_fsm; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_from_matmul_fsm = _issue_entry_WIRE_286_cmd_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_319_from_conv_fsm; // @[Mux.scala:30:73]
assign issue_entry_2_bits_cmd_from_conv_fsm = _issue_entry_WIRE_286_cmd_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_0; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_0 = _issue_entry_WIRE_286_deps_ld_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_1; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_1 = _issue_entry_WIRE_286_deps_ld_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_2; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_2 = _issue_entry_WIRE_286_deps_ld_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_3; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_3 = _issue_entry_WIRE_286_deps_ld_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_4; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_4 = _issue_entry_WIRE_286_deps_ld_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_5; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_5 = _issue_entry_WIRE_286_deps_ld_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_6; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_6 = _issue_entry_WIRE_286_deps_ld_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_310_7; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ld_7 = _issue_entry_WIRE_286_deps_ld_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_0; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_0 = _issue_entry_WIRE_286_deps_ex_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_1; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_1 = _issue_entry_WIRE_286_deps_ex_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_2; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_2 = _issue_entry_WIRE_286_deps_ex_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_3; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_3 = _issue_entry_WIRE_286_deps_ex_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_4; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_4 = _issue_entry_WIRE_286_deps_ex_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_5; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_5 = _issue_entry_WIRE_286_deps_ex_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_6; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_6 = _issue_entry_WIRE_286_deps_ex_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_7; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_7 = _issue_entry_WIRE_286_deps_ex_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_8; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_8 = _issue_entry_WIRE_286_deps_ex_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_9; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_9 = _issue_entry_WIRE_286_deps_ex_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_10; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_10 = _issue_entry_WIRE_286_deps_ex_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_11; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_11 = _issue_entry_WIRE_286_deps_ex_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_12; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_12 = _issue_entry_WIRE_286_deps_ex_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_13; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_13 = _issue_entry_WIRE_286_deps_ex_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_14; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_14 = _issue_entry_WIRE_286_deps_ex_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_293_15; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_ex_15 = _issue_entry_WIRE_286_deps_ex_15; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_288_0; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_st_0 = _issue_entry_WIRE_286_deps_st_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_288_1; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_st_1 = _issue_entry_WIRE_286_deps_st_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_288_2; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_st_2 = _issue_entry_WIRE_286_deps_st_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_288_3; // @[Mux.scala:30:73]
assign issue_entry_2_bits_deps_st_3 = _issue_entry_WIRE_286_deps_st_3; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_287; // @[Mux.scala:30:73]
assign issue_entry_2_bits_allocated_at = _issue_entry_WIRE_286_allocated_at; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_5524 = issue_sel_0_2 ? entries_st_0_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5525 = issue_sel_1_2 ? entries_st_1_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5526 = issue_sel_2_2 ? entries_st_2_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5527 = issue_sel_3_2 ? entries_st_3_bits_allocated_at : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5528 = _issue_entry_T_5524 | _issue_entry_T_5525; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_5529 = _issue_entry_T_5528 | _issue_entry_T_5526; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_5530 = _issue_entry_T_5529 | _issue_entry_T_5527; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_287 = _issue_entry_T_5530; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_allocated_at = _issue_entry_WIRE_287; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_289; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_st_0 = _issue_entry_WIRE_288_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_290; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_st_1 = _issue_entry_WIRE_288_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_291; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_st_2 = _issue_entry_WIRE_288_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_292; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_st_3 = _issue_entry_WIRE_288_3; // @[Mux.scala:30:73]
wire _issue_entry_T_5531 = issue_sel_0_2 & entries_st_0_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5532 = issue_sel_1_2 & entries_st_1_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5533 = issue_sel_2_2 & entries_st_2_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5534 = issue_sel_3_2 & entries_st_3_bits_deps_st_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5535 = _issue_entry_T_5531 | _issue_entry_T_5532; // @[Mux.scala:30:73]
wire _issue_entry_T_5536 = _issue_entry_T_5535 | _issue_entry_T_5533; // @[Mux.scala:30:73]
wire _issue_entry_T_5537 = _issue_entry_T_5536 | _issue_entry_T_5534; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_289 = _issue_entry_T_5537; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_288_0 = _issue_entry_WIRE_289; // @[Mux.scala:30:73]
wire _issue_entry_T_5538 = issue_sel_0_2 & entries_st_0_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5539 = issue_sel_1_2 & entries_st_1_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5540 = issue_sel_2_2 & entries_st_2_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5541 = issue_sel_3_2 & entries_st_3_bits_deps_st_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5542 = _issue_entry_T_5538 | _issue_entry_T_5539; // @[Mux.scala:30:73]
wire _issue_entry_T_5543 = _issue_entry_T_5542 | _issue_entry_T_5540; // @[Mux.scala:30:73]
wire _issue_entry_T_5544 = _issue_entry_T_5543 | _issue_entry_T_5541; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_290 = _issue_entry_T_5544; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_288_1 = _issue_entry_WIRE_290; // @[Mux.scala:30:73]
wire _issue_entry_T_5545 = issue_sel_0_2 & entries_st_0_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5546 = issue_sel_1_2 & entries_st_1_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5547 = issue_sel_2_2 & entries_st_2_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5548 = issue_sel_3_2 & entries_st_3_bits_deps_st_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5549 = _issue_entry_T_5545 | _issue_entry_T_5546; // @[Mux.scala:30:73]
wire _issue_entry_T_5550 = _issue_entry_T_5549 | _issue_entry_T_5547; // @[Mux.scala:30:73]
wire _issue_entry_T_5551 = _issue_entry_T_5550 | _issue_entry_T_5548; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_291 = _issue_entry_T_5551; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_288_2 = _issue_entry_WIRE_291; // @[Mux.scala:30:73]
wire _issue_entry_T_5552 = issue_sel_0_2 & entries_st_0_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5553 = issue_sel_1_2 & entries_st_1_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5554 = issue_sel_2_2 & entries_st_2_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5555 = issue_sel_3_2 & entries_st_3_bits_deps_st_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5556 = _issue_entry_T_5552 | _issue_entry_T_5553; // @[Mux.scala:30:73]
wire _issue_entry_T_5557 = _issue_entry_T_5556 | _issue_entry_T_5554; // @[Mux.scala:30:73]
wire _issue_entry_T_5558 = _issue_entry_T_5557 | _issue_entry_T_5555; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_292 = _issue_entry_T_5558; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_288_3 = _issue_entry_WIRE_292; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_294; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_0 = _issue_entry_WIRE_293_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_295; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_1 = _issue_entry_WIRE_293_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_296; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_2 = _issue_entry_WIRE_293_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_297; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_3 = _issue_entry_WIRE_293_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_298; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_4 = _issue_entry_WIRE_293_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_299; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_5 = _issue_entry_WIRE_293_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_300; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_6 = _issue_entry_WIRE_293_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_301; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_7 = _issue_entry_WIRE_293_7; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_302; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_8 = _issue_entry_WIRE_293_8; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_303; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_9 = _issue_entry_WIRE_293_9; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_304; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_10 = _issue_entry_WIRE_293_10; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_305; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_11 = _issue_entry_WIRE_293_11; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_306; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_12 = _issue_entry_WIRE_293_12; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_307; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_13 = _issue_entry_WIRE_293_13; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_308; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_14 = _issue_entry_WIRE_293_14; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_309; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ex_15 = _issue_entry_WIRE_293_15; // @[Mux.scala:30:73]
wire _issue_entry_T_5559 = issue_sel_0_2 & entries_st_0_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5560 = issue_sel_1_2 & entries_st_1_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5561 = issue_sel_2_2 & entries_st_2_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5562 = issue_sel_3_2 & entries_st_3_bits_deps_ex_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5563 = _issue_entry_T_5559 | _issue_entry_T_5560; // @[Mux.scala:30:73]
wire _issue_entry_T_5564 = _issue_entry_T_5563 | _issue_entry_T_5561; // @[Mux.scala:30:73]
wire _issue_entry_T_5565 = _issue_entry_T_5564 | _issue_entry_T_5562; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_294 = _issue_entry_T_5565; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_0 = _issue_entry_WIRE_294; // @[Mux.scala:30:73]
wire _issue_entry_T_5566 = issue_sel_0_2 & entries_st_0_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5567 = issue_sel_1_2 & entries_st_1_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5568 = issue_sel_2_2 & entries_st_2_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5569 = issue_sel_3_2 & entries_st_3_bits_deps_ex_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5570 = _issue_entry_T_5566 | _issue_entry_T_5567; // @[Mux.scala:30:73]
wire _issue_entry_T_5571 = _issue_entry_T_5570 | _issue_entry_T_5568; // @[Mux.scala:30:73]
wire _issue_entry_T_5572 = _issue_entry_T_5571 | _issue_entry_T_5569; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_295 = _issue_entry_T_5572; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_1 = _issue_entry_WIRE_295; // @[Mux.scala:30:73]
wire _issue_entry_T_5573 = issue_sel_0_2 & entries_st_0_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5574 = issue_sel_1_2 & entries_st_1_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5575 = issue_sel_2_2 & entries_st_2_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5576 = issue_sel_3_2 & entries_st_3_bits_deps_ex_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5577 = _issue_entry_T_5573 | _issue_entry_T_5574; // @[Mux.scala:30:73]
wire _issue_entry_T_5578 = _issue_entry_T_5577 | _issue_entry_T_5575; // @[Mux.scala:30:73]
wire _issue_entry_T_5579 = _issue_entry_T_5578 | _issue_entry_T_5576; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_296 = _issue_entry_T_5579; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_2 = _issue_entry_WIRE_296; // @[Mux.scala:30:73]
wire _issue_entry_T_5580 = issue_sel_0_2 & entries_st_0_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5581 = issue_sel_1_2 & entries_st_1_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5582 = issue_sel_2_2 & entries_st_2_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5583 = issue_sel_3_2 & entries_st_3_bits_deps_ex_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5584 = _issue_entry_T_5580 | _issue_entry_T_5581; // @[Mux.scala:30:73]
wire _issue_entry_T_5585 = _issue_entry_T_5584 | _issue_entry_T_5582; // @[Mux.scala:30:73]
wire _issue_entry_T_5586 = _issue_entry_T_5585 | _issue_entry_T_5583; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_297 = _issue_entry_T_5586; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_3 = _issue_entry_WIRE_297; // @[Mux.scala:30:73]
wire _issue_entry_T_5587 = issue_sel_0_2 & entries_st_0_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5588 = issue_sel_1_2 & entries_st_1_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5589 = issue_sel_2_2 & entries_st_2_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5590 = issue_sel_3_2 & entries_st_3_bits_deps_ex_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5591 = _issue_entry_T_5587 | _issue_entry_T_5588; // @[Mux.scala:30:73]
wire _issue_entry_T_5592 = _issue_entry_T_5591 | _issue_entry_T_5589; // @[Mux.scala:30:73]
wire _issue_entry_T_5593 = _issue_entry_T_5592 | _issue_entry_T_5590; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_298 = _issue_entry_T_5593; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_4 = _issue_entry_WIRE_298; // @[Mux.scala:30:73]
wire _issue_entry_T_5594 = issue_sel_0_2 & entries_st_0_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5595 = issue_sel_1_2 & entries_st_1_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5596 = issue_sel_2_2 & entries_st_2_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5597 = issue_sel_3_2 & entries_st_3_bits_deps_ex_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5598 = _issue_entry_T_5594 | _issue_entry_T_5595; // @[Mux.scala:30:73]
wire _issue_entry_T_5599 = _issue_entry_T_5598 | _issue_entry_T_5596; // @[Mux.scala:30:73]
wire _issue_entry_T_5600 = _issue_entry_T_5599 | _issue_entry_T_5597; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_299 = _issue_entry_T_5600; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_5 = _issue_entry_WIRE_299; // @[Mux.scala:30:73]
wire _issue_entry_T_5601 = issue_sel_0_2 & entries_st_0_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5602 = issue_sel_1_2 & entries_st_1_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5603 = issue_sel_2_2 & entries_st_2_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5604 = issue_sel_3_2 & entries_st_3_bits_deps_ex_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5605 = _issue_entry_T_5601 | _issue_entry_T_5602; // @[Mux.scala:30:73]
wire _issue_entry_T_5606 = _issue_entry_T_5605 | _issue_entry_T_5603; // @[Mux.scala:30:73]
wire _issue_entry_T_5607 = _issue_entry_T_5606 | _issue_entry_T_5604; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_300 = _issue_entry_T_5607; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_6 = _issue_entry_WIRE_300; // @[Mux.scala:30:73]
wire _issue_entry_T_5608 = issue_sel_0_2 & entries_st_0_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5609 = issue_sel_1_2 & entries_st_1_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5610 = issue_sel_2_2 & entries_st_2_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5611 = issue_sel_3_2 & entries_st_3_bits_deps_ex_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5612 = _issue_entry_T_5608 | _issue_entry_T_5609; // @[Mux.scala:30:73]
wire _issue_entry_T_5613 = _issue_entry_T_5612 | _issue_entry_T_5610; // @[Mux.scala:30:73]
wire _issue_entry_T_5614 = _issue_entry_T_5613 | _issue_entry_T_5611; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_301 = _issue_entry_T_5614; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_7 = _issue_entry_WIRE_301; // @[Mux.scala:30:73]
wire _issue_entry_T_5615 = issue_sel_0_2 & entries_st_0_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_5616 = issue_sel_1_2 & entries_st_1_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_5617 = issue_sel_2_2 & entries_st_2_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_5618 = issue_sel_3_2 & entries_st_3_bits_deps_ex_8; // @[OneHot.scala:83:30]
wire _issue_entry_T_5619 = _issue_entry_T_5615 | _issue_entry_T_5616; // @[Mux.scala:30:73]
wire _issue_entry_T_5620 = _issue_entry_T_5619 | _issue_entry_T_5617; // @[Mux.scala:30:73]
wire _issue_entry_T_5621 = _issue_entry_T_5620 | _issue_entry_T_5618; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_302 = _issue_entry_T_5621; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_8 = _issue_entry_WIRE_302; // @[Mux.scala:30:73]
wire _issue_entry_T_5622 = issue_sel_0_2 & entries_st_0_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_5623 = issue_sel_1_2 & entries_st_1_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_5624 = issue_sel_2_2 & entries_st_2_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_5625 = issue_sel_3_2 & entries_st_3_bits_deps_ex_9; // @[OneHot.scala:83:30]
wire _issue_entry_T_5626 = _issue_entry_T_5622 | _issue_entry_T_5623; // @[Mux.scala:30:73]
wire _issue_entry_T_5627 = _issue_entry_T_5626 | _issue_entry_T_5624; // @[Mux.scala:30:73]
wire _issue_entry_T_5628 = _issue_entry_T_5627 | _issue_entry_T_5625; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_303 = _issue_entry_T_5628; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_9 = _issue_entry_WIRE_303; // @[Mux.scala:30:73]
wire _issue_entry_T_5629 = issue_sel_0_2 & entries_st_0_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_5630 = issue_sel_1_2 & entries_st_1_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_5631 = issue_sel_2_2 & entries_st_2_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_5632 = issue_sel_3_2 & entries_st_3_bits_deps_ex_10; // @[OneHot.scala:83:30]
wire _issue_entry_T_5633 = _issue_entry_T_5629 | _issue_entry_T_5630; // @[Mux.scala:30:73]
wire _issue_entry_T_5634 = _issue_entry_T_5633 | _issue_entry_T_5631; // @[Mux.scala:30:73]
wire _issue_entry_T_5635 = _issue_entry_T_5634 | _issue_entry_T_5632; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_304 = _issue_entry_T_5635; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_10 = _issue_entry_WIRE_304; // @[Mux.scala:30:73]
wire _issue_entry_T_5636 = issue_sel_0_2 & entries_st_0_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_5637 = issue_sel_1_2 & entries_st_1_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_5638 = issue_sel_2_2 & entries_st_2_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_5639 = issue_sel_3_2 & entries_st_3_bits_deps_ex_11; // @[OneHot.scala:83:30]
wire _issue_entry_T_5640 = _issue_entry_T_5636 | _issue_entry_T_5637; // @[Mux.scala:30:73]
wire _issue_entry_T_5641 = _issue_entry_T_5640 | _issue_entry_T_5638; // @[Mux.scala:30:73]
wire _issue_entry_T_5642 = _issue_entry_T_5641 | _issue_entry_T_5639; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_305 = _issue_entry_T_5642; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_11 = _issue_entry_WIRE_305; // @[Mux.scala:30:73]
wire _issue_entry_T_5643 = issue_sel_0_2 & entries_st_0_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_5644 = issue_sel_1_2 & entries_st_1_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_5645 = issue_sel_2_2 & entries_st_2_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_5646 = issue_sel_3_2 & entries_st_3_bits_deps_ex_12; // @[OneHot.scala:83:30]
wire _issue_entry_T_5647 = _issue_entry_T_5643 | _issue_entry_T_5644; // @[Mux.scala:30:73]
wire _issue_entry_T_5648 = _issue_entry_T_5647 | _issue_entry_T_5645; // @[Mux.scala:30:73]
wire _issue_entry_T_5649 = _issue_entry_T_5648 | _issue_entry_T_5646; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_306 = _issue_entry_T_5649; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_12 = _issue_entry_WIRE_306; // @[Mux.scala:30:73]
wire _issue_entry_T_5650 = issue_sel_0_2 & entries_st_0_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_5651 = issue_sel_1_2 & entries_st_1_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_5652 = issue_sel_2_2 & entries_st_2_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_5653 = issue_sel_3_2 & entries_st_3_bits_deps_ex_13; // @[OneHot.scala:83:30]
wire _issue_entry_T_5654 = _issue_entry_T_5650 | _issue_entry_T_5651; // @[Mux.scala:30:73]
wire _issue_entry_T_5655 = _issue_entry_T_5654 | _issue_entry_T_5652; // @[Mux.scala:30:73]
wire _issue_entry_T_5656 = _issue_entry_T_5655 | _issue_entry_T_5653; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_307 = _issue_entry_T_5656; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_13 = _issue_entry_WIRE_307; // @[Mux.scala:30:73]
wire _issue_entry_T_5657 = issue_sel_0_2 & entries_st_0_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_5658 = issue_sel_1_2 & entries_st_1_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_5659 = issue_sel_2_2 & entries_st_2_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_5660 = issue_sel_3_2 & entries_st_3_bits_deps_ex_14; // @[OneHot.scala:83:30]
wire _issue_entry_T_5661 = _issue_entry_T_5657 | _issue_entry_T_5658; // @[Mux.scala:30:73]
wire _issue_entry_T_5662 = _issue_entry_T_5661 | _issue_entry_T_5659; // @[Mux.scala:30:73]
wire _issue_entry_T_5663 = _issue_entry_T_5662 | _issue_entry_T_5660; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_308 = _issue_entry_T_5663; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_14 = _issue_entry_WIRE_308; // @[Mux.scala:30:73]
wire _issue_entry_T_5664 = issue_sel_0_2 & entries_st_0_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_5665 = issue_sel_1_2 & entries_st_1_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_5666 = issue_sel_2_2 & entries_st_2_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_5667 = issue_sel_3_2 & entries_st_3_bits_deps_ex_15; // @[OneHot.scala:83:30]
wire _issue_entry_T_5668 = _issue_entry_T_5664 | _issue_entry_T_5665; // @[Mux.scala:30:73]
wire _issue_entry_T_5669 = _issue_entry_T_5668 | _issue_entry_T_5666; // @[Mux.scala:30:73]
wire _issue_entry_T_5670 = _issue_entry_T_5669 | _issue_entry_T_5667; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_309 = _issue_entry_T_5670; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_293_15 = _issue_entry_WIRE_309; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_311; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_0 = _issue_entry_WIRE_310_0; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_312; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_1 = _issue_entry_WIRE_310_1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_313; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_2 = _issue_entry_WIRE_310_2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_314; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_3 = _issue_entry_WIRE_310_3; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_315; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_4 = _issue_entry_WIRE_310_4; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_316; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_5 = _issue_entry_WIRE_310_5; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_317; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_6 = _issue_entry_WIRE_310_6; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_318; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_deps_ld_7 = _issue_entry_WIRE_310_7; // @[Mux.scala:30:73]
wire _issue_entry_T_5671 = issue_sel_0_2 & entries_st_0_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5672 = issue_sel_1_2 & entries_st_1_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5673 = issue_sel_2_2 & entries_st_2_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5674 = issue_sel_3_2 & entries_st_3_bits_deps_ld_0; // @[OneHot.scala:83:30]
wire _issue_entry_T_5675 = _issue_entry_T_5671 | _issue_entry_T_5672; // @[Mux.scala:30:73]
wire _issue_entry_T_5676 = _issue_entry_T_5675 | _issue_entry_T_5673; // @[Mux.scala:30:73]
wire _issue_entry_T_5677 = _issue_entry_T_5676 | _issue_entry_T_5674; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_311 = _issue_entry_T_5677; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_0 = _issue_entry_WIRE_311; // @[Mux.scala:30:73]
wire _issue_entry_T_5678 = issue_sel_0_2 & entries_st_0_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5679 = issue_sel_1_2 & entries_st_1_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5680 = issue_sel_2_2 & entries_st_2_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5681 = issue_sel_3_2 & entries_st_3_bits_deps_ld_1; // @[OneHot.scala:83:30]
wire _issue_entry_T_5682 = _issue_entry_T_5678 | _issue_entry_T_5679; // @[Mux.scala:30:73]
wire _issue_entry_T_5683 = _issue_entry_T_5682 | _issue_entry_T_5680; // @[Mux.scala:30:73]
wire _issue_entry_T_5684 = _issue_entry_T_5683 | _issue_entry_T_5681; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_312 = _issue_entry_T_5684; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_1 = _issue_entry_WIRE_312; // @[Mux.scala:30:73]
wire _issue_entry_T_5685 = issue_sel_0_2 & entries_st_0_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5686 = issue_sel_1_2 & entries_st_1_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5687 = issue_sel_2_2 & entries_st_2_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5688 = issue_sel_3_2 & entries_st_3_bits_deps_ld_2; // @[OneHot.scala:83:30]
wire _issue_entry_T_5689 = _issue_entry_T_5685 | _issue_entry_T_5686; // @[Mux.scala:30:73]
wire _issue_entry_T_5690 = _issue_entry_T_5689 | _issue_entry_T_5687; // @[Mux.scala:30:73]
wire _issue_entry_T_5691 = _issue_entry_T_5690 | _issue_entry_T_5688; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_313 = _issue_entry_T_5691; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_2 = _issue_entry_WIRE_313; // @[Mux.scala:30:73]
wire _issue_entry_T_5692 = issue_sel_0_2 & entries_st_0_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5693 = issue_sel_1_2 & entries_st_1_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5694 = issue_sel_2_2 & entries_st_2_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5695 = issue_sel_3_2 & entries_st_3_bits_deps_ld_3; // @[OneHot.scala:83:30]
wire _issue_entry_T_5696 = _issue_entry_T_5692 | _issue_entry_T_5693; // @[Mux.scala:30:73]
wire _issue_entry_T_5697 = _issue_entry_T_5696 | _issue_entry_T_5694; // @[Mux.scala:30:73]
wire _issue_entry_T_5698 = _issue_entry_T_5697 | _issue_entry_T_5695; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_314 = _issue_entry_T_5698; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_3 = _issue_entry_WIRE_314; // @[Mux.scala:30:73]
wire _issue_entry_T_5699 = issue_sel_0_2 & entries_st_0_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5700 = issue_sel_1_2 & entries_st_1_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5701 = issue_sel_2_2 & entries_st_2_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5702 = issue_sel_3_2 & entries_st_3_bits_deps_ld_4; // @[OneHot.scala:83:30]
wire _issue_entry_T_5703 = _issue_entry_T_5699 | _issue_entry_T_5700; // @[Mux.scala:30:73]
wire _issue_entry_T_5704 = _issue_entry_T_5703 | _issue_entry_T_5701; // @[Mux.scala:30:73]
wire _issue_entry_T_5705 = _issue_entry_T_5704 | _issue_entry_T_5702; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_315 = _issue_entry_T_5705; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_4 = _issue_entry_WIRE_315; // @[Mux.scala:30:73]
wire _issue_entry_T_5706 = issue_sel_0_2 & entries_st_0_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5707 = issue_sel_1_2 & entries_st_1_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5708 = issue_sel_2_2 & entries_st_2_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5709 = issue_sel_3_2 & entries_st_3_bits_deps_ld_5; // @[OneHot.scala:83:30]
wire _issue_entry_T_5710 = _issue_entry_T_5706 | _issue_entry_T_5707; // @[Mux.scala:30:73]
wire _issue_entry_T_5711 = _issue_entry_T_5710 | _issue_entry_T_5708; // @[Mux.scala:30:73]
wire _issue_entry_T_5712 = _issue_entry_T_5711 | _issue_entry_T_5709; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_316 = _issue_entry_T_5712; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_5 = _issue_entry_WIRE_316; // @[Mux.scala:30:73]
wire _issue_entry_T_5713 = issue_sel_0_2 & entries_st_0_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5714 = issue_sel_1_2 & entries_st_1_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5715 = issue_sel_2_2 & entries_st_2_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5716 = issue_sel_3_2 & entries_st_3_bits_deps_ld_6; // @[OneHot.scala:83:30]
wire _issue_entry_T_5717 = _issue_entry_T_5713 | _issue_entry_T_5714; // @[Mux.scala:30:73]
wire _issue_entry_T_5718 = _issue_entry_T_5717 | _issue_entry_T_5715; // @[Mux.scala:30:73]
wire _issue_entry_T_5719 = _issue_entry_T_5718 | _issue_entry_T_5716; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_317 = _issue_entry_T_5719; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_6 = _issue_entry_WIRE_317; // @[Mux.scala:30:73]
wire _issue_entry_T_5720 = issue_sel_0_2 & entries_st_0_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5721 = issue_sel_1_2 & entries_st_1_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5722 = issue_sel_2_2 & entries_st_2_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5723 = issue_sel_3_2 & entries_st_3_bits_deps_ld_7; // @[OneHot.scala:83:30]
wire _issue_entry_T_5724 = _issue_entry_T_5720 | _issue_entry_T_5721; // @[Mux.scala:30:73]
wire _issue_entry_T_5725 = _issue_entry_T_5724 | _issue_entry_T_5722; // @[Mux.scala:30:73]
wire _issue_entry_T_5726 = _issue_entry_T_5725 | _issue_entry_T_5723; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_318 = _issue_entry_T_5726; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_310_7 = _issue_entry_WIRE_318; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_325_inst_funct; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_funct = _issue_entry_WIRE_319_cmd_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_325_inst_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_rs2 = _issue_entry_WIRE_319_cmd_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_325_inst_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_rs1 = _issue_entry_WIRE_319_cmd_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_inst_xd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_xd = _issue_entry_WIRE_319_cmd_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_inst_xs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_xs1 = _issue_entry_WIRE_319_cmd_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_inst_xs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_xs2 = _issue_entry_WIRE_319_cmd_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_325_inst_rd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_rd = _issue_entry_WIRE_319_cmd_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_325_inst_opcode; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_inst_opcode = _issue_entry_WIRE_319_cmd_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_325_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_rs1 = _issue_entry_WIRE_319_cmd_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_325_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_rs2 = _issue_entry_WIRE_319_cmd_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_debug; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_debug = _issue_entry_WIRE_319_cmd_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_cease; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_cease = _issue_entry_WIRE_319_cmd_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_wfi; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_wfi = _issue_entry_WIRE_319_cmd_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_325_status_isa; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_isa = _issue_entry_WIRE_319_cmd_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_dprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_dprv = _issue_entry_WIRE_319_cmd_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_dv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_dv = _issue_entry_WIRE_319_cmd_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_prv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_prv = _issue_entry_WIRE_319_cmd_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_v; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_v = _issue_entry_WIRE_319_cmd_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_sd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_sd = _issue_entry_WIRE_319_cmd_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_325_status_zero2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_zero2 = _issue_entry_WIRE_319_cmd_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_mpv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_mpv = _issue_entry_WIRE_319_cmd_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_gva; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_gva = _issue_entry_WIRE_319_cmd_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_mbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_mbe = _issue_entry_WIRE_319_cmd_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_sbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_sbe = _issue_entry_WIRE_319_cmd_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_sxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_sxl = _issue_entry_WIRE_319_cmd_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_uxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_uxl = _issue_entry_WIRE_319_cmd_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_sd_rv32; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_sd_rv32 = _issue_entry_WIRE_319_cmd_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_325_status_zero1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_zero1 = _issue_entry_WIRE_319_cmd_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_tsr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_tsr = _issue_entry_WIRE_319_cmd_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_tw; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_tw = _issue_entry_WIRE_319_cmd_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_tvm; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_tvm = _issue_entry_WIRE_319_cmd_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_mxr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_mxr = _issue_entry_WIRE_319_cmd_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_sum; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_sum = _issue_entry_WIRE_319_cmd_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_mprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_mprv = _issue_entry_WIRE_319_cmd_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_xs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_xs = _issue_entry_WIRE_319_cmd_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_fs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_fs = _issue_entry_WIRE_319_cmd_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_mpp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_mpp = _issue_entry_WIRE_319_cmd_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_325_status_vs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_vs = _issue_entry_WIRE_319_cmd_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_spp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_spp = _issue_entry_WIRE_319_cmd_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_mpie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_mpie = _issue_entry_WIRE_319_cmd_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_ube; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_ube = _issue_entry_WIRE_319_cmd_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_spie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_spie = _issue_entry_WIRE_319_cmd_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_upie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_upie = _issue_entry_WIRE_319_cmd_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_mie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_mie = _issue_entry_WIRE_319_cmd_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_hie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_hie = _issue_entry_WIRE_319_cmd_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_sie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_sie = _issue_entry_WIRE_319_cmd_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_325_status_uie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_cmd_status_uie = _issue_entry_WIRE_319_cmd_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_322_valid; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_rob_id_valid = _issue_entry_WIRE_319_rob_id_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_322_bits; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_rob_id_bits = _issue_entry_WIRE_319_rob_id_bits; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_321; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_from_matmul_fsm = _issue_entry_WIRE_319_from_matmul_fsm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_320; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_cmd_from_conv_fsm = _issue_entry_WIRE_319_from_conv_fsm; // @[Mux.scala:30:73]
wire _issue_entry_T_5727 = issue_sel_0_2 & entries_st_0_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5728 = issue_sel_1_2 & entries_st_1_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5729 = issue_sel_2_2 & entries_st_2_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5730 = issue_sel_3_2 & entries_st_3_bits_cmd_from_conv_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5731 = _issue_entry_T_5727 | _issue_entry_T_5728; // @[Mux.scala:30:73]
wire _issue_entry_T_5732 = _issue_entry_T_5731 | _issue_entry_T_5729; // @[Mux.scala:30:73]
wire _issue_entry_T_5733 = _issue_entry_T_5732 | _issue_entry_T_5730; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_320 = _issue_entry_T_5733; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_from_conv_fsm = _issue_entry_WIRE_320; // @[Mux.scala:30:73]
wire _issue_entry_T_5734 = issue_sel_0_2 & entries_st_0_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5735 = issue_sel_1_2 & entries_st_1_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5736 = issue_sel_2_2 & entries_st_2_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5737 = issue_sel_3_2 & entries_st_3_bits_cmd_from_matmul_fsm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5738 = _issue_entry_T_5734 | _issue_entry_T_5735; // @[Mux.scala:30:73]
wire _issue_entry_T_5739 = _issue_entry_T_5738 | _issue_entry_T_5736; // @[Mux.scala:30:73]
wire _issue_entry_T_5740 = _issue_entry_T_5739 | _issue_entry_T_5737; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_321 = _issue_entry_T_5740; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_from_matmul_fsm = _issue_entry_WIRE_321; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_324; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_rob_id_valid = _issue_entry_WIRE_322_valid; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_WIRE_323; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_rob_id_bits = _issue_entry_WIRE_322_bits; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_5741 = issue_sel_0_2 ? entries_st_0_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_5742 = issue_sel_1_2 ? entries_st_1_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_5743 = issue_sel_2_2 ? entries_st_2_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_5744 = issue_sel_3_2 ? entries_st_3_bits_cmd_rob_id_bits : 6'h0; // @[OneHot.scala:83:30]
wire [5:0] _issue_entry_T_5745 = _issue_entry_T_5741 | _issue_entry_T_5742; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_5746 = _issue_entry_T_5745 | _issue_entry_T_5743; // @[Mux.scala:30:73]
wire [5:0] _issue_entry_T_5747 = _issue_entry_T_5746 | _issue_entry_T_5744; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_323 = _issue_entry_T_5747; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_322_bits = _issue_entry_WIRE_323; // @[Mux.scala:30:73]
wire _issue_entry_T_5748 = issue_sel_0_2 & entries_st_0_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5749 = issue_sel_1_2 & entries_st_1_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5750 = issue_sel_2_2 & entries_st_2_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5751 = issue_sel_3_2 & entries_st_3_bits_cmd_rob_id_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_5752 = _issue_entry_T_5748 | _issue_entry_T_5749; // @[Mux.scala:30:73]
wire _issue_entry_T_5753 = _issue_entry_T_5752 | _issue_entry_T_5750; // @[Mux.scala:30:73]
wire _issue_entry_T_5754 = _issue_entry_T_5753 | _issue_entry_T_5751; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_324 = _issue_entry_T_5754; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_322_valid = _issue_entry_WIRE_324; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_366_funct; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_funct = _issue_entry_WIRE_325_inst_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_366_rs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_rs2 = _issue_entry_WIRE_325_inst_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_366_rs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_rs1 = _issue_entry_WIRE_325_inst_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_366_xd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_xd = _issue_entry_WIRE_325_inst_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_366_xs1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_xs1 = _issue_entry_WIRE_325_inst_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_366_xs2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_xs2 = _issue_entry_WIRE_325_inst_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_366_rd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_rd = _issue_entry_WIRE_325_inst_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_366_opcode; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_inst_opcode = _issue_entry_WIRE_325_inst_opcode; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_365; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_rs1 = _issue_entry_WIRE_325_rs1; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_WIRE_364; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_rs2 = _issue_entry_WIRE_325_rs2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_debug; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_debug = _issue_entry_WIRE_325_status_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_cease; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_cease = _issue_entry_WIRE_325_status_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_wfi; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_wfi = _issue_entry_WIRE_325_status_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_326_isa; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_isa = _issue_entry_WIRE_325_status_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_dprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_dprv = _issue_entry_WIRE_325_status_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_dv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_dv = _issue_entry_WIRE_325_status_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_prv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_prv = _issue_entry_WIRE_325_status_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_v; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_v = _issue_entry_WIRE_325_status_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_sd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_sd = _issue_entry_WIRE_325_status_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_326_zero2; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_zero2 = _issue_entry_WIRE_325_status_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_mpv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_mpv = _issue_entry_WIRE_325_status_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_gva; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_gva = _issue_entry_WIRE_325_status_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_mbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_mbe = _issue_entry_WIRE_325_status_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_sbe; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_sbe = _issue_entry_WIRE_325_status_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_sxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_sxl = _issue_entry_WIRE_325_status_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_uxl; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_uxl = _issue_entry_WIRE_325_status_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_sd_rv32; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_sd_rv32 = _issue_entry_WIRE_325_status_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_326_zero1; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_zero1 = _issue_entry_WIRE_325_status_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_tsr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_tsr = _issue_entry_WIRE_325_status_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_tw; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_tw = _issue_entry_WIRE_325_status_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_tvm; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_tvm = _issue_entry_WIRE_325_status_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_mxr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_mxr = _issue_entry_WIRE_325_status_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_sum; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_sum = _issue_entry_WIRE_325_status_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_mprv; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_mprv = _issue_entry_WIRE_325_status_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_xs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_xs = _issue_entry_WIRE_325_status_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_fs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_fs = _issue_entry_WIRE_325_status_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_mpp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_mpp = _issue_entry_WIRE_325_status_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_326_vs; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_vs = _issue_entry_WIRE_325_status_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_spp; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_spp = _issue_entry_WIRE_325_status_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_mpie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_mpie = _issue_entry_WIRE_325_status_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_ube; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_ube = _issue_entry_WIRE_325_status_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_spie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_spie = _issue_entry_WIRE_325_status_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_upie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_upie = _issue_entry_WIRE_325_status_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_mie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_mie = _issue_entry_WIRE_325_status_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_hie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_hie = _issue_entry_WIRE_325_status_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_sie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_sie = _issue_entry_WIRE_325_status_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_326_uie; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_319_cmd_status_uie = _issue_entry_WIRE_325_status_uie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_363; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_debug = _issue_entry_WIRE_326_debug; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_362; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_cease = _issue_entry_WIRE_326_cease; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_361; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_wfi = _issue_entry_WIRE_326_wfi; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_WIRE_360; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_isa = _issue_entry_WIRE_326_isa; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_359; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_dprv = _issue_entry_WIRE_326_dprv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_358; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_dv = _issue_entry_WIRE_326_dv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_357; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_prv = _issue_entry_WIRE_326_prv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_356; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_v = _issue_entry_WIRE_326_v; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_355; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_sd = _issue_entry_WIRE_326_sd; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_WIRE_354; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_zero2 = _issue_entry_WIRE_326_zero2; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_353; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_mpv = _issue_entry_WIRE_326_mpv; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_352; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_gva = _issue_entry_WIRE_326_gva; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_351; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_mbe = _issue_entry_WIRE_326_mbe; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_350; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_sbe = _issue_entry_WIRE_326_sbe; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_349; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_sxl = _issue_entry_WIRE_326_sxl; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_348; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_uxl = _issue_entry_WIRE_326_uxl; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_347; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_sd_rv32 = _issue_entry_WIRE_326_sd_rv32; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_WIRE_346; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_zero1 = _issue_entry_WIRE_326_zero1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_345; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_tsr = _issue_entry_WIRE_326_tsr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_344; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_tw = _issue_entry_WIRE_326_tw; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_343; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_tvm = _issue_entry_WIRE_326_tvm; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_342; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_mxr = _issue_entry_WIRE_326_mxr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_341; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_sum = _issue_entry_WIRE_326_sum; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_340; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_mprv = _issue_entry_WIRE_326_mprv; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_339; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_xs = _issue_entry_WIRE_326_xs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_338; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_fs = _issue_entry_WIRE_326_fs; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_337; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_mpp = _issue_entry_WIRE_326_mpp; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_WIRE_336; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_vs = _issue_entry_WIRE_326_vs; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_335; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_spp = _issue_entry_WIRE_326_spp; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_334; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_mpie = _issue_entry_WIRE_326_mpie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_333; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_ube = _issue_entry_WIRE_326_ube; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_332; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_spie = _issue_entry_WIRE_326_spie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_331; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_upie = _issue_entry_WIRE_326_upie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_330; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_mie = _issue_entry_WIRE_326_mie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_329; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_hie = _issue_entry_WIRE_326_hie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_328; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_sie = _issue_entry_WIRE_326_sie; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_327; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_status_uie = _issue_entry_WIRE_326_uie; // @[Mux.scala:30:73]
wire _issue_entry_T_5755 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5756 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5757 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5758 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_uie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5759 = _issue_entry_T_5755 | _issue_entry_T_5756; // @[Mux.scala:30:73]
wire _issue_entry_T_5760 = _issue_entry_T_5759 | _issue_entry_T_5757; // @[Mux.scala:30:73]
wire _issue_entry_T_5761 = _issue_entry_T_5760 | _issue_entry_T_5758; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_327 = _issue_entry_T_5761; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_uie = _issue_entry_WIRE_327; // @[Mux.scala:30:73]
wire _issue_entry_T_5762 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5763 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5764 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5765 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5766 = _issue_entry_T_5762 | _issue_entry_T_5763; // @[Mux.scala:30:73]
wire _issue_entry_T_5767 = _issue_entry_T_5766 | _issue_entry_T_5764; // @[Mux.scala:30:73]
wire _issue_entry_T_5768 = _issue_entry_T_5767 | _issue_entry_T_5765; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_328 = _issue_entry_T_5768; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_sie = _issue_entry_WIRE_328; // @[Mux.scala:30:73]
wire _issue_entry_T_5769 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5770 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5771 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5772 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_hie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5773 = _issue_entry_T_5769 | _issue_entry_T_5770; // @[Mux.scala:30:73]
wire _issue_entry_T_5774 = _issue_entry_T_5773 | _issue_entry_T_5771; // @[Mux.scala:30:73]
wire _issue_entry_T_5775 = _issue_entry_T_5774 | _issue_entry_T_5772; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_329 = _issue_entry_T_5775; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_hie = _issue_entry_WIRE_329; // @[Mux.scala:30:73]
wire _issue_entry_T_5776 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5777 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5778 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5779 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5780 = _issue_entry_T_5776 | _issue_entry_T_5777; // @[Mux.scala:30:73]
wire _issue_entry_T_5781 = _issue_entry_T_5780 | _issue_entry_T_5778; // @[Mux.scala:30:73]
wire _issue_entry_T_5782 = _issue_entry_T_5781 | _issue_entry_T_5779; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_330 = _issue_entry_T_5782; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_mie = _issue_entry_WIRE_330; // @[Mux.scala:30:73]
wire _issue_entry_T_5783 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5784 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5785 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5786 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_upie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5787 = _issue_entry_T_5783 | _issue_entry_T_5784; // @[Mux.scala:30:73]
wire _issue_entry_T_5788 = _issue_entry_T_5787 | _issue_entry_T_5785; // @[Mux.scala:30:73]
wire _issue_entry_T_5789 = _issue_entry_T_5788 | _issue_entry_T_5786; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_331 = _issue_entry_T_5789; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_upie = _issue_entry_WIRE_331; // @[Mux.scala:30:73]
wire _issue_entry_T_5790 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5791 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5792 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5793 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_spie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5794 = _issue_entry_T_5790 | _issue_entry_T_5791; // @[Mux.scala:30:73]
wire _issue_entry_T_5795 = _issue_entry_T_5794 | _issue_entry_T_5792; // @[Mux.scala:30:73]
wire _issue_entry_T_5796 = _issue_entry_T_5795 | _issue_entry_T_5793; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_332 = _issue_entry_T_5796; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_spie = _issue_entry_WIRE_332; // @[Mux.scala:30:73]
wire _issue_entry_T_5797 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_5798 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_5799 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_5800 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_ube; // @[OneHot.scala:83:30]
wire _issue_entry_T_5801 = _issue_entry_T_5797 | _issue_entry_T_5798; // @[Mux.scala:30:73]
wire _issue_entry_T_5802 = _issue_entry_T_5801 | _issue_entry_T_5799; // @[Mux.scala:30:73]
wire _issue_entry_T_5803 = _issue_entry_T_5802 | _issue_entry_T_5800; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_333 = _issue_entry_T_5803; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_ube = _issue_entry_WIRE_333; // @[Mux.scala:30:73]
wire _issue_entry_T_5804 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5805 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5806 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5807 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mpie; // @[OneHot.scala:83:30]
wire _issue_entry_T_5808 = _issue_entry_T_5804 | _issue_entry_T_5805; // @[Mux.scala:30:73]
wire _issue_entry_T_5809 = _issue_entry_T_5808 | _issue_entry_T_5806; // @[Mux.scala:30:73]
wire _issue_entry_T_5810 = _issue_entry_T_5809 | _issue_entry_T_5807; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_334 = _issue_entry_T_5810; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_mpie = _issue_entry_WIRE_334; // @[Mux.scala:30:73]
wire _issue_entry_T_5811 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_5812 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_5813 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_5814 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_spp; // @[OneHot.scala:83:30]
wire _issue_entry_T_5815 = _issue_entry_T_5811 | _issue_entry_T_5812; // @[Mux.scala:30:73]
wire _issue_entry_T_5816 = _issue_entry_T_5815 | _issue_entry_T_5813; // @[Mux.scala:30:73]
wire _issue_entry_T_5817 = _issue_entry_T_5816 | _issue_entry_T_5814; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_335 = _issue_entry_T_5817; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_spp = _issue_entry_WIRE_335; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5818 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5819 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5820 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5821 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_vs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5822 = _issue_entry_T_5818 | _issue_entry_T_5819; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5823 = _issue_entry_T_5822 | _issue_entry_T_5820; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5824 = _issue_entry_T_5823 | _issue_entry_T_5821; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_336 = _issue_entry_T_5824; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_vs = _issue_entry_WIRE_336; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5825 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5826 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5827 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5828 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_mpp : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5829 = _issue_entry_T_5825 | _issue_entry_T_5826; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5830 = _issue_entry_T_5829 | _issue_entry_T_5827; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5831 = _issue_entry_T_5830 | _issue_entry_T_5828; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_337 = _issue_entry_T_5831; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_mpp = _issue_entry_WIRE_337; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5832 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5833 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5834 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5835 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_fs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5836 = _issue_entry_T_5832 | _issue_entry_T_5833; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5837 = _issue_entry_T_5836 | _issue_entry_T_5834; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5838 = _issue_entry_T_5837 | _issue_entry_T_5835; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_338 = _issue_entry_T_5838; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_fs = _issue_entry_WIRE_338; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5839 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5840 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5841 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5842 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_xs : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5843 = _issue_entry_T_5839 | _issue_entry_T_5840; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5844 = _issue_entry_T_5843 | _issue_entry_T_5841; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5845 = _issue_entry_T_5844 | _issue_entry_T_5842; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_339 = _issue_entry_T_5845; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_xs = _issue_entry_WIRE_339; // @[Mux.scala:30:73]
wire _issue_entry_T_5846 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5847 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5848 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5849 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mprv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5850 = _issue_entry_T_5846 | _issue_entry_T_5847; // @[Mux.scala:30:73]
wire _issue_entry_T_5851 = _issue_entry_T_5850 | _issue_entry_T_5848; // @[Mux.scala:30:73]
wire _issue_entry_T_5852 = _issue_entry_T_5851 | _issue_entry_T_5849; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_340 = _issue_entry_T_5852; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_mprv = _issue_entry_WIRE_340; // @[Mux.scala:30:73]
wire _issue_entry_T_5853 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_5854 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_5855 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_5856 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sum; // @[OneHot.scala:83:30]
wire _issue_entry_T_5857 = _issue_entry_T_5853 | _issue_entry_T_5854; // @[Mux.scala:30:73]
wire _issue_entry_T_5858 = _issue_entry_T_5857 | _issue_entry_T_5855; // @[Mux.scala:30:73]
wire _issue_entry_T_5859 = _issue_entry_T_5858 | _issue_entry_T_5856; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_341 = _issue_entry_T_5859; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_sum = _issue_entry_WIRE_341; // @[Mux.scala:30:73]
wire _issue_entry_T_5860 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5861 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5862 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5863 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mxr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5864 = _issue_entry_T_5860 | _issue_entry_T_5861; // @[Mux.scala:30:73]
wire _issue_entry_T_5865 = _issue_entry_T_5864 | _issue_entry_T_5862; // @[Mux.scala:30:73]
wire _issue_entry_T_5866 = _issue_entry_T_5865 | _issue_entry_T_5863; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_342 = _issue_entry_T_5866; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_mxr = _issue_entry_WIRE_342; // @[Mux.scala:30:73]
wire _issue_entry_T_5867 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5868 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5869 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5870 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_tvm; // @[OneHot.scala:83:30]
wire _issue_entry_T_5871 = _issue_entry_T_5867 | _issue_entry_T_5868; // @[Mux.scala:30:73]
wire _issue_entry_T_5872 = _issue_entry_T_5871 | _issue_entry_T_5869; // @[Mux.scala:30:73]
wire _issue_entry_T_5873 = _issue_entry_T_5872 | _issue_entry_T_5870; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_343 = _issue_entry_T_5873; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_tvm = _issue_entry_WIRE_343; // @[Mux.scala:30:73]
wire _issue_entry_T_5874 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_5875 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_5876 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_5877 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_tw; // @[OneHot.scala:83:30]
wire _issue_entry_T_5878 = _issue_entry_T_5874 | _issue_entry_T_5875; // @[Mux.scala:30:73]
wire _issue_entry_T_5879 = _issue_entry_T_5878 | _issue_entry_T_5876; // @[Mux.scala:30:73]
wire _issue_entry_T_5880 = _issue_entry_T_5879 | _issue_entry_T_5877; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_344 = _issue_entry_T_5880; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_tw = _issue_entry_WIRE_344; // @[Mux.scala:30:73]
wire _issue_entry_T_5881 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5882 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5883 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5884 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_tsr; // @[OneHot.scala:83:30]
wire _issue_entry_T_5885 = _issue_entry_T_5881 | _issue_entry_T_5882; // @[Mux.scala:30:73]
wire _issue_entry_T_5886 = _issue_entry_T_5885 | _issue_entry_T_5883; // @[Mux.scala:30:73]
wire _issue_entry_T_5887 = _issue_entry_T_5886 | _issue_entry_T_5884; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_345 = _issue_entry_T_5887; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_tsr = _issue_entry_WIRE_345; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_5888 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_5889 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_5890 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_5891 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_zero1 : 8'h0; // @[OneHot.scala:83:30]
wire [7:0] _issue_entry_T_5892 = _issue_entry_T_5888 | _issue_entry_T_5889; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_5893 = _issue_entry_T_5892 | _issue_entry_T_5890; // @[Mux.scala:30:73]
wire [7:0] _issue_entry_T_5894 = _issue_entry_T_5893 | _issue_entry_T_5891; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_346 = _issue_entry_T_5894; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_zero1 = _issue_entry_WIRE_346; // @[Mux.scala:30:73]
wire _issue_entry_T_5895 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_5896 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_5897 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_5898 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sd_rv32; // @[OneHot.scala:83:30]
wire _issue_entry_T_5899 = _issue_entry_T_5895 | _issue_entry_T_5896; // @[Mux.scala:30:73]
wire _issue_entry_T_5900 = _issue_entry_T_5899 | _issue_entry_T_5897; // @[Mux.scala:30:73]
wire _issue_entry_T_5901 = _issue_entry_T_5900 | _issue_entry_T_5898; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_347 = _issue_entry_T_5901; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_sd_rv32 = _issue_entry_WIRE_347; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5902 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5903 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5904 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5905 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_uxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5906 = _issue_entry_T_5902 | _issue_entry_T_5903; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5907 = _issue_entry_T_5906 | _issue_entry_T_5904; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5908 = _issue_entry_T_5907 | _issue_entry_T_5905; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_348 = _issue_entry_T_5908; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_uxl = _issue_entry_WIRE_348; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5909 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5910 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5911 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5912 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_sxl : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5913 = _issue_entry_T_5909 | _issue_entry_T_5910; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5914 = _issue_entry_T_5913 | _issue_entry_T_5911; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5915 = _issue_entry_T_5914 | _issue_entry_T_5912; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_349 = _issue_entry_T_5915; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_sxl = _issue_entry_WIRE_349; // @[Mux.scala:30:73]
wire _issue_entry_T_5916 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5917 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5918 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5919 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5920 = _issue_entry_T_5916 | _issue_entry_T_5917; // @[Mux.scala:30:73]
wire _issue_entry_T_5921 = _issue_entry_T_5920 | _issue_entry_T_5918; // @[Mux.scala:30:73]
wire _issue_entry_T_5922 = _issue_entry_T_5921 | _issue_entry_T_5919; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_350 = _issue_entry_T_5922; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_sbe = _issue_entry_WIRE_350; // @[Mux.scala:30:73]
wire _issue_entry_T_5923 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5924 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5925 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5926 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mbe; // @[OneHot.scala:83:30]
wire _issue_entry_T_5927 = _issue_entry_T_5923 | _issue_entry_T_5924; // @[Mux.scala:30:73]
wire _issue_entry_T_5928 = _issue_entry_T_5927 | _issue_entry_T_5925; // @[Mux.scala:30:73]
wire _issue_entry_T_5929 = _issue_entry_T_5928 | _issue_entry_T_5926; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_351 = _issue_entry_T_5929; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_mbe = _issue_entry_WIRE_351; // @[Mux.scala:30:73]
wire _issue_entry_T_5930 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_5931 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_5932 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_5933 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_gva; // @[OneHot.scala:83:30]
wire _issue_entry_T_5934 = _issue_entry_T_5930 | _issue_entry_T_5931; // @[Mux.scala:30:73]
wire _issue_entry_T_5935 = _issue_entry_T_5934 | _issue_entry_T_5932; // @[Mux.scala:30:73]
wire _issue_entry_T_5936 = _issue_entry_T_5935 | _issue_entry_T_5933; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_352 = _issue_entry_T_5936; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_gva = _issue_entry_WIRE_352; // @[Mux.scala:30:73]
wire _issue_entry_T_5937 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5938 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5939 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5940 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_mpv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5941 = _issue_entry_T_5937 | _issue_entry_T_5938; // @[Mux.scala:30:73]
wire _issue_entry_T_5942 = _issue_entry_T_5941 | _issue_entry_T_5939; // @[Mux.scala:30:73]
wire _issue_entry_T_5943 = _issue_entry_T_5942 | _issue_entry_T_5940; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_353 = _issue_entry_T_5943; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_mpv = _issue_entry_WIRE_353; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_5944 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_5945 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_5946 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_5947 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_zero2 : 23'h0; // @[OneHot.scala:83:30]
wire [22:0] _issue_entry_T_5948 = _issue_entry_T_5944 | _issue_entry_T_5945; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_5949 = _issue_entry_T_5948 | _issue_entry_T_5946; // @[Mux.scala:30:73]
wire [22:0] _issue_entry_T_5950 = _issue_entry_T_5949 | _issue_entry_T_5947; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_354 = _issue_entry_T_5950; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_zero2 = _issue_entry_WIRE_354; // @[Mux.scala:30:73]
wire _issue_entry_T_5951 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_5952 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_5953 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_5954 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_sd; // @[OneHot.scala:83:30]
wire _issue_entry_T_5955 = _issue_entry_T_5951 | _issue_entry_T_5952; // @[Mux.scala:30:73]
wire _issue_entry_T_5956 = _issue_entry_T_5955 | _issue_entry_T_5953; // @[Mux.scala:30:73]
wire _issue_entry_T_5957 = _issue_entry_T_5956 | _issue_entry_T_5954; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_355 = _issue_entry_T_5957; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_sd = _issue_entry_WIRE_355; // @[Mux.scala:30:73]
wire _issue_entry_T_5958 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_5959 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_5960 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_5961 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_v; // @[OneHot.scala:83:30]
wire _issue_entry_T_5962 = _issue_entry_T_5958 | _issue_entry_T_5959; // @[Mux.scala:30:73]
wire _issue_entry_T_5963 = _issue_entry_T_5962 | _issue_entry_T_5960; // @[Mux.scala:30:73]
wire _issue_entry_T_5964 = _issue_entry_T_5963 | _issue_entry_T_5961; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_356 = _issue_entry_T_5964; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_v = _issue_entry_WIRE_356; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5965 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5966 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5967 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5968 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_prv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5969 = _issue_entry_T_5965 | _issue_entry_T_5966; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5970 = _issue_entry_T_5969 | _issue_entry_T_5967; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5971 = _issue_entry_T_5970 | _issue_entry_T_5968; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_357 = _issue_entry_T_5971; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_prv = _issue_entry_WIRE_357; // @[Mux.scala:30:73]
wire _issue_entry_T_5972 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5973 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5974 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5975 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_dv; // @[OneHot.scala:83:30]
wire _issue_entry_T_5976 = _issue_entry_T_5972 | _issue_entry_T_5973; // @[Mux.scala:30:73]
wire _issue_entry_T_5977 = _issue_entry_T_5976 | _issue_entry_T_5974; // @[Mux.scala:30:73]
wire _issue_entry_T_5978 = _issue_entry_T_5977 | _issue_entry_T_5975; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_358 = _issue_entry_T_5978; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_dv = _issue_entry_WIRE_358; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5979 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5980 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5981 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5982 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_dprv : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_5983 = _issue_entry_T_5979 | _issue_entry_T_5980; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5984 = _issue_entry_T_5983 | _issue_entry_T_5981; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_5985 = _issue_entry_T_5984 | _issue_entry_T_5982; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_359 = _issue_entry_T_5985; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_dprv = _issue_entry_WIRE_359; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_5986 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5987 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5988 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5989 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_status_isa : 32'h0; // @[OneHot.scala:83:30]
wire [31:0] _issue_entry_T_5990 = _issue_entry_T_5986 | _issue_entry_T_5987; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_5991 = _issue_entry_T_5990 | _issue_entry_T_5988; // @[Mux.scala:30:73]
wire [31:0] _issue_entry_T_5992 = _issue_entry_T_5991 | _issue_entry_T_5989; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_360 = _issue_entry_T_5992; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_isa = _issue_entry_WIRE_360; // @[Mux.scala:30:73]
wire _issue_entry_T_5993 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_5994 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_5995 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_5996 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_wfi; // @[OneHot.scala:83:30]
wire _issue_entry_T_5997 = _issue_entry_T_5993 | _issue_entry_T_5994; // @[Mux.scala:30:73]
wire _issue_entry_T_5998 = _issue_entry_T_5997 | _issue_entry_T_5995; // @[Mux.scala:30:73]
wire _issue_entry_T_5999 = _issue_entry_T_5998 | _issue_entry_T_5996; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_361 = _issue_entry_T_5999; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_wfi = _issue_entry_WIRE_361; // @[Mux.scala:30:73]
wire _issue_entry_T_6000 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_6001 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_6002 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_6003 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_cease; // @[OneHot.scala:83:30]
wire _issue_entry_T_6004 = _issue_entry_T_6000 | _issue_entry_T_6001; // @[Mux.scala:30:73]
wire _issue_entry_T_6005 = _issue_entry_T_6004 | _issue_entry_T_6002; // @[Mux.scala:30:73]
wire _issue_entry_T_6006 = _issue_entry_T_6005 | _issue_entry_T_6003; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_362 = _issue_entry_T_6006; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_cease = _issue_entry_WIRE_362; // @[Mux.scala:30:73]
wire _issue_entry_T_6007 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_6008 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_6009 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_6010 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_status_debug; // @[OneHot.scala:83:30]
wire _issue_entry_T_6011 = _issue_entry_T_6007 | _issue_entry_T_6008; // @[Mux.scala:30:73]
wire _issue_entry_T_6012 = _issue_entry_T_6011 | _issue_entry_T_6009; // @[Mux.scala:30:73]
wire _issue_entry_T_6013 = _issue_entry_T_6012 | _issue_entry_T_6010; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_363 = _issue_entry_T_6013; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_326_debug = _issue_entry_WIRE_363; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_6014 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6015 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6016 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6017 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_rs2 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6018 = _issue_entry_T_6014 | _issue_entry_T_6015; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_6019 = _issue_entry_T_6018 | _issue_entry_T_6016; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_6020 = _issue_entry_T_6019 | _issue_entry_T_6017; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_364 = _issue_entry_T_6020; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_rs2 = _issue_entry_WIRE_364; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_6021 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6022 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6023 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6024 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_rs1 : 64'h0; // @[OneHot.scala:83:30]
wire [63:0] _issue_entry_T_6025 = _issue_entry_T_6021 | _issue_entry_T_6022; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_6026 = _issue_entry_T_6025 | _issue_entry_T_6023; // @[Mux.scala:30:73]
wire [63:0] _issue_entry_T_6027 = _issue_entry_T_6026 | _issue_entry_T_6024; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_365 = _issue_entry_T_6027; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_rs1 = _issue_entry_WIRE_365; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_374; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_funct = _issue_entry_WIRE_366_funct; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_373; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_rs2 = _issue_entry_WIRE_366_rs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_372; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_rs1 = _issue_entry_WIRE_366_rs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_371; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_xd = _issue_entry_WIRE_366_xd; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_370; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_xs1 = _issue_entry_WIRE_366_xs1; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_369; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_xs2 = _issue_entry_WIRE_366_xs2; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_WIRE_368; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_rd = _issue_entry_WIRE_366_rd; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_WIRE_367; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_325_inst_opcode = _issue_entry_WIRE_366_opcode; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_6028 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6029 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6030 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6031 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_opcode : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6032 = _issue_entry_T_6028 | _issue_entry_T_6029; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_6033 = _issue_entry_T_6032 | _issue_entry_T_6030; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_6034 = _issue_entry_T_6033 | _issue_entry_T_6031; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_367 = _issue_entry_T_6034; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_opcode = _issue_entry_WIRE_367; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6035 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6036 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6037 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6038 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_rd : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6039 = _issue_entry_T_6035 | _issue_entry_T_6036; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6040 = _issue_entry_T_6039 | _issue_entry_T_6037; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6041 = _issue_entry_T_6040 | _issue_entry_T_6038; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_368 = _issue_entry_T_6041; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_rd = _issue_entry_WIRE_368; // @[Mux.scala:30:73]
wire _issue_entry_T_6042 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_6043 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_6044 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_6045 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_inst_xs2; // @[OneHot.scala:83:30]
wire _issue_entry_T_6046 = _issue_entry_T_6042 | _issue_entry_T_6043; // @[Mux.scala:30:73]
wire _issue_entry_T_6047 = _issue_entry_T_6046 | _issue_entry_T_6044; // @[Mux.scala:30:73]
wire _issue_entry_T_6048 = _issue_entry_T_6047 | _issue_entry_T_6045; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_369 = _issue_entry_T_6048; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_xs2 = _issue_entry_WIRE_369; // @[Mux.scala:30:73]
wire _issue_entry_T_6049 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_6050 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_6051 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_6052 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_inst_xs1; // @[OneHot.scala:83:30]
wire _issue_entry_T_6053 = _issue_entry_T_6049 | _issue_entry_T_6050; // @[Mux.scala:30:73]
wire _issue_entry_T_6054 = _issue_entry_T_6053 | _issue_entry_T_6051; // @[Mux.scala:30:73]
wire _issue_entry_T_6055 = _issue_entry_T_6054 | _issue_entry_T_6052; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_370 = _issue_entry_T_6055; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_xs1 = _issue_entry_WIRE_370; // @[Mux.scala:30:73]
wire _issue_entry_T_6056 = issue_sel_0_2 & entries_st_0_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_6057 = issue_sel_1_2 & entries_st_1_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_6058 = issue_sel_2_2 & entries_st_2_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_6059 = issue_sel_3_2 & entries_st_3_bits_cmd_cmd_inst_xd; // @[OneHot.scala:83:30]
wire _issue_entry_T_6060 = _issue_entry_T_6056 | _issue_entry_T_6057; // @[Mux.scala:30:73]
wire _issue_entry_T_6061 = _issue_entry_T_6060 | _issue_entry_T_6058; // @[Mux.scala:30:73]
wire _issue_entry_T_6062 = _issue_entry_T_6061 | _issue_entry_T_6059; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_371 = _issue_entry_T_6062; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_xd = _issue_entry_WIRE_371; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6063 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6064 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6065 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6066 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_rs1 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6067 = _issue_entry_T_6063 | _issue_entry_T_6064; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6068 = _issue_entry_T_6067 | _issue_entry_T_6065; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6069 = _issue_entry_T_6068 | _issue_entry_T_6066; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_372 = _issue_entry_T_6069; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_rs1 = _issue_entry_WIRE_372; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6070 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6071 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6072 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6073 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_rs2 : 5'h0; // @[OneHot.scala:83:30]
wire [4:0] _issue_entry_T_6074 = _issue_entry_T_6070 | _issue_entry_T_6071; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6075 = _issue_entry_T_6074 | _issue_entry_T_6072; // @[Mux.scala:30:73]
wire [4:0] _issue_entry_T_6076 = _issue_entry_T_6075 | _issue_entry_T_6073; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_373 = _issue_entry_T_6076; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_rs2 = _issue_entry_WIRE_373; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_6077 = issue_sel_0_2 ? entries_st_0_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6078 = issue_sel_1_2 ? entries_st_1_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6079 = issue_sel_2_2 ? entries_st_2_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6080 = issue_sel_3_2 ? entries_st_3_bits_cmd_cmd_inst_funct : 7'h0; // @[OneHot.scala:83:30]
wire [6:0] _issue_entry_T_6081 = _issue_entry_T_6077 | _issue_entry_T_6078; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_6082 = _issue_entry_T_6081 | _issue_entry_T_6079; // @[Mux.scala:30:73]
wire [6:0] _issue_entry_T_6083 = _issue_entry_T_6082 | _issue_entry_T_6080; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_374 = _issue_entry_T_6083; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_366_funct = _issue_entry_WIRE_374; // @[Mux.scala:30:73]
wire _issue_entry_T_6084 = issue_sel_0_2 & entries_st_0_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_6085 = issue_sel_1_2 & entries_st_1_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_6086 = issue_sel_2_2 & entries_st_2_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_6087 = issue_sel_3_2 & entries_st_3_bits_complete_on_issue; // @[OneHot.scala:83:30]
wire _issue_entry_T_6088 = _issue_entry_T_6084 | _issue_entry_T_6085; // @[Mux.scala:30:73]
wire _issue_entry_T_6089 = _issue_entry_T_6088 | _issue_entry_T_6086; // @[Mux.scala:30:73]
wire _issue_entry_T_6090 = _issue_entry_T_6089 | _issue_entry_T_6087; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_375 = _issue_entry_T_6090; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_complete_on_issue = _issue_entry_WIRE_375; // @[Mux.scala:30:73]
wire _issue_entry_T_6091 = issue_sel_0_2 & entries_st_0_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_6092 = issue_sel_1_2 & entries_st_1_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_6093 = issue_sel_2_2 & entries_st_2_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_6094 = issue_sel_3_2 & entries_st_3_bits_issued; // @[OneHot.scala:83:30]
wire _issue_entry_T_6095 = _issue_entry_T_6091 | _issue_entry_T_6092; // @[Mux.scala:30:73]
wire _issue_entry_T_6096 = _issue_entry_T_6095 | _issue_entry_T_6093; // @[Mux.scala:30:73]
wire _issue_entry_T_6097 = _issue_entry_T_6096 | _issue_entry_T_6094; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_376 = _issue_entry_T_6097; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_issued = _issue_entry_WIRE_376; // @[Mux.scala:30:73]
wire _issue_entry_T_6218 = issue_sel_0_2 & entries_st_0_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_6219 = issue_sel_1_2 & entries_st_1_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_6220 = issue_sel_2_2 & entries_st_2_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_6221 = issue_sel_3_2 & entries_st_3_bits_opa_is_dst; // @[OneHot.scala:83:30]
wire _issue_entry_T_6222 = _issue_entry_T_6218 | _issue_entry_T_6219; // @[Mux.scala:30:73]
wire _issue_entry_T_6223 = _issue_entry_T_6222 | _issue_entry_T_6220; // @[Mux.scala:30:73]
wire _issue_entry_T_6224 = _issue_entry_T_6223 | _issue_entry_T_6221; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_401 = _issue_entry_T_6224; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_is_dst = _issue_entry_WIRE_401; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_425; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_valid = _issue_entry_WIRE_402_valid; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_start_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_start_is_acc_addr = _issue_entry_WIRE_402_bits_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_start_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_start_accumulate = _issue_entry_WIRE_402_bits_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_start_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_start_read_full_acc_row = _issue_entry_WIRE_402_bits_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_403_start_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_start_norm_cmd = _issue_entry_WIRE_402_bits_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_403_start_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_start_garbage = _issue_entry_WIRE_402_bits_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_start_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_start_garbage_bit = _issue_entry_WIRE_402_bits_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_403_start_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_start_data = _issue_entry_WIRE_402_bits_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_end_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_end_is_acc_addr = _issue_entry_WIRE_402_bits_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_end_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_end_accumulate = _issue_entry_WIRE_402_bits_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_end_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_end_read_full_acc_row = _issue_entry_WIRE_402_bits_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_403_end_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_end_norm_cmd = _issue_entry_WIRE_402_bits_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_403_end_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_end_garbage = _issue_entry_WIRE_402_bits_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_end_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_end_garbage_bit = _issue_entry_WIRE_402_bits_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_403_end_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_end_data = _issue_entry_WIRE_402_bits_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_403_wraps_around; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_opa_bits_wraps_around = _issue_entry_WIRE_402_bits_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_415_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_start_is_acc_addr = _issue_entry_WIRE_403_start_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_415_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_start_accumulate = _issue_entry_WIRE_403_start_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_415_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_start_read_full_acc_row = _issue_entry_WIRE_403_start_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_415_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_start_norm_cmd = _issue_entry_WIRE_403_start_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_415_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_start_garbage = _issue_entry_WIRE_403_start_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_415_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_start_garbage_bit = _issue_entry_WIRE_403_start_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_415_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_start_data = _issue_entry_WIRE_403_start_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_405_is_acc_addr; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_end_is_acc_addr = _issue_entry_WIRE_403_end_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_405_accumulate; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_end_accumulate = _issue_entry_WIRE_403_end_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_405_read_full_acc_row; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_end_read_full_acc_row = _issue_entry_WIRE_403_end_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_405_norm_cmd; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_end_norm_cmd = _issue_entry_WIRE_403_end_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_405_garbage; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_end_garbage = _issue_entry_WIRE_403_end_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_405_garbage_bit; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_end_garbage_bit = _issue_entry_WIRE_403_end_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_405_data; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_end_data = _issue_entry_WIRE_403_end_data; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_404; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_bits_wraps_around = _issue_entry_WIRE_403_wraps_around; // @[Mux.scala:30:73]
wire _issue_entry_T_6225 = issue_sel_0_2 & entries_st_0_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_6226 = issue_sel_1_2 & entries_st_1_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_6227 = issue_sel_2_2 & entries_st_2_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_6228 = issue_sel_3_2 & entries_st_3_bits_opa_bits_wraps_around; // @[OneHot.scala:83:30]
wire _issue_entry_T_6229 = _issue_entry_T_6225 | _issue_entry_T_6226; // @[Mux.scala:30:73]
wire _issue_entry_T_6230 = _issue_entry_T_6229 | _issue_entry_T_6227; // @[Mux.scala:30:73]
wire _issue_entry_T_6231 = _issue_entry_T_6230 | _issue_entry_T_6228; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_404 = _issue_entry_T_6231; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_wraps_around = _issue_entry_WIRE_404; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_414; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_end_is_acc_addr = _issue_entry_WIRE_405_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_413; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_end_accumulate = _issue_entry_WIRE_405_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_412; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_end_read_full_acc_row = _issue_entry_WIRE_405_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_409; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_end_norm_cmd = _issue_entry_WIRE_405_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_408; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_end_garbage = _issue_entry_WIRE_405_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_407; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_end_garbage_bit = _issue_entry_WIRE_405_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_406; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_end_data = _issue_entry_WIRE_405_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6232 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6233 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6234 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6235 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_end_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6236 = _issue_entry_T_6232 | _issue_entry_T_6233; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6237 = _issue_entry_T_6236 | _issue_entry_T_6234; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6238 = _issue_entry_T_6237 | _issue_entry_T_6235; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_406 = _issue_entry_T_6238; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_405_data = _issue_entry_WIRE_406; // @[Mux.scala:30:73]
wire _issue_entry_T_6239 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6240 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6241 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6242 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6243 = _issue_entry_T_6239 | _issue_entry_T_6240; // @[Mux.scala:30:73]
wire _issue_entry_T_6244 = _issue_entry_T_6243 | _issue_entry_T_6241; // @[Mux.scala:30:73]
wire _issue_entry_T_6245 = _issue_entry_T_6244 | _issue_entry_T_6242; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_407 = _issue_entry_T_6245; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_405_garbage_bit = _issue_entry_WIRE_407; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6246 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6247 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6248 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6249 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_end_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6250 = _issue_entry_T_6246 | _issue_entry_T_6247; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6251 = _issue_entry_T_6250 | _issue_entry_T_6248; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6252 = _issue_entry_T_6251 | _issue_entry_T_6249; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_408 = _issue_entry_T_6252; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_405_garbage = _issue_entry_WIRE_408; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6254 = issue_sel_0_2 ? _issue_entry_T_6253 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6256 = issue_sel_1_2 ? _issue_entry_T_6255 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6258 = issue_sel_2_2 ? _issue_entry_T_6257 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6260 = issue_sel_3_2 ? _issue_entry_T_6259 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6261 = _issue_entry_T_6254 | _issue_entry_T_6256; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6262 = _issue_entry_T_6261 | _issue_entry_T_6258; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6263 = _issue_entry_T_6262 | _issue_entry_T_6260; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_410 = _issue_entry_T_6263; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_411; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_405_norm_cmd = _issue_entry_WIRE_409; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_411 = _issue_entry_WIRE_410; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_409 = _issue_entry_WIRE_411; // @[Mux.scala:30:73]
wire _issue_entry_T_6264 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6265 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6266 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6267 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6268 = _issue_entry_T_6264 | _issue_entry_T_6265; // @[Mux.scala:30:73]
wire _issue_entry_T_6269 = _issue_entry_T_6268 | _issue_entry_T_6266; // @[Mux.scala:30:73]
wire _issue_entry_T_6270 = _issue_entry_T_6269 | _issue_entry_T_6267; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_412 = _issue_entry_T_6270; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_405_read_full_acc_row = _issue_entry_WIRE_412; // @[Mux.scala:30:73]
wire _issue_entry_T_6271 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6272 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6273 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6274 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6275 = _issue_entry_T_6271 | _issue_entry_T_6272; // @[Mux.scala:30:73]
wire _issue_entry_T_6276 = _issue_entry_T_6275 | _issue_entry_T_6273; // @[Mux.scala:30:73]
wire _issue_entry_T_6277 = _issue_entry_T_6276 | _issue_entry_T_6274; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_413 = _issue_entry_T_6277; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_405_accumulate = _issue_entry_WIRE_413; // @[Mux.scala:30:73]
wire _issue_entry_T_6278 = issue_sel_0_2 & entries_st_0_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6279 = issue_sel_1_2 & entries_st_1_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6280 = issue_sel_2_2 & entries_st_2_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6281 = issue_sel_3_2 & entries_st_3_bits_opa_bits_end_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6282 = _issue_entry_T_6278 | _issue_entry_T_6279; // @[Mux.scala:30:73]
wire _issue_entry_T_6283 = _issue_entry_T_6282 | _issue_entry_T_6280; // @[Mux.scala:30:73]
wire _issue_entry_T_6284 = _issue_entry_T_6283 | _issue_entry_T_6281; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_414 = _issue_entry_T_6284; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_405_is_acc_addr = _issue_entry_WIRE_414; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_424; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_start_is_acc_addr = _issue_entry_WIRE_415_is_acc_addr; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_423; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_start_accumulate = _issue_entry_WIRE_415_accumulate; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_422; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_start_read_full_acc_row = _issue_entry_WIRE_415_read_full_acc_row; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_419; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_start_norm_cmd = _issue_entry_WIRE_415_norm_cmd; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_WIRE_418; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_start_garbage = _issue_entry_WIRE_415_garbage; // @[Mux.scala:30:73]
wire _issue_entry_WIRE_417; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_start_garbage_bit = _issue_entry_WIRE_415_garbage_bit; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_WIRE_416; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_403_start_data = _issue_entry_WIRE_415_data; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6285 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6286 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6287 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6288 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_start_data : 14'h0; // @[OneHot.scala:83:30]
wire [13:0] _issue_entry_T_6289 = _issue_entry_T_6285 | _issue_entry_T_6286; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6290 = _issue_entry_T_6289 | _issue_entry_T_6287; // @[Mux.scala:30:73]
wire [13:0] _issue_entry_T_6291 = _issue_entry_T_6290 | _issue_entry_T_6288; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_416 = _issue_entry_T_6291; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_415_data = _issue_entry_WIRE_416; // @[Mux.scala:30:73]
wire _issue_entry_T_6292 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6293 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6294 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6295 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_garbage_bit; // @[OneHot.scala:83:30]
wire _issue_entry_T_6296 = _issue_entry_T_6292 | _issue_entry_T_6293; // @[Mux.scala:30:73]
wire _issue_entry_T_6297 = _issue_entry_T_6296 | _issue_entry_T_6294; // @[Mux.scala:30:73]
wire _issue_entry_T_6298 = _issue_entry_T_6297 | _issue_entry_T_6295; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_417 = _issue_entry_T_6298; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_415_garbage_bit = _issue_entry_WIRE_417; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6299 = issue_sel_0_2 ? entries_st_0_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6300 = issue_sel_1_2 ? entries_st_1_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6301 = issue_sel_2_2 ? entries_st_2_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6302 = issue_sel_3_2 ? entries_st_3_bits_opa_bits_start_garbage : 11'h0; // @[OneHot.scala:83:30]
wire [10:0] _issue_entry_T_6303 = _issue_entry_T_6299 | _issue_entry_T_6300; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6304 = _issue_entry_T_6303 | _issue_entry_T_6301; // @[Mux.scala:30:73]
wire [10:0] _issue_entry_T_6305 = _issue_entry_T_6304 | _issue_entry_T_6302; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_418 = _issue_entry_T_6305; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_415_garbage = _issue_entry_WIRE_418; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6307 = issue_sel_0_2 ? _issue_entry_T_6306 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6309 = issue_sel_1_2 ? _issue_entry_T_6308 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6311 = issue_sel_2_2 ? _issue_entry_T_6310 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6313 = issue_sel_3_2 ? _issue_entry_T_6312 : 3'h0; // @[OneHot.scala:83:30]
wire [2:0] _issue_entry_T_6314 = _issue_entry_T_6307 | _issue_entry_T_6309; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6315 = _issue_entry_T_6314 | _issue_entry_T_6311; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_T_6316 = _issue_entry_T_6315 | _issue_entry_T_6313; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_420 = _issue_entry_T_6316; // @[Mux.scala:30:73]
wire [2:0] _issue_entry_WIRE_421; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_415_norm_cmd = _issue_entry_WIRE_419; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_421 = _issue_entry_WIRE_420; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_419 = _issue_entry_WIRE_421; // @[Mux.scala:30:73]
wire _issue_entry_T_6317 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6318 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6319 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6320 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_read_full_acc_row; // @[OneHot.scala:83:30]
wire _issue_entry_T_6321 = _issue_entry_T_6317 | _issue_entry_T_6318; // @[Mux.scala:30:73]
wire _issue_entry_T_6322 = _issue_entry_T_6321 | _issue_entry_T_6319; // @[Mux.scala:30:73]
wire _issue_entry_T_6323 = _issue_entry_T_6322 | _issue_entry_T_6320; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_422 = _issue_entry_T_6323; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_415_read_full_acc_row = _issue_entry_WIRE_422; // @[Mux.scala:30:73]
wire _issue_entry_T_6324 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6325 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6326 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6327 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_accumulate; // @[OneHot.scala:83:30]
wire _issue_entry_T_6328 = _issue_entry_T_6324 | _issue_entry_T_6325; // @[Mux.scala:30:73]
wire _issue_entry_T_6329 = _issue_entry_T_6328 | _issue_entry_T_6326; // @[Mux.scala:30:73]
wire _issue_entry_T_6330 = _issue_entry_T_6329 | _issue_entry_T_6327; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_423 = _issue_entry_T_6330; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_415_accumulate = _issue_entry_WIRE_423; // @[Mux.scala:30:73]
wire _issue_entry_T_6331 = issue_sel_0_2 & entries_st_0_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6332 = issue_sel_1_2 & entries_st_1_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6333 = issue_sel_2_2 & entries_st_2_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6334 = issue_sel_3_2 & entries_st_3_bits_opa_bits_start_is_acc_addr; // @[OneHot.scala:83:30]
wire _issue_entry_T_6335 = _issue_entry_T_6331 | _issue_entry_T_6332; // @[Mux.scala:30:73]
wire _issue_entry_T_6336 = _issue_entry_T_6335 | _issue_entry_T_6333; // @[Mux.scala:30:73]
wire _issue_entry_T_6337 = _issue_entry_T_6336 | _issue_entry_T_6334; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_424 = _issue_entry_T_6337; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_415_is_acc_addr = _issue_entry_WIRE_424; // @[Mux.scala:30:73]
wire _issue_entry_T_6338 = issue_sel_0_2 & entries_st_0_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6339 = issue_sel_1_2 & entries_st_1_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6340 = issue_sel_2_2 & entries_st_2_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6341 = issue_sel_3_2 & entries_st_3_bits_opa_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6342 = _issue_entry_T_6338 | _issue_entry_T_6339; // @[Mux.scala:30:73]
wire _issue_entry_T_6343 = _issue_entry_T_6342 | _issue_entry_T_6340; // @[Mux.scala:30:73]
wire _issue_entry_T_6344 = _issue_entry_T_6343 | _issue_entry_T_6341; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_425 = _issue_entry_T_6344; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_402_valid = _issue_entry_WIRE_425; // @[Mux.scala:30:73]
wire _issue_entry_T_6345 = issue_sel_0_2 & entries_st_0_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_6346 = issue_sel_1_2 & entries_st_1_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_6347 = issue_sel_2_2 & entries_st_2_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_6348 = issue_sel_3_2 & entries_st_3_bits_is_config; // @[OneHot.scala:83:30]
wire _issue_entry_T_6349 = _issue_entry_T_6345 | _issue_entry_T_6346; // @[Mux.scala:30:73]
wire _issue_entry_T_6350 = _issue_entry_T_6349 | _issue_entry_T_6347; // @[Mux.scala:30:73]
wire _issue_entry_T_6351 = _issue_entry_T_6350 | _issue_entry_T_6348; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_426 = _issue_entry_T_6351; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_is_config = _issue_entry_WIRE_426; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_6352 = issue_sel_0_2 ? entries_st_0_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_6353 = issue_sel_1_2 ? entries_st_1_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_6354 = issue_sel_2_2 ? entries_st_2_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_6355 = issue_sel_3_2 ? entries_st_3_bits_q : 2'h0; // @[OneHot.scala:83:30]
wire [1:0] _issue_entry_T_6356 = _issue_entry_T_6352 | _issue_entry_T_6353; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_6357 = _issue_entry_T_6356 | _issue_entry_T_6354; // @[Mux.scala:30:73]
wire [1:0] _issue_entry_T_6358 = _issue_entry_T_6357 | _issue_entry_T_6355; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_427 = _issue_entry_T_6358; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_286_q = _issue_entry_WIRE_427; // @[Mux.scala:30:73]
wire _issue_entry_T_6359 = issue_sel_0_2 & entries_st_0_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6360 = issue_sel_1_2 & entries_st_1_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6361 = issue_sel_2_2 & entries_st_2_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6362 = issue_sel_3_2 & entries_st_3_valid; // @[OneHot.scala:83:30]
wire _issue_entry_T_6363 = _issue_entry_T_6359 | _issue_entry_T_6360; // @[Mux.scala:30:73]
wire _issue_entry_T_6364 = _issue_entry_T_6363 | _issue_entry_T_6361; // @[Mux.scala:30:73]
wire _issue_entry_T_6365 = _issue_entry_T_6364 | _issue_entry_T_6362; // @[Mux.scala:30:73]
assign _issue_entry_WIRE_428 = _issue_entry_T_6365; // @[Mux.scala:30:73]
assign issue_entry_2_valid = _issue_entry_WIRE_428; // @[Mux.scala:30:73]
wire _io_issue_st_valid_T = issue_valids_0_2 | issue_valids_1_2; // @[ReservationStation.scala:395:72, :404:38]
wire _io_issue_st_valid_T_1 = _io_issue_st_valid_T | issue_valids_2_2; // @[ReservationStation.scala:395:72, :404:38]
assign _io_issue_st_valid_T_2 = _io_issue_st_valid_T_1 | issue_valids_3_2; // @[ReservationStation.scala:395:72, :404:38]
assign io_issue_st_valid_0 = _io_issue_st_valid_T_2; // @[ReservationStation.scala:26:7, :404:38]
wire _T_5014 = io_issue_st_valid_0 & io_issue_st_ready_0; // @[ReservationStation.scala:22:20, :26:7]
wire _entries_st_0_valid_T = ~entries_st_0_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22]
wire _entries_st_1_valid_T = ~entries_st_1_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22]
wire _entries_st_2_valid_T = ~entries_st_2_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22]
wire _entries_st_3_valid_T = ~entries_st_3_bits_complete_on_issue; // @[ReservationStation.scala:119:23, :417:22]
wire [3:0] _GEN_99 = {{entries_st_3_bits_complete_on_issue}, {entries_st_2_bits_complete_on_issue}, {entries_st_1_bits_complete_on_issue}, {entries_st_0_bits_complete_on_issue}}; // @[ReservationStation.scala:119:23, :440:71]
wire [3:0] _GEN_100 = {{entries_st_3_bits_cmd_from_conv_fsm}, {entries_st_2_bits_cmd_from_conv_fsm}, {entries_st_1_bits_cmd_from_conv_fsm}, {entries_st_0_bits_cmd_from_conv_fsm}}; // @[ReservationStation.scala:119:23, :440:71]
wire _GEN_101 = _GEN_99[issue_id_2] & _GEN_100[issue_id_2]; // @[OneHot.scala:32:10]
wire _conv_ld_issue_completed_T_2; // @[ReservationStation.scala:440:71]
assign _conv_ld_issue_completed_T_2 = _GEN_101; // @[ReservationStation.scala:440:71]
wire _conv_st_issue_completed_T_2; // @[ReservationStation.scala:441:71]
assign _conv_st_issue_completed_T_2 = _GEN_101; // @[ReservationStation.scala:440:71, :441:71]
wire _conv_ex_issue_completed_T_2; // @[ReservationStation.scala:442:71]
assign _conv_ex_issue_completed_T_2 = _GEN_101; // @[ReservationStation.scala:440:71, :442:71]
assign conv_st_issue_completed = _T_5014 & _conv_st_issue_completed_T_2; // @[ReservationStation.scala:22:20, :139:41, :413:20, :441:{24,71}]
wire [3:0] _GEN_102 = {{entries_st_3_bits_cmd_from_matmul_fsm}, {entries_st_2_bits_cmd_from_matmul_fsm}, {entries_st_1_bits_cmd_from_matmul_fsm}, {entries_st_0_bits_cmd_from_matmul_fsm}}; // @[ReservationStation.scala:119:23, :444:73]
wire _GEN_103 = _GEN_99[issue_id_2] & _GEN_102[issue_id_2]; // @[OneHot.scala:32:10]
wire _matmul_ld_issue_completed_T_2; // @[ReservationStation.scala:444:73]
assign _matmul_ld_issue_completed_T_2 = _GEN_103; // @[ReservationStation.scala:444:73]
wire _matmul_st_issue_completed_T_2; // @[ReservationStation.scala:445:73]
assign _matmul_st_issue_completed_T_2 = _GEN_103; // @[ReservationStation.scala:444:73, :445:73]
wire _matmul_ex_issue_completed_T_2; // @[ReservationStation.scala:446:73]
assign _matmul_ex_issue_completed_T_2 = _GEN_103; // @[ReservationStation.scala:444:73, :446:73]
assign matmul_st_issue_completed = _T_5014 & _matmul_st_issue_completed_T_2; // @[ReservationStation.scala:22:20, :147:43, :413:20, :445:{24,73}]
wire [1:0] queue_type = io_completed_bits_0[5:4]; // @[ReservationStation.scala:26:7, :453:39]
wire [3:0] issue_id_3 = io_completed_bits_0[3:0]; // @[ReservationStation.scala:26:7, :454:37]
wire _GEN_104 = io_completed_valid_0 & ~(|queue_type); // @[ReservationStation.scala:26:7, :453:39, :456:{22,31}]
wire [2:0] _conv_ld_completed_T = issue_id_3[2:0]; // @[ReservationStation.scala:454:37]
wire [2:0] _matmul_ld_completed_T = issue_id_3[2:0]; // @[ReservationStation.scala:454:37]
assign conv_ld_completed = _GEN_104 & _GEN_90[_conv_ld_completed_T]; // @[ReservationStation.scala:142:35, :440:71, :451:28, :456:31, :460:25]
assign matmul_ld_completed = _GEN_104 & _GEN_92[_matmul_ld_completed_T]; // @[ReservationStation.scala:150:37, :444:73, :451:28, :456:31, :461:27]
wire _GEN_105 = _GEN_104 & ~reset; // @[ReservationStation.scala:456:31, :463:13]
wire _GEN_106 = _GEN_56[issue_id_3[2:0]]; // @[ReservationStation.scala:357:17, :454:37, :463:13]
wire _GEN_107 = io_completed_valid_0 & (|queue_type); // @[ReservationStation.scala:26:7, :453:39, :456:{22,31}]
wire _T_4971 = queue_type == 2'h1; // @[ReservationStation.scala:453:39, :464:28]
assign conv_ex_completed = io_completed_valid_0 & (|queue_type) & _T_4971 & _GEN_95[issue_id_3]; // @[ReservationStation.scala:26:7, :144:35, :440:71, :451:28, :453:39, :454:37, :456:{22,31}, :464:{28,37}, :466:34, :468:25]
assign matmul_ex_completed = io_completed_valid_0 & (|queue_type) & _T_4971 & _GEN_97[issue_id_3]; // @[ReservationStation.scala:26:7, :152:37, :444:73, :451:28, :453:39, :454:37, :456:{22,31}, :464:{28,37}, :466:34, :469:27]
wire _GEN_108 = _GEN_107 & _T_4971 & ~reset; // @[ReservationStation.scala:456:31, :464:{28,37}, :471:13]
wire _GEN_109 = _GEN_107 & queue_type != 2'h1; // @[ReservationStation.scala:453:39, :456:31, :464:{28,37}]
wire _T_4975 = queue_type == 2'h2; // @[ReservationStation.scala:453:39, :472:28]
wire [1:0] _conv_st_completed_T = issue_id_3[1:0]; // @[ReservationStation.scala:454:37]
wire [1:0] _matmul_st_completed_T = issue_id_3[1:0]; // @[ReservationStation.scala:454:37]
wire _GEN_110 = ~(|queue_type) | _T_4971; // @[ReservationStation.scala:413:20, :453:39, :456:{22,31}, :464:{28,37}, :472:37]
assign conv_st_completed = io_completed_valid_0 & ~_GEN_110 & _T_4975 & _GEN_100[_conv_st_completed_T]; // @[ReservationStation.scala:26:7, :143:35, :413:20, :440:71, :451:28, :456:31, :464:37, :472:{28,37}, :476:25]
assign matmul_st_completed = io_completed_valid_0 & ~_GEN_110 & _T_4975 & _GEN_102[_matmul_st_completed_T]; // @[ReservationStation.scala:26:7, :143:35, :151:37, :413:20, :444:73, :451:28, :456:31, :464:37, :472:{28,37}, :477:27]
wire _GEN_111 = _GEN_109 & _T_4975 & ~reset; // @[ReservationStation.scala:464:37, :472:{28,37}, :479:13]
wire _GEN_112 = _GEN_84[issue_id_3[1:0]]; // @[ReservationStation.scala:357:17, :454:37, :479:13]
wire _utilization_ld_q_unissued_T = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_1 = entries_ld_0_valid & _utilization_ld_q_unissued_T; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_2 = entries_ld_0_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_3 = _utilization_ld_q_unissued_T_1 & _utilization_ld_q_unissued_T_2; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_4 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_5 = entries_ld_1_valid & _utilization_ld_q_unissued_T_4; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_6 = entries_ld_1_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_7 = _utilization_ld_q_unissued_T_5 & _utilization_ld_q_unissued_T_6; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_8 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_9 = entries_ld_2_valid & _utilization_ld_q_unissued_T_8; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_10 = entries_ld_2_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_11 = _utilization_ld_q_unissued_T_9 & _utilization_ld_q_unissued_T_10; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_12 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_13 = entries_ld_3_valid & _utilization_ld_q_unissued_T_12; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_14 = entries_ld_3_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_15 = _utilization_ld_q_unissued_T_13 & _utilization_ld_q_unissued_T_14; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_16 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_17 = entries_ld_4_valid & _utilization_ld_q_unissued_T_16; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_18 = entries_ld_4_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_19 = _utilization_ld_q_unissued_T_17 & _utilization_ld_q_unissued_T_18; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_20 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_21 = entries_ld_5_valid & _utilization_ld_q_unissued_T_20; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_22 = entries_ld_5_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_23 = _utilization_ld_q_unissued_T_21 & _utilization_ld_q_unissued_T_22; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_24 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_25 = entries_ld_6_valid & _utilization_ld_q_unissued_T_24; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_26 = entries_ld_6_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_27 = _utilization_ld_q_unissued_T_25 & _utilization_ld_q_unissued_T_26; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_28 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_29 = entries_ld_7_valid & _utilization_ld_q_unissued_T_28; // @[ReservationStation.scala:117:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_30 = entries_ld_7_bits_q == 2'h0; // @[ReservationStation.scala:117:23, :495:99]
wire _utilization_ld_q_unissued_T_31 = _utilization_ld_q_unissued_T_29 & _utilization_ld_q_unissued_T_30; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_32 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_33 = entries_ex_0_valid & _utilization_ld_q_unissued_T_32; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_34 = entries_ex_0_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_35 = _utilization_ld_q_unissued_T_33 & _utilization_ld_q_unissued_T_34; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_36 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_37 = entries_ex_1_valid & _utilization_ld_q_unissued_T_36; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_38 = entries_ex_1_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_39 = _utilization_ld_q_unissued_T_37 & _utilization_ld_q_unissued_T_38; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_40 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_41 = entries_ex_2_valid & _utilization_ld_q_unissued_T_40; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_42 = entries_ex_2_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_43 = _utilization_ld_q_unissued_T_41 & _utilization_ld_q_unissued_T_42; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_44 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_45 = entries_ex_3_valid & _utilization_ld_q_unissued_T_44; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_46 = entries_ex_3_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_47 = _utilization_ld_q_unissued_T_45 & _utilization_ld_q_unissued_T_46; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_48 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_49 = entries_ex_4_valid & _utilization_ld_q_unissued_T_48; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_50 = entries_ex_4_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_51 = _utilization_ld_q_unissued_T_49 & _utilization_ld_q_unissued_T_50; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_52 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_53 = entries_ex_5_valid & _utilization_ld_q_unissued_T_52; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_54 = entries_ex_5_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_55 = _utilization_ld_q_unissued_T_53 & _utilization_ld_q_unissued_T_54; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_56 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_57 = entries_ex_6_valid & _utilization_ld_q_unissued_T_56; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_58 = entries_ex_6_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_59 = _utilization_ld_q_unissued_T_57 & _utilization_ld_q_unissued_T_58; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_60 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_61 = entries_ex_7_valid & _utilization_ld_q_unissued_T_60; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_62 = entries_ex_7_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_63 = _utilization_ld_q_unissued_T_61 & _utilization_ld_q_unissued_T_62; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_64 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_65 = entries_ex_8_valid & _utilization_ld_q_unissued_T_64; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_66 = entries_ex_8_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_67 = _utilization_ld_q_unissued_T_65 & _utilization_ld_q_unissued_T_66; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_68 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_69 = entries_ex_9_valid & _utilization_ld_q_unissued_T_68; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_70 = entries_ex_9_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_71 = _utilization_ld_q_unissued_T_69 & _utilization_ld_q_unissued_T_70; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_72 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_73 = entries_ex_10_valid & _utilization_ld_q_unissued_T_72; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_74 = entries_ex_10_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_75 = _utilization_ld_q_unissued_T_73 & _utilization_ld_q_unissued_T_74; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_76 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_77 = entries_ex_11_valid & _utilization_ld_q_unissued_T_76; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_78 = entries_ex_11_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_79 = _utilization_ld_q_unissued_T_77 & _utilization_ld_q_unissued_T_78; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_80 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_81 = entries_ex_12_valid & _utilization_ld_q_unissued_T_80; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_82 = entries_ex_12_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_83 = _utilization_ld_q_unissued_T_81 & _utilization_ld_q_unissued_T_82; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_84 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_85 = entries_ex_13_valid & _utilization_ld_q_unissued_T_84; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_86 = entries_ex_13_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_87 = _utilization_ld_q_unissued_T_85 & _utilization_ld_q_unissued_T_86; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_88 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_89 = entries_ex_14_valid & _utilization_ld_q_unissued_T_88; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_90 = entries_ex_14_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_91 = _utilization_ld_q_unissued_T_89 & _utilization_ld_q_unissued_T_90; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_92 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_93 = entries_ex_15_valid & _utilization_ld_q_unissued_T_92; // @[ReservationStation.scala:118:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_94 = entries_ex_15_bits_q == 2'h0; // @[ReservationStation.scala:118:23, :495:99]
wire _utilization_ld_q_unissued_T_95 = _utilization_ld_q_unissued_T_93 & _utilization_ld_q_unissued_T_94; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_96 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_97 = entries_st_0_valid & _utilization_ld_q_unissued_T_96; // @[ReservationStation.scala:119:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_98 = entries_st_0_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99]
wire _utilization_ld_q_unissued_T_99 = _utilization_ld_q_unissued_T_97 & _utilization_ld_q_unissued_T_98; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_100 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_101 = entries_st_1_valid & _utilization_ld_q_unissued_T_100; // @[ReservationStation.scala:119:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_102 = entries_st_1_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99]
wire _utilization_ld_q_unissued_T_103 = _utilization_ld_q_unissued_T_101 & _utilization_ld_q_unissued_T_102; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_104 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_105 = entries_st_2_valid & _utilization_ld_q_unissued_T_104; // @[ReservationStation.scala:119:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_106 = entries_st_2_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99]
wire _utilization_ld_q_unissued_T_107 = _utilization_ld_q_unissued_T_105 & _utilization_ld_q_unissued_T_106; // @[ReservationStation.scala:495:{69,87,99}]
wire _utilization_ld_q_unissued_T_108 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :495:72]
wire _utilization_ld_q_unissued_T_109 = entries_st_3_valid & _utilization_ld_q_unissued_T_108; // @[ReservationStation.scala:119:23, :495:{69,72}]
wire _utilization_ld_q_unissued_T_110 = entries_st_3_bits_q == 2'h0; // @[ReservationStation.scala:119:23, :495:99]
wire _utilization_ld_q_unissued_T_111 = _utilization_ld_q_unissued_T_109 & _utilization_ld_q_unissued_T_110; // @[ReservationStation.scala:495:{69,87,99}]
wire [1:0] _utilization_ld_q_unissued_T_112 = {1'h0, _utilization_ld_q_unissued_T_7} + {1'h0, _utilization_ld_q_unissued_T_11}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_113 = _utilization_ld_q_unissued_T_112; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_114 = {2'h0, _utilization_ld_q_unissued_T_3} + {1'h0, _utilization_ld_q_unissued_T_113}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_115 = _utilization_ld_q_unissued_T_114[1:0]; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_116 = {1'h0, _utilization_ld_q_unissued_T_15} + {1'h0, _utilization_ld_q_unissued_T_19}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_117 = _utilization_ld_q_unissued_T_116; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_118 = {1'h0, _utilization_ld_q_unissued_T_23} + {1'h0, _utilization_ld_q_unissued_T_27}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_119 = _utilization_ld_q_unissued_T_118; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_120 = {1'h0, _utilization_ld_q_unissued_T_117} + {1'h0, _utilization_ld_q_unissued_T_119}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_121 = _utilization_ld_q_unissued_T_120; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_122 = {2'h0, _utilization_ld_q_unissued_T_115} + {1'h0, _utilization_ld_q_unissued_T_121}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_123 = _utilization_ld_q_unissued_T_122[2:0]; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_124 = {1'h0, _utilization_ld_q_unissued_T_35} + {1'h0, _utilization_ld_q_unissued_T_39}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_125 = _utilization_ld_q_unissued_T_124; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_126 = {2'h0, _utilization_ld_q_unissued_T_31} + {1'h0, _utilization_ld_q_unissued_T_125}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_127 = _utilization_ld_q_unissued_T_126[1:0]; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_128 = {1'h0, _utilization_ld_q_unissued_T_43} + {1'h0, _utilization_ld_q_unissued_T_47}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_129 = _utilization_ld_q_unissued_T_128; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_130 = {1'h0, _utilization_ld_q_unissued_T_51} + {1'h0, _utilization_ld_q_unissued_T_55}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_131 = _utilization_ld_q_unissued_T_130; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_132 = {1'h0, _utilization_ld_q_unissued_T_129} + {1'h0, _utilization_ld_q_unissued_T_131}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_133 = _utilization_ld_q_unissued_T_132; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_134 = {2'h0, _utilization_ld_q_unissued_T_127} + {1'h0, _utilization_ld_q_unissued_T_133}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_135 = _utilization_ld_q_unissued_T_134[2:0]; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_136 = {1'h0, _utilization_ld_q_unissued_T_123} + {1'h0, _utilization_ld_q_unissued_T_135}; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_137 = _utilization_ld_q_unissued_T_136; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_138 = {1'h0, _utilization_ld_q_unissued_T_63} + {1'h0, _utilization_ld_q_unissued_T_67}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_139 = _utilization_ld_q_unissued_T_138; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_140 = {2'h0, _utilization_ld_q_unissued_T_59} + {1'h0, _utilization_ld_q_unissued_T_139}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_141 = _utilization_ld_q_unissued_T_140[1:0]; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_142 = {1'h0, _utilization_ld_q_unissued_T_71} + {1'h0, _utilization_ld_q_unissued_T_75}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_143 = _utilization_ld_q_unissued_T_142; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_144 = {1'h0, _utilization_ld_q_unissued_T_79} + {1'h0, _utilization_ld_q_unissued_T_83}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_145 = _utilization_ld_q_unissued_T_144; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_146 = {1'h0, _utilization_ld_q_unissued_T_143} + {1'h0, _utilization_ld_q_unissued_T_145}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_147 = _utilization_ld_q_unissued_T_146; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_148 = {2'h0, _utilization_ld_q_unissued_T_141} + {1'h0, _utilization_ld_q_unissued_T_147}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_149 = _utilization_ld_q_unissued_T_148[2:0]; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_150 = {1'h0, _utilization_ld_q_unissued_T_91} + {1'h0, _utilization_ld_q_unissued_T_95}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_151 = _utilization_ld_q_unissued_T_150; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_152 = {2'h0, _utilization_ld_q_unissued_T_87} + {1'h0, _utilization_ld_q_unissued_T_151}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_153 = _utilization_ld_q_unissued_T_152[1:0]; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_154 = {1'h0, _utilization_ld_q_unissued_T_99} + {1'h0, _utilization_ld_q_unissued_T_103}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_155 = _utilization_ld_q_unissued_T_154; // @[ReservationStation.scala:495:43]
wire [1:0] _utilization_ld_q_unissued_T_156 = {1'h0, _utilization_ld_q_unissued_T_107} + {1'h0, _utilization_ld_q_unissued_T_111}; // @[ReservationStation.scala:495:{43,87}]
wire [1:0] _utilization_ld_q_unissued_T_157 = _utilization_ld_q_unissued_T_156; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_158 = {1'h0, _utilization_ld_q_unissued_T_155} + {1'h0, _utilization_ld_q_unissued_T_157}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_159 = _utilization_ld_q_unissued_T_158; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_160 = {2'h0, _utilization_ld_q_unissued_T_153} + {1'h0, _utilization_ld_q_unissued_T_159}; // @[ReservationStation.scala:495:43]
wire [2:0] _utilization_ld_q_unissued_T_161 = _utilization_ld_q_unissued_T_160[2:0]; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_162 = {1'h0, _utilization_ld_q_unissued_T_149} + {1'h0, _utilization_ld_q_unissued_T_161}; // @[ReservationStation.scala:495:43]
wire [3:0] _utilization_ld_q_unissued_T_163 = _utilization_ld_q_unissued_T_162; // @[ReservationStation.scala:495:43]
wire [4:0] _utilization_ld_q_unissued_T_164 = {1'h0, _utilization_ld_q_unissued_T_137} + {1'h0, _utilization_ld_q_unissued_T_163}; // @[ReservationStation.scala:495:43]
wire [4:0] utilization_ld_q_unissued = _utilization_ld_q_unissued_T_164; // @[ReservationStation.scala:495:43]
wire _utilization_st_q_unissued_T = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_1 = entries_ld_0_valid & _utilization_st_q_unissued_T; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_2 = entries_ld_0_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_3 = _utilization_st_q_unissued_T_1 & _utilization_st_q_unissued_T_2; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_4 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_5 = entries_ld_1_valid & _utilization_st_q_unissued_T_4; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_6 = entries_ld_1_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_7 = _utilization_st_q_unissued_T_5 & _utilization_st_q_unissued_T_6; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_8 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_9 = entries_ld_2_valid & _utilization_st_q_unissued_T_8; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_10 = entries_ld_2_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_11 = _utilization_st_q_unissued_T_9 & _utilization_st_q_unissued_T_10; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_12 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_13 = entries_ld_3_valid & _utilization_st_q_unissued_T_12; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_14 = entries_ld_3_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_15 = _utilization_st_q_unissued_T_13 & _utilization_st_q_unissued_T_14; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_16 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_17 = entries_ld_4_valid & _utilization_st_q_unissued_T_16; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_18 = entries_ld_4_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_19 = _utilization_st_q_unissued_T_17 & _utilization_st_q_unissued_T_18; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_20 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_21 = entries_ld_5_valid & _utilization_st_q_unissued_T_20; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_22 = entries_ld_5_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_23 = _utilization_st_q_unissued_T_21 & _utilization_st_q_unissued_T_22; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_24 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_25 = entries_ld_6_valid & _utilization_st_q_unissued_T_24; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_26 = entries_ld_6_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_27 = _utilization_st_q_unissued_T_25 & _utilization_st_q_unissued_T_26; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_28 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_29 = entries_ld_7_valid & _utilization_st_q_unissued_T_28; // @[ReservationStation.scala:117:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_30 = entries_ld_7_bits_q == 2'h2; // @[ReservationStation.scala:117:23, :496:99]
wire _utilization_st_q_unissued_T_31 = _utilization_st_q_unissued_T_29 & _utilization_st_q_unissued_T_30; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_32 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_33 = entries_ex_0_valid & _utilization_st_q_unissued_T_32; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_34 = entries_ex_0_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_35 = _utilization_st_q_unissued_T_33 & _utilization_st_q_unissued_T_34; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_36 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_37 = entries_ex_1_valid & _utilization_st_q_unissued_T_36; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_38 = entries_ex_1_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_39 = _utilization_st_q_unissued_T_37 & _utilization_st_q_unissued_T_38; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_40 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_41 = entries_ex_2_valid & _utilization_st_q_unissued_T_40; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_42 = entries_ex_2_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_43 = _utilization_st_q_unissued_T_41 & _utilization_st_q_unissued_T_42; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_44 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_45 = entries_ex_3_valid & _utilization_st_q_unissued_T_44; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_46 = entries_ex_3_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_47 = _utilization_st_q_unissued_T_45 & _utilization_st_q_unissued_T_46; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_48 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_49 = entries_ex_4_valid & _utilization_st_q_unissued_T_48; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_50 = entries_ex_4_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_51 = _utilization_st_q_unissued_T_49 & _utilization_st_q_unissued_T_50; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_52 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_53 = entries_ex_5_valid & _utilization_st_q_unissued_T_52; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_54 = entries_ex_5_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_55 = _utilization_st_q_unissued_T_53 & _utilization_st_q_unissued_T_54; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_56 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_57 = entries_ex_6_valid & _utilization_st_q_unissued_T_56; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_58 = entries_ex_6_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_59 = _utilization_st_q_unissued_T_57 & _utilization_st_q_unissued_T_58; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_60 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_61 = entries_ex_7_valid & _utilization_st_q_unissued_T_60; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_62 = entries_ex_7_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_63 = _utilization_st_q_unissued_T_61 & _utilization_st_q_unissued_T_62; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_64 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_65 = entries_ex_8_valid & _utilization_st_q_unissued_T_64; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_66 = entries_ex_8_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_67 = _utilization_st_q_unissued_T_65 & _utilization_st_q_unissued_T_66; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_68 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_69 = entries_ex_9_valid & _utilization_st_q_unissued_T_68; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_70 = entries_ex_9_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_71 = _utilization_st_q_unissued_T_69 & _utilization_st_q_unissued_T_70; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_72 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_73 = entries_ex_10_valid & _utilization_st_q_unissued_T_72; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_74 = entries_ex_10_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_75 = _utilization_st_q_unissued_T_73 & _utilization_st_q_unissued_T_74; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_76 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_77 = entries_ex_11_valid & _utilization_st_q_unissued_T_76; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_78 = entries_ex_11_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_79 = _utilization_st_q_unissued_T_77 & _utilization_st_q_unissued_T_78; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_80 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_81 = entries_ex_12_valid & _utilization_st_q_unissued_T_80; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_82 = entries_ex_12_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_83 = _utilization_st_q_unissued_T_81 & _utilization_st_q_unissued_T_82; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_84 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_85 = entries_ex_13_valid & _utilization_st_q_unissued_T_84; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_86 = entries_ex_13_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_87 = _utilization_st_q_unissued_T_85 & _utilization_st_q_unissued_T_86; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_88 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_89 = entries_ex_14_valid & _utilization_st_q_unissued_T_88; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_90 = entries_ex_14_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_91 = _utilization_st_q_unissued_T_89 & _utilization_st_q_unissued_T_90; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_92 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_93 = entries_ex_15_valid & _utilization_st_q_unissued_T_92; // @[ReservationStation.scala:118:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_94 = entries_ex_15_bits_q == 2'h2; // @[ReservationStation.scala:118:23, :496:99]
wire _utilization_st_q_unissued_T_95 = _utilization_st_q_unissued_T_93 & _utilization_st_q_unissued_T_94; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_96 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_97 = entries_st_0_valid & _utilization_st_q_unissued_T_96; // @[ReservationStation.scala:119:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_98 = entries_st_0_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99]
wire _utilization_st_q_unissued_T_99 = _utilization_st_q_unissued_T_97 & _utilization_st_q_unissued_T_98; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_100 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_101 = entries_st_1_valid & _utilization_st_q_unissued_T_100; // @[ReservationStation.scala:119:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_102 = entries_st_1_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99]
wire _utilization_st_q_unissued_T_103 = _utilization_st_q_unissued_T_101 & _utilization_st_q_unissued_T_102; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_104 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_105 = entries_st_2_valid & _utilization_st_q_unissued_T_104; // @[ReservationStation.scala:119:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_106 = entries_st_2_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99]
wire _utilization_st_q_unissued_T_107 = _utilization_st_q_unissued_T_105 & _utilization_st_q_unissued_T_106; // @[ReservationStation.scala:496:{69,87,99}]
wire _utilization_st_q_unissued_T_108 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :496:72]
wire _utilization_st_q_unissued_T_109 = entries_st_3_valid & _utilization_st_q_unissued_T_108; // @[ReservationStation.scala:119:23, :496:{69,72}]
wire _utilization_st_q_unissued_T_110 = entries_st_3_bits_q == 2'h2; // @[ReservationStation.scala:119:23, :496:99]
wire _utilization_st_q_unissued_T_111 = _utilization_st_q_unissued_T_109 & _utilization_st_q_unissued_T_110; // @[ReservationStation.scala:496:{69,87,99}]
wire [1:0] _utilization_st_q_unissued_T_112 = {1'h0, _utilization_st_q_unissued_T_7} + {1'h0, _utilization_st_q_unissued_T_11}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_113 = _utilization_st_q_unissued_T_112; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_114 = {2'h0, _utilization_st_q_unissued_T_3} + {1'h0, _utilization_st_q_unissued_T_113}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_115 = _utilization_st_q_unissued_T_114[1:0]; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_116 = {1'h0, _utilization_st_q_unissued_T_15} + {1'h0, _utilization_st_q_unissued_T_19}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_117 = _utilization_st_q_unissued_T_116; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_118 = {1'h0, _utilization_st_q_unissued_T_23} + {1'h0, _utilization_st_q_unissued_T_27}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_119 = _utilization_st_q_unissued_T_118; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_120 = {1'h0, _utilization_st_q_unissued_T_117} + {1'h0, _utilization_st_q_unissued_T_119}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_121 = _utilization_st_q_unissued_T_120; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_122 = {2'h0, _utilization_st_q_unissued_T_115} + {1'h0, _utilization_st_q_unissued_T_121}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_123 = _utilization_st_q_unissued_T_122[2:0]; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_124 = {1'h0, _utilization_st_q_unissued_T_35} + {1'h0, _utilization_st_q_unissued_T_39}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_125 = _utilization_st_q_unissued_T_124; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_126 = {2'h0, _utilization_st_q_unissued_T_31} + {1'h0, _utilization_st_q_unissued_T_125}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_127 = _utilization_st_q_unissued_T_126[1:0]; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_128 = {1'h0, _utilization_st_q_unissued_T_43} + {1'h0, _utilization_st_q_unissued_T_47}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_129 = _utilization_st_q_unissued_T_128; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_130 = {1'h0, _utilization_st_q_unissued_T_51} + {1'h0, _utilization_st_q_unissued_T_55}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_131 = _utilization_st_q_unissued_T_130; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_132 = {1'h0, _utilization_st_q_unissued_T_129} + {1'h0, _utilization_st_q_unissued_T_131}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_133 = _utilization_st_q_unissued_T_132; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_134 = {2'h0, _utilization_st_q_unissued_T_127} + {1'h0, _utilization_st_q_unissued_T_133}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_135 = _utilization_st_q_unissued_T_134[2:0]; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_136 = {1'h0, _utilization_st_q_unissued_T_123} + {1'h0, _utilization_st_q_unissued_T_135}; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_137 = _utilization_st_q_unissued_T_136; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_138 = {1'h0, _utilization_st_q_unissued_T_63} + {1'h0, _utilization_st_q_unissued_T_67}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_139 = _utilization_st_q_unissued_T_138; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_140 = {2'h0, _utilization_st_q_unissued_T_59} + {1'h0, _utilization_st_q_unissued_T_139}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_141 = _utilization_st_q_unissued_T_140[1:0]; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_142 = {1'h0, _utilization_st_q_unissued_T_71} + {1'h0, _utilization_st_q_unissued_T_75}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_143 = _utilization_st_q_unissued_T_142; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_144 = {1'h0, _utilization_st_q_unissued_T_79} + {1'h0, _utilization_st_q_unissued_T_83}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_145 = _utilization_st_q_unissued_T_144; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_146 = {1'h0, _utilization_st_q_unissued_T_143} + {1'h0, _utilization_st_q_unissued_T_145}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_147 = _utilization_st_q_unissued_T_146; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_148 = {2'h0, _utilization_st_q_unissued_T_141} + {1'h0, _utilization_st_q_unissued_T_147}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_149 = _utilization_st_q_unissued_T_148[2:0]; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_150 = {1'h0, _utilization_st_q_unissued_T_91} + {1'h0, _utilization_st_q_unissued_T_95}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_151 = _utilization_st_q_unissued_T_150; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_152 = {2'h0, _utilization_st_q_unissued_T_87} + {1'h0, _utilization_st_q_unissued_T_151}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_153 = _utilization_st_q_unissued_T_152[1:0]; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_154 = {1'h0, _utilization_st_q_unissued_T_99} + {1'h0, _utilization_st_q_unissued_T_103}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_155 = _utilization_st_q_unissued_T_154; // @[ReservationStation.scala:496:43]
wire [1:0] _utilization_st_q_unissued_T_156 = {1'h0, _utilization_st_q_unissued_T_107} + {1'h0, _utilization_st_q_unissued_T_111}; // @[ReservationStation.scala:496:{43,87}]
wire [1:0] _utilization_st_q_unissued_T_157 = _utilization_st_q_unissued_T_156; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_158 = {1'h0, _utilization_st_q_unissued_T_155} + {1'h0, _utilization_st_q_unissued_T_157}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_159 = _utilization_st_q_unissued_T_158; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_160 = {2'h0, _utilization_st_q_unissued_T_153} + {1'h0, _utilization_st_q_unissued_T_159}; // @[ReservationStation.scala:496:43]
wire [2:0] _utilization_st_q_unissued_T_161 = _utilization_st_q_unissued_T_160[2:0]; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_162 = {1'h0, _utilization_st_q_unissued_T_149} + {1'h0, _utilization_st_q_unissued_T_161}; // @[ReservationStation.scala:496:43]
wire [3:0] _utilization_st_q_unissued_T_163 = _utilization_st_q_unissued_T_162; // @[ReservationStation.scala:496:43]
wire [4:0] _utilization_st_q_unissued_T_164 = {1'h0, _utilization_st_q_unissued_T_137} + {1'h0, _utilization_st_q_unissued_T_163}; // @[ReservationStation.scala:496:43]
wire [4:0] utilization_st_q_unissued = _utilization_st_q_unissued_T_164; // @[ReservationStation.scala:496:43]
wire _utilization_ex_q_unissued_T = ~entries_ld_0_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_1 = entries_ld_0_valid & _utilization_ex_q_unissued_T; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_2 = entries_ld_0_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_3 = _utilization_ex_q_unissued_T_1 & _utilization_ex_q_unissued_T_2; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_4 = ~entries_ld_1_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_5 = entries_ld_1_valid & _utilization_ex_q_unissued_T_4; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_6 = entries_ld_1_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_7 = _utilization_ex_q_unissued_T_5 & _utilization_ex_q_unissued_T_6; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_8 = ~entries_ld_2_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_9 = entries_ld_2_valid & _utilization_ex_q_unissued_T_8; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_10 = entries_ld_2_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_11 = _utilization_ex_q_unissued_T_9 & _utilization_ex_q_unissued_T_10; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_12 = ~entries_ld_3_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_13 = entries_ld_3_valid & _utilization_ex_q_unissued_T_12; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_14 = entries_ld_3_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_15 = _utilization_ex_q_unissued_T_13 & _utilization_ex_q_unissued_T_14; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_16 = ~entries_ld_4_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_17 = entries_ld_4_valid & _utilization_ex_q_unissued_T_16; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_18 = entries_ld_4_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_19 = _utilization_ex_q_unissued_T_17 & _utilization_ex_q_unissued_T_18; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_20 = ~entries_ld_5_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_21 = entries_ld_5_valid & _utilization_ex_q_unissued_T_20; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_22 = entries_ld_5_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_23 = _utilization_ex_q_unissued_T_21 & _utilization_ex_q_unissued_T_22; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_24 = ~entries_ld_6_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_25 = entries_ld_6_valid & _utilization_ex_q_unissued_T_24; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_26 = entries_ld_6_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_27 = _utilization_ex_q_unissued_T_25 & _utilization_ex_q_unissued_T_26; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_28 = ~entries_ld_7_bits_issued; // @[ReservationStation.scala:117:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_29 = entries_ld_7_valid & _utilization_ex_q_unissued_T_28; // @[ReservationStation.scala:117:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_30 = entries_ld_7_bits_q == 2'h1; // @[ReservationStation.scala:117:23, :497:99]
wire _utilization_ex_q_unissued_T_31 = _utilization_ex_q_unissued_T_29 & _utilization_ex_q_unissued_T_30; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_32 = ~entries_ex_0_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_33 = entries_ex_0_valid & _utilization_ex_q_unissued_T_32; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_34 = entries_ex_0_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_35 = _utilization_ex_q_unissued_T_33 & _utilization_ex_q_unissued_T_34; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_36 = ~entries_ex_1_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_37 = entries_ex_1_valid & _utilization_ex_q_unissued_T_36; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_38 = entries_ex_1_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_39 = _utilization_ex_q_unissued_T_37 & _utilization_ex_q_unissued_T_38; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_40 = ~entries_ex_2_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_41 = entries_ex_2_valid & _utilization_ex_q_unissued_T_40; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_42 = entries_ex_2_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_43 = _utilization_ex_q_unissued_T_41 & _utilization_ex_q_unissued_T_42; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_44 = ~entries_ex_3_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_45 = entries_ex_3_valid & _utilization_ex_q_unissued_T_44; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_46 = entries_ex_3_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_47 = _utilization_ex_q_unissued_T_45 & _utilization_ex_q_unissued_T_46; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_48 = ~entries_ex_4_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_49 = entries_ex_4_valid & _utilization_ex_q_unissued_T_48; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_50 = entries_ex_4_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_51 = _utilization_ex_q_unissued_T_49 & _utilization_ex_q_unissued_T_50; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_52 = ~entries_ex_5_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_53 = entries_ex_5_valid & _utilization_ex_q_unissued_T_52; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_54 = entries_ex_5_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_55 = _utilization_ex_q_unissued_T_53 & _utilization_ex_q_unissued_T_54; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_56 = ~entries_ex_6_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_57 = entries_ex_6_valid & _utilization_ex_q_unissued_T_56; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_58 = entries_ex_6_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_59 = _utilization_ex_q_unissued_T_57 & _utilization_ex_q_unissued_T_58; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_60 = ~entries_ex_7_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_61 = entries_ex_7_valid & _utilization_ex_q_unissued_T_60; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_62 = entries_ex_7_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_63 = _utilization_ex_q_unissued_T_61 & _utilization_ex_q_unissued_T_62; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_64 = ~entries_ex_8_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_65 = entries_ex_8_valid & _utilization_ex_q_unissued_T_64; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_66 = entries_ex_8_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_67 = _utilization_ex_q_unissued_T_65 & _utilization_ex_q_unissued_T_66; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_68 = ~entries_ex_9_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_69 = entries_ex_9_valid & _utilization_ex_q_unissued_T_68; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_70 = entries_ex_9_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_71 = _utilization_ex_q_unissued_T_69 & _utilization_ex_q_unissued_T_70; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_72 = ~entries_ex_10_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_73 = entries_ex_10_valid & _utilization_ex_q_unissued_T_72; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_74 = entries_ex_10_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_75 = _utilization_ex_q_unissued_T_73 & _utilization_ex_q_unissued_T_74; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_76 = ~entries_ex_11_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_77 = entries_ex_11_valid & _utilization_ex_q_unissued_T_76; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_78 = entries_ex_11_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_79 = _utilization_ex_q_unissued_T_77 & _utilization_ex_q_unissued_T_78; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_80 = ~entries_ex_12_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_81 = entries_ex_12_valid & _utilization_ex_q_unissued_T_80; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_82 = entries_ex_12_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_83 = _utilization_ex_q_unissued_T_81 & _utilization_ex_q_unissued_T_82; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_84 = ~entries_ex_13_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_85 = entries_ex_13_valid & _utilization_ex_q_unissued_T_84; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_86 = entries_ex_13_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_87 = _utilization_ex_q_unissued_T_85 & _utilization_ex_q_unissued_T_86; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_88 = ~entries_ex_14_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_89 = entries_ex_14_valid & _utilization_ex_q_unissued_T_88; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_90 = entries_ex_14_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_91 = _utilization_ex_q_unissued_T_89 & _utilization_ex_q_unissued_T_90; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_92 = ~entries_ex_15_bits_issued; // @[ReservationStation.scala:118:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_93 = entries_ex_15_valid & _utilization_ex_q_unissued_T_92; // @[ReservationStation.scala:118:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_94 = entries_ex_15_bits_q == 2'h1; // @[ReservationStation.scala:118:23, :497:99]
wire _utilization_ex_q_unissued_T_95 = _utilization_ex_q_unissued_T_93 & _utilization_ex_q_unissued_T_94; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_96 = ~entries_st_0_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_97 = entries_st_0_valid & _utilization_ex_q_unissued_T_96; // @[ReservationStation.scala:119:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_98 = entries_st_0_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99]
wire _utilization_ex_q_unissued_T_99 = _utilization_ex_q_unissued_T_97 & _utilization_ex_q_unissued_T_98; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_100 = ~entries_st_1_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_101 = entries_st_1_valid & _utilization_ex_q_unissued_T_100; // @[ReservationStation.scala:119:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_102 = entries_st_1_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99]
wire _utilization_ex_q_unissued_T_103 = _utilization_ex_q_unissued_T_101 & _utilization_ex_q_unissued_T_102; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_104 = ~entries_st_2_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_105 = entries_st_2_valid & _utilization_ex_q_unissued_T_104; // @[ReservationStation.scala:119:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_106 = entries_st_2_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99]
wire _utilization_ex_q_unissued_T_107 = _utilization_ex_q_unissued_T_105 & _utilization_ex_q_unissued_T_106; // @[ReservationStation.scala:497:{69,87,99}]
wire _utilization_ex_q_unissued_T_108 = ~entries_st_3_bits_issued; // @[ReservationStation.scala:119:23, :395:75, :497:72]
wire _utilization_ex_q_unissued_T_109 = entries_st_3_valid & _utilization_ex_q_unissued_T_108; // @[ReservationStation.scala:119:23, :497:{69,72}]
wire _utilization_ex_q_unissued_T_110 = entries_st_3_bits_q == 2'h1; // @[ReservationStation.scala:119:23, :497:99]
wire _utilization_ex_q_unissued_T_111 = _utilization_ex_q_unissued_T_109 & _utilization_ex_q_unissued_T_110; // @[ReservationStation.scala:497:{69,87,99}]
wire [1:0] _utilization_ex_q_unissued_T_112 = {1'h0, _utilization_ex_q_unissued_T_7} + {1'h0, _utilization_ex_q_unissued_T_11}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_113 = _utilization_ex_q_unissued_T_112; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_114 = {2'h0, _utilization_ex_q_unissued_T_3} + {1'h0, _utilization_ex_q_unissued_T_113}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_115 = _utilization_ex_q_unissued_T_114[1:0]; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_116 = {1'h0, _utilization_ex_q_unissued_T_15} + {1'h0, _utilization_ex_q_unissued_T_19}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_117 = _utilization_ex_q_unissued_T_116; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_118 = {1'h0, _utilization_ex_q_unissued_T_23} + {1'h0, _utilization_ex_q_unissued_T_27}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_119 = _utilization_ex_q_unissued_T_118; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_120 = {1'h0, _utilization_ex_q_unissued_T_117} + {1'h0, _utilization_ex_q_unissued_T_119}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_121 = _utilization_ex_q_unissued_T_120; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_122 = {2'h0, _utilization_ex_q_unissued_T_115} + {1'h0, _utilization_ex_q_unissued_T_121}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_123 = _utilization_ex_q_unissued_T_122[2:0]; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_124 = {1'h0, _utilization_ex_q_unissued_T_35} + {1'h0, _utilization_ex_q_unissued_T_39}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_125 = _utilization_ex_q_unissued_T_124; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_126 = {2'h0, _utilization_ex_q_unissued_T_31} + {1'h0, _utilization_ex_q_unissued_T_125}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_127 = _utilization_ex_q_unissued_T_126[1:0]; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_128 = {1'h0, _utilization_ex_q_unissued_T_43} + {1'h0, _utilization_ex_q_unissued_T_47}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_129 = _utilization_ex_q_unissued_T_128; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_130 = {1'h0, _utilization_ex_q_unissued_T_51} + {1'h0, _utilization_ex_q_unissued_T_55}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_131 = _utilization_ex_q_unissued_T_130; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_132 = {1'h0, _utilization_ex_q_unissued_T_129} + {1'h0, _utilization_ex_q_unissued_T_131}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_133 = _utilization_ex_q_unissued_T_132; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_134 = {2'h0, _utilization_ex_q_unissued_T_127} + {1'h0, _utilization_ex_q_unissued_T_133}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_135 = _utilization_ex_q_unissued_T_134[2:0]; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_136 = {1'h0, _utilization_ex_q_unissued_T_123} + {1'h0, _utilization_ex_q_unissued_T_135}; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_137 = _utilization_ex_q_unissued_T_136; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_138 = {1'h0, _utilization_ex_q_unissued_T_63} + {1'h0, _utilization_ex_q_unissued_T_67}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_139 = _utilization_ex_q_unissued_T_138; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_140 = {2'h0, _utilization_ex_q_unissued_T_59} + {1'h0, _utilization_ex_q_unissued_T_139}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_141 = _utilization_ex_q_unissued_T_140[1:0]; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_142 = {1'h0, _utilization_ex_q_unissued_T_71} + {1'h0, _utilization_ex_q_unissued_T_75}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_143 = _utilization_ex_q_unissued_T_142; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_144 = {1'h0, _utilization_ex_q_unissued_T_79} + {1'h0, _utilization_ex_q_unissued_T_83}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_145 = _utilization_ex_q_unissued_T_144; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_146 = {1'h0, _utilization_ex_q_unissued_T_143} + {1'h0, _utilization_ex_q_unissued_T_145}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_147 = _utilization_ex_q_unissued_T_146; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_148 = {2'h0, _utilization_ex_q_unissued_T_141} + {1'h0, _utilization_ex_q_unissued_T_147}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_149 = _utilization_ex_q_unissued_T_148[2:0]; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_150 = {1'h0, _utilization_ex_q_unissued_T_91} + {1'h0, _utilization_ex_q_unissued_T_95}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_151 = _utilization_ex_q_unissued_T_150; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_152 = {2'h0, _utilization_ex_q_unissued_T_87} + {1'h0, _utilization_ex_q_unissued_T_151}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_153 = _utilization_ex_q_unissued_T_152[1:0]; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_154 = {1'h0, _utilization_ex_q_unissued_T_99} + {1'h0, _utilization_ex_q_unissued_T_103}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_155 = _utilization_ex_q_unissued_T_154; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ex_q_unissued_T_156 = {1'h0, _utilization_ex_q_unissued_T_107} + {1'h0, _utilization_ex_q_unissued_T_111}; // @[ReservationStation.scala:497:{43,87}]
wire [1:0] _utilization_ex_q_unissued_T_157 = _utilization_ex_q_unissued_T_156; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_158 = {1'h0, _utilization_ex_q_unissued_T_155} + {1'h0, _utilization_ex_q_unissued_T_157}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_159 = _utilization_ex_q_unissued_T_158; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_160 = {2'h0, _utilization_ex_q_unissued_T_153} + {1'h0, _utilization_ex_q_unissued_T_159}; // @[ReservationStation.scala:497:43]
wire [2:0] _utilization_ex_q_unissued_T_161 = _utilization_ex_q_unissued_T_160[2:0]; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_162 = {1'h0, _utilization_ex_q_unissued_T_149} + {1'h0, _utilization_ex_q_unissued_T_161}; // @[ReservationStation.scala:497:43]
wire [3:0] _utilization_ex_q_unissued_T_163 = _utilization_ex_q_unissued_T_162; // @[ReservationStation.scala:497:43]
wire [4:0] _utilization_ex_q_unissued_T_164 = {1'h0, _utilization_ex_q_unissued_T_137} + {1'h0, _utilization_ex_q_unissued_T_163}; // @[ReservationStation.scala:497:43]
wire [4:0] utilization_ex_q_unissued = _utilization_ex_q_unissued_T_164; // @[ReservationStation.scala:497:43]
wire [1:0] _utilization_ld_q_T = {1'h0, entries_ld_0_valid} + _GEN_1; // @[ReservationStation.scala:117:23, :133:29, :498:34]
wire [1:0] _utilization_ld_q_T_1 = _utilization_ld_q_T; // @[ReservationStation.scala:498:34]
wire [1:0] _utilization_ld_q_T_2 = _GEN_2 + _GEN_3; // @[ReservationStation.scala:133:29, :498:34]
wire [1:0] _utilization_ld_q_T_3 = _utilization_ld_q_T_2; // @[ReservationStation.scala:498:34]
wire [2:0] _utilization_ld_q_T_4 = {1'h0, _utilization_ld_q_T_1} + {1'h0, _utilization_ld_q_T_3}; // @[ReservationStation.scala:498:34]
wire [2:0] _utilization_ld_q_T_5 = _utilization_ld_q_T_4; // @[ReservationStation.scala:498:34]
wire [1:0] _utilization_ld_q_T_6 = _GEN_4 + _GEN_5; // @[ReservationStation.scala:133:29, :498:34]
wire [1:0] _utilization_ld_q_T_7 = _utilization_ld_q_T_6; // @[ReservationStation.scala:498:34]
wire [1:0] _utilization_ld_q_T_8 = _GEN_6 + {1'h0, entries_ld_7_valid}; // @[ReservationStation.scala:117:23, :133:29, :498:34]
wire [1:0] _utilization_ld_q_T_9 = _utilization_ld_q_T_8; // @[ReservationStation.scala:498:34]
wire [2:0] _utilization_ld_q_T_10 = {1'h0, _utilization_ld_q_T_7} + {1'h0, _utilization_ld_q_T_9}; // @[ReservationStation.scala:498:34]
wire [2:0] _utilization_ld_q_T_11 = _utilization_ld_q_T_10; // @[ReservationStation.scala:498:34]
wire [3:0] _utilization_ld_q_T_12 = {1'h0, _utilization_ld_q_T_5} + {1'h0, _utilization_ld_q_T_11}; // @[ReservationStation.scala:498:34]
wire [3:0] utilization_ld_q = _utilization_ld_q_T_12; // @[ReservationStation.scala:498:34]
wire [1:0] _utilization_st_q_T_1 = _utilization_st_q_T; // @[ReservationStation.scala:499:34]
wire [1:0] _utilization_st_q_T_3 = _utilization_st_q_T_2; // @[ReservationStation.scala:499:34]
wire [2:0] _utilization_st_q_T_4 = {1'h0, _utilization_st_q_T_1} + {1'h0, _utilization_st_q_T_3}; // @[ReservationStation.scala:499:34]
wire [2:0] utilization_st_q = _utilization_st_q_T_4; // @[ReservationStation.scala:499:34]
wire [1:0] _utilization_ex_q_T_1 = _utilization_ex_q_T; // @[ReservationStation.scala:500:34]
wire [1:0] _utilization_ex_q_T_3 = _utilization_ex_q_T_2; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_4 = {1'h0, _utilization_ex_q_T_1} + {1'h0, _utilization_ex_q_T_3}; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_5 = _utilization_ex_q_T_4; // @[ReservationStation.scala:500:34]
wire [1:0] _utilization_ex_q_T_7 = _utilization_ex_q_T_6; // @[ReservationStation.scala:500:34]
wire [1:0] _utilization_ex_q_T_8 = {1'h0, entries_ex_6_valid} + _GEN_10; // @[ReservationStation.scala:118:23, :133:29, :500:34]
wire [1:0] _utilization_ex_q_T_9 = _utilization_ex_q_T_8; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_10 = {1'h0, _utilization_ex_q_T_7} + {1'h0, _utilization_ex_q_T_9}; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_11 = _utilization_ex_q_T_10; // @[ReservationStation.scala:500:34]
wire [3:0] _utilization_ex_q_T_12 = {1'h0, _utilization_ex_q_T_5} + {1'h0, _utilization_ex_q_T_11}; // @[ReservationStation.scala:500:34]
wire [3:0] _utilization_ex_q_T_13 = _utilization_ex_q_T_12; // @[ReservationStation.scala:500:34]
wire [1:0] _utilization_ex_q_T_14 = _GEN_11 + _GEN_12; // @[ReservationStation.scala:133:29, :500:34]
wire [1:0] _utilization_ex_q_T_15 = _utilization_ex_q_T_14; // @[ReservationStation.scala:500:34]
wire [1:0] _utilization_ex_q_T_16 = _GEN_13 + _GEN_14; // @[ReservationStation.scala:133:29, :500:34]
wire [1:0] _utilization_ex_q_T_17 = _utilization_ex_q_T_16; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_18 = {1'h0, _utilization_ex_q_T_15} + {1'h0, _utilization_ex_q_T_17}; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_19 = _utilization_ex_q_T_18; // @[ReservationStation.scala:500:34]
wire [1:0] _utilization_ex_q_T_20 = _GEN_15 + {1'h0, entries_ex_13_valid}; // @[ReservationStation.scala:118:23, :133:29, :500:34]
wire [1:0] _utilization_ex_q_T_21 = _utilization_ex_q_T_20; // @[ReservationStation.scala:500:34]
wire [1:0] _utilization_ex_q_T_23 = _utilization_ex_q_T_22; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_24 = {1'h0, _utilization_ex_q_T_21} + {1'h0, _utilization_ex_q_T_23}; // @[ReservationStation.scala:500:34]
wire [2:0] _utilization_ex_q_T_25 = _utilization_ex_q_T_24; // @[ReservationStation.scala:500:34]
wire [3:0] _utilization_ex_q_T_26 = {1'h0, _utilization_ex_q_T_19} + {1'h0, _utilization_ex_q_T_25}; // @[ReservationStation.scala:500:34]
wire [3:0] _utilization_ex_q_T_27 = _utilization_ex_q_T_26; // @[ReservationStation.scala:500:34]
wire [4:0] _utilization_ex_q_T_28 = {1'h0, _utilization_ex_q_T_13} + {1'h0, _utilization_ex_q_T_27}; // @[ReservationStation.scala:500:34]
wire [4:0] utilization_ex_q = _utilization_ex_q_T_28; // @[ReservationStation.scala:500:34]
wire [1:0] packed_deps_lo_lo = {entries_ld_0_bits_deps_ld_1, entries_ld_0_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi = {entries_ld_0_bits_deps_ld_3, entries_ld_0_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo = {packed_deps_lo_hi, packed_deps_lo_lo}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo = {entries_ld_0_bits_deps_ld_5, entries_ld_0_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi = {entries_ld_0_bits_deps_ld_7, entries_ld_0_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi = {packed_deps_hi_hi, packed_deps_hi_lo}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T = {packed_deps_hi, packed_deps_lo}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo = {entries_ld_0_bits_deps_ex_1, entries_ld_0_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi = {entries_ld_0_bits_deps_ex_3, entries_ld_0_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_1 = {packed_deps_lo_lo_hi, packed_deps_lo_lo_lo}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo = {entries_ld_0_bits_deps_ex_5, entries_ld_0_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi = {entries_ld_0_bits_deps_ex_7, entries_ld_0_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_1 = {packed_deps_lo_hi_hi, packed_deps_lo_hi_lo}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_1 = {packed_deps_lo_hi_1, packed_deps_lo_lo_1}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo = {entries_ld_0_bits_deps_ex_9, entries_ld_0_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi = {entries_ld_0_bits_deps_ex_11, entries_ld_0_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_1 = {packed_deps_hi_lo_hi, packed_deps_hi_lo_lo}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo = {entries_ld_0_bits_deps_ex_13, entries_ld_0_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi = {entries_ld_0_bits_deps_ex_15, entries_ld_0_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_1 = {packed_deps_hi_hi_hi, packed_deps_hi_hi_lo}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_1 = {packed_deps_hi_hi_1, packed_deps_hi_lo_1}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_1 = {packed_deps_hi_1, packed_deps_lo_1}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_2 = {entries_ld_0_bits_deps_st_1, entries_ld_0_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_2 = {entries_ld_0_bits_deps_st_3, entries_ld_0_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_2 = {packed_deps_hi_2, packed_deps_lo_2}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_3 = {_packed_deps_T, _packed_deps_T_1}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_3 = {packed_deps_hi_3, _packed_deps_T_2}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_0 = _packed_deps_T_3; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_2 = {entries_ld_1_bits_deps_ld_1, entries_ld_1_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi_2 = {entries_ld_1_bits_deps_ld_3, entries_ld_1_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo_3 = {packed_deps_lo_hi_2, packed_deps_lo_lo_2}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_2 = {entries_ld_1_bits_deps_ld_5, entries_ld_1_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi_2 = {entries_ld_1_bits_deps_ld_7, entries_ld_1_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi_4 = {packed_deps_hi_hi_2, packed_deps_hi_lo_2}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_4 = {packed_deps_hi_4, packed_deps_lo_3}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_1 = {entries_ld_1_bits_deps_ex_1, entries_ld_1_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_1 = {entries_ld_1_bits_deps_ex_3, entries_ld_1_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_3 = {packed_deps_lo_lo_hi_1, packed_deps_lo_lo_lo_1}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_1 = {entries_ld_1_bits_deps_ex_5, entries_ld_1_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_1 = {entries_ld_1_bits_deps_ex_7, entries_ld_1_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_3 = {packed_deps_lo_hi_hi_1, packed_deps_lo_hi_lo_1}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_4 = {packed_deps_lo_hi_3, packed_deps_lo_lo_3}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_1 = {entries_ld_1_bits_deps_ex_9, entries_ld_1_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_1 = {entries_ld_1_bits_deps_ex_11, entries_ld_1_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_3 = {packed_deps_hi_lo_hi_1, packed_deps_hi_lo_lo_1}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_1 = {entries_ld_1_bits_deps_ex_13, entries_ld_1_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_1 = {entries_ld_1_bits_deps_ex_15, entries_ld_1_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_3 = {packed_deps_hi_hi_hi_1, packed_deps_hi_hi_lo_1}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_5 = {packed_deps_hi_hi_3, packed_deps_hi_lo_3}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_5 = {packed_deps_hi_5, packed_deps_lo_4}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_5 = {entries_ld_1_bits_deps_st_1, entries_ld_1_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_6 = {entries_ld_1_bits_deps_st_3, entries_ld_1_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_6 = {packed_deps_hi_6, packed_deps_lo_5}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_7 = {_packed_deps_T_4, _packed_deps_T_5}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_7 = {packed_deps_hi_7, _packed_deps_T_6}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_1 = _packed_deps_T_7; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_4 = {entries_ld_2_bits_deps_ld_1, entries_ld_2_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi_4 = {entries_ld_2_bits_deps_ld_3, entries_ld_2_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo_6 = {packed_deps_lo_hi_4, packed_deps_lo_lo_4}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_4 = {entries_ld_2_bits_deps_ld_5, entries_ld_2_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi_4 = {entries_ld_2_bits_deps_ld_7, entries_ld_2_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi_8 = {packed_deps_hi_hi_4, packed_deps_hi_lo_4}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_8 = {packed_deps_hi_8, packed_deps_lo_6}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_2 = {entries_ld_2_bits_deps_ex_1, entries_ld_2_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_2 = {entries_ld_2_bits_deps_ex_3, entries_ld_2_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_5 = {packed_deps_lo_lo_hi_2, packed_deps_lo_lo_lo_2}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_2 = {entries_ld_2_bits_deps_ex_5, entries_ld_2_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_2 = {entries_ld_2_bits_deps_ex_7, entries_ld_2_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_5 = {packed_deps_lo_hi_hi_2, packed_deps_lo_hi_lo_2}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_7 = {packed_deps_lo_hi_5, packed_deps_lo_lo_5}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_2 = {entries_ld_2_bits_deps_ex_9, entries_ld_2_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_2 = {entries_ld_2_bits_deps_ex_11, entries_ld_2_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_5 = {packed_deps_hi_lo_hi_2, packed_deps_hi_lo_lo_2}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_2 = {entries_ld_2_bits_deps_ex_13, entries_ld_2_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_2 = {entries_ld_2_bits_deps_ex_15, entries_ld_2_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_5 = {packed_deps_hi_hi_hi_2, packed_deps_hi_hi_lo_2}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_9 = {packed_deps_hi_hi_5, packed_deps_hi_lo_5}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_9 = {packed_deps_hi_9, packed_deps_lo_7}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_8 = {entries_ld_2_bits_deps_st_1, entries_ld_2_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_10 = {entries_ld_2_bits_deps_st_3, entries_ld_2_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_10 = {packed_deps_hi_10, packed_deps_lo_8}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_11 = {_packed_deps_T_8, _packed_deps_T_9}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_11 = {packed_deps_hi_11, _packed_deps_T_10}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_2 = _packed_deps_T_11; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_6 = {entries_ld_3_bits_deps_ld_1, entries_ld_3_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi_6 = {entries_ld_3_bits_deps_ld_3, entries_ld_3_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo_9 = {packed_deps_lo_hi_6, packed_deps_lo_lo_6}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_6 = {entries_ld_3_bits_deps_ld_5, entries_ld_3_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi_6 = {entries_ld_3_bits_deps_ld_7, entries_ld_3_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi_12 = {packed_deps_hi_hi_6, packed_deps_hi_lo_6}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_12 = {packed_deps_hi_12, packed_deps_lo_9}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_3 = {entries_ld_3_bits_deps_ex_1, entries_ld_3_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_3 = {entries_ld_3_bits_deps_ex_3, entries_ld_3_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_7 = {packed_deps_lo_lo_hi_3, packed_deps_lo_lo_lo_3}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_3 = {entries_ld_3_bits_deps_ex_5, entries_ld_3_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_3 = {entries_ld_3_bits_deps_ex_7, entries_ld_3_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_7 = {packed_deps_lo_hi_hi_3, packed_deps_lo_hi_lo_3}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_10 = {packed_deps_lo_hi_7, packed_deps_lo_lo_7}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_3 = {entries_ld_3_bits_deps_ex_9, entries_ld_3_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_3 = {entries_ld_3_bits_deps_ex_11, entries_ld_3_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_7 = {packed_deps_hi_lo_hi_3, packed_deps_hi_lo_lo_3}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_3 = {entries_ld_3_bits_deps_ex_13, entries_ld_3_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_3 = {entries_ld_3_bits_deps_ex_15, entries_ld_3_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_7 = {packed_deps_hi_hi_hi_3, packed_deps_hi_hi_lo_3}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_13 = {packed_deps_hi_hi_7, packed_deps_hi_lo_7}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_13 = {packed_deps_hi_13, packed_deps_lo_10}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_11 = {entries_ld_3_bits_deps_st_1, entries_ld_3_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_14 = {entries_ld_3_bits_deps_st_3, entries_ld_3_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_14 = {packed_deps_hi_14, packed_deps_lo_11}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_15 = {_packed_deps_T_12, _packed_deps_T_13}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_15 = {packed_deps_hi_15, _packed_deps_T_14}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_3 = _packed_deps_T_15; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_8 = {entries_ld_4_bits_deps_ld_1, entries_ld_4_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi_8 = {entries_ld_4_bits_deps_ld_3, entries_ld_4_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo_12 = {packed_deps_lo_hi_8, packed_deps_lo_lo_8}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_8 = {entries_ld_4_bits_deps_ld_5, entries_ld_4_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi_8 = {entries_ld_4_bits_deps_ld_7, entries_ld_4_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi_16 = {packed_deps_hi_hi_8, packed_deps_hi_lo_8}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_16 = {packed_deps_hi_16, packed_deps_lo_12}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_4 = {entries_ld_4_bits_deps_ex_1, entries_ld_4_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_4 = {entries_ld_4_bits_deps_ex_3, entries_ld_4_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_9 = {packed_deps_lo_lo_hi_4, packed_deps_lo_lo_lo_4}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_4 = {entries_ld_4_bits_deps_ex_5, entries_ld_4_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_4 = {entries_ld_4_bits_deps_ex_7, entries_ld_4_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_9 = {packed_deps_lo_hi_hi_4, packed_deps_lo_hi_lo_4}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_13 = {packed_deps_lo_hi_9, packed_deps_lo_lo_9}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_4 = {entries_ld_4_bits_deps_ex_9, entries_ld_4_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_4 = {entries_ld_4_bits_deps_ex_11, entries_ld_4_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_9 = {packed_deps_hi_lo_hi_4, packed_deps_hi_lo_lo_4}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_4 = {entries_ld_4_bits_deps_ex_13, entries_ld_4_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_4 = {entries_ld_4_bits_deps_ex_15, entries_ld_4_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_9 = {packed_deps_hi_hi_hi_4, packed_deps_hi_hi_lo_4}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_17 = {packed_deps_hi_hi_9, packed_deps_hi_lo_9}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_17 = {packed_deps_hi_17, packed_deps_lo_13}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_14 = {entries_ld_4_bits_deps_st_1, entries_ld_4_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_18 = {entries_ld_4_bits_deps_st_3, entries_ld_4_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_18 = {packed_deps_hi_18, packed_deps_lo_14}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_19 = {_packed_deps_T_16, _packed_deps_T_17}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_19 = {packed_deps_hi_19, _packed_deps_T_18}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_4 = _packed_deps_T_19; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_10 = {entries_ld_5_bits_deps_ld_1, entries_ld_5_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi_10 = {entries_ld_5_bits_deps_ld_3, entries_ld_5_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo_15 = {packed_deps_lo_hi_10, packed_deps_lo_lo_10}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_10 = {entries_ld_5_bits_deps_ld_5, entries_ld_5_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi_10 = {entries_ld_5_bits_deps_ld_7, entries_ld_5_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi_20 = {packed_deps_hi_hi_10, packed_deps_hi_lo_10}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_20 = {packed_deps_hi_20, packed_deps_lo_15}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_5 = {entries_ld_5_bits_deps_ex_1, entries_ld_5_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_5 = {entries_ld_5_bits_deps_ex_3, entries_ld_5_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_11 = {packed_deps_lo_lo_hi_5, packed_deps_lo_lo_lo_5}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_5 = {entries_ld_5_bits_deps_ex_5, entries_ld_5_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_5 = {entries_ld_5_bits_deps_ex_7, entries_ld_5_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_11 = {packed_deps_lo_hi_hi_5, packed_deps_lo_hi_lo_5}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_16 = {packed_deps_lo_hi_11, packed_deps_lo_lo_11}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_5 = {entries_ld_5_bits_deps_ex_9, entries_ld_5_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_5 = {entries_ld_5_bits_deps_ex_11, entries_ld_5_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_11 = {packed_deps_hi_lo_hi_5, packed_deps_hi_lo_lo_5}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_5 = {entries_ld_5_bits_deps_ex_13, entries_ld_5_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_5 = {entries_ld_5_bits_deps_ex_15, entries_ld_5_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_11 = {packed_deps_hi_hi_hi_5, packed_deps_hi_hi_lo_5}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_21 = {packed_deps_hi_hi_11, packed_deps_hi_lo_11}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_21 = {packed_deps_hi_21, packed_deps_lo_16}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_17 = {entries_ld_5_bits_deps_st_1, entries_ld_5_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_22 = {entries_ld_5_bits_deps_st_3, entries_ld_5_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_22 = {packed_deps_hi_22, packed_deps_lo_17}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_23 = {_packed_deps_T_20, _packed_deps_T_21}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_23 = {packed_deps_hi_23, _packed_deps_T_22}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_5 = _packed_deps_T_23; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_12 = {entries_ld_6_bits_deps_ld_1, entries_ld_6_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi_12 = {entries_ld_6_bits_deps_ld_3, entries_ld_6_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo_18 = {packed_deps_lo_hi_12, packed_deps_lo_lo_12}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_12 = {entries_ld_6_bits_deps_ld_5, entries_ld_6_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi_12 = {entries_ld_6_bits_deps_ld_7, entries_ld_6_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi_24 = {packed_deps_hi_hi_12, packed_deps_hi_lo_12}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_24 = {packed_deps_hi_24, packed_deps_lo_18}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_6 = {entries_ld_6_bits_deps_ex_1, entries_ld_6_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_6 = {entries_ld_6_bits_deps_ex_3, entries_ld_6_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_13 = {packed_deps_lo_lo_hi_6, packed_deps_lo_lo_lo_6}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_6 = {entries_ld_6_bits_deps_ex_5, entries_ld_6_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_6 = {entries_ld_6_bits_deps_ex_7, entries_ld_6_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_13 = {packed_deps_lo_hi_hi_6, packed_deps_lo_hi_lo_6}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_19 = {packed_deps_lo_hi_13, packed_deps_lo_lo_13}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_6 = {entries_ld_6_bits_deps_ex_9, entries_ld_6_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_6 = {entries_ld_6_bits_deps_ex_11, entries_ld_6_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_13 = {packed_deps_hi_lo_hi_6, packed_deps_hi_lo_lo_6}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_6 = {entries_ld_6_bits_deps_ex_13, entries_ld_6_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_6 = {entries_ld_6_bits_deps_ex_15, entries_ld_6_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_13 = {packed_deps_hi_hi_hi_6, packed_deps_hi_hi_lo_6}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_25 = {packed_deps_hi_hi_13, packed_deps_hi_lo_13}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_25 = {packed_deps_hi_25, packed_deps_lo_19}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_20 = {entries_ld_6_bits_deps_st_1, entries_ld_6_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_26 = {entries_ld_6_bits_deps_st_3, entries_ld_6_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_26 = {packed_deps_hi_26, packed_deps_lo_20}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_27 = {_packed_deps_T_24, _packed_deps_T_25}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_27 = {packed_deps_hi_27, _packed_deps_T_26}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_6 = _packed_deps_T_27; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_14 = {entries_ld_7_bits_deps_ld_1, entries_ld_7_bits_deps_ld_0}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_lo_hi_14 = {entries_ld_7_bits_deps_ld_3, entries_ld_7_bits_deps_ld_2}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_lo_21 = {packed_deps_lo_hi_14, packed_deps_lo_lo_14}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_14 = {entries_ld_7_bits_deps_ld_5, entries_ld_7_bits_deps_ld_4}; // @[ReservationStation.scala:117:23, :506:12]
wire [1:0] packed_deps_hi_hi_14 = {entries_ld_7_bits_deps_ld_7, entries_ld_7_bits_deps_ld_6}; // @[ReservationStation.scala:117:23, :506:12]
wire [3:0] packed_deps_hi_28 = {packed_deps_hi_hi_14, packed_deps_hi_lo_14}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_28 = {packed_deps_hi_28, packed_deps_lo_21}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_7 = {entries_ld_7_bits_deps_ex_1, entries_ld_7_bits_deps_ex_0}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_7 = {entries_ld_7_bits_deps_ex_3, entries_ld_7_bits_deps_ex_2}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_lo_15 = {packed_deps_lo_lo_hi_7, packed_deps_lo_lo_lo_7}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_7 = {entries_ld_7_bits_deps_ex_5, entries_ld_7_bits_deps_ex_4}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_7 = {entries_ld_7_bits_deps_ex_7, entries_ld_7_bits_deps_ex_6}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_lo_hi_15 = {packed_deps_lo_hi_hi_7, packed_deps_lo_hi_lo_7}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_22 = {packed_deps_lo_hi_15, packed_deps_lo_lo_15}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_7 = {entries_ld_7_bits_deps_ex_9, entries_ld_7_bits_deps_ex_8}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_7 = {entries_ld_7_bits_deps_ex_11, entries_ld_7_bits_deps_ex_10}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_lo_15 = {packed_deps_hi_lo_hi_7, packed_deps_hi_lo_lo_7}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_7 = {entries_ld_7_bits_deps_ex_13, entries_ld_7_bits_deps_ex_12}; // @[ReservationStation.scala:117:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_7 = {entries_ld_7_bits_deps_ex_15, entries_ld_7_bits_deps_ex_14}; // @[ReservationStation.scala:117:23, :506:41]
wire [3:0] packed_deps_hi_hi_15 = {packed_deps_hi_hi_hi_7, packed_deps_hi_hi_lo_7}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_29 = {packed_deps_hi_hi_15, packed_deps_hi_lo_15}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_29 = {packed_deps_hi_29, packed_deps_lo_22}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_23 = {entries_ld_7_bits_deps_st_1, entries_ld_7_bits_deps_st_0}; // @[ReservationStation.scala:117:23, :506:70]
wire [1:0] packed_deps_hi_30 = {entries_ld_7_bits_deps_st_3, entries_ld_7_bits_deps_st_2}; // @[ReservationStation.scala:117:23, :506:70]
wire [3:0] _packed_deps_T_30 = {packed_deps_hi_30, packed_deps_lo_23}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_31 = {_packed_deps_T_28, _packed_deps_T_29}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_31 = {packed_deps_hi_31, _packed_deps_T_30}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_7 = _packed_deps_T_31; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_16 = {entries_ex_0_bits_deps_ld_1, entries_ex_0_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_16 = {entries_ex_0_bits_deps_ld_3, entries_ex_0_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_24 = {packed_deps_lo_hi_16, packed_deps_lo_lo_16}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_16 = {entries_ex_0_bits_deps_ld_5, entries_ex_0_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_16 = {entries_ex_0_bits_deps_ld_7, entries_ex_0_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_32 = {packed_deps_hi_hi_16, packed_deps_hi_lo_16}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_32 = {packed_deps_hi_32, packed_deps_lo_24}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_8 = {entries_ex_0_bits_deps_ex_1, entries_ex_0_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_8 = {entries_ex_0_bits_deps_ex_3, entries_ex_0_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_17 = {packed_deps_lo_lo_hi_8, packed_deps_lo_lo_lo_8}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_8 = {entries_ex_0_bits_deps_ex_5, entries_ex_0_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_8 = {entries_ex_0_bits_deps_ex_7, entries_ex_0_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_17 = {packed_deps_lo_hi_hi_8, packed_deps_lo_hi_lo_8}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_25 = {packed_deps_lo_hi_17, packed_deps_lo_lo_17}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_8 = {entries_ex_0_bits_deps_ex_9, entries_ex_0_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_8 = {entries_ex_0_bits_deps_ex_11, entries_ex_0_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_17 = {packed_deps_hi_lo_hi_8, packed_deps_hi_lo_lo_8}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_8 = {entries_ex_0_bits_deps_ex_13, entries_ex_0_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_8 = {entries_ex_0_bits_deps_ex_15, entries_ex_0_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_17 = {packed_deps_hi_hi_hi_8, packed_deps_hi_hi_lo_8}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_33 = {packed_deps_hi_hi_17, packed_deps_hi_lo_17}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_33 = {packed_deps_hi_33, packed_deps_lo_25}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_26 = {entries_ex_0_bits_deps_st_1, entries_ex_0_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_34 = {entries_ex_0_bits_deps_st_3, entries_ex_0_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_34 = {packed_deps_hi_34, packed_deps_lo_26}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_35 = {_packed_deps_T_32, _packed_deps_T_33}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_35 = {packed_deps_hi_35, _packed_deps_T_34}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_8 = _packed_deps_T_35; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_18 = {entries_ex_1_bits_deps_ld_1, entries_ex_1_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_18 = {entries_ex_1_bits_deps_ld_3, entries_ex_1_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_27 = {packed_deps_lo_hi_18, packed_deps_lo_lo_18}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_18 = {entries_ex_1_bits_deps_ld_5, entries_ex_1_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_18 = {entries_ex_1_bits_deps_ld_7, entries_ex_1_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_36 = {packed_deps_hi_hi_18, packed_deps_hi_lo_18}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_36 = {packed_deps_hi_36, packed_deps_lo_27}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_9 = {entries_ex_1_bits_deps_ex_1, entries_ex_1_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_9 = {entries_ex_1_bits_deps_ex_3, entries_ex_1_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_19 = {packed_deps_lo_lo_hi_9, packed_deps_lo_lo_lo_9}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_9 = {entries_ex_1_bits_deps_ex_5, entries_ex_1_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_9 = {entries_ex_1_bits_deps_ex_7, entries_ex_1_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_19 = {packed_deps_lo_hi_hi_9, packed_deps_lo_hi_lo_9}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_28 = {packed_deps_lo_hi_19, packed_deps_lo_lo_19}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_9 = {entries_ex_1_bits_deps_ex_9, entries_ex_1_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_9 = {entries_ex_1_bits_deps_ex_11, entries_ex_1_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_19 = {packed_deps_hi_lo_hi_9, packed_deps_hi_lo_lo_9}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_9 = {entries_ex_1_bits_deps_ex_13, entries_ex_1_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_9 = {entries_ex_1_bits_deps_ex_15, entries_ex_1_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_19 = {packed_deps_hi_hi_hi_9, packed_deps_hi_hi_lo_9}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_37 = {packed_deps_hi_hi_19, packed_deps_hi_lo_19}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_37 = {packed_deps_hi_37, packed_deps_lo_28}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_29 = {entries_ex_1_bits_deps_st_1, entries_ex_1_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_38 = {entries_ex_1_bits_deps_st_3, entries_ex_1_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_38 = {packed_deps_hi_38, packed_deps_lo_29}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_39 = {_packed_deps_T_36, _packed_deps_T_37}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_39 = {packed_deps_hi_39, _packed_deps_T_38}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_9 = _packed_deps_T_39; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_20 = {entries_ex_2_bits_deps_ld_1, entries_ex_2_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_20 = {entries_ex_2_bits_deps_ld_3, entries_ex_2_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_30 = {packed_deps_lo_hi_20, packed_deps_lo_lo_20}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_20 = {entries_ex_2_bits_deps_ld_5, entries_ex_2_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_20 = {entries_ex_2_bits_deps_ld_7, entries_ex_2_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_40 = {packed_deps_hi_hi_20, packed_deps_hi_lo_20}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_40 = {packed_deps_hi_40, packed_deps_lo_30}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_10 = {entries_ex_2_bits_deps_ex_1, entries_ex_2_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_10 = {entries_ex_2_bits_deps_ex_3, entries_ex_2_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_21 = {packed_deps_lo_lo_hi_10, packed_deps_lo_lo_lo_10}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_10 = {entries_ex_2_bits_deps_ex_5, entries_ex_2_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_10 = {entries_ex_2_bits_deps_ex_7, entries_ex_2_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_21 = {packed_deps_lo_hi_hi_10, packed_deps_lo_hi_lo_10}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_31 = {packed_deps_lo_hi_21, packed_deps_lo_lo_21}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_10 = {entries_ex_2_bits_deps_ex_9, entries_ex_2_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_10 = {entries_ex_2_bits_deps_ex_11, entries_ex_2_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_21 = {packed_deps_hi_lo_hi_10, packed_deps_hi_lo_lo_10}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_10 = {entries_ex_2_bits_deps_ex_13, entries_ex_2_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_10 = {entries_ex_2_bits_deps_ex_15, entries_ex_2_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_21 = {packed_deps_hi_hi_hi_10, packed_deps_hi_hi_lo_10}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_41 = {packed_deps_hi_hi_21, packed_deps_hi_lo_21}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_41 = {packed_deps_hi_41, packed_deps_lo_31}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_32 = {entries_ex_2_bits_deps_st_1, entries_ex_2_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_42 = {entries_ex_2_bits_deps_st_3, entries_ex_2_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_42 = {packed_deps_hi_42, packed_deps_lo_32}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_43 = {_packed_deps_T_40, _packed_deps_T_41}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_43 = {packed_deps_hi_43, _packed_deps_T_42}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_10 = _packed_deps_T_43; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_22 = {entries_ex_3_bits_deps_ld_1, entries_ex_3_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_22 = {entries_ex_3_bits_deps_ld_3, entries_ex_3_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_33 = {packed_deps_lo_hi_22, packed_deps_lo_lo_22}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_22 = {entries_ex_3_bits_deps_ld_5, entries_ex_3_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_22 = {entries_ex_3_bits_deps_ld_7, entries_ex_3_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_44 = {packed_deps_hi_hi_22, packed_deps_hi_lo_22}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_44 = {packed_deps_hi_44, packed_deps_lo_33}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_11 = {entries_ex_3_bits_deps_ex_1, entries_ex_3_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_11 = {entries_ex_3_bits_deps_ex_3, entries_ex_3_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_23 = {packed_deps_lo_lo_hi_11, packed_deps_lo_lo_lo_11}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_11 = {entries_ex_3_bits_deps_ex_5, entries_ex_3_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_11 = {entries_ex_3_bits_deps_ex_7, entries_ex_3_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_23 = {packed_deps_lo_hi_hi_11, packed_deps_lo_hi_lo_11}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_34 = {packed_deps_lo_hi_23, packed_deps_lo_lo_23}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_11 = {entries_ex_3_bits_deps_ex_9, entries_ex_3_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_11 = {entries_ex_3_bits_deps_ex_11, entries_ex_3_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_23 = {packed_deps_hi_lo_hi_11, packed_deps_hi_lo_lo_11}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_11 = {entries_ex_3_bits_deps_ex_13, entries_ex_3_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_11 = {entries_ex_3_bits_deps_ex_15, entries_ex_3_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_23 = {packed_deps_hi_hi_hi_11, packed_deps_hi_hi_lo_11}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_45 = {packed_deps_hi_hi_23, packed_deps_hi_lo_23}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_45 = {packed_deps_hi_45, packed_deps_lo_34}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_35 = {entries_ex_3_bits_deps_st_1, entries_ex_3_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_46 = {entries_ex_3_bits_deps_st_3, entries_ex_3_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_46 = {packed_deps_hi_46, packed_deps_lo_35}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_47 = {_packed_deps_T_44, _packed_deps_T_45}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_47 = {packed_deps_hi_47, _packed_deps_T_46}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_11 = _packed_deps_T_47; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_24 = {entries_ex_4_bits_deps_ld_1, entries_ex_4_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_24 = {entries_ex_4_bits_deps_ld_3, entries_ex_4_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_36 = {packed_deps_lo_hi_24, packed_deps_lo_lo_24}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_24 = {entries_ex_4_bits_deps_ld_5, entries_ex_4_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_24 = {entries_ex_4_bits_deps_ld_7, entries_ex_4_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_48 = {packed_deps_hi_hi_24, packed_deps_hi_lo_24}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_48 = {packed_deps_hi_48, packed_deps_lo_36}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_12 = {entries_ex_4_bits_deps_ex_1, entries_ex_4_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_12 = {entries_ex_4_bits_deps_ex_3, entries_ex_4_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_25 = {packed_deps_lo_lo_hi_12, packed_deps_lo_lo_lo_12}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_12 = {entries_ex_4_bits_deps_ex_5, entries_ex_4_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_12 = {entries_ex_4_bits_deps_ex_7, entries_ex_4_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_25 = {packed_deps_lo_hi_hi_12, packed_deps_lo_hi_lo_12}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_37 = {packed_deps_lo_hi_25, packed_deps_lo_lo_25}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_12 = {entries_ex_4_bits_deps_ex_9, entries_ex_4_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_12 = {entries_ex_4_bits_deps_ex_11, entries_ex_4_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_25 = {packed_deps_hi_lo_hi_12, packed_deps_hi_lo_lo_12}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_12 = {entries_ex_4_bits_deps_ex_13, entries_ex_4_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_12 = {entries_ex_4_bits_deps_ex_15, entries_ex_4_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_25 = {packed_deps_hi_hi_hi_12, packed_deps_hi_hi_lo_12}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_49 = {packed_deps_hi_hi_25, packed_deps_hi_lo_25}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_49 = {packed_deps_hi_49, packed_deps_lo_37}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_38 = {entries_ex_4_bits_deps_st_1, entries_ex_4_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_50 = {entries_ex_4_bits_deps_st_3, entries_ex_4_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_50 = {packed_deps_hi_50, packed_deps_lo_38}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_51 = {_packed_deps_T_48, _packed_deps_T_49}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_51 = {packed_deps_hi_51, _packed_deps_T_50}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_12 = _packed_deps_T_51; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_26 = {entries_ex_5_bits_deps_ld_1, entries_ex_5_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_26 = {entries_ex_5_bits_deps_ld_3, entries_ex_5_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_39 = {packed_deps_lo_hi_26, packed_deps_lo_lo_26}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_26 = {entries_ex_5_bits_deps_ld_5, entries_ex_5_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_26 = {entries_ex_5_bits_deps_ld_7, entries_ex_5_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_52 = {packed_deps_hi_hi_26, packed_deps_hi_lo_26}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_52 = {packed_deps_hi_52, packed_deps_lo_39}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_13 = {entries_ex_5_bits_deps_ex_1, entries_ex_5_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_13 = {entries_ex_5_bits_deps_ex_3, entries_ex_5_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_27 = {packed_deps_lo_lo_hi_13, packed_deps_lo_lo_lo_13}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_13 = {entries_ex_5_bits_deps_ex_5, entries_ex_5_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_13 = {entries_ex_5_bits_deps_ex_7, entries_ex_5_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_27 = {packed_deps_lo_hi_hi_13, packed_deps_lo_hi_lo_13}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_40 = {packed_deps_lo_hi_27, packed_deps_lo_lo_27}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_13 = {entries_ex_5_bits_deps_ex_9, entries_ex_5_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_13 = {entries_ex_5_bits_deps_ex_11, entries_ex_5_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_27 = {packed_deps_hi_lo_hi_13, packed_deps_hi_lo_lo_13}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_13 = {entries_ex_5_bits_deps_ex_13, entries_ex_5_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_13 = {entries_ex_5_bits_deps_ex_15, entries_ex_5_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_27 = {packed_deps_hi_hi_hi_13, packed_deps_hi_hi_lo_13}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_53 = {packed_deps_hi_hi_27, packed_deps_hi_lo_27}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_53 = {packed_deps_hi_53, packed_deps_lo_40}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_41 = {entries_ex_5_bits_deps_st_1, entries_ex_5_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_54 = {entries_ex_5_bits_deps_st_3, entries_ex_5_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_54 = {packed_deps_hi_54, packed_deps_lo_41}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_55 = {_packed_deps_T_52, _packed_deps_T_53}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_55 = {packed_deps_hi_55, _packed_deps_T_54}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_13 = _packed_deps_T_55; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_28 = {entries_ex_6_bits_deps_ld_1, entries_ex_6_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_28 = {entries_ex_6_bits_deps_ld_3, entries_ex_6_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_42 = {packed_deps_lo_hi_28, packed_deps_lo_lo_28}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_28 = {entries_ex_6_bits_deps_ld_5, entries_ex_6_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_28 = {entries_ex_6_bits_deps_ld_7, entries_ex_6_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_56 = {packed_deps_hi_hi_28, packed_deps_hi_lo_28}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_56 = {packed_deps_hi_56, packed_deps_lo_42}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_14 = {entries_ex_6_bits_deps_ex_1, entries_ex_6_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_14 = {entries_ex_6_bits_deps_ex_3, entries_ex_6_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_29 = {packed_deps_lo_lo_hi_14, packed_deps_lo_lo_lo_14}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_14 = {entries_ex_6_bits_deps_ex_5, entries_ex_6_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_14 = {entries_ex_6_bits_deps_ex_7, entries_ex_6_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_29 = {packed_deps_lo_hi_hi_14, packed_deps_lo_hi_lo_14}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_43 = {packed_deps_lo_hi_29, packed_deps_lo_lo_29}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_14 = {entries_ex_6_bits_deps_ex_9, entries_ex_6_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_14 = {entries_ex_6_bits_deps_ex_11, entries_ex_6_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_29 = {packed_deps_hi_lo_hi_14, packed_deps_hi_lo_lo_14}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_14 = {entries_ex_6_bits_deps_ex_13, entries_ex_6_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_14 = {entries_ex_6_bits_deps_ex_15, entries_ex_6_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_29 = {packed_deps_hi_hi_hi_14, packed_deps_hi_hi_lo_14}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_57 = {packed_deps_hi_hi_29, packed_deps_hi_lo_29}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_57 = {packed_deps_hi_57, packed_deps_lo_43}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_44 = {entries_ex_6_bits_deps_st_1, entries_ex_6_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_58 = {entries_ex_6_bits_deps_st_3, entries_ex_6_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_58 = {packed_deps_hi_58, packed_deps_lo_44}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_59 = {_packed_deps_T_56, _packed_deps_T_57}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_59 = {packed_deps_hi_59, _packed_deps_T_58}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_14 = _packed_deps_T_59; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_30 = {entries_ex_7_bits_deps_ld_1, entries_ex_7_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_30 = {entries_ex_7_bits_deps_ld_3, entries_ex_7_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_45 = {packed_deps_lo_hi_30, packed_deps_lo_lo_30}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_30 = {entries_ex_7_bits_deps_ld_5, entries_ex_7_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_30 = {entries_ex_7_bits_deps_ld_7, entries_ex_7_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_60 = {packed_deps_hi_hi_30, packed_deps_hi_lo_30}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_60 = {packed_deps_hi_60, packed_deps_lo_45}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_15 = {entries_ex_7_bits_deps_ex_1, entries_ex_7_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_15 = {entries_ex_7_bits_deps_ex_3, entries_ex_7_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_31 = {packed_deps_lo_lo_hi_15, packed_deps_lo_lo_lo_15}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_15 = {entries_ex_7_bits_deps_ex_5, entries_ex_7_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_15 = {entries_ex_7_bits_deps_ex_7, entries_ex_7_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_31 = {packed_deps_lo_hi_hi_15, packed_deps_lo_hi_lo_15}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_46 = {packed_deps_lo_hi_31, packed_deps_lo_lo_31}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_15 = {entries_ex_7_bits_deps_ex_9, entries_ex_7_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_15 = {entries_ex_7_bits_deps_ex_11, entries_ex_7_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_31 = {packed_deps_hi_lo_hi_15, packed_deps_hi_lo_lo_15}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_15 = {entries_ex_7_bits_deps_ex_13, entries_ex_7_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_15 = {entries_ex_7_bits_deps_ex_15, entries_ex_7_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_31 = {packed_deps_hi_hi_hi_15, packed_deps_hi_hi_lo_15}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_61 = {packed_deps_hi_hi_31, packed_deps_hi_lo_31}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_61 = {packed_deps_hi_61, packed_deps_lo_46}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_47 = {entries_ex_7_bits_deps_st_1, entries_ex_7_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_62 = {entries_ex_7_bits_deps_st_3, entries_ex_7_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_62 = {packed_deps_hi_62, packed_deps_lo_47}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_63 = {_packed_deps_T_60, _packed_deps_T_61}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_63 = {packed_deps_hi_63, _packed_deps_T_62}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_15 = _packed_deps_T_63; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_32 = {entries_ex_8_bits_deps_ld_1, entries_ex_8_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_32 = {entries_ex_8_bits_deps_ld_3, entries_ex_8_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_48 = {packed_deps_lo_hi_32, packed_deps_lo_lo_32}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_32 = {entries_ex_8_bits_deps_ld_5, entries_ex_8_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_32 = {entries_ex_8_bits_deps_ld_7, entries_ex_8_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_64 = {packed_deps_hi_hi_32, packed_deps_hi_lo_32}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_64 = {packed_deps_hi_64, packed_deps_lo_48}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_16 = {entries_ex_8_bits_deps_ex_1, entries_ex_8_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_16 = {entries_ex_8_bits_deps_ex_3, entries_ex_8_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_33 = {packed_deps_lo_lo_hi_16, packed_deps_lo_lo_lo_16}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_16 = {entries_ex_8_bits_deps_ex_5, entries_ex_8_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_16 = {entries_ex_8_bits_deps_ex_7, entries_ex_8_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_33 = {packed_deps_lo_hi_hi_16, packed_deps_lo_hi_lo_16}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_49 = {packed_deps_lo_hi_33, packed_deps_lo_lo_33}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_16 = {entries_ex_8_bits_deps_ex_9, entries_ex_8_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_16 = {entries_ex_8_bits_deps_ex_11, entries_ex_8_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_33 = {packed_deps_hi_lo_hi_16, packed_deps_hi_lo_lo_16}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_16 = {entries_ex_8_bits_deps_ex_13, entries_ex_8_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_16 = {entries_ex_8_bits_deps_ex_15, entries_ex_8_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_33 = {packed_deps_hi_hi_hi_16, packed_deps_hi_hi_lo_16}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_65 = {packed_deps_hi_hi_33, packed_deps_hi_lo_33}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_65 = {packed_deps_hi_65, packed_deps_lo_49}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_50 = {entries_ex_8_bits_deps_st_1, entries_ex_8_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_66 = {entries_ex_8_bits_deps_st_3, entries_ex_8_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_66 = {packed_deps_hi_66, packed_deps_lo_50}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_67 = {_packed_deps_T_64, _packed_deps_T_65}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_67 = {packed_deps_hi_67, _packed_deps_T_66}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_16 = _packed_deps_T_67; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_34 = {entries_ex_9_bits_deps_ld_1, entries_ex_9_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_34 = {entries_ex_9_bits_deps_ld_3, entries_ex_9_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_51 = {packed_deps_lo_hi_34, packed_deps_lo_lo_34}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_34 = {entries_ex_9_bits_deps_ld_5, entries_ex_9_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_34 = {entries_ex_9_bits_deps_ld_7, entries_ex_9_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_68 = {packed_deps_hi_hi_34, packed_deps_hi_lo_34}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_68 = {packed_deps_hi_68, packed_deps_lo_51}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_17 = {entries_ex_9_bits_deps_ex_1, entries_ex_9_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_17 = {entries_ex_9_bits_deps_ex_3, entries_ex_9_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_35 = {packed_deps_lo_lo_hi_17, packed_deps_lo_lo_lo_17}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_17 = {entries_ex_9_bits_deps_ex_5, entries_ex_9_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_17 = {entries_ex_9_bits_deps_ex_7, entries_ex_9_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_35 = {packed_deps_lo_hi_hi_17, packed_deps_lo_hi_lo_17}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_52 = {packed_deps_lo_hi_35, packed_deps_lo_lo_35}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_17 = {entries_ex_9_bits_deps_ex_9, entries_ex_9_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_17 = {entries_ex_9_bits_deps_ex_11, entries_ex_9_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_35 = {packed_deps_hi_lo_hi_17, packed_deps_hi_lo_lo_17}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_17 = {entries_ex_9_bits_deps_ex_13, entries_ex_9_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_17 = {entries_ex_9_bits_deps_ex_15, entries_ex_9_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_35 = {packed_deps_hi_hi_hi_17, packed_deps_hi_hi_lo_17}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_69 = {packed_deps_hi_hi_35, packed_deps_hi_lo_35}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_69 = {packed_deps_hi_69, packed_deps_lo_52}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_53 = {entries_ex_9_bits_deps_st_1, entries_ex_9_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_70 = {entries_ex_9_bits_deps_st_3, entries_ex_9_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_70 = {packed_deps_hi_70, packed_deps_lo_53}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_71 = {_packed_deps_T_68, _packed_deps_T_69}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_71 = {packed_deps_hi_71, _packed_deps_T_70}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_17 = _packed_deps_T_71; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_36 = {entries_ex_10_bits_deps_ld_1, entries_ex_10_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_36 = {entries_ex_10_bits_deps_ld_3, entries_ex_10_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_54 = {packed_deps_lo_hi_36, packed_deps_lo_lo_36}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_36 = {entries_ex_10_bits_deps_ld_5, entries_ex_10_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_36 = {entries_ex_10_bits_deps_ld_7, entries_ex_10_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_72 = {packed_deps_hi_hi_36, packed_deps_hi_lo_36}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_72 = {packed_deps_hi_72, packed_deps_lo_54}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_18 = {entries_ex_10_bits_deps_ex_1, entries_ex_10_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_18 = {entries_ex_10_bits_deps_ex_3, entries_ex_10_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_37 = {packed_deps_lo_lo_hi_18, packed_deps_lo_lo_lo_18}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_18 = {entries_ex_10_bits_deps_ex_5, entries_ex_10_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_18 = {entries_ex_10_bits_deps_ex_7, entries_ex_10_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_37 = {packed_deps_lo_hi_hi_18, packed_deps_lo_hi_lo_18}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_55 = {packed_deps_lo_hi_37, packed_deps_lo_lo_37}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_18 = {entries_ex_10_bits_deps_ex_9, entries_ex_10_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_18 = {entries_ex_10_bits_deps_ex_11, entries_ex_10_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_37 = {packed_deps_hi_lo_hi_18, packed_deps_hi_lo_lo_18}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_18 = {entries_ex_10_bits_deps_ex_13, entries_ex_10_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_18 = {entries_ex_10_bits_deps_ex_15, entries_ex_10_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_37 = {packed_deps_hi_hi_hi_18, packed_deps_hi_hi_lo_18}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_73 = {packed_deps_hi_hi_37, packed_deps_hi_lo_37}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_73 = {packed_deps_hi_73, packed_deps_lo_55}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_56 = {entries_ex_10_bits_deps_st_1, entries_ex_10_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_74 = {entries_ex_10_bits_deps_st_3, entries_ex_10_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_74 = {packed_deps_hi_74, packed_deps_lo_56}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_75 = {_packed_deps_T_72, _packed_deps_T_73}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_75 = {packed_deps_hi_75, _packed_deps_T_74}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_18 = _packed_deps_T_75; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_38 = {entries_ex_11_bits_deps_ld_1, entries_ex_11_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_38 = {entries_ex_11_bits_deps_ld_3, entries_ex_11_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_57 = {packed_deps_lo_hi_38, packed_deps_lo_lo_38}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_38 = {entries_ex_11_bits_deps_ld_5, entries_ex_11_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_38 = {entries_ex_11_bits_deps_ld_7, entries_ex_11_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_76 = {packed_deps_hi_hi_38, packed_deps_hi_lo_38}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_76 = {packed_deps_hi_76, packed_deps_lo_57}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_19 = {entries_ex_11_bits_deps_ex_1, entries_ex_11_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_19 = {entries_ex_11_bits_deps_ex_3, entries_ex_11_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_39 = {packed_deps_lo_lo_hi_19, packed_deps_lo_lo_lo_19}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_19 = {entries_ex_11_bits_deps_ex_5, entries_ex_11_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_19 = {entries_ex_11_bits_deps_ex_7, entries_ex_11_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_39 = {packed_deps_lo_hi_hi_19, packed_deps_lo_hi_lo_19}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_58 = {packed_deps_lo_hi_39, packed_deps_lo_lo_39}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_19 = {entries_ex_11_bits_deps_ex_9, entries_ex_11_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_19 = {entries_ex_11_bits_deps_ex_11, entries_ex_11_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_39 = {packed_deps_hi_lo_hi_19, packed_deps_hi_lo_lo_19}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_19 = {entries_ex_11_bits_deps_ex_13, entries_ex_11_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_19 = {entries_ex_11_bits_deps_ex_15, entries_ex_11_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_39 = {packed_deps_hi_hi_hi_19, packed_deps_hi_hi_lo_19}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_77 = {packed_deps_hi_hi_39, packed_deps_hi_lo_39}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_77 = {packed_deps_hi_77, packed_deps_lo_58}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_59 = {entries_ex_11_bits_deps_st_1, entries_ex_11_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_78 = {entries_ex_11_bits_deps_st_3, entries_ex_11_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_78 = {packed_deps_hi_78, packed_deps_lo_59}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_79 = {_packed_deps_T_76, _packed_deps_T_77}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_79 = {packed_deps_hi_79, _packed_deps_T_78}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_19 = _packed_deps_T_79; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_40 = {entries_ex_12_bits_deps_ld_1, entries_ex_12_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_40 = {entries_ex_12_bits_deps_ld_3, entries_ex_12_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_60 = {packed_deps_lo_hi_40, packed_deps_lo_lo_40}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_40 = {entries_ex_12_bits_deps_ld_5, entries_ex_12_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_40 = {entries_ex_12_bits_deps_ld_7, entries_ex_12_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_80 = {packed_deps_hi_hi_40, packed_deps_hi_lo_40}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_80 = {packed_deps_hi_80, packed_deps_lo_60}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_20 = {entries_ex_12_bits_deps_ex_1, entries_ex_12_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_20 = {entries_ex_12_bits_deps_ex_3, entries_ex_12_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_41 = {packed_deps_lo_lo_hi_20, packed_deps_lo_lo_lo_20}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_20 = {entries_ex_12_bits_deps_ex_5, entries_ex_12_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_20 = {entries_ex_12_bits_deps_ex_7, entries_ex_12_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_41 = {packed_deps_lo_hi_hi_20, packed_deps_lo_hi_lo_20}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_61 = {packed_deps_lo_hi_41, packed_deps_lo_lo_41}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_20 = {entries_ex_12_bits_deps_ex_9, entries_ex_12_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_20 = {entries_ex_12_bits_deps_ex_11, entries_ex_12_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_41 = {packed_deps_hi_lo_hi_20, packed_deps_hi_lo_lo_20}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_20 = {entries_ex_12_bits_deps_ex_13, entries_ex_12_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_20 = {entries_ex_12_bits_deps_ex_15, entries_ex_12_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_41 = {packed_deps_hi_hi_hi_20, packed_deps_hi_hi_lo_20}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_81 = {packed_deps_hi_hi_41, packed_deps_hi_lo_41}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_81 = {packed_deps_hi_81, packed_deps_lo_61}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_62 = {entries_ex_12_bits_deps_st_1, entries_ex_12_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_82 = {entries_ex_12_bits_deps_st_3, entries_ex_12_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_82 = {packed_deps_hi_82, packed_deps_lo_62}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_83 = {_packed_deps_T_80, _packed_deps_T_81}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_83 = {packed_deps_hi_83, _packed_deps_T_82}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_20 = _packed_deps_T_83; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_42 = {entries_ex_13_bits_deps_ld_1, entries_ex_13_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_42 = {entries_ex_13_bits_deps_ld_3, entries_ex_13_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_63 = {packed_deps_lo_hi_42, packed_deps_lo_lo_42}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_42 = {entries_ex_13_bits_deps_ld_5, entries_ex_13_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_42 = {entries_ex_13_bits_deps_ld_7, entries_ex_13_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_84 = {packed_deps_hi_hi_42, packed_deps_hi_lo_42}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_84 = {packed_deps_hi_84, packed_deps_lo_63}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_21 = {entries_ex_13_bits_deps_ex_1, entries_ex_13_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_21 = {entries_ex_13_bits_deps_ex_3, entries_ex_13_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_43 = {packed_deps_lo_lo_hi_21, packed_deps_lo_lo_lo_21}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_21 = {entries_ex_13_bits_deps_ex_5, entries_ex_13_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_21 = {entries_ex_13_bits_deps_ex_7, entries_ex_13_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_43 = {packed_deps_lo_hi_hi_21, packed_deps_lo_hi_lo_21}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_64 = {packed_deps_lo_hi_43, packed_deps_lo_lo_43}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_21 = {entries_ex_13_bits_deps_ex_9, entries_ex_13_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_21 = {entries_ex_13_bits_deps_ex_11, entries_ex_13_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_43 = {packed_deps_hi_lo_hi_21, packed_deps_hi_lo_lo_21}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_21 = {entries_ex_13_bits_deps_ex_13, entries_ex_13_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_21 = {entries_ex_13_bits_deps_ex_15, entries_ex_13_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_43 = {packed_deps_hi_hi_hi_21, packed_deps_hi_hi_lo_21}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_85 = {packed_deps_hi_hi_43, packed_deps_hi_lo_43}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_85 = {packed_deps_hi_85, packed_deps_lo_64}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_65 = {entries_ex_13_bits_deps_st_1, entries_ex_13_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_86 = {entries_ex_13_bits_deps_st_3, entries_ex_13_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_86 = {packed_deps_hi_86, packed_deps_lo_65}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_87 = {_packed_deps_T_84, _packed_deps_T_85}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_87 = {packed_deps_hi_87, _packed_deps_T_86}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_21 = _packed_deps_T_87; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_44 = {entries_ex_14_bits_deps_ld_1, entries_ex_14_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_44 = {entries_ex_14_bits_deps_ld_3, entries_ex_14_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_66 = {packed_deps_lo_hi_44, packed_deps_lo_lo_44}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_44 = {entries_ex_14_bits_deps_ld_5, entries_ex_14_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_44 = {entries_ex_14_bits_deps_ld_7, entries_ex_14_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_88 = {packed_deps_hi_hi_44, packed_deps_hi_lo_44}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_88 = {packed_deps_hi_88, packed_deps_lo_66}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_22 = {entries_ex_14_bits_deps_ex_1, entries_ex_14_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_22 = {entries_ex_14_bits_deps_ex_3, entries_ex_14_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_45 = {packed_deps_lo_lo_hi_22, packed_deps_lo_lo_lo_22}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_22 = {entries_ex_14_bits_deps_ex_5, entries_ex_14_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_22 = {entries_ex_14_bits_deps_ex_7, entries_ex_14_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_45 = {packed_deps_lo_hi_hi_22, packed_deps_lo_hi_lo_22}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_67 = {packed_deps_lo_hi_45, packed_deps_lo_lo_45}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_22 = {entries_ex_14_bits_deps_ex_9, entries_ex_14_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_22 = {entries_ex_14_bits_deps_ex_11, entries_ex_14_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_45 = {packed_deps_hi_lo_hi_22, packed_deps_hi_lo_lo_22}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_22 = {entries_ex_14_bits_deps_ex_13, entries_ex_14_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_22 = {entries_ex_14_bits_deps_ex_15, entries_ex_14_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_45 = {packed_deps_hi_hi_hi_22, packed_deps_hi_hi_lo_22}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_89 = {packed_deps_hi_hi_45, packed_deps_hi_lo_45}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_89 = {packed_deps_hi_89, packed_deps_lo_67}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_68 = {entries_ex_14_bits_deps_st_1, entries_ex_14_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_90 = {entries_ex_14_bits_deps_st_3, entries_ex_14_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_90 = {packed_deps_hi_90, packed_deps_lo_68}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_91 = {_packed_deps_T_88, _packed_deps_T_89}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_91 = {packed_deps_hi_91, _packed_deps_T_90}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_22 = _packed_deps_T_91; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_46 = {entries_ex_15_bits_deps_ld_1, entries_ex_15_bits_deps_ld_0}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_lo_hi_46 = {entries_ex_15_bits_deps_ld_3, entries_ex_15_bits_deps_ld_2}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_lo_69 = {packed_deps_lo_hi_46, packed_deps_lo_lo_46}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_46 = {entries_ex_15_bits_deps_ld_5, entries_ex_15_bits_deps_ld_4}; // @[ReservationStation.scala:118:23, :506:12]
wire [1:0] packed_deps_hi_hi_46 = {entries_ex_15_bits_deps_ld_7, entries_ex_15_bits_deps_ld_6}; // @[ReservationStation.scala:118:23, :506:12]
wire [3:0] packed_deps_hi_92 = {packed_deps_hi_hi_46, packed_deps_hi_lo_46}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_92 = {packed_deps_hi_92, packed_deps_lo_69}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_23 = {entries_ex_15_bits_deps_ex_1, entries_ex_15_bits_deps_ex_0}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_23 = {entries_ex_15_bits_deps_ex_3, entries_ex_15_bits_deps_ex_2}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_lo_47 = {packed_deps_lo_lo_hi_23, packed_deps_lo_lo_lo_23}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_23 = {entries_ex_15_bits_deps_ex_5, entries_ex_15_bits_deps_ex_4}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_23 = {entries_ex_15_bits_deps_ex_7, entries_ex_15_bits_deps_ex_6}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_lo_hi_47 = {packed_deps_lo_hi_hi_23, packed_deps_lo_hi_lo_23}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_70 = {packed_deps_lo_hi_47, packed_deps_lo_lo_47}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_23 = {entries_ex_15_bits_deps_ex_9, entries_ex_15_bits_deps_ex_8}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_23 = {entries_ex_15_bits_deps_ex_11, entries_ex_15_bits_deps_ex_10}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_lo_47 = {packed_deps_hi_lo_hi_23, packed_deps_hi_lo_lo_23}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_23 = {entries_ex_15_bits_deps_ex_13, entries_ex_15_bits_deps_ex_12}; // @[ReservationStation.scala:118:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_23 = {entries_ex_15_bits_deps_ex_15, entries_ex_15_bits_deps_ex_14}; // @[ReservationStation.scala:118:23, :506:41]
wire [3:0] packed_deps_hi_hi_47 = {packed_deps_hi_hi_hi_23, packed_deps_hi_hi_lo_23}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_93 = {packed_deps_hi_hi_47, packed_deps_hi_lo_47}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_93 = {packed_deps_hi_93, packed_deps_lo_70}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_71 = {entries_ex_15_bits_deps_st_1, entries_ex_15_bits_deps_st_0}; // @[ReservationStation.scala:118:23, :506:70]
wire [1:0] packed_deps_hi_94 = {entries_ex_15_bits_deps_st_3, entries_ex_15_bits_deps_st_2}; // @[ReservationStation.scala:118:23, :506:70]
wire [3:0] _packed_deps_T_94 = {packed_deps_hi_94, packed_deps_lo_71}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_95 = {_packed_deps_T_92, _packed_deps_T_93}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_95 = {packed_deps_hi_95, _packed_deps_T_94}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_23 = _packed_deps_T_95; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_48 = {entries_st_0_bits_deps_ld_1, entries_st_0_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_lo_hi_48 = {entries_st_0_bits_deps_ld_3, entries_st_0_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_lo_72 = {packed_deps_lo_hi_48, packed_deps_lo_lo_48}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_48 = {entries_st_0_bits_deps_ld_5, entries_st_0_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_hi_hi_48 = {entries_st_0_bits_deps_ld_7, entries_st_0_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_hi_96 = {packed_deps_hi_hi_48, packed_deps_hi_lo_48}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_96 = {packed_deps_hi_96, packed_deps_lo_72}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_24 = {entries_st_0_bits_deps_ex_1, entries_st_0_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_24 = {entries_st_0_bits_deps_ex_3, entries_st_0_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_lo_49 = {packed_deps_lo_lo_hi_24, packed_deps_lo_lo_lo_24}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_24 = {entries_st_0_bits_deps_ex_5, entries_st_0_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_24 = {entries_st_0_bits_deps_ex_7, entries_st_0_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_hi_49 = {packed_deps_lo_hi_hi_24, packed_deps_lo_hi_lo_24}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_73 = {packed_deps_lo_hi_49, packed_deps_lo_lo_49}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_24 = {entries_st_0_bits_deps_ex_9, entries_st_0_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_24 = {entries_st_0_bits_deps_ex_11, entries_st_0_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_lo_49 = {packed_deps_hi_lo_hi_24, packed_deps_hi_lo_lo_24}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_24 = {entries_st_0_bits_deps_ex_13, entries_st_0_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_24 = {entries_st_0_bits_deps_ex_15, entries_st_0_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_hi_49 = {packed_deps_hi_hi_hi_24, packed_deps_hi_hi_lo_24}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_97 = {packed_deps_hi_hi_49, packed_deps_hi_lo_49}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_97 = {packed_deps_hi_97, packed_deps_lo_73}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_74 = {entries_st_0_bits_deps_st_1, entries_st_0_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70]
wire [1:0] packed_deps_hi_98 = {entries_st_0_bits_deps_st_3, entries_st_0_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70]
wire [3:0] _packed_deps_T_98 = {packed_deps_hi_98, packed_deps_lo_74}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_99 = {_packed_deps_T_96, _packed_deps_T_97}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_99 = {packed_deps_hi_99, _packed_deps_T_98}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_24 = _packed_deps_T_99; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_50 = {entries_st_1_bits_deps_ld_1, entries_st_1_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_lo_hi_50 = {entries_st_1_bits_deps_ld_3, entries_st_1_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_lo_75 = {packed_deps_lo_hi_50, packed_deps_lo_lo_50}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_50 = {entries_st_1_bits_deps_ld_5, entries_st_1_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_hi_hi_50 = {entries_st_1_bits_deps_ld_7, entries_st_1_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_hi_100 = {packed_deps_hi_hi_50, packed_deps_hi_lo_50}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_100 = {packed_deps_hi_100, packed_deps_lo_75}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_25 = {entries_st_1_bits_deps_ex_1, entries_st_1_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_25 = {entries_st_1_bits_deps_ex_3, entries_st_1_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_lo_51 = {packed_deps_lo_lo_hi_25, packed_deps_lo_lo_lo_25}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_25 = {entries_st_1_bits_deps_ex_5, entries_st_1_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_25 = {entries_st_1_bits_deps_ex_7, entries_st_1_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_hi_51 = {packed_deps_lo_hi_hi_25, packed_deps_lo_hi_lo_25}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_76 = {packed_deps_lo_hi_51, packed_deps_lo_lo_51}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_25 = {entries_st_1_bits_deps_ex_9, entries_st_1_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_25 = {entries_st_1_bits_deps_ex_11, entries_st_1_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_lo_51 = {packed_deps_hi_lo_hi_25, packed_deps_hi_lo_lo_25}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_25 = {entries_st_1_bits_deps_ex_13, entries_st_1_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_25 = {entries_st_1_bits_deps_ex_15, entries_st_1_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_hi_51 = {packed_deps_hi_hi_hi_25, packed_deps_hi_hi_lo_25}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_101 = {packed_deps_hi_hi_51, packed_deps_hi_lo_51}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_101 = {packed_deps_hi_101, packed_deps_lo_76}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_77 = {entries_st_1_bits_deps_st_1, entries_st_1_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70]
wire [1:0] packed_deps_hi_102 = {entries_st_1_bits_deps_st_3, entries_st_1_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70]
wire [3:0] _packed_deps_T_102 = {packed_deps_hi_102, packed_deps_lo_77}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_103 = {_packed_deps_T_100, _packed_deps_T_101}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_103 = {packed_deps_hi_103, _packed_deps_T_102}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_25 = _packed_deps_T_103; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_52 = {entries_st_2_bits_deps_ld_1, entries_st_2_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_lo_hi_52 = {entries_st_2_bits_deps_ld_3, entries_st_2_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_lo_78 = {packed_deps_lo_hi_52, packed_deps_lo_lo_52}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_52 = {entries_st_2_bits_deps_ld_5, entries_st_2_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_hi_hi_52 = {entries_st_2_bits_deps_ld_7, entries_st_2_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_hi_104 = {packed_deps_hi_hi_52, packed_deps_hi_lo_52}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_104 = {packed_deps_hi_104, packed_deps_lo_78}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_26 = {entries_st_2_bits_deps_ex_1, entries_st_2_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_26 = {entries_st_2_bits_deps_ex_3, entries_st_2_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_lo_53 = {packed_deps_lo_lo_hi_26, packed_deps_lo_lo_lo_26}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_26 = {entries_st_2_bits_deps_ex_5, entries_st_2_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_26 = {entries_st_2_bits_deps_ex_7, entries_st_2_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_hi_53 = {packed_deps_lo_hi_hi_26, packed_deps_lo_hi_lo_26}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_79 = {packed_deps_lo_hi_53, packed_deps_lo_lo_53}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_26 = {entries_st_2_bits_deps_ex_9, entries_st_2_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_26 = {entries_st_2_bits_deps_ex_11, entries_st_2_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_lo_53 = {packed_deps_hi_lo_hi_26, packed_deps_hi_lo_lo_26}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_26 = {entries_st_2_bits_deps_ex_13, entries_st_2_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_26 = {entries_st_2_bits_deps_ex_15, entries_st_2_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_hi_53 = {packed_deps_hi_hi_hi_26, packed_deps_hi_hi_lo_26}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_105 = {packed_deps_hi_hi_53, packed_deps_hi_lo_53}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_105 = {packed_deps_hi_105, packed_deps_lo_79}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_80 = {entries_st_2_bits_deps_st_1, entries_st_2_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70]
wire [1:0] packed_deps_hi_106 = {entries_st_2_bits_deps_st_3, entries_st_2_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70]
wire [3:0] _packed_deps_T_106 = {packed_deps_hi_106, packed_deps_lo_80}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_107 = {_packed_deps_T_104, _packed_deps_T_105}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_107 = {packed_deps_hi_107, _packed_deps_T_106}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_26 = _packed_deps_T_107; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] packed_deps_lo_lo_54 = {entries_st_3_bits_deps_ld_1, entries_st_3_bits_deps_ld_0}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_lo_hi_54 = {entries_st_3_bits_deps_ld_3, entries_st_3_bits_deps_ld_2}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_lo_81 = {packed_deps_lo_hi_54, packed_deps_lo_lo_54}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_hi_lo_54 = {entries_st_3_bits_deps_ld_5, entries_st_3_bits_deps_ld_4}; // @[ReservationStation.scala:119:23, :506:12]
wire [1:0] packed_deps_hi_hi_54 = {entries_st_3_bits_deps_ld_7, entries_st_3_bits_deps_ld_6}; // @[ReservationStation.scala:119:23, :506:12]
wire [3:0] packed_deps_hi_108 = {packed_deps_hi_hi_54, packed_deps_hi_lo_54}; // @[ReservationStation.scala:506:12]
wire [7:0] _packed_deps_T_108 = {packed_deps_hi_108, packed_deps_lo_81}; // @[ReservationStation.scala:506:12]
wire [1:0] packed_deps_lo_lo_lo_27 = {entries_st_3_bits_deps_ex_1, entries_st_3_bits_deps_ex_0}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_lo_hi_27 = {entries_st_3_bits_deps_ex_3, entries_st_3_bits_deps_ex_2}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_lo_55 = {packed_deps_lo_lo_hi_27, packed_deps_lo_lo_lo_27}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_hi_lo_27 = {entries_st_3_bits_deps_ex_5, entries_st_3_bits_deps_ex_4}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_lo_hi_hi_27 = {entries_st_3_bits_deps_ex_7, entries_st_3_bits_deps_ex_6}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_lo_hi_55 = {packed_deps_lo_hi_hi_27, packed_deps_lo_hi_lo_27}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_lo_82 = {packed_deps_lo_hi_55, packed_deps_lo_lo_55}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_lo_lo_27 = {entries_st_3_bits_deps_ex_9, entries_st_3_bits_deps_ex_8}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_lo_hi_27 = {entries_st_3_bits_deps_ex_11, entries_st_3_bits_deps_ex_10}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_lo_55 = {packed_deps_hi_lo_hi_27, packed_deps_hi_lo_lo_27}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_hi_hi_lo_27 = {entries_st_3_bits_deps_ex_13, entries_st_3_bits_deps_ex_12}; // @[ReservationStation.scala:119:23, :506:41]
wire [1:0] packed_deps_hi_hi_hi_27 = {entries_st_3_bits_deps_ex_15, entries_st_3_bits_deps_ex_14}; // @[ReservationStation.scala:119:23, :506:41]
wire [3:0] packed_deps_hi_hi_55 = {packed_deps_hi_hi_hi_27, packed_deps_hi_hi_lo_27}; // @[ReservationStation.scala:506:41]
wire [7:0] packed_deps_hi_109 = {packed_deps_hi_hi_55, packed_deps_hi_lo_55}; // @[ReservationStation.scala:506:41]
wire [15:0] _packed_deps_T_109 = {packed_deps_hi_109, packed_deps_lo_82}; // @[ReservationStation.scala:506:41]
wire [1:0] packed_deps_lo_83 = {entries_st_3_bits_deps_st_1, entries_st_3_bits_deps_st_0}; // @[ReservationStation.scala:119:23, :506:70]
wire [1:0] packed_deps_hi_110 = {entries_st_3_bits_deps_st_3, entries_st_3_bits_deps_st_2}; // @[ReservationStation.scala:119:23, :506:70]
wire [3:0] _packed_deps_T_110 = {packed_deps_hi_110, packed_deps_lo_83}; // @[ReservationStation.scala:506:70]
wire [23:0] packed_deps_hi_111 = {_packed_deps_T_108, _packed_deps_T_109}; // @[ReservationStation.scala:506:{8,12,41}]
wire [27:0] _packed_deps_T_111 = {packed_deps_hi_111, _packed_deps_T_110}; // @[ReservationStation.scala:506:{8,70}]
wire [27:0] packed_deps_27 = _packed_deps_T_111; // @[ReservationStation.scala:505:28, :506:8]
wire [1:0] _pop_count_packed_deps_T = {1'h0, entries_ld_0_bits_deps_ld_0} + {1'h0, entries_ld_0_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1 = _pop_count_packed_deps_T; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_2 = {1'h0, entries_ld_0_bits_deps_ld_2} + {1'h0, entries_ld_0_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_3 = _pop_count_packed_deps_T_2; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_4 = {1'h0, _pop_count_packed_deps_T_1} + {1'h0, _pop_count_packed_deps_T_3}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_5 = _pop_count_packed_deps_T_4; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_6 = {1'h0, entries_ld_0_bits_deps_ld_4} + {1'h0, entries_ld_0_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_7 = _pop_count_packed_deps_T_6; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_8 = {1'h0, entries_ld_0_bits_deps_ld_6} + {1'h0, entries_ld_0_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_9 = _pop_count_packed_deps_T_8; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_10 = {1'h0, _pop_count_packed_deps_T_7} + {1'h0, _pop_count_packed_deps_T_9}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_11 = _pop_count_packed_deps_T_10; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_12 = {1'h0, _pop_count_packed_deps_T_5} + {1'h0, _pop_count_packed_deps_T_11}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_13 = _pop_count_packed_deps_T_12; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_14 = {1'h0, entries_ld_0_bits_deps_ex_0} + {1'h0, entries_ld_0_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_15 = _pop_count_packed_deps_T_14; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_16 = {1'h0, entries_ld_0_bits_deps_ex_2} + {1'h0, entries_ld_0_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_17 = _pop_count_packed_deps_T_16; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_18 = {1'h0, _pop_count_packed_deps_T_15} + {1'h0, _pop_count_packed_deps_T_17}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_19 = _pop_count_packed_deps_T_18; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_20 = {1'h0, entries_ld_0_bits_deps_ex_4} + {1'h0, entries_ld_0_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_21 = _pop_count_packed_deps_T_20; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_22 = {1'h0, entries_ld_0_bits_deps_ex_6} + {1'h0, entries_ld_0_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_23 = _pop_count_packed_deps_T_22; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_24 = {1'h0, _pop_count_packed_deps_T_21} + {1'h0, _pop_count_packed_deps_T_23}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_25 = _pop_count_packed_deps_T_24; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_26 = {1'h0, _pop_count_packed_deps_T_19} + {1'h0, _pop_count_packed_deps_T_25}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_27 = _pop_count_packed_deps_T_26; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_28 = {1'h0, entries_ld_0_bits_deps_ex_8} + {1'h0, entries_ld_0_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_29 = _pop_count_packed_deps_T_28; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_30 = {1'h0, entries_ld_0_bits_deps_ex_10} + {1'h0, entries_ld_0_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_31 = _pop_count_packed_deps_T_30; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_32 = {1'h0, _pop_count_packed_deps_T_29} + {1'h0, _pop_count_packed_deps_T_31}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_33 = _pop_count_packed_deps_T_32; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_34 = {1'h0, entries_ld_0_bits_deps_ex_12} + {1'h0, entries_ld_0_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_35 = _pop_count_packed_deps_T_34; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_36 = {1'h0, entries_ld_0_bits_deps_ex_14} + {1'h0, entries_ld_0_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_37 = _pop_count_packed_deps_T_36; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_38 = {1'h0, _pop_count_packed_deps_T_35} + {1'h0, _pop_count_packed_deps_T_37}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_39 = _pop_count_packed_deps_T_38; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_40 = {1'h0, _pop_count_packed_deps_T_33} + {1'h0, _pop_count_packed_deps_T_39}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_41 = _pop_count_packed_deps_T_40; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_42 = {1'h0, _pop_count_packed_deps_T_27} + {1'h0, _pop_count_packed_deps_T_41}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_43 = _pop_count_packed_deps_T_42; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_44 = {2'h0, _pop_count_packed_deps_T_13} + {1'h0, _pop_count_packed_deps_T_43}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_45 = _pop_count_packed_deps_T_44[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_46 = {1'h0, entries_ld_0_bits_deps_st_0} + {1'h0, entries_ld_0_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_47 = _pop_count_packed_deps_T_46; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_48 = {1'h0, entries_ld_0_bits_deps_st_2} + {1'h0, entries_ld_0_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_49 = _pop_count_packed_deps_T_48; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_50 = {1'h0, _pop_count_packed_deps_T_47} + {1'h0, _pop_count_packed_deps_T_49}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_51 = _pop_count_packed_deps_T_50; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_52 = {1'h0, _pop_count_packed_deps_T_45} + {3'h0, _pop_count_packed_deps_T_51}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_53 = _pop_count_packed_deps_T_52[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_54 = entries_ld_0_valid ? _pop_count_packed_deps_T_53 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_0 = _pop_count_packed_deps_T_54; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_55 = {1'h0, entries_ld_1_bits_deps_ld_0} + {1'h0, entries_ld_1_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_56 = _pop_count_packed_deps_T_55; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_57 = {1'h0, entries_ld_1_bits_deps_ld_2} + {1'h0, entries_ld_1_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_58 = _pop_count_packed_deps_T_57; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_59 = {1'h0, _pop_count_packed_deps_T_56} + {1'h0, _pop_count_packed_deps_T_58}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_60 = _pop_count_packed_deps_T_59; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_61 = {1'h0, entries_ld_1_bits_deps_ld_4} + {1'h0, entries_ld_1_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_62 = _pop_count_packed_deps_T_61; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_63 = {1'h0, entries_ld_1_bits_deps_ld_6} + {1'h0, entries_ld_1_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_64 = _pop_count_packed_deps_T_63; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_65 = {1'h0, _pop_count_packed_deps_T_62} + {1'h0, _pop_count_packed_deps_T_64}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_66 = _pop_count_packed_deps_T_65; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_67 = {1'h0, _pop_count_packed_deps_T_60} + {1'h0, _pop_count_packed_deps_T_66}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_68 = _pop_count_packed_deps_T_67; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_69 = {1'h0, entries_ld_1_bits_deps_ex_0} + {1'h0, entries_ld_1_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_70 = _pop_count_packed_deps_T_69; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_71 = {1'h0, entries_ld_1_bits_deps_ex_2} + {1'h0, entries_ld_1_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_72 = _pop_count_packed_deps_T_71; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_73 = {1'h0, _pop_count_packed_deps_T_70} + {1'h0, _pop_count_packed_deps_T_72}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_74 = _pop_count_packed_deps_T_73; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_75 = {1'h0, entries_ld_1_bits_deps_ex_4} + {1'h0, entries_ld_1_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_76 = _pop_count_packed_deps_T_75; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_77 = {1'h0, entries_ld_1_bits_deps_ex_6} + {1'h0, entries_ld_1_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_78 = _pop_count_packed_deps_T_77; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_79 = {1'h0, _pop_count_packed_deps_T_76} + {1'h0, _pop_count_packed_deps_T_78}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_80 = _pop_count_packed_deps_T_79; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_81 = {1'h0, _pop_count_packed_deps_T_74} + {1'h0, _pop_count_packed_deps_T_80}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_82 = _pop_count_packed_deps_T_81; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_83 = {1'h0, entries_ld_1_bits_deps_ex_8} + {1'h0, entries_ld_1_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_84 = _pop_count_packed_deps_T_83; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_85 = {1'h0, entries_ld_1_bits_deps_ex_10} + {1'h0, entries_ld_1_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_86 = _pop_count_packed_deps_T_85; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_87 = {1'h0, _pop_count_packed_deps_T_84} + {1'h0, _pop_count_packed_deps_T_86}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_88 = _pop_count_packed_deps_T_87; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_89 = {1'h0, entries_ld_1_bits_deps_ex_12} + {1'h0, entries_ld_1_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_90 = _pop_count_packed_deps_T_89; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_91 = {1'h0, entries_ld_1_bits_deps_ex_14} + {1'h0, entries_ld_1_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_92 = _pop_count_packed_deps_T_91; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_93 = {1'h0, _pop_count_packed_deps_T_90} + {1'h0, _pop_count_packed_deps_T_92}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_94 = _pop_count_packed_deps_T_93; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_95 = {1'h0, _pop_count_packed_deps_T_88} + {1'h0, _pop_count_packed_deps_T_94}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_96 = _pop_count_packed_deps_T_95; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_97 = {1'h0, _pop_count_packed_deps_T_82} + {1'h0, _pop_count_packed_deps_T_96}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_98 = _pop_count_packed_deps_T_97; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_99 = {2'h0, _pop_count_packed_deps_T_68} + {1'h0, _pop_count_packed_deps_T_98}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_100 = _pop_count_packed_deps_T_99[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_101 = {1'h0, entries_ld_1_bits_deps_st_0} + {1'h0, entries_ld_1_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_102 = _pop_count_packed_deps_T_101; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_103 = {1'h0, entries_ld_1_bits_deps_st_2} + {1'h0, entries_ld_1_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_104 = _pop_count_packed_deps_T_103; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_105 = {1'h0, _pop_count_packed_deps_T_102} + {1'h0, _pop_count_packed_deps_T_104}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_106 = _pop_count_packed_deps_T_105; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_107 = {1'h0, _pop_count_packed_deps_T_100} + {3'h0, _pop_count_packed_deps_T_106}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_108 = _pop_count_packed_deps_T_107[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_109 = entries_ld_1_valid ? _pop_count_packed_deps_T_108 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_1 = _pop_count_packed_deps_T_109; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_110 = {1'h0, entries_ld_2_bits_deps_ld_0} + {1'h0, entries_ld_2_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_111 = _pop_count_packed_deps_T_110; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_112 = {1'h0, entries_ld_2_bits_deps_ld_2} + {1'h0, entries_ld_2_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_113 = _pop_count_packed_deps_T_112; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_114 = {1'h0, _pop_count_packed_deps_T_111} + {1'h0, _pop_count_packed_deps_T_113}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_115 = _pop_count_packed_deps_T_114; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_116 = {1'h0, entries_ld_2_bits_deps_ld_4} + {1'h0, entries_ld_2_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_117 = _pop_count_packed_deps_T_116; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_118 = {1'h0, entries_ld_2_bits_deps_ld_6} + {1'h0, entries_ld_2_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_119 = _pop_count_packed_deps_T_118; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_120 = {1'h0, _pop_count_packed_deps_T_117} + {1'h0, _pop_count_packed_deps_T_119}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_121 = _pop_count_packed_deps_T_120; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_122 = {1'h0, _pop_count_packed_deps_T_115} + {1'h0, _pop_count_packed_deps_T_121}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_123 = _pop_count_packed_deps_T_122; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_124 = {1'h0, entries_ld_2_bits_deps_ex_0} + {1'h0, entries_ld_2_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_125 = _pop_count_packed_deps_T_124; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_126 = {1'h0, entries_ld_2_bits_deps_ex_2} + {1'h0, entries_ld_2_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_127 = _pop_count_packed_deps_T_126; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_128 = {1'h0, _pop_count_packed_deps_T_125} + {1'h0, _pop_count_packed_deps_T_127}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_129 = _pop_count_packed_deps_T_128; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_130 = {1'h0, entries_ld_2_bits_deps_ex_4} + {1'h0, entries_ld_2_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_131 = _pop_count_packed_deps_T_130; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_132 = {1'h0, entries_ld_2_bits_deps_ex_6} + {1'h0, entries_ld_2_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_133 = _pop_count_packed_deps_T_132; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_134 = {1'h0, _pop_count_packed_deps_T_131} + {1'h0, _pop_count_packed_deps_T_133}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_135 = _pop_count_packed_deps_T_134; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_136 = {1'h0, _pop_count_packed_deps_T_129} + {1'h0, _pop_count_packed_deps_T_135}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_137 = _pop_count_packed_deps_T_136; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_138 = {1'h0, entries_ld_2_bits_deps_ex_8} + {1'h0, entries_ld_2_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_139 = _pop_count_packed_deps_T_138; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_140 = {1'h0, entries_ld_2_bits_deps_ex_10} + {1'h0, entries_ld_2_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_141 = _pop_count_packed_deps_T_140; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_142 = {1'h0, _pop_count_packed_deps_T_139} + {1'h0, _pop_count_packed_deps_T_141}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_143 = _pop_count_packed_deps_T_142; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_144 = {1'h0, entries_ld_2_bits_deps_ex_12} + {1'h0, entries_ld_2_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_145 = _pop_count_packed_deps_T_144; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_146 = {1'h0, entries_ld_2_bits_deps_ex_14} + {1'h0, entries_ld_2_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_147 = _pop_count_packed_deps_T_146; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_148 = {1'h0, _pop_count_packed_deps_T_145} + {1'h0, _pop_count_packed_deps_T_147}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_149 = _pop_count_packed_deps_T_148; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_150 = {1'h0, _pop_count_packed_deps_T_143} + {1'h0, _pop_count_packed_deps_T_149}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_151 = _pop_count_packed_deps_T_150; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_152 = {1'h0, _pop_count_packed_deps_T_137} + {1'h0, _pop_count_packed_deps_T_151}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_153 = _pop_count_packed_deps_T_152; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_154 = {2'h0, _pop_count_packed_deps_T_123} + {1'h0, _pop_count_packed_deps_T_153}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_155 = _pop_count_packed_deps_T_154[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_156 = {1'h0, entries_ld_2_bits_deps_st_0} + {1'h0, entries_ld_2_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_157 = _pop_count_packed_deps_T_156; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_158 = {1'h0, entries_ld_2_bits_deps_st_2} + {1'h0, entries_ld_2_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_159 = _pop_count_packed_deps_T_158; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_160 = {1'h0, _pop_count_packed_deps_T_157} + {1'h0, _pop_count_packed_deps_T_159}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_161 = _pop_count_packed_deps_T_160; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_162 = {1'h0, _pop_count_packed_deps_T_155} + {3'h0, _pop_count_packed_deps_T_161}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_163 = _pop_count_packed_deps_T_162[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_164 = entries_ld_2_valid ? _pop_count_packed_deps_T_163 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_2 = _pop_count_packed_deps_T_164; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_165 = {1'h0, entries_ld_3_bits_deps_ld_0} + {1'h0, entries_ld_3_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_166 = _pop_count_packed_deps_T_165; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_167 = {1'h0, entries_ld_3_bits_deps_ld_2} + {1'h0, entries_ld_3_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_168 = _pop_count_packed_deps_T_167; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_169 = {1'h0, _pop_count_packed_deps_T_166} + {1'h0, _pop_count_packed_deps_T_168}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_170 = _pop_count_packed_deps_T_169; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_171 = {1'h0, entries_ld_3_bits_deps_ld_4} + {1'h0, entries_ld_3_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_172 = _pop_count_packed_deps_T_171; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_173 = {1'h0, entries_ld_3_bits_deps_ld_6} + {1'h0, entries_ld_3_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_174 = _pop_count_packed_deps_T_173; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_175 = {1'h0, _pop_count_packed_deps_T_172} + {1'h0, _pop_count_packed_deps_T_174}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_176 = _pop_count_packed_deps_T_175; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_177 = {1'h0, _pop_count_packed_deps_T_170} + {1'h0, _pop_count_packed_deps_T_176}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_178 = _pop_count_packed_deps_T_177; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_179 = {1'h0, entries_ld_3_bits_deps_ex_0} + {1'h0, entries_ld_3_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_180 = _pop_count_packed_deps_T_179; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_181 = {1'h0, entries_ld_3_bits_deps_ex_2} + {1'h0, entries_ld_3_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_182 = _pop_count_packed_deps_T_181; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_183 = {1'h0, _pop_count_packed_deps_T_180} + {1'h0, _pop_count_packed_deps_T_182}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_184 = _pop_count_packed_deps_T_183; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_185 = {1'h0, entries_ld_3_bits_deps_ex_4} + {1'h0, entries_ld_3_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_186 = _pop_count_packed_deps_T_185; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_187 = {1'h0, entries_ld_3_bits_deps_ex_6} + {1'h0, entries_ld_3_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_188 = _pop_count_packed_deps_T_187; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_189 = {1'h0, _pop_count_packed_deps_T_186} + {1'h0, _pop_count_packed_deps_T_188}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_190 = _pop_count_packed_deps_T_189; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_191 = {1'h0, _pop_count_packed_deps_T_184} + {1'h0, _pop_count_packed_deps_T_190}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_192 = _pop_count_packed_deps_T_191; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_193 = {1'h0, entries_ld_3_bits_deps_ex_8} + {1'h0, entries_ld_3_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_194 = _pop_count_packed_deps_T_193; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_195 = {1'h0, entries_ld_3_bits_deps_ex_10} + {1'h0, entries_ld_3_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_196 = _pop_count_packed_deps_T_195; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_197 = {1'h0, _pop_count_packed_deps_T_194} + {1'h0, _pop_count_packed_deps_T_196}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_198 = _pop_count_packed_deps_T_197; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_199 = {1'h0, entries_ld_3_bits_deps_ex_12} + {1'h0, entries_ld_3_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_200 = _pop_count_packed_deps_T_199; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_201 = {1'h0, entries_ld_3_bits_deps_ex_14} + {1'h0, entries_ld_3_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_202 = _pop_count_packed_deps_T_201; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_203 = {1'h0, _pop_count_packed_deps_T_200} + {1'h0, _pop_count_packed_deps_T_202}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_204 = _pop_count_packed_deps_T_203; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_205 = {1'h0, _pop_count_packed_deps_T_198} + {1'h0, _pop_count_packed_deps_T_204}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_206 = _pop_count_packed_deps_T_205; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_207 = {1'h0, _pop_count_packed_deps_T_192} + {1'h0, _pop_count_packed_deps_T_206}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_208 = _pop_count_packed_deps_T_207; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_209 = {2'h0, _pop_count_packed_deps_T_178} + {1'h0, _pop_count_packed_deps_T_208}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_210 = _pop_count_packed_deps_T_209[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_211 = {1'h0, entries_ld_3_bits_deps_st_0} + {1'h0, entries_ld_3_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_212 = _pop_count_packed_deps_T_211; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_213 = {1'h0, entries_ld_3_bits_deps_st_2} + {1'h0, entries_ld_3_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_214 = _pop_count_packed_deps_T_213; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_215 = {1'h0, _pop_count_packed_deps_T_212} + {1'h0, _pop_count_packed_deps_T_214}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_216 = _pop_count_packed_deps_T_215; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_217 = {1'h0, _pop_count_packed_deps_T_210} + {3'h0, _pop_count_packed_deps_T_216}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_218 = _pop_count_packed_deps_T_217[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_219 = entries_ld_3_valid ? _pop_count_packed_deps_T_218 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_3 = _pop_count_packed_deps_T_219; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_220 = {1'h0, entries_ld_4_bits_deps_ld_0} + {1'h0, entries_ld_4_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_221 = _pop_count_packed_deps_T_220; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_222 = {1'h0, entries_ld_4_bits_deps_ld_2} + {1'h0, entries_ld_4_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_223 = _pop_count_packed_deps_T_222; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_224 = {1'h0, _pop_count_packed_deps_T_221} + {1'h0, _pop_count_packed_deps_T_223}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_225 = _pop_count_packed_deps_T_224; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_226 = {1'h0, entries_ld_4_bits_deps_ld_4} + {1'h0, entries_ld_4_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_227 = _pop_count_packed_deps_T_226; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_228 = {1'h0, entries_ld_4_bits_deps_ld_6} + {1'h0, entries_ld_4_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_229 = _pop_count_packed_deps_T_228; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_230 = {1'h0, _pop_count_packed_deps_T_227} + {1'h0, _pop_count_packed_deps_T_229}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_231 = _pop_count_packed_deps_T_230; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_232 = {1'h0, _pop_count_packed_deps_T_225} + {1'h0, _pop_count_packed_deps_T_231}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_233 = _pop_count_packed_deps_T_232; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_234 = {1'h0, entries_ld_4_bits_deps_ex_0} + {1'h0, entries_ld_4_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_235 = _pop_count_packed_deps_T_234; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_236 = {1'h0, entries_ld_4_bits_deps_ex_2} + {1'h0, entries_ld_4_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_237 = _pop_count_packed_deps_T_236; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_238 = {1'h0, _pop_count_packed_deps_T_235} + {1'h0, _pop_count_packed_deps_T_237}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_239 = _pop_count_packed_deps_T_238; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_240 = {1'h0, entries_ld_4_bits_deps_ex_4} + {1'h0, entries_ld_4_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_241 = _pop_count_packed_deps_T_240; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_242 = {1'h0, entries_ld_4_bits_deps_ex_6} + {1'h0, entries_ld_4_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_243 = _pop_count_packed_deps_T_242; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_244 = {1'h0, _pop_count_packed_deps_T_241} + {1'h0, _pop_count_packed_deps_T_243}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_245 = _pop_count_packed_deps_T_244; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_246 = {1'h0, _pop_count_packed_deps_T_239} + {1'h0, _pop_count_packed_deps_T_245}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_247 = _pop_count_packed_deps_T_246; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_248 = {1'h0, entries_ld_4_bits_deps_ex_8} + {1'h0, entries_ld_4_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_249 = _pop_count_packed_deps_T_248; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_250 = {1'h0, entries_ld_4_bits_deps_ex_10} + {1'h0, entries_ld_4_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_251 = _pop_count_packed_deps_T_250; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_252 = {1'h0, _pop_count_packed_deps_T_249} + {1'h0, _pop_count_packed_deps_T_251}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_253 = _pop_count_packed_deps_T_252; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_254 = {1'h0, entries_ld_4_bits_deps_ex_12} + {1'h0, entries_ld_4_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_255 = _pop_count_packed_deps_T_254; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_256 = {1'h0, entries_ld_4_bits_deps_ex_14} + {1'h0, entries_ld_4_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_257 = _pop_count_packed_deps_T_256; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_258 = {1'h0, _pop_count_packed_deps_T_255} + {1'h0, _pop_count_packed_deps_T_257}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_259 = _pop_count_packed_deps_T_258; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_260 = {1'h0, _pop_count_packed_deps_T_253} + {1'h0, _pop_count_packed_deps_T_259}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_261 = _pop_count_packed_deps_T_260; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_262 = {1'h0, _pop_count_packed_deps_T_247} + {1'h0, _pop_count_packed_deps_T_261}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_263 = _pop_count_packed_deps_T_262; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_264 = {2'h0, _pop_count_packed_deps_T_233} + {1'h0, _pop_count_packed_deps_T_263}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_265 = _pop_count_packed_deps_T_264[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_266 = {1'h0, entries_ld_4_bits_deps_st_0} + {1'h0, entries_ld_4_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_267 = _pop_count_packed_deps_T_266; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_268 = {1'h0, entries_ld_4_bits_deps_st_2} + {1'h0, entries_ld_4_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_269 = _pop_count_packed_deps_T_268; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_270 = {1'h0, _pop_count_packed_deps_T_267} + {1'h0, _pop_count_packed_deps_T_269}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_271 = _pop_count_packed_deps_T_270; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_272 = {1'h0, _pop_count_packed_deps_T_265} + {3'h0, _pop_count_packed_deps_T_271}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_273 = _pop_count_packed_deps_T_272[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_274 = entries_ld_4_valid ? _pop_count_packed_deps_T_273 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_4 = _pop_count_packed_deps_T_274; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_275 = {1'h0, entries_ld_5_bits_deps_ld_0} + {1'h0, entries_ld_5_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_276 = _pop_count_packed_deps_T_275; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_277 = {1'h0, entries_ld_5_bits_deps_ld_2} + {1'h0, entries_ld_5_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_278 = _pop_count_packed_deps_T_277; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_279 = {1'h0, _pop_count_packed_deps_T_276} + {1'h0, _pop_count_packed_deps_T_278}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_280 = _pop_count_packed_deps_T_279; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_281 = {1'h0, entries_ld_5_bits_deps_ld_4} + {1'h0, entries_ld_5_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_282 = _pop_count_packed_deps_T_281; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_283 = {1'h0, entries_ld_5_bits_deps_ld_6} + {1'h0, entries_ld_5_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_284 = _pop_count_packed_deps_T_283; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_285 = {1'h0, _pop_count_packed_deps_T_282} + {1'h0, _pop_count_packed_deps_T_284}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_286 = _pop_count_packed_deps_T_285; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_287 = {1'h0, _pop_count_packed_deps_T_280} + {1'h0, _pop_count_packed_deps_T_286}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_288 = _pop_count_packed_deps_T_287; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_289 = {1'h0, entries_ld_5_bits_deps_ex_0} + {1'h0, entries_ld_5_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_290 = _pop_count_packed_deps_T_289; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_291 = {1'h0, entries_ld_5_bits_deps_ex_2} + {1'h0, entries_ld_5_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_292 = _pop_count_packed_deps_T_291; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_293 = {1'h0, _pop_count_packed_deps_T_290} + {1'h0, _pop_count_packed_deps_T_292}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_294 = _pop_count_packed_deps_T_293; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_295 = {1'h0, entries_ld_5_bits_deps_ex_4} + {1'h0, entries_ld_5_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_296 = _pop_count_packed_deps_T_295; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_297 = {1'h0, entries_ld_5_bits_deps_ex_6} + {1'h0, entries_ld_5_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_298 = _pop_count_packed_deps_T_297; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_299 = {1'h0, _pop_count_packed_deps_T_296} + {1'h0, _pop_count_packed_deps_T_298}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_300 = _pop_count_packed_deps_T_299; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_301 = {1'h0, _pop_count_packed_deps_T_294} + {1'h0, _pop_count_packed_deps_T_300}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_302 = _pop_count_packed_deps_T_301; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_303 = {1'h0, entries_ld_5_bits_deps_ex_8} + {1'h0, entries_ld_5_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_304 = _pop_count_packed_deps_T_303; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_305 = {1'h0, entries_ld_5_bits_deps_ex_10} + {1'h0, entries_ld_5_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_306 = _pop_count_packed_deps_T_305; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_307 = {1'h0, _pop_count_packed_deps_T_304} + {1'h0, _pop_count_packed_deps_T_306}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_308 = _pop_count_packed_deps_T_307; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_309 = {1'h0, entries_ld_5_bits_deps_ex_12} + {1'h0, entries_ld_5_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_310 = _pop_count_packed_deps_T_309; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_311 = {1'h0, entries_ld_5_bits_deps_ex_14} + {1'h0, entries_ld_5_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_312 = _pop_count_packed_deps_T_311; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_313 = {1'h0, _pop_count_packed_deps_T_310} + {1'h0, _pop_count_packed_deps_T_312}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_314 = _pop_count_packed_deps_T_313; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_315 = {1'h0, _pop_count_packed_deps_T_308} + {1'h0, _pop_count_packed_deps_T_314}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_316 = _pop_count_packed_deps_T_315; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_317 = {1'h0, _pop_count_packed_deps_T_302} + {1'h0, _pop_count_packed_deps_T_316}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_318 = _pop_count_packed_deps_T_317; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_319 = {2'h0, _pop_count_packed_deps_T_288} + {1'h0, _pop_count_packed_deps_T_318}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_320 = _pop_count_packed_deps_T_319[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_321 = {1'h0, entries_ld_5_bits_deps_st_0} + {1'h0, entries_ld_5_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_322 = _pop_count_packed_deps_T_321; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_323 = {1'h0, entries_ld_5_bits_deps_st_2} + {1'h0, entries_ld_5_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_324 = _pop_count_packed_deps_T_323; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_325 = {1'h0, _pop_count_packed_deps_T_322} + {1'h0, _pop_count_packed_deps_T_324}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_326 = _pop_count_packed_deps_T_325; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_327 = {1'h0, _pop_count_packed_deps_T_320} + {3'h0, _pop_count_packed_deps_T_326}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_328 = _pop_count_packed_deps_T_327[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_329 = entries_ld_5_valid ? _pop_count_packed_deps_T_328 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_5 = _pop_count_packed_deps_T_329; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_330 = {1'h0, entries_ld_6_bits_deps_ld_0} + {1'h0, entries_ld_6_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_331 = _pop_count_packed_deps_T_330; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_332 = {1'h0, entries_ld_6_bits_deps_ld_2} + {1'h0, entries_ld_6_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_333 = _pop_count_packed_deps_T_332; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_334 = {1'h0, _pop_count_packed_deps_T_331} + {1'h0, _pop_count_packed_deps_T_333}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_335 = _pop_count_packed_deps_T_334; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_336 = {1'h0, entries_ld_6_bits_deps_ld_4} + {1'h0, entries_ld_6_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_337 = _pop_count_packed_deps_T_336; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_338 = {1'h0, entries_ld_6_bits_deps_ld_6} + {1'h0, entries_ld_6_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_339 = _pop_count_packed_deps_T_338; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_340 = {1'h0, _pop_count_packed_deps_T_337} + {1'h0, _pop_count_packed_deps_T_339}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_341 = _pop_count_packed_deps_T_340; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_342 = {1'h0, _pop_count_packed_deps_T_335} + {1'h0, _pop_count_packed_deps_T_341}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_343 = _pop_count_packed_deps_T_342; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_344 = {1'h0, entries_ld_6_bits_deps_ex_0} + {1'h0, entries_ld_6_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_345 = _pop_count_packed_deps_T_344; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_346 = {1'h0, entries_ld_6_bits_deps_ex_2} + {1'h0, entries_ld_6_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_347 = _pop_count_packed_deps_T_346; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_348 = {1'h0, _pop_count_packed_deps_T_345} + {1'h0, _pop_count_packed_deps_T_347}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_349 = _pop_count_packed_deps_T_348; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_350 = {1'h0, entries_ld_6_bits_deps_ex_4} + {1'h0, entries_ld_6_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_351 = _pop_count_packed_deps_T_350; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_352 = {1'h0, entries_ld_6_bits_deps_ex_6} + {1'h0, entries_ld_6_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_353 = _pop_count_packed_deps_T_352; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_354 = {1'h0, _pop_count_packed_deps_T_351} + {1'h0, _pop_count_packed_deps_T_353}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_355 = _pop_count_packed_deps_T_354; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_356 = {1'h0, _pop_count_packed_deps_T_349} + {1'h0, _pop_count_packed_deps_T_355}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_357 = _pop_count_packed_deps_T_356; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_358 = {1'h0, entries_ld_6_bits_deps_ex_8} + {1'h0, entries_ld_6_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_359 = _pop_count_packed_deps_T_358; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_360 = {1'h0, entries_ld_6_bits_deps_ex_10} + {1'h0, entries_ld_6_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_361 = _pop_count_packed_deps_T_360; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_362 = {1'h0, _pop_count_packed_deps_T_359} + {1'h0, _pop_count_packed_deps_T_361}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_363 = _pop_count_packed_deps_T_362; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_364 = {1'h0, entries_ld_6_bits_deps_ex_12} + {1'h0, entries_ld_6_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_365 = _pop_count_packed_deps_T_364; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_366 = {1'h0, entries_ld_6_bits_deps_ex_14} + {1'h0, entries_ld_6_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_367 = _pop_count_packed_deps_T_366; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_368 = {1'h0, _pop_count_packed_deps_T_365} + {1'h0, _pop_count_packed_deps_T_367}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_369 = _pop_count_packed_deps_T_368; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_370 = {1'h0, _pop_count_packed_deps_T_363} + {1'h0, _pop_count_packed_deps_T_369}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_371 = _pop_count_packed_deps_T_370; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_372 = {1'h0, _pop_count_packed_deps_T_357} + {1'h0, _pop_count_packed_deps_T_371}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_373 = _pop_count_packed_deps_T_372; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_374 = {2'h0, _pop_count_packed_deps_T_343} + {1'h0, _pop_count_packed_deps_T_373}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_375 = _pop_count_packed_deps_T_374[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_376 = {1'h0, entries_ld_6_bits_deps_st_0} + {1'h0, entries_ld_6_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_377 = _pop_count_packed_deps_T_376; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_378 = {1'h0, entries_ld_6_bits_deps_st_2} + {1'h0, entries_ld_6_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_379 = _pop_count_packed_deps_T_378; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_380 = {1'h0, _pop_count_packed_deps_T_377} + {1'h0, _pop_count_packed_deps_T_379}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_381 = _pop_count_packed_deps_T_380; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_382 = {1'h0, _pop_count_packed_deps_T_375} + {3'h0, _pop_count_packed_deps_T_381}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_383 = _pop_count_packed_deps_T_382[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_384 = entries_ld_6_valid ? _pop_count_packed_deps_T_383 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_6 = _pop_count_packed_deps_T_384; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_385 = {1'h0, entries_ld_7_bits_deps_ld_0} + {1'h0, entries_ld_7_bits_deps_ld_1}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_386 = _pop_count_packed_deps_T_385; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_387 = {1'h0, entries_ld_7_bits_deps_ld_2} + {1'h0, entries_ld_7_bits_deps_ld_3}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_388 = _pop_count_packed_deps_T_387; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_389 = {1'h0, _pop_count_packed_deps_T_386} + {1'h0, _pop_count_packed_deps_T_388}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_390 = _pop_count_packed_deps_T_389; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_391 = {1'h0, entries_ld_7_bits_deps_ld_4} + {1'h0, entries_ld_7_bits_deps_ld_5}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_392 = _pop_count_packed_deps_T_391; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_393 = {1'h0, entries_ld_7_bits_deps_ld_6} + {1'h0, entries_ld_7_bits_deps_ld_7}; // @[ReservationStation.scala:117:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_394 = _pop_count_packed_deps_T_393; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_395 = {1'h0, _pop_count_packed_deps_T_392} + {1'h0, _pop_count_packed_deps_T_394}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_396 = _pop_count_packed_deps_T_395; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_397 = {1'h0, _pop_count_packed_deps_T_390} + {1'h0, _pop_count_packed_deps_T_396}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_398 = _pop_count_packed_deps_T_397; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_399 = {1'h0, entries_ld_7_bits_deps_ex_0} + {1'h0, entries_ld_7_bits_deps_ex_1}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_400 = _pop_count_packed_deps_T_399; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_401 = {1'h0, entries_ld_7_bits_deps_ex_2} + {1'h0, entries_ld_7_bits_deps_ex_3}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_402 = _pop_count_packed_deps_T_401; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_403 = {1'h0, _pop_count_packed_deps_T_400} + {1'h0, _pop_count_packed_deps_T_402}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_404 = _pop_count_packed_deps_T_403; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_405 = {1'h0, entries_ld_7_bits_deps_ex_4} + {1'h0, entries_ld_7_bits_deps_ex_5}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_406 = _pop_count_packed_deps_T_405; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_407 = {1'h0, entries_ld_7_bits_deps_ex_6} + {1'h0, entries_ld_7_bits_deps_ex_7}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_408 = _pop_count_packed_deps_T_407; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_409 = {1'h0, _pop_count_packed_deps_T_406} + {1'h0, _pop_count_packed_deps_T_408}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_410 = _pop_count_packed_deps_T_409; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_411 = {1'h0, _pop_count_packed_deps_T_404} + {1'h0, _pop_count_packed_deps_T_410}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_412 = _pop_count_packed_deps_T_411; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_413 = {1'h0, entries_ld_7_bits_deps_ex_8} + {1'h0, entries_ld_7_bits_deps_ex_9}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_414 = _pop_count_packed_deps_T_413; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_415 = {1'h0, entries_ld_7_bits_deps_ex_10} + {1'h0, entries_ld_7_bits_deps_ex_11}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_416 = _pop_count_packed_deps_T_415; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_417 = {1'h0, _pop_count_packed_deps_T_414} + {1'h0, _pop_count_packed_deps_T_416}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_418 = _pop_count_packed_deps_T_417; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_419 = {1'h0, entries_ld_7_bits_deps_ex_12} + {1'h0, entries_ld_7_bits_deps_ex_13}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_420 = _pop_count_packed_deps_T_419; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_421 = {1'h0, entries_ld_7_bits_deps_ex_14} + {1'h0, entries_ld_7_bits_deps_ex_15}; // @[ReservationStation.scala:117:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_422 = _pop_count_packed_deps_T_421; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_423 = {1'h0, _pop_count_packed_deps_T_420} + {1'h0, _pop_count_packed_deps_T_422}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_424 = _pop_count_packed_deps_T_423; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_425 = {1'h0, _pop_count_packed_deps_T_418} + {1'h0, _pop_count_packed_deps_T_424}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_426 = _pop_count_packed_deps_T_425; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_427 = {1'h0, _pop_count_packed_deps_T_412} + {1'h0, _pop_count_packed_deps_T_426}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_428 = _pop_count_packed_deps_T_427; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_429 = {2'h0, _pop_count_packed_deps_T_398} + {1'h0, _pop_count_packed_deps_T_428}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_430 = _pop_count_packed_deps_T_429[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_431 = {1'h0, entries_ld_7_bits_deps_st_0} + {1'h0, entries_ld_7_bits_deps_st_1}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_432 = _pop_count_packed_deps_T_431; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_433 = {1'h0, entries_ld_7_bits_deps_st_2} + {1'h0, entries_ld_7_bits_deps_st_3}; // @[ReservationStation.scala:117:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_434 = _pop_count_packed_deps_T_433; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_435 = {1'h0, _pop_count_packed_deps_T_432} + {1'h0, _pop_count_packed_deps_T_434}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_436 = _pop_count_packed_deps_T_435; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_437 = {1'h0, _pop_count_packed_deps_T_430} + {3'h0, _pop_count_packed_deps_T_436}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_438 = _pop_count_packed_deps_T_437[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_439 = entries_ld_7_valid ? _pop_count_packed_deps_T_438 : 5'h0; // @[ReservationStation.scala:117:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_7 = _pop_count_packed_deps_T_439; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_440 = {1'h0, entries_ex_0_bits_deps_ld_0} + {1'h0, entries_ex_0_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_441 = _pop_count_packed_deps_T_440; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_442 = {1'h0, entries_ex_0_bits_deps_ld_2} + {1'h0, entries_ex_0_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_443 = _pop_count_packed_deps_T_442; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_444 = {1'h0, _pop_count_packed_deps_T_441} + {1'h0, _pop_count_packed_deps_T_443}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_445 = _pop_count_packed_deps_T_444; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_446 = {1'h0, entries_ex_0_bits_deps_ld_4} + {1'h0, entries_ex_0_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_447 = _pop_count_packed_deps_T_446; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_448 = {1'h0, entries_ex_0_bits_deps_ld_6} + {1'h0, entries_ex_0_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_449 = _pop_count_packed_deps_T_448; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_450 = {1'h0, _pop_count_packed_deps_T_447} + {1'h0, _pop_count_packed_deps_T_449}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_451 = _pop_count_packed_deps_T_450; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_452 = {1'h0, _pop_count_packed_deps_T_445} + {1'h0, _pop_count_packed_deps_T_451}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_453 = _pop_count_packed_deps_T_452; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_454 = {1'h0, entries_ex_0_bits_deps_ex_0} + {1'h0, entries_ex_0_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_455 = _pop_count_packed_deps_T_454; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_456 = {1'h0, entries_ex_0_bits_deps_ex_2} + {1'h0, entries_ex_0_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_457 = _pop_count_packed_deps_T_456; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_458 = {1'h0, _pop_count_packed_deps_T_455} + {1'h0, _pop_count_packed_deps_T_457}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_459 = _pop_count_packed_deps_T_458; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_460 = {1'h0, entries_ex_0_bits_deps_ex_4} + {1'h0, entries_ex_0_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_461 = _pop_count_packed_deps_T_460; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_462 = {1'h0, entries_ex_0_bits_deps_ex_6} + {1'h0, entries_ex_0_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_463 = _pop_count_packed_deps_T_462; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_464 = {1'h0, _pop_count_packed_deps_T_461} + {1'h0, _pop_count_packed_deps_T_463}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_465 = _pop_count_packed_deps_T_464; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_466 = {1'h0, _pop_count_packed_deps_T_459} + {1'h0, _pop_count_packed_deps_T_465}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_467 = _pop_count_packed_deps_T_466; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_468 = {1'h0, entries_ex_0_bits_deps_ex_8} + {1'h0, entries_ex_0_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_469 = _pop_count_packed_deps_T_468; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_470 = {1'h0, entries_ex_0_bits_deps_ex_10} + {1'h0, entries_ex_0_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_471 = _pop_count_packed_deps_T_470; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_472 = {1'h0, _pop_count_packed_deps_T_469} + {1'h0, _pop_count_packed_deps_T_471}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_473 = _pop_count_packed_deps_T_472; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_474 = {1'h0, entries_ex_0_bits_deps_ex_12} + {1'h0, entries_ex_0_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_475 = _pop_count_packed_deps_T_474; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_476 = {1'h0, entries_ex_0_bits_deps_ex_14} + {1'h0, entries_ex_0_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_477 = _pop_count_packed_deps_T_476; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_478 = {1'h0, _pop_count_packed_deps_T_475} + {1'h0, _pop_count_packed_deps_T_477}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_479 = _pop_count_packed_deps_T_478; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_480 = {1'h0, _pop_count_packed_deps_T_473} + {1'h0, _pop_count_packed_deps_T_479}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_481 = _pop_count_packed_deps_T_480; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_482 = {1'h0, _pop_count_packed_deps_T_467} + {1'h0, _pop_count_packed_deps_T_481}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_483 = _pop_count_packed_deps_T_482; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_484 = {2'h0, _pop_count_packed_deps_T_453} + {1'h0, _pop_count_packed_deps_T_483}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_485 = _pop_count_packed_deps_T_484[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_486 = {1'h0, entries_ex_0_bits_deps_st_0} + {1'h0, entries_ex_0_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_487 = _pop_count_packed_deps_T_486; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_488 = {1'h0, entries_ex_0_bits_deps_st_2} + {1'h0, entries_ex_0_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_489 = _pop_count_packed_deps_T_488; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_490 = {1'h0, _pop_count_packed_deps_T_487} + {1'h0, _pop_count_packed_deps_T_489}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_491 = _pop_count_packed_deps_T_490; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_492 = {1'h0, _pop_count_packed_deps_T_485} + {3'h0, _pop_count_packed_deps_T_491}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_493 = _pop_count_packed_deps_T_492[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_494 = entries_ex_0_valid ? _pop_count_packed_deps_T_493 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_8 = _pop_count_packed_deps_T_494; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_495 = {1'h0, entries_ex_1_bits_deps_ld_0} + {1'h0, entries_ex_1_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_496 = _pop_count_packed_deps_T_495; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_497 = {1'h0, entries_ex_1_bits_deps_ld_2} + {1'h0, entries_ex_1_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_498 = _pop_count_packed_deps_T_497; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_499 = {1'h0, _pop_count_packed_deps_T_496} + {1'h0, _pop_count_packed_deps_T_498}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_500 = _pop_count_packed_deps_T_499; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_501 = {1'h0, entries_ex_1_bits_deps_ld_4} + {1'h0, entries_ex_1_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_502 = _pop_count_packed_deps_T_501; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_503 = {1'h0, entries_ex_1_bits_deps_ld_6} + {1'h0, entries_ex_1_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_504 = _pop_count_packed_deps_T_503; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_505 = {1'h0, _pop_count_packed_deps_T_502} + {1'h0, _pop_count_packed_deps_T_504}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_506 = _pop_count_packed_deps_T_505; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_507 = {1'h0, _pop_count_packed_deps_T_500} + {1'h0, _pop_count_packed_deps_T_506}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_508 = _pop_count_packed_deps_T_507; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_509 = {1'h0, entries_ex_1_bits_deps_ex_0} + {1'h0, entries_ex_1_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_510 = _pop_count_packed_deps_T_509; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_511 = {1'h0, entries_ex_1_bits_deps_ex_2} + {1'h0, entries_ex_1_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_512 = _pop_count_packed_deps_T_511; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_513 = {1'h0, _pop_count_packed_deps_T_510} + {1'h0, _pop_count_packed_deps_T_512}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_514 = _pop_count_packed_deps_T_513; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_515 = {1'h0, entries_ex_1_bits_deps_ex_4} + {1'h0, entries_ex_1_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_516 = _pop_count_packed_deps_T_515; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_517 = {1'h0, entries_ex_1_bits_deps_ex_6} + {1'h0, entries_ex_1_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_518 = _pop_count_packed_deps_T_517; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_519 = {1'h0, _pop_count_packed_deps_T_516} + {1'h0, _pop_count_packed_deps_T_518}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_520 = _pop_count_packed_deps_T_519; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_521 = {1'h0, _pop_count_packed_deps_T_514} + {1'h0, _pop_count_packed_deps_T_520}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_522 = _pop_count_packed_deps_T_521; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_523 = {1'h0, entries_ex_1_bits_deps_ex_8} + {1'h0, entries_ex_1_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_524 = _pop_count_packed_deps_T_523; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_525 = {1'h0, entries_ex_1_bits_deps_ex_10} + {1'h0, entries_ex_1_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_526 = _pop_count_packed_deps_T_525; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_527 = {1'h0, _pop_count_packed_deps_T_524} + {1'h0, _pop_count_packed_deps_T_526}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_528 = _pop_count_packed_deps_T_527; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_529 = {1'h0, entries_ex_1_bits_deps_ex_12} + {1'h0, entries_ex_1_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_530 = _pop_count_packed_deps_T_529; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_531 = {1'h0, entries_ex_1_bits_deps_ex_14} + {1'h0, entries_ex_1_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_532 = _pop_count_packed_deps_T_531; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_533 = {1'h0, _pop_count_packed_deps_T_530} + {1'h0, _pop_count_packed_deps_T_532}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_534 = _pop_count_packed_deps_T_533; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_535 = {1'h0, _pop_count_packed_deps_T_528} + {1'h0, _pop_count_packed_deps_T_534}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_536 = _pop_count_packed_deps_T_535; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_537 = {1'h0, _pop_count_packed_deps_T_522} + {1'h0, _pop_count_packed_deps_T_536}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_538 = _pop_count_packed_deps_T_537; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_539 = {2'h0, _pop_count_packed_deps_T_508} + {1'h0, _pop_count_packed_deps_T_538}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_540 = _pop_count_packed_deps_T_539[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_541 = {1'h0, entries_ex_1_bits_deps_st_0} + {1'h0, entries_ex_1_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_542 = _pop_count_packed_deps_T_541; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_543 = {1'h0, entries_ex_1_bits_deps_st_2} + {1'h0, entries_ex_1_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_544 = _pop_count_packed_deps_T_543; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_545 = {1'h0, _pop_count_packed_deps_T_542} + {1'h0, _pop_count_packed_deps_T_544}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_546 = _pop_count_packed_deps_T_545; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_547 = {1'h0, _pop_count_packed_deps_T_540} + {3'h0, _pop_count_packed_deps_T_546}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_548 = _pop_count_packed_deps_T_547[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_549 = entries_ex_1_valid ? _pop_count_packed_deps_T_548 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_9 = _pop_count_packed_deps_T_549; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_550 = {1'h0, entries_ex_2_bits_deps_ld_0} + {1'h0, entries_ex_2_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_551 = _pop_count_packed_deps_T_550; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_552 = {1'h0, entries_ex_2_bits_deps_ld_2} + {1'h0, entries_ex_2_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_553 = _pop_count_packed_deps_T_552; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_554 = {1'h0, _pop_count_packed_deps_T_551} + {1'h0, _pop_count_packed_deps_T_553}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_555 = _pop_count_packed_deps_T_554; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_556 = {1'h0, entries_ex_2_bits_deps_ld_4} + {1'h0, entries_ex_2_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_557 = _pop_count_packed_deps_T_556; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_558 = {1'h0, entries_ex_2_bits_deps_ld_6} + {1'h0, entries_ex_2_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_559 = _pop_count_packed_deps_T_558; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_560 = {1'h0, _pop_count_packed_deps_T_557} + {1'h0, _pop_count_packed_deps_T_559}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_561 = _pop_count_packed_deps_T_560; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_562 = {1'h0, _pop_count_packed_deps_T_555} + {1'h0, _pop_count_packed_deps_T_561}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_563 = _pop_count_packed_deps_T_562; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_564 = {1'h0, entries_ex_2_bits_deps_ex_0} + {1'h0, entries_ex_2_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_565 = _pop_count_packed_deps_T_564; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_566 = {1'h0, entries_ex_2_bits_deps_ex_2} + {1'h0, entries_ex_2_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_567 = _pop_count_packed_deps_T_566; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_568 = {1'h0, _pop_count_packed_deps_T_565} + {1'h0, _pop_count_packed_deps_T_567}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_569 = _pop_count_packed_deps_T_568; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_570 = {1'h0, entries_ex_2_bits_deps_ex_4} + {1'h0, entries_ex_2_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_571 = _pop_count_packed_deps_T_570; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_572 = {1'h0, entries_ex_2_bits_deps_ex_6} + {1'h0, entries_ex_2_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_573 = _pop_count_packed_deps_T_572; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_574 = {1'h0, _pop_count_packed_deps_T_571} + {1'h0, _pop_count_packed_deps_T_573}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_575 = _pop_count_packed_deps_T_574; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_576 = {1'h0, _pop_count_packed_deps_T_569} + {1'h0, _pop_count_packed_deps_T_575}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_577 = _pop_count_packed_deps_T_576; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_578 = {1'h0, entries_ex_2_bits_deps_ex_8} + {1'h0, entries_ex_2_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_579 = _pop_count_packed_deps_T_578; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_580 = {1'h0, entries_ex_2_bits_deps_ex_10} + {1'h0, entries_ex_2_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_581 = _pop_count_packed_deps_T_580; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_582 = {1'h0, _pop_count_packed_deps_T_579} + {1'h0, _pop_count_packed_deps_T_581}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_583 = _pop_count_packed_deps_T_582; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_584 = {1'h0, entries_ex_2_bits_deps_ex_12} + {1'h0, entries_ex_2_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_585 = _pop_count_packed_deps_T_584; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_586 = {1'h0, entries_ex_2_bits_deps_ex_14} + {1'h0, entries_ex_2_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_587 = _pop_count_packed_deps_T_586; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_588 = {1'h0, _pop_count_packed_deps_T_585} + {1'h0, _pop_count_packed_deps_T_587}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_589 = _pop_count_packed_deps_T_588; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_590 = {1'h0, _pop_count_packed_deps_T_583} + {1'h0, _pop_count_packed_deps_T_589}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_591 = _pop_count_packed_deps_T_590; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_592 = {1'h0, _pop_count_packed_deps_T_577} + {1'h0, _pop_count_packed_deps_T_591}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_593 = _pop_count_packed_deps_T_592; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_594 = {2'h0, _pop_count_packed_deps_T_563} + {1'h0, _pop_count_packed_deps_T_593}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_595 = _pop_count_packed_deps_T_594[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_596 = {1'h0, entries_ex_2_bits_deps_st_0} + {1'h0, entries_ex_2_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_597 = _pop_count_packed_deps_T_596; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_598 = {1'h0, entries_ex_2_bits_deps_st_2} + {1'h0, entries_ex_2_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_599 = _pop_count_packed_deps_T_598; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_600 = {1'h0, _pop_count_packed_deps_T_597} + {1'h0, _pop_count_packed_deps_T_599}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_601 = _pop_count_packed_deps_T_600; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_602 = {1'h0, _pop_count_packed_deps_T_595} + {3'h0, _pop_count_packed_deps_T_601}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_603 = _pop_count_packed_deps_T_602[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_604 = entries_ex_2_valid ? _pop_count_packed_deps_T_603 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_10 = _pop_count_packed_deps_T_604; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_605 = {1'h0, entries_ex_3_bits_deps_ld_0} + {1'h0, entries_ex_3_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_606 = _pop_count_packed_deps_T_605; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_607 = {1'h0, entries_ex_3_bits_deps_ld_2} + {1'h0, entries_ex_3_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_608 = _pop_count_packed_deps_T_607; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_609 = {1'h0, _pop_count_packed_deps_T_606} + {1'h0, _pop_count_packed_deps_T_608}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_610 = _pop_count_packed_deps_T_609; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_611 = {1'h0, entries_ex_3_bits_deps_ld_4} + {1'h0, entries_ex_3_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_612 = _pop_count_packed_deps_T_611; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_613 = {1'h0, entries_ex_3_bits_deps_ld_6} + {1'h0, entries_ex_3_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_614 = _pop_count_packed_deps_T_613; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_615 = {1'h0, _pop_count_packed_deps_T_612} + {1'h0, _pop_count_packed_deps_T_614}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_616 = _pop_count_packed_deps_T_615; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_617 = {1'h0, _pop_count_packed_deps_T_610} + {1'h0, _pop_count_packed_deps_T_616}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_618 = _pop_count_packed_deps_T_617; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_619 = {1'h0, entries_ex_3_bits_deps_ex_0} + {1'h0, entries_ex_3_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_620 = _pop_count_packed_deps_T_619; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_621 = {1'h0, entries_ex_3_bits_deps_ex_2} + {1'h0, entries_ex_3_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_622 = _pop_count_packed_deps_T_621; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_623 = {1'h0, _pop_count_packed_deps_T_620} + {1'h0, _pop_count_packed_deps_T_622}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_624 = _pop_count_packed_deps_T_623; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_625 = {1'h0, entries_ex_3_bits_deps_ex_4} + {1'h0, entries_ex_3_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_626 = _pop_count_packed_deps_T_625; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_627 = {1'h0, entries_ex_3_bits_deps_ex_6} + {1'h0, entries_ex_3_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_628 = _pop_count_packed_deps_T_627; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_629 = {1'h0, _pop_count_packed_deps_T_626} + {1'h0, _pop_count_packed_deps_T_628}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_630 = _pop_count_packed_deps_T_629; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_631 = {1'h0, _pop_count_packed_deps_T_624} + {1'h0, _pop_count_packed_deps_T_630}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_632 = _pop_count_packed_deps_T_631; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_633 = {1'h0, entries_ex_3_bits_deps_ex_8} + {1'h0, entries_ex_3_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_634 = _pop_count_packed_deps_T_633; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_635 = {1'h0, entries_ex_3_bits_deps_ex_10} + {1'h0, entries_ex_3_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_636 = _pop_count_packed_deps_T_635; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_637 = {1'h0, _pop_count_packed_deps_T_634} + {1'h0, _pop_count_packed_deps_T_636}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_638 = _pop_count_packed_deps_T_637; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_639 = {1'h0, entries_ex_3_bits_deps_ex_12} + {1'h0, entries_ex_3_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_640 = _pop_count_packed_deps_T_639; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_641 = {1'h0, entries_ex_3_bits_deps_ex_14} + {1'h0, entries_ex_3_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_642 = _pop_count_packed_deps_T_641; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_643 = {1'h0, _pop_count_packed_deps_T_640} + {1'h0, _pop_count_packed_deps_T_642}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_644 = _pop_count_packed_deps_T_643; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_645 = {1'h0, _pop_count_packed_deps_T_638} + {1'h0, _pop_count_packed_deps_T_644}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_646 = _pop_count_packed_deps_T_645; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_647 = {1'h0, _pop_count_packed_deps_T_632} + {1'h0, _pop_count_packed_deps_T_646}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_648 = _pop_count_packed_deps_T_647; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_649 = {2'h0, _pop_count_packed_deps_T_618} + {1'h0, _pop_count_packed_deps_T_648}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_650 = _pop_count_packed_deps_T_649[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_651 = {1'h0, entries_ex_3_bits_deps_st_0} + {1'h0, entries_ex_3_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_652 = _pop_count_packed_deps_T_651; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_653 = {1'h0, entries_ex_3_bits_deps_st_2} + {1'h0, entries_ex_3_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_654 = _pop_count_packed_deps_T_653; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_655 = {1'h0, _pop_count_packed_deps_T_652} + {1'h0, _pop_count_packed_deps_T_654}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_656 = _pop_count_packed_deps_T_655; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_657 = {1'h0, _pop_count_packed_deps_T_650} + {3'h0, _pop_count_packed_deps_T_656}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_658 = _pop_count_packed_deps_T_657[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_659 = entries_ex_3_valid ? _pop_count_packed_deps_T_658 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_11 = _pop_count_packed_deps_T_659; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_660 = {1'h0, entries_ex_4_bits_deps_ld_0} + {1'h0, entries_ex_4_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_661 = _pop_count_packed_deps_T_660; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_662 = {1'h0, entries_ex_4_bits_deps_ld_2} + {1'h0, entries_ex_4_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_663 = _pop_count_packed_deps_T_662; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_664 = {1'h0, _pop_count_packed_deps_T_661} + {1'h0, _pop_count_packed_deps_T_663}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_665 = _pop_count_packed_deps_T_664; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_666 = {1'h0, entries_ex_4_bits_deps_ld_4} + {1'h0, entries_ex_4_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_667 = _pop_count_packed_deps_T_666; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_668 = {1'h0, entries_ex_4_bits_deps_ld_6} + {1'h0, entries_ex_4_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_669 = _pop_count_packed_deps_T_668; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_670 = {1'h0, _pop_count_packed_deps_T_667} + {1'h0, _pop_count_packed_deps_T_669}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_671 = _pop_count_packed_deps_T_670; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_672 = {1'h0, _pop_count_packed_deps_T_665} + {1'h0, _pop_count_packed_deps_T_671}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_673 = _pop_count_packed_deps_T_672; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_674 = {1'h0, entries_ex_4_bits_deps_ex_0} + {1'h0, entries_ex_4_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_675 = _pop_count_packed_deps_T_674; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_676 = {1'h0, entries_ex_4_bits_deps_ex_2} + {1'h0, entries_ex_4_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_677 = _pop_count_packed_deps_T_676; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_678 = {1'h0, _pop_count_packed_deps_T_675} + {1'h0, _pop_count_packed_deps_T_677}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_679 = _pop_count_packed_deps_T_678; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_680 = {1'h0, entries_ex_4_bits_deps_ex_4} + {1'h0, entries_ex_4_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_681 = _pop_count_packed_deps_T_680; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_682 = {1'h0, entries_ex_4_bits_deps_ex_6} + {1'h0, entries_ex_4_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_683 = _pop_count_packed_deps_T_682; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_684 = {1'h0, _pop_count_packed_deps_T_681} + {1'h0, _pop_count_packed_deps_T_683}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_685 = _pop_count_packed_deps_T_684; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_686 = {1'h0, _pop_count_packed_deps_T_679} + {1'h0, _pop_count_packed_deps_T_685}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_687 = _pop_count_packed_deps_T_686; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_688 = {1'h0, entries_ex_4_bits_deps_ex_8} + {1'h0, entries_ex_4_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_689 = _pop_count_packed_deps_T_688; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_690 = {1'h0, entries_ex_4_bits_deps_ex_10} + {1'h0, entries_ex_4_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_691 = _pop_count_packed_deps_T_690; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_692 = {1'h0, _pop_count_packed_deps_T_689} + {1'h0, _pop_count_packed_deps_T_691}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_693 = _pop_count_packed_deps_T_692; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_694 = {1'h0, entries_ex_4_bits_deps_ex_12} + {1'h0, entries_ex_4_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_695 = _pop_count_packed_deps_T_694; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_696 = {1'h0, entries_ex_4_bits_deps_ex_14} + {1'h0, entries_ex_4_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_697 = _pop_count_packed_deps_T_696; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_698 = {1'h0, _pop_count_packed_deps_T_695} + {1'h0, _pop_count_packed_deps_T_697}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_699 = _pop_count_packed_deps_T_698; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_700 = {1'h0, _pop_count_packed_deps_T_693} + {1'h0, _pop_count_packed_deps_T_699}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_701 = _pop_count_packed_deps_T_700; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_702 = {1'h0, _pop_count_packed_deps_T_687} + {1'h0, _pop_count_packed_deps_T_701}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_703 = _pop_count_packed_deps_T_702; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_704 = {2'h0, _pop_count_packed_deps_T_673} + {1'h0, _pop_count_packed_deps_T_703}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_705 = _pop_count_packed_deps_T_704[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_706 = {1'h0, entries_ex_4_bits_deps_st_0} + {1'h0, entries_ex_4_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_707 = _pop_count_packed_deps_T_706; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_708 = {1'h0, entries_ex_4_bits_deps_st_2} + {1'h0, entries_ex_4_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_709 = _pop_count_packed_deps_T_708; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_710 = {1'h0, _pop_count_packed_deps_T_707} + {1'h0, _pop_count_packed_deps_T_709}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_711 = _pop_count_packed_deps_T_710; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_712 = {1'h0, _pop_count_packed_deps_T_705} + {3'h0, _pop_count_packed_deps_T_711}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_713 = _pop_count_packed_deps_T_712[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_714 = entries_ex_4_valid ? _pop_count_packed_deps_T_713 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_12 = _pop_count_packed_deps_T_714; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_715 = {1'h0, entries_ex_5_bits_deps_ld_0} + {1'h0, entries_ex_5_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_716 = _pop_count_packed_deps_T_715; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_717 = {1'h0, entries_ex_5_bits_deps_ld_2} + {1'h0, entries_ex_5_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_718 = _pop_count_packed_deps_T_717; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_719 = {1'h0, _pop_count_packed_deps_T_716} + {1'h0, _pop_count_packed_deps_T_718}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_720 = _pop_count_packed_deps_T_719; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_721 = {1'h0, entries_ex_5_bits_deps_ld_4} + {1'h0, entries_ex_5_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_722 = _pop_count_packed_deps_T_721; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_723 = {1'h0, entries_ex_5_bits_deps_ld_6} + {1'h0, entries_ex_5_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_724 = _pop_count_packed_deps_T_723; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_725 = {1'h0, _pop_count_packed_deps_T_722} + {1'h0, _pop_count_packed_deps_T_724}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_726 = _pop_count_packed_deps_T_725; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_727 = {1'h0, _pop_count_packed_deps_T_720} + {1'h0, _pop_count_packed_deps_T_726}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_728 = _pop_count_packed_deps_T_727; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_729 = {1'h0, entries_ex_5_bits_deps_ex_0} + {1'h0, entries_ex_5_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_730 = _pop_count_packed_deps_T_729; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_731 = {1'h0, entries_ex_5_bits_deps_ex_2} + {1'h0, entries_ex_5_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_732 = _pop_count_packed_deps_T_731; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_733 = {1'h0, _pop_count_packed_deps_T_730} + {1'h0, _pop_count_packed_deps_T_732}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_734 = _pop_count_packed_deps_T_733; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_735 = {1'h0, entries_ex_5_bits_deps_ex_4} + {1'h0, entries_ex_5_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_736 = _pop_count_packed_deps_T_735; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_737 = {1'h0, entries_ex_5_bits_deps_ex_6} + {1'h0, entries_ex_5_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_738 = _pop_count_packed_deps_T_737; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_739 = {1'h0, _pop_count_packed_deps_T_736} + {1'h0, _pop_count_packed_deps_T_738}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_740 = _pop_count_packed_deps_T_739; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_741 = {1'h0, _pop_count_packed_deps_T_734} + {1'h0, _pop_count_packed_deps_T_740}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_742 = _pop_count_packed_deps_T_741; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_743 = {1'h0, entries_ex_5_bits_deps_ex_8} + {1'h0, entries_ex_5_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_744 = _pop_count_packed_deps_T_743; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_745 = {1'h0, entries_ex_5_bits_deps_ex_10} + {1'h0, entries_ex_5_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_746 = _pop_count_packed_deps_T_745; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_747 = {1'h0, _pop_count_packed_deps_T_744} + {1'h0, _pop_count_packed_deps_T_746}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_748 = _pop_count_packed_deps_T_747; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_749 = {1'h0, entries_ex_5_bits_deps_ex_12} + {1'h0, entries_ex_5_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_750 = _pop_count_packed_deps_T_749; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_751 = {1'h0, entries_ex_5_bits_deps_ex_14} + {1'h0, entries_ex_5_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_752 = _pop_count_packed_deps_T_751; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_753 = {1'h0, _pop_count_packed_deps_T_750} + {1'h0, _pop_count_packed_deps_T_752}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_754 = _pop_count_packed_deps_T_753; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_755 = {1'h0, _pop_count_packed_deps_T_748} + {1'h0, _pop_count_packed_deps_T_754}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_756 = _pop_count_packed_deps_T_755; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_757 = {1'h0, _pop_count_packed_deps_T_742} + {1'h0, _pop_count_packed_deps_T_756}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_758 = _pop_count_packed_deps_T_757; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_759 = {2'h0, _pop_count_packed_deps_T_728} + {1'h0, _pop_count_packed_deps_T_758}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_760 = _pop_count_packed_deps_T_759[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_761 = {1'h0, entries_ex_5_bits_deps_st_0} + {1'h0, entries_ex_5_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_762 = _pop_count_packed_deps_T_761; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_763 = {1'h0, entries_ex_5_bits_deps_st_2} + {1'h0, entries_ex_5_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_764 = _pop_count_packed_deps_T_763; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_765 = {1'h0, _pop_count_packed_deps_T_762} + {1'h0, _pop_count_packed_deps_T_764}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_766 = _pop_count_packed_deps_T_765; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_767 = {1'h0, _pop_count_packed_deps_T_760} + {3'h0, _pop_count_packed_deps_T_766}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_768 = _pop_count_packed_deps_T_767[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_769 = entries_ex_5_valid ? _pop_count_packed_deps_T_768 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_13 = _pop_count_packed_deps_T_769; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_770 = {1'h0, entries_ex_6_bits_deps_ld_0} + {1'h0, entries_ex_6_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_771 = _pop_count_packed_deps_T_770; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_772 = {1'h0, entries_ex_6_bits_deps_ld_2} + {1'h0, entries_ex_6_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_773 = _pop_count_packed_deps_T_772; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_774 = {1'h0, _pop_count_packed_deps_T_771} + {1'h0, _pop_count_packed_deps_T_773}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_775 = _pop_count_packed_deps_T_774; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_776 = {1'h0, entries_ex_6_bits_deps_ld_4} + {1'h0, entries_ex_6_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_777 = _pop_count_packed_deps_T_776; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_778 = {1'h0, entries_ex_6_bits_deps_ld_6} + {1'h0, entries_ex_6_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_779 = _pop_count_packed_deps_T_778; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_780 = {1'h0, _pop_count_packed_deps_T_777} + {1'h0, _pop_count_packed_deps_T_779}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_781 = _pop_count_packed_deps_T_780; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_782 = {1'h0, _pop_count_packed_deps_T_775} + {1'h0, _pop_count_packed_deps_T_781}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_783 = _pop_count_packed_deps_T_782; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_784 = {1'h0, entries_ex_6_bits_deps_ex_0} + {1'h0, entries_ex_6_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_785 = _pop_count_packed_deps_T_784; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_786 = {1'h0, entries_ex_6_bits_deps_ex_2} + {1'h0, entries_ex_6_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_787 = _pop_count_packed_deps_T_786; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_788 = {1'h0, _pop_count_packed_deps_T_785} + {1'h0, _pop_count_packed_deps_T_787}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_789 = _pop_count_packed_deps_T_788; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_790 = {1'h0, entries_ex_6_bits_deps_ex_4} + {1'h0, entries_ex_6_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_791 = _pop_count_packed_deps_T_790; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_792 = {1'h0, entries_ex_6_bits_deps_ex_6} + {1'h0, entries_ex_6_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_793 = _pop_count_packed_deps_T_792; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_794 = {1'h0, _pop_count_packed_deps_T_791} + {1'h0, _pop_count_packed_deps_T_793}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_795 = _pop_count_packed_deps_T_794; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_796 = {1'h0, _pop_count_packed_deps_T_789} + {1'h0, _pop_count_packed_deps_T_795}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_797 = _pop_count_packed_deps_T_796; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_798 = {1'h0, entries_ex_6_bits_deps_ex_8} + {1'h0, entries_ex_6_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_799 = _pop_count_packed_deps_T_798; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_800 = {1'h0, entries_ex_6_bits_deps_ex_10} + {1'h0, entries_ex_6_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_801 = _pop_count_packed_deps_T_800; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_802 = {1'h0, _pop_count_packed_deps_T_799} + {1'h0, _pop_count_packed_deps_T_801}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_803 = _pop_count_packed_deps_T_802; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_804 = {1'h0, entries_ex_6_bits_deps_ex_12} + {1'h0, entries_ex_6_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_805 = _pop_count_packed_deps_T_804; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_806 = {1'h0, entries_ex_6_bits_deps_ex_14} + {1'h0, entries_ex_6_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_807 = _pop_count_packed_deps_T_806; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_808 = {1'h0, _pop_count_packed_deps_T_805} + {1'h0, _pop_count_packed_deps_T_807}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_809 = _pop_count_packed_deps_T_808; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_810 = {1'h0, _pop_count_packed_deps_T_803} + {1'h0, _pop_count_packed_deps_T_809}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_811 = _pop_count_packed_deps_T_810; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_812 = {1'h0, _pop_count_packed_deps_T_797} + {1'h0, _pop_count_packed_deps_T_811}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_813 = _pop_count_packed_deps_T_812; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_814 = {2'h0, _pop_count_packed_deps_T_783} + {1'h0, _pop_count_packed_deps_T_813}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_815 = _pop_count_packed_deps_T_814[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_816 = {1'h0, entries_ex_6_bits_deps_st_0} + {1'h0, entries_ex_6_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_817 = _pop_count_packed_deps_T_816; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_818 = {1'h0, entries_ex_6_bits_deps_st_2} + {1'h0, entries_ex_6_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_819 = _pop_count_packed_deps_T_818; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_820 = {1'h0, _pop_count_packed_deps_T_817} + {1'h0, _pop_count_packed_deps_T_819}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_821 = _pop_count_packed_deps_T_820; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_822 = {1'h0, _pop_count_packed_deps_T_815} + {3'h0, _pop_count_packed_deps_T_821}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_823 = _pop_count_packed_deps_T_822[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_824 = entries_ex_6_valid ? _pop_count_packed_deps_T_823 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_14 = _pop_count_packed_deps_T_824; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_825 = {1'h0, entries_ex_7_bits_deps_ld_0} + {1'h0, entries_ex_7_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_826 = _pop_count_packed_deps_T_825; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_827 = {1'h0, entries_ex_7_bits_deps_ld_2} + {1'h0, entries_ex_7_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_828 = _pop_count_packed_deps_T_827; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_829 = {1'h0, _pop_count_packed_deps_T_826} + {1'h0, _pop_count_packed_deps_T_828}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_830 = _pop_count_packed_deps_T_829; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_831 = {1'h0, entries_ex_7_bits_deps_ld_4} + {1'h0, entries_ex_7_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_832 = _pop_count_packed_deps_T_831; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_833 = {1'h0, entries_ex_7_bits_deps_ld_6} + {1'h0, entries_ex_7_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_834 = _pop_count_packed_deps_T_833; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_835 = {1'h0, _pop_count_packed_deps_T_832} + {1'h0, _pop_count_packed_deps_T_834}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_836 = _pop_count_packed_deps_T_835; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_837 = {1'h0, _pop_count_packed_deps_T_830} + {1'h0, _pop_count_packed_deps_T_836}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_838 = _pop_count_packed_deps_T_837; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_839 = {1'h0, entries_ex_7_bits_deps_ex_0} + {1'h0, entries_ex_7_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_840 = _pop_count_packed_deps_T_839; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_841 = {1'h0, entries_ex_7_bits_deps_ex_2} + {1'h0, entries_ex_7_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_842 = _pop_count_packed_deps_T_841; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_843 = {1'h0, _pop_count_packed_deps_T_840} + {1'h0, _pop_count_packed_deps_T_842}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_844 = _pop_count_packed_deps_T_843; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_845 = {1'h0, entries_ex_7_bits_deps_ex_4} + {1'h0, entries_ex_7_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_846 = _pop_count_packed_deps_T_845; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_847 = {1'h0, entries_ex_7_bits_deps_ex_6} + {1'h0, entries_ex_7_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_848 = _pop_count_packed_deps_T_847; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_849 = {1'h0, _pop_count_packed_deps_T_846} + {1'h0, _pop_count_packed_deps_T_848}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_850 = _pop_count_packed_deps_T_849; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_851 = {1'h0, _pop_count_packed_deps_T_844} + {1'h0, _pop_count_packed_deps_T_850}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_852 = _pop_count_packed_deps_T_851; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_853 = {1'h0, entries_ex_7_bits_deps_ex_8} + {1'h0, entries_ex_7_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_854 = _pop_count_packed_deps_T_853; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_855 = {1'h0, entries_ex_7_bits_deps_ex_10} + {1'h0, entries_ex_7_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_856 = _pop_count_packed_deps_T_855; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_857 = {1'h0, _pop_count_packed_deps_T_854} + {1'h0, _pop_count_packed_deps_T_856}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_858 = _pop_count_packed_deps_T_857; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_859 = {1'h0, entries_ex_7_bits_deps_ex_12} + {1'h0, entries_ex_7_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_860 = _pop_count_packed_deps_T_859; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_861 = {1'h0, entries_ex_7_bits_deps_ex_14} + {1'h0, entries_ex_7_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_862 = _pop_count_packed_deps_T_861; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_863 = {1'h0, _pop_count_packed_deps_T_860} + {1'h0, _pop_count_packed_deps_T_862}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_864 = _pop_count_packed_deps_T_863; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_865 = {1'h0, _pop_count_packed_deps_T_858} + {1'h0, _pop_count_packed_deps_T_864}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_866 = _pop_count_packed_deps_T_865; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_867 = {1'h0, _pop_count_packed_deps_T_852} + {1'h0, _pop_count_packed_deps_T_866}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_868 = _pop_count_packed_deps_T_867; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_869 = {2'h0, _pop_count_packed_deps_T_838} + {1'h0, _pop_count_packed_deps_T_868}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_870 = _pop_count_packed_deps_T_869[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_871 = {1'h0, entries_ex_7_bits_deps_st_0} + {1'h0, entries_ex_7_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_872 = _pop_count_packed_deps_T_871; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_873 = {1'h0, entries_ex_7_bits_deps_st_2} + {1'h0, entries_ex_7_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_874 = _pop_count_packed_deps_T_873; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_875 = {1'h0, _pop_count_packed_deps_T_872} + {1'h0, _pop_count_packed_deps_T_874}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_876 = _pop_count_packed_deps_T_875; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_877 = {1'h0, _pop_count_packed_deps_T_870} + {3'h0, _pop_count_packed_deps_T_876}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_878 = _pop_count_packed_deps_T_877[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_879 = entries_ex_7_valid ? _pop_count_packed_deps_T_878 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_15 = _pop_count_packed_deps_T_879; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_880 = {1'h0, entries_ex_8_bits_deps_ld_0} + {1'h0, entries_ex_8_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_881 = _pop_count_packed_deps_T_880; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_882 = {1'h0, entries_ex_8_bits_deps_ld_2} + {1'h0, entries_ex_8_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_883 = _pop_count_packed_deps_T_882; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_884 = {1'h0, _pop_count_packed_deps_T_881} + {1'h0, _pop_count_packed_deps_T_883}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_885 = _pop_count_packed_deps_T_884; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_886 = {1'h0, entries_ex_8_bits_deps_ld_4} + {1'h0, entries_ex_8_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_887 = _pop_count_packed_deps_T_886; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_888 = {1'h0, entries_ex_8_bits_deps_ld_6} + {1'h0, entries_ex_8_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_889 = _pop_count_packed_deps_T_888; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_890 = {1'h0, _pop_count_packed_deps_T_887} + {1'h0, _pop_count_packed_deps_T_889}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_891 = _pop_count_packed_deps_T_890; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_892 = {1'h0, _pop_count_packed_deps_T_885} + {1'h0, _pop_count_packed_deps_T_891}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_893 = _pop_count_packed_deps_T_892; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_894 = {1'h0, entries_ex_8_bits_deps_ex_0} + {1'h0, entries_ex_8_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_895 = _pop_count_packed_deps_T_894; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_896 = {1'h0, entries_ex_8_bits_deps_ex_2} + {1'h0, entries_ex_8_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_897 = _pop_count_packed_deps_T_896; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_898 = {1'h0, _pop_count_packed_deps_T_895} + {1'h0, _pop_count_packed_deps_T_897}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_899 = _pop_count_packed_deps_T_898; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_900 = {1'h0, entries_ex_8_bits_deps_ex_4} + {1'h0, entries_ex_8_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_901 = _pop_count_packed_deps_T_900; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_902 = {1'h0, entries_ex_8_bits_deps_ex_6} + {1'h0, entries_ex_8_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_903 = _pop_count_packed_deps_T_902; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_904 = {1'h0, _pop_count_packed_deps_T_901} + {1'h0, _pop_count_packed_deps_T_903}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_905 = _pop_count_packed_deps_T_904; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_906 = {1'h0, _pop_count_packed_deps_T_899} + {1'h0, _pop_count_packed_deps_T_905}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_907 = _pop_count_packed_deps_T_906; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_908 = {1'h0, entries_ex_8_bits_deps_ex_8} + {1'h0, entries_ex_8_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_909 = _pop_count_packed_deps_T_908; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_910 = {1'h0, entries_ex_8_bits_deps_ex_10} + {1'h0, entries_ex_8_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_911 = _pop_count_packed_deps_T_910; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_912 = {1'h0, _pop_count_packed_deps_T_909} + {1'h0, _pop_count_packed_deps_T_911}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_913 = _pop_count_packed_deps_T_912; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_914 = {1'h0, entries_ex_8_bits_deps_ex_12} + {1'h0, entries_ex_8_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_915 = _pop_count_packed_deps_T_914; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_916 = {1'h0, entries_ex_8_bits_deps_ex_14} + {1'h0, entries_ex_8_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_917 = _pop_count_packed_deps_T_916; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_918 = {1'h0, _pop_count_packed_deps_T_915} + {1'h0, _pop_count_packed_deps_T_917}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_919 = _pop_count_packed_deps_T_918; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_920 = {1'h0, _pop_count_packed_deps_T_913} + {1'h0, _pop_count_packed_deps_T_919}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_921 = _pop_count_packed_deps_T_920; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_922 = {1'h0, _pop_count_packed_deps_T_907} + {1'h0, _pop_count_packed_deps_T_921}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_923 = _pop_count_packed_deps_T_922; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_924 = {2'h0, _pop_count_packed_deps_T_893} + {1'h0, _pop_count_packed_deps_T_923}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_925 = _pop_count_packed_deps_T_924[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_926 = {1'h0, entries_ex_8_bits_deps_st_0} + {1'h0, entries_ex_8_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_927 = _pop_count_packed_deps_T_926; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_928 = {1'h0, entries_ex_8_bits_deps_st_2} + {1'h0, entries_ex_8_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_929 = _pop_count_packed_deps_T_928; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_930 = {1'h0, _pop_count_packed_deps_T_927} + {1'h0, _pop_count_packed_deps_T_929}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_931 = _pop_count_packed_deps_T_930; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_932 = {1'h0, _pop_count_packed_deps_T_925} + {3'h0, _pop_count_packed_deps_T_931}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_933 = _pop_count_packed_deps_T_932[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_934 = entries_ex_8_valid ? _pop_count_packed_deps_T_933 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_16 = _pop_count_packed_deps_T_934; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_935 = {1'h0, entries_ex_9_bits_deps_ld_0} + {1'h0, entries_ex_9_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_936 = _pop_count_packed_deps_T_935; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_937 = {1'h0, entries_ex_9_bits_deps_ld_2} + {1'h0, entries_ex_9_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_938 = _pop_count_packed_deps_T_937; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_939 = {1'h0, _pop_count_packed_deps_T_936} + {1'h0, _pop_count_packed_deps_T_938}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_940 = _pop_count_packed_deps_T_939; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_941 = {1'h0, entries_ex_9_bits_deps_ld_4} + {1'h0, entries_ex_9_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_942 = _pop_count_packed_deps_T_941; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_943 = {1'h0, entries_ex_9_bits_deps_ld_6} + {1'h0, entries_ex_9_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_944 = _pop_count_packed_deps_T_943; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_945 = {1'h0, _pop_count_packed_deps_T_942} + {1'h0, _pop_count_packed_deps_T_944}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_946 = _pop_count_packed_deps_T_945; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_947 = {1'h0, _pop_count_packed_deps_T_940} + {1'h0, _pop_count_packed_deps_T_946}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_948 = _pop_count_packed_deps_T_947; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_949 = {1'h0, entries_ex_9_bits_deps_ex_0} + {1'h0, entries_ex_9_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_950 = _pop_count_packed_deps_T_949; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_951 = {1'h0, entries_ex_9_bits_deps_ex_2} + {1'h0, entries_ex_9_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_952 = _pop_count_packed_deps_T_951; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_953 = {1'h0, _pop_count_packed_deps_T_950} + {1'h0, _pop_count_packed_deps_T_952}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_954 = _pop_count_packed_deps_T_953; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_955 = {1'h0, entries_ex_9_bits_deps_ex_4} + {1'h0, entries_ex_9_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_956 = _pop_count_packed_deps_T_955; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_957 = {1'h0, entries_ex_9_bits_deps_ex_6} + {1'h0, entries_ex_9_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_958 = _pop_count_packed_deps_T_957; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_959 = {1'h0, _pop_count_packed_deps_T_956} + {1'h0, _pop_count_packed_deps_T_958}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_960 = _pop_count_packed_deps_T_959; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_961 = {1'h0, _pop_count_packed_deps_T_954} + {1'h0, _pop_count_packed_deps_T_960}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_962 = _pop_count_packed_deps_T_961; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_963 = {1'h0, entries_ex_9_bits_deps_ex_8} + {1'h0, entries_ex_9_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_964 = _pop_count_packed_deps_T_963; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_965 = {1'h0, entries_ex_9_bits_deps_ex_10} + {1'h0, entries_ex_9_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_966 = _pop_count_packed_deps_T_965; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_967 = {1'h0, _pop_count_packed_deps_T_964} + {1'h0, _pop_count_packed_deps_T_966}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_968 = _pop_count_packed_deps_T_967; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_969 = {1'h0, entries_ex_9_bits_deps_ex_12} + {1'h0, entries_ex_9_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_970 = _pop_count_packed_deps_T_969; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_971 = {1'h0, entries_ex_9_bits_deps_ex_14} + {1'h0, entries_ex_9_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_972 = _pop_count_packed_deps_T_971; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_973 = {1'h0, _pop_count_packed_deps_T_970} + {1'h0, _pop_count_packed_deps_T_972}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_974 = _pop_count_packed_deps_T_973; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_975 = {1'h0, _pop_count_packed_deps_T_968} + {1'h0, _pop_count_packed_deps_T_974}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_976 = _pop_count_packed_deps_T_975; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_977 = {1'h0, _pop_count_packed_deps_T_962} + {1'h0, _pop_count_packed_deps_T_976}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_978 = _pop_count_packed_deps_T_977; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_979 = {2'h0, _pop_count_packed_deps_T_948} + {1'h0, _pop_count_packed_deps_T_978}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_980 = _pop_count_packed_deps_T_979[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_981 = {1'h0, entries_ex_9_bits_deps_st_0} + {1'h0, entries_ex_9_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_982 = _pop_count_packed_deps_T_981; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_983 = {1'h0, entries_ex_9_bits_deps_st_2} + {1'h0, entries_ex_9_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_984 = _pop_count_packed_deps_T_983; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_985 = {1'h0, _pop_count_packed_deps_T_982} + {1'h0, _pop_count_packed_deps_T_984}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_986 = _pop_count_packed_deps_T_985; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_987 = {1'h0, _pop_count_packed_deps_T_980} + {3'h0, _pop_count_packed_deps_T_986}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_988 = _pop_count_packed_deps_T_987[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_989 = entries_ex_9_valid ? _pop_count_packed_deps_T_988 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_17 = _pop_count_packed_deps_T_989; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_990 = {1'h0, entries_ex_10_bits_deps_ld_0} + {1'h0, entries_ex_10_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_991 = _pop_count_packed_deps_T_990; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_992 = {1'h0, entries_ex_10_bits_deps_ld_2} + {1'h0, entries_ex_10_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_993 = _pop_count_packed_deps_T_992; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_994 = {1'h0, _pop_count_packed_deps_T_991} + {1'h0, _pop_count_packed_deps_T_993}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_995 = _pop_count_packed_deps_T_994; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_996 = {1'h0, entries_ex_10_bits_deps_ld_4} + {1'h0, entries_ex_10_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_997 = _pop_count_packed_deps_T_996; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_998 = {1'h0, entries_ex_10_bits_deps_ld_6} + {1'h0, entries_ex_10_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_999 = _pop_count_packed_deps_T_998; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1000 = {1'h0, _pop_count_packed_deps_T_997} + {1'h0, _pop_count_packed_deps_T_999}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1001 = _pop_count_packed_deps_T_1000; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1002 = {1'h0, _pop_count_packed_deps_T_995} + {1'h0, _pop_count_packed_deps_T_1001}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1003 = _pop_count_packed_deps_T_1002; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1004 = {1'h0, entries_ex_10_bits_deps_ex_0} + {1'h0, entries_ex_10_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1005 = _pop_count_packed_deps_T_1004; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1006 = {1'h0, entries_ex_10_bits_deps_ex_2} + {1'h0, entries_ex_10_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1007 = _pop_count_packed_deps_T_1006; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1008 = {1'h0, _pop_count_packed_deps_T_1005} + {1'h0, _pop_count_packed_deps_T_1007}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1009 = _pop_count_packed_deps_T_1008; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1010 = {1'h0, entries_ex_10_bits_deps_ex_4} + {1'h0, entries_ex_10_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1011 = _pop_count_packed_deps_T_1010; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1012 = {1'h0, entries_ex_10_bits_deps_ex_6} + {1'h0, entries_ex_10_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1013 = _pop_count_packed_deps_T_1012; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1014 = {1'h0, _pop_count_packed_deps_T_1011} + {1'h0, _pop_count_packed_deps_T_1013}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1015 = _pop_count_packed_deps_T_1014; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1016 = {1'h0, _pop_count_packed_deps_T_1009} + {1'h0, _pop_count_packed_deps_T_1015}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1017 = _pop_count_packed_deps_T_1016; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1018 = {1'h0, entries_ex_10_bits_deps_ex_8} + {1'h0, entries_ex_10_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1019 = _pop_count_packed_deps_T_1018; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1020 = {1'h0, entries_ex_10_bits_deps_ex_10} + {1'h0, entries_ex_10_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1021 = _pop_count_packed_deps_T_1020; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1022 = {1'h0, _pop_count_packed_deps_T_1019} + {1'h0, _pop_count_packed_deps_T_1021}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1023 = _pop_count_packed_deps_T_1022; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1024 = {1'h0, entries_ex_10_bits_deps_ex_12} + {1'h0, entries_ex_10_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1025 = _pop_count_packed_deps_T_1024; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1026 = {1'h0, entries_ex_10_bits_deps_ex_14} + {1'h0, entries_ex_10_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1027 = _pop_count_packed_deps_T_1026; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1028 = {1'h0, _pop_count_packed_deps_T_1025} + {1'h0, _pop_count_packed_deps_T_1027}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1029 = _pop_count_packed_deps_T_1028; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1030 = {1'h0, _pop_count_packed_deps_T_1023} + {1'h0, _pop_count_packed_deps_T_1029}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1031 = _pop_count_packed_deps_T_1030; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1032 = {1'h0, _pop_count_packed_deps_T_1017} + {1'h0, _pop_count_packed_deps_T_1031}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1033 = _pop_count_packed_deps_T_1032; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1034 = {2'h0, _pop_count_packed_deps_T_1003} + {1'h0, _pop_count_packed_deps_T_1033}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1035 = _pop_count_packed_deps_T_1034[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1036 = {1'h0, entries_ex_10_bits_deps_st_0} + {1'h0, entries_ex_10_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1037 = _pop_count_packed_deps_T_1036; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1038 = {1'h0, entries_ex_10_bits_deps_st_2} + {1'h0, entries_ex_10_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1039 = _pop_count_packed_deps_T_1038; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1040 = {1'h0, _pop_count_packed_deps_T_1037} + {1'h0, _pop_count_packed_deps_T_1039}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1041 = _pop_count_packed_deps_T_1040; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1042 = {1'h0, _pop_count_packed_deps_T_1035} + {3'h0, _pop_count_packed_deps_T_1041}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1043 = _pop_count_packed_deps_T_1042[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1044 = entries_ex_10_valid ? _pop_count_packed_deps_T_1043 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_18 = _pop_count_packed_deps_T_1044; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1045 = {1'h0, entries_ex_11_bits_deps_ld_0} + {1'h0, entries_ex_11_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1046 = _pop_count_packed_deps_T_1045; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1047 = {1'h0, entries_ex_11_bits_deps_ld_2} + {1'h0, entries_ex_11_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1048 = _pop_count_packed_deps_T_1047; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1049 = {1'h0, _pop_count_packed_deps_T_1046} + {1'h0, _pop_count_packed_deps_T_1048}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1050 = _pop_count_packed_deps_T_1049; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1051 = {1'h0, entries_ex_11_bits_deps_ld_4} + {1'h0, entries_ex_11_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1052 = _pop_count_packed_deps_T_1051; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1053 = {1'h0, entries_ex_11_bits_deps_ld_6} + {1'h0, entries_ex_11_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1054 = _pop_count_packed_deps_T_1053; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1055 = {1'h0, _pop_count_packed_deps_T_1052} + {1'h0, _pop_count_packed_deps_T_1054}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1056 = _pop_count_packed_deps_T_1055; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1057 = {1'h0, _pop_count_packed_deps_T_1050} + {1'h0, _pop_count_packed_deps_T_1056}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1058 = _pop_count_packed_deps_T_1057; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1059 = {1'h0, entries_ex_11_bits_deps_ex_0} + {1'h0, entries_ex_11_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1060 = _pop_count_packed_deps_T_1059; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1061 = {1'h0, entries_ex_11_bits_deps_ex_2} + {1'h0, entries_ex_11_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1062 = _pop_count_packed_deps_T_1061; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1063 = {1'h0, _pop_count_packed_deps_T_1060} + {1'h0, _pop_count_packed_deps_T_1062}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1064 = _pop_count_packed_deps_T_1063; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1065 = {1'h0, entries_ex_11_bits_deps_ex_4} + {1'h0, entries_ex_11_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1066 = _pop_count_packed_deps_T_1065; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1067 = {1'h0, entries_ex_11_bits_deps_ex_6} + {1'h0, entries_ex_11_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1068 = _pop_count_packed_deps_T_1067; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1069 = {1'h0, _pop_count_packed_deps_T_1066} + {1'h0, _pop_count_packed_deps_T_1068}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1070 = _pop_count_packed_deps_T_1069; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1071 = {1'h0, _pop_count_packed_deps_T_1064} + {1'h0, _pop_count_packed_deps_T_1070}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1072 = _pop_count_packed_deps_T_1071; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1073 = {1'h0, entries_ex_11_bits_deps_ex_8} + {1'h0, entries_ex_11_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1074 = _pop_count_packed_deps_T_1073; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1075 = {1'h0, entries_ex_11_bits_deps_ex_10} + {1'h0, entries_ex_11_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1076 = _pop_count_packed_deps_T_1075; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1077 = {1'h0, _pop_count_packed_deps_T_1074} + {1'h0, _pop_count_packed_deps_T_1076}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1078 = _pop_count_packed_deps_T_1077; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1079 = {1'h0, entries_ex_11_bits_deps_ex_12} + {1'h0, entries_ex_11_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1080 = _pop_count_packed_deps_T_1079; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1081 = {1'h0, entries_ex_11_bits_deps_ex_14} + {1'h0, entries_ex_11_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1082 = _pop_count_packed_deps_T_1081; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1083 = {1'h0, _pop_count_packed_deps_T_1080} + {1'h0, _pop_count_packed_deps_T_1082}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1084 = _pop_count_packed_deps_T_1083; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1085 = {1'h0, _pop_count_packed_deps_T_1078} + {1'h0, _pop_count_packed_deps_T_1084}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1086 = _pop_count_packed_deps_T_1085; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1087 = {1'h0, _pop_count_packed_deps_T_1072} + {1'h0, _pop_count_packed_deps_T_1086}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1088 = _pop_count_packed_deps_T_1087; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1089 = {2'h0, _pop_count_packed_deps_T_1058} + {1'h0, _pop_count_packed_deps_T_1088}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1090 = _pop_count_packed_deps_T_1089[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1091 = {1'h0, entries_ex_11_bits_deps_st_0} + {1'h0, entries_ex_11_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1092 = _pop_count_packed_deps_T_1091; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1093 = {1'h0, entries_ex_11_bits_deps_st_2} + {1'h0, entries_ex_11_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1094 = _pop_count_packed_deps_T_1093; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1095 = {1'h0, _pop_count_packed_deps_T_1092} + {1'h0, _pop_count_packed_deps_T_1094}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1096 = _pop_count_packed_deps_T_1095; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1097 = {1'h0, _pop_count_packed_deps_T_1090} + {3'h0, _pop_count_packed_deps_T_1096}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1098 = _pop_count_packed_deps_T_1097[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1099 = entries_ex_11_valid ? _pop_count_packed_deps_T_1098 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_19 = _pop_count_packed_deps_T_1099; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1100 = {1'h0, entries_ex_12_bits_deps_ld_0} + {1'h0, entries_ex_12_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1101 = _pop_count_packed_deps_T_1100; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1102 = {1'h0, entries_ex_12_bits_deps_ld_2} + {1'h0, entries_ex_12_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1103 = _pop_count_packed_deps_T_1102; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1104 = {1'h0, _pop_count_packed_deps_T_1101} + {1'h0, _pop_count_packed_deps_T_1103}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1105 = _pop_count_packed_deps_T_1104; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1106 = {1'h0, entries_ex_12_bits_deps_ld_4} + {1'h0, entries_ex_12_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1107 = _pop_count_packed_deps_T_1106; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1108 = {1'h0, entries_ex_12_bits_deps_ld_6} + {1'h0, entries_ex_12_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1109 = _pop_count_packed_deps_T_1108; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1110 = {1'h0, _pop_count_packed_deps_T_1107} + {1'h0, _pop_count_packed_deps_T_1109}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1111 = _pop_count_packed_deps_T_1110; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1112 = {1'h0, _pop_count_packed_deps_T_1105} + {1'h0, _pop_count_packed_deps_T_1111}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1113 = _pop_count_packed_deps_T_1112; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1114 = {1'h0, entries_ex_12_bits_deps_ex_0} + {1'h0, entries_ex_12_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1115 = _pop_count_packed_deps_T_1114; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1116 = {1'h0, entries_ex_12_bits_deps_ex_2} + {1'h0, entries_ex_12_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1117 = _pop_count_packed_deps_T_1116; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1118 = {1'h0, _pop_count_packed_deps_T_1115} + {1'h0, _pop_count_packed_deps_T_1117}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1119 = _pop_count_packed_deps_T_1118; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1120 = {1'h0, entries_ex_12_bits_deps_ex_4} + {1'h0, entries_ex_12_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1121 = _pop_count_packed_deps_T_1120; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1122 = {1'h0, entries_ex_12_bits_deps_ex_6} + {1'h0, entries_ex_12_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1123 = _pop_count_packed_deps_T_1122; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1124 = {1'h0, _pop_count_packed_deps_T_1121} + {1'h0, _pop_count_packed_deps_T_1123}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1125 = _pop_count_packed_deps_T_1124; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1126 = {1'h0, _pop_count_packed_deps_T_1119} + {1'h0, _pop_count_packed_deps_T_1125}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1127 = _pop_count_packed_deps_T_1126; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1128 = {1'h0, entries_ex_12_bits_deps_ex_8} + {1'h0, entries_ex_12_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1129 = _pop_count_packed_deps_T_1128; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1130 = {1'h0, entries_ex_12_bits_deps_ex_10} + {1'h0, entries_ex_12_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1131 = _pop_count_packed_deps_T_1130; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1132 = {1'h0, _pop_count_packed_deps_T_1129} + {1'h0, _pop_count_packed_deps_T_1131}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1133 = _pop_count_packed_deps_T_1132; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1134 = {1'h0, entries_ex_12_bits_deps_ex_12} + {1'h0, entries_ex_12_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1135 = _pop_count_packed_deps_T_1134; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1136 = {1'h0, entries_ex_12_bits_deps_ex_14} + {1'h0, entries_ex_12_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1137 = _pop_count_packed_deps_T_1136; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1138 = {1'h0, _pop_count_packed_deps_T_1135} + {1'h0, _pop_count_packed_deps_T_1137}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1139 = _pop_count_packed_deps_T_1138; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1140 = {1'h0, _pop_count_packed_deps_T_1133} + {1'h0, _pop_count_packed_deps_T_1139}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1141 = _pop_count_packed_deps_T_1140; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1142 = {1'h0, _pop_count_packed_deps_T_1127} + {1'h0, _pop_count_packed_deps_T_1141}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1143 = _pop_count_packed_deps_T_1142; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1144 = {2'h0, _pop_count_packed_deps_T_1113} + {1'h0, _pop_count_packed_deps_T_1143}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1145 = _pop_count_packed_deps_T_1144[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1146 = {1'h0, entries_ex_12_bits_deps_st_0} + {1'h0, entries_ex_12_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1147 = _pop_count_packed_deps_T_1146; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1148 = {1'h0, entries_ex_12_bits_deps_st_2} + {1'h0, entries_ex_12_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1149 = _pop_count_packed_deps_T_1148; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1150 = {1'h0, _pop_count_packed_deps_T_1147} + {1'h0, _pop_count_packed_deps_T_1149}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1151 = _pop_count_packed_deps_T_1150; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1152 = {1'h0, _pop_count_packed_deps_T_1145} + {3'h0, _pop_count_packed_deps_T_1151}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1153 = _pop_count_packed_deps_T_1152[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1154 = entries_ex_12_valid ? _pop_count_packed_deps_T_1153 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_20 = _pop_count_packed_deps_T_1154; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1155 = {1'h0, entries_ex_13_bits_deps_ld_0} + {1'h0, entries_ex_13_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1156 = _pop_count_packed_deps_T_1155; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1157 = {1'h0, entries_ex_13_bits_deps_ld_2} + {1'h0, entries_ex_13_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1158 = _pop_count_packed_deps_T_1157; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1159 = {1'h0, _pop_count_packed_deps_T_1156} + {1'h0, _pop_count_packed_deps_T_1158}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1160 = _pop_count_packed_deps_T_1159; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1161 = {1'h0, entries_ex_13_bits_deps_ld_4} + {1'h0, entries_ex_13_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1162 = _pop_count_packed_deps_T_1161; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1163 = {1'h0, entries_ex_13_bits_deps_ld_6} + {1'h0, entries_ex_13_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1164 = _pop_count_packed_deps_T_1163; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1165 = {1'h0, _pop_count_packed_deps_T_1162} + {1'h0, _pop_count_packed_deps_T_1164}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1166 = _pop_count_packed_deps_T_1165; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1167 = {1'h0, _pop_count_packed_deps_T_1160} + {1'h0, _pop_count_packed_deps_T_1166}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1168 = _pop_count_packed_deps_T_1167; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1169 = {1'h0, entries_ex_13_bits_deps_ex_0} + {1'h0, entries_ex_13_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1170 = _pop_count_packed_deps_T_1169; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1171 = {1'h0, entries_ex_13_bits_deps_ex_2} + {1'h0, entries_ex_13_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1172 = _pop_count_packed_deps_T_1171; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1173 = {1'h0, _pop_count_packed_deps_T_1170} + {1'h0, _pop_count_packed_deps_T_1172}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1174 = _pop_count_packed_deps_T_1173; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1175 = {1'h0, entries_ex_13_bits_deps_ex_4} + {1'h0, entries_ex_13_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1176 = _pop_count_packed_deps_T_1175; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1177 = {1'h0, entries_ex_13_bits_deps_ex_6} + {1'h0, entries_ex_13_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1178 = _pop_count_packed_deps_T_1177; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1179 = {1'h0, _pop_count_packed_deps_T_1176} + {1'h0, _pop_count_packed_deps_T_1178}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1180 = _pop_count_packed_deps_T_1179; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1181 = {1'h0, _pop_count_packed_deps_T_1174} + {1'h0, _pop_count_packed_deps_T_1180}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1182 = _pop_count_packed_deps_T_1181; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1183 = {1'h0, entries_ex_13_bits_deps_ex_8} + {1'h0, entries_ex_13_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1184 = _pop_count_packed_deps_T_1183; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1185 = {1'h0, entries_ex_13_bits_deps_ex_10} + {1'h0, entries_ex_13_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1186 = _pop_count_packed_deps_T_1185; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1187 = {1'h0, _pop_count_packed_deps_T_1184} + {1'h0, _pop_count_packed_deps_T_1186}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1188 = _pop_count_packed_deps_T_1187; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1189 = {1'h0, entries_ex_13_bits_deps_ex_12} + {1'h0, entries_ex_13_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1190 = _pop_count_packed_deps_T_1189; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1191 = {1'h0, entries_ex_13_bits_deps_ex_14} + {1'h0, entries_ex_13_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1192 = _pop_count_packed_deps_T_1191; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1193 = {1'h0, _pop_count_packed_deps_T_1190} + {1'h0, _pop_count_packed_deps_T_1192}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1194 = _pop_count_packed_deps_T_1193; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1195 = {1'h0, _pop_count_packed_deps_T_1188} + {1'h0, _pop_count_packed_deps_T_1194}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1196 = _pop_count_packed_deps_T_1195; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1197 = {1'h0, _pop_count_packed_deps_T_1182} + {1'h0, _pop_count_packed_deps_T_1196}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1198 = _pop_count_packed_deps_T_1197; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1199 = {2'h0, _pop_count_packed_deps_T_1168} + {1'h0, _pop_count_packed_deps_T_1198}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1200 = _pop_count_packed_deps_T_1199[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1201 = {1'h0, entries_ex_13_bits_deps_st_0} + {1'h0, entries_ex_13_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1202 = _pop_count_packed_deps_T_1201; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1203 = {1'h0, entries_ex_13_bits_deps_st_2} + {1'h0, entries_ex_13_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1204 = _pop_count_packed_deps_T_1203; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1205 = {1'h0, _pop_count_packed_deps_T_1202} + {1'h0, _pop_count_packed_deps_T_1204}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1206 = _pop_count_packed_deps_T_1205; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1207 = {1'h0, _pop_count_packed_deps_T_1200} + {3'h0, _pop_count_packed_deps_T_1206}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1208 = _pop_count_packed_deps_T_1207[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1209 = entries_ex_13_valid ? _pop_count_packed_deps_T_1208 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_21 = _pop_count_packed_deps_T_1209; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1210 = {1'h0, entries_ex_14_bits_deps_ld_0} + {1'h0, entries_ex_14_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1211 = _pop_count_packed_deps_T_1210; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1212 = {1'h0, entries_ex_14_bits_deps_ld_2} + {1'h0, entries_ex_14_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1213 = _pop_count_packed_deps_T_1212; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1214 = {1'h0, _pop_count_packed_deps_T_1211} + {1'h0, _pop_count_packed_deps_T_1213}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1215 = _pop_count_packed_deps_T_1214; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1216 = {1'h0, entries_ex_14_bits_deps_ld_4} + {1'h0, entries_ex_14_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1217 = _pop_count_packed_deps_T_1216; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1218 = {1'h0, entries_ex_14_bits_deps_ld_6} + {1'h0, entries_ex_14_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1219 = _pop_count_packed_deps_T_1218; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1220 = {1'h0, _pop_count_packed_deps_T_1217} + {1'h0, _pop_count_packed_deps_T_1219}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1221 = _pop_count_packed_deps_T_1220; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1222 = {1'h0, _pop_count_packed_deps_T_1215} + {1'h0, _pop_count_packed_deps_T_1221}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1223 = _pop_count_packed_deps_T_1222; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1224 = {1'h0, entries_ex_14_bits_deps_ex_0} + {1'h0, entries_ex_14_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1225 = _pop_count_packed_deps_T_1224; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1226 = {1'h0, entries_ex_14_bits_deps_ex_2} + {1'h0, entries_ex_14_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1227 = _pop_count_packed_deps_T_1226; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1228 = {1'h0, _pop_count_packed_deps_T_1225} + {1'h0, _pop_count_packed_deps_T_1227}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1229 = _pop_count_packed_deps_T_1228; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1230 = {1'h0, entries_ex_14_bits_deps_ex_4} + {1'h0, entries_ex_14_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1231 = _pop_count_packed_deps_T_1230; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1232 = {1'h0, entries_ex_14_bits_deps_ex_6} + {1'h0, entries_ex_14_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1233 = _pop_count_packed_deps_T_1232; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1234 = {1'h0, _pop_count_packed_deps_T_1231} + {1'h0, _pop_count_packed_deps_T_1233}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1235 = _pop_count_packed_deps_T_1234; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1236 = {1'h0, _pop_count_packed_deps_T_1229} + {1'h0, _pop_count_packed_deps_T_1235}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1237 = _pop_count_packed_deps_T_1236; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1238 = {1'h0, entries_ex_14_bits_deps_ex_8} + {1'h0, entries_ex_14_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1239 = _pop_count_packed_deps_T_1238; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1240 = {1'h0, entries_ex_14_bits_deps_ex_10} + {1'h0, entries_ex_14_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1241 = _pop_count_packed_deps_T_1240; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1242 = {1'h0, _pop_count_packed_deps_T_1239} + {1'h0, _pop_count_packed_deps_T_1241}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1243 = _pop_count_packed_deps_T_1242; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1244 = {1'h0, entries_ex_14_bits_deps_ex_12} + {1'h0, entries_ex_14_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1245 = _pop_count_packed_deps_T_1244; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1246 = {1'h0, entries_ex_14_bits_deps_ex_14} + {1'h0, entries_ex_14_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1247 = _pop_count_packed_deps_T_1246; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1248 = {1'h0, _pop_count_packed_deps_T_1245} + {1'h0, _pop_count_packed_deps_T_1247}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1249 = _pop_count_packed_deps_T_1248; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1250 = {1'h0, _pop_count_packed_deps_T_1243} + {1'h0, _pop_count_packed_deps_T_1249}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1251 = _pop_count_packed_deps_T_1250; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1252 = {1'h0, _pop_count_packed_deps_T_1237} + {1'h0, _pop_count_packed_deps_T_1251}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1253 = _pop_count_packed_deps_T_1252; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1254 = {2'h0, _pop_count_packed_deps_T_1223} + {1'h0, _pop_count_packed_deps_T_1253}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1255 = _pop_count_packed_deps_T_1254[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1256 = {1'h0, entries_ex_14_bits_deps_st_0} + {1'h0, entries_ex_14_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1257 = _pop_count_packed_deps_T_1256; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1258 = {1'h0, entries_ex_14_bits_deps_st_2} + {1'h0, entries_ex_14_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1259 = _pop_count_packed_deps_T_1258; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1260 = {1'h0, _pop_count_packed_deps_T_1257} + {1'h0, _pop_count_packed_deps_T_1259}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1261 = _pop_count_packed_deps_T_1260; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1262 = {1'h0, _pop_count_packed_deps_T_1255} + {3'h0, _pop_count_packed_deps_T_1261}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1263 = _pop_count_packed_deps_T_1262[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1264 = entries_ex_14_valid ? _pop_count_packed_deps_T_1263 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_22 = _pop_count_packed_deps_T_1264; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1265 = {1'h0, entries_ex_15_bits_deps_ld_0} + {1'h0, entries_ex_15_bits_deps_ld_1}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1266 = _pop_count_packed_deps_T_1265; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1267 = {1'h0, entries_ex_15_bits_deps_ld_2} + {1'h0, entries_ex_15_bits_deps_ld_3}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1268 = _pop_count_packed_deps_T_1267; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1269 = {1'h0, _pop_count_packed_deps_T_1266} + {1'h0, _pop_count_packed_deps_T_1268}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1270 = _pop_count_packed_deps_T_1269; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1271 = {1'h0, entries_ex_15_bits_deps_ld_4} + {1'h0, entries_ex_15_bits_deps_ld_5}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1272 = _pop_count_packed_deps_T_1271; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1273 = {1'h0, entries_ex_15_bits_deps_ld_6} + {1'h0, entries_ex_15_bits_deps_ld_7}; // @[ReservationStation.scala:118:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1274 = _pop_count_packed_deps_T_1273; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1275 = {1'h0, _pop_count_packed_deps_T_1272} + {1'h0, _pop_count_packed_deps_T_1274}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1276 = _pop_count_packed_deps_T_1275; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1277 = {1'h0, _pop_count_packed_deps_T_1270} + {1'h0, _pop_count_packed_deps_T_1276}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1278 = _pop_count_packed_deps_T_1277; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1279 = {1'h0, entries_ex_15_bits_deps_ex_0} + {1'h0, entries_ex_15_bits_deps_ex_1}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1280 = _pop_count_packed_deps_T_1279; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1281 = {1'h0, entries_ex_15_bits_deps_ex_2} + {1'h0, entries_ex_15_bits_deps_ex_3}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1282 = _pop_count_packed_deps_T_1281; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1283 = {1'h0, _pop_count_packed_deps_T_1280} + {1'h0, _pop_count_packed_deps_T_1282}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1284 = _pop_count_packed_deps_T_1283; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1285 = {1'h0, entries_ex_15_bits_deps_ex_4} + {1'h0, entries_ex_15_bits_deps_ex_5}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1286 = _pop_count_packed_deps_T_1285; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1287 = {1'h0, entries_ex_15_bits_deps_ex_6} + {1'h0, entries_ex_15_bits_deps_ex_7}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1288 = _pop_count_packed_deps_T_1287; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1289 = {1'h0, _pop_count_packed_deps_T_1286} + {1'h0, _pop_count_packed_deps_T_1288}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1290 = _pop_count_packed_deps_T_1289; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1291 = {1'h0, _pop_count_packed_deps_T_1284} + {1'h0, _pop_count_packed_deps_T_1290}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1292 = _pop_count_packed_deps_T_1291; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1293 = {1'h0, entries_ex_15_bits_deps_ex_8} + {1'h0, entries_ex_15_bits_deps_ex_9}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1294 = _pop_count_packed_deps_T_1293; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1295 = {1'h0, entries_ex_15_bits_deps_ex_10} + {1'h0, entries_ex_15_bits_deps_ex_11}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1296 = _pop_count_packed_deps_T_1295; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1297 = {1'h0, _pop_count_packed_deps_T_1294} + {1'h0, _pop_count_packed_deps_T_1296}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1298 = _pop_count_packed_deps_T_1297; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1299 = {1'h0, entries_ex_15_bits_deps_ex_12} + {1'h0, entries_ex_15_bits_deps_ex_13}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1300 = _pop_count_packed_deps_T_1299; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1301 = {1'h0, entries_ex_15_bits_deps_ex_14} + {1'h0, entries_ex_15_bits_deps_ex_15}; // @[ReservationStation.scala:118:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1302 = _pop_count_packed_deps_T_1301; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1303 = {1'h0, _pop_count_packed_deps_T_1300} + {1'h0, _pop_count_packed_deps_T_1302}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1304 = _pop_count_packed_deps_T_1303; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1305 = {1'h0, _pop_count_packed_deps_T_1298} + {1'h0, _pop_count_packed_deps_T_1304}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1306 = _pop_count_packed_deps_T_1305; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1307 = {1'h0, _pop_count_packed_deps_T_1292} + {1'h0, _pop_count_packed_deps_T_1306}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1308 = _pop_count_packed_deps_T_1307; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1309 = {2'h0, _pop_count_packed_deps_T_1278} + {1'h0, _pop_count_packed_deps_T_1308}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1310 = _pop_count_packed_deps_T_1309[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1311 = {1'h0, entries_ex_15_bits_deps_st_0} + {1'h0, entries_ex_15_bits_deps_st_1}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1312 = _pop_count_packed_deps_T_1311; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1313 = {1'h0, entries_ex_15_bits_deps_st_2} + {1'h0, entries_ex_15_bits_deps_st_3}; // @[ReservationStation.scala:118:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1314 = _pop_count_packed_deps_T_1313; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1315 = {1'h0, _pop_count_packed_deps_T_1312} + {1'h0, _pop_count_packed_deps_T_1314}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1316 = _pop_count_packed_deps_T_1315; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1317 = {1'h0, _pop_count_packed_deps_T_1310} + {3'h0, _pop_count_packed_deps_T_1316}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1318 = _pop_count_packed_deps_T_1317[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1319 = entries_ex_15_valid ? _pop_count_packed_deps_T_1318 : 5'h0; // @[ReservationStation.scala:118:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_23 = _pop_count_packed_deps_T_1319; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1320 = {1'h0, entries_st_0_bits_deps_ld_0} + {1'h0, entries_st_0_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1321 = _pop_count_packed_deps_T_1320; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1322 = {1'h0, entries_st_0_bits_deps_ld_2} + {1'h0, entries_st_0_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1323 = _pop_count_packed_deps_T_1322; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1324 = {1'h0, _pop_count_packed_deps_T_1321} + {1'h0, _pop_count_packed_deps_T_1323}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1325 = _pop_count_packed_deps_T_1324; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1326 = {1'h0, entries_st_0_bits_deps_ld_4} + {1'h0, entries_st_0_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1327 = _pop_count_packed_deps_T_1326; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1328 = {1'h0, entries_st_0_bits_deps_ld_6} + {1'h0, entries_st_0_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1329 = _pop_count_packed_deps_T_1328; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1330 = {1'h0, _pop_count_packed_deps_T_1327} + {1'h0, _pop_count_packed_deps_T_1329}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1331 = _pop_count_packed_deps_T_1330; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1332 = {1'h0, _pop_count_packed_deps_T_1325} + {1'h0, _pop_count_packed_deps_T_1331}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1333 = _pop_count_packed_deps_T_1332; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1334 = {1'h0, entries_st_0_bits_deps_ex_0} + {1'h0, entries_st_0_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1335 = _pop_count_packed_deps_T_1334; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1336 = {1'h0, entries_st_0_bits_deps_ex_2} + {1'h0, entries_st_0_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1337 = _pop_count_packed_deps_T_1336; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1338 = {1'h0, _pop_count_packed_deps_T_1335} + {1'h0, _pop_count_packed_deps_T_1337}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1339 = _pop_count_packed_deps_T_1338; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1340 = {1'h0, entries_st_0_bits_deps_ex_4} + {1'h0, entries_st_0_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1341 = _pop_count_packed_deps_T_1340; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1342 = {1'h0, entries_st_0_bits_deps_ex_6} + {1'h0, entries_st_0_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1343 = _pop_count_packed_deps_T_1342; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1344 = {1'h0, _pop_count_packed_deps_T_1341} + {1'h0, _pop_count_packed_deps_T_1343}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1345 = _pop_count_packed_deps_T_1344; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1346 = {1'h0, _pop_count_packed_deps_T_1339} + {1'h0, _pop_count_packed_deps_T_1345}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1347 = _pop_count_packed_deps_T_1346; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1348 = {1'h0, entries_st_0_bits_deps_ex_8} + {1'h0, entries_st_0_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1349 = _pop_count_packed_deps_T_1348; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1350 = {1'h0, entries_st_0_bits_deps_ex_10} + {1'h0, entries_st_0_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1351 = _pop_count_packed_deps_T_1350; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1352 = {1'h0, _pop_count_packed_deps_T_1349} + {1'h0, _pop_count_packed_deps_T_1351}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1353 = _pop_count_packed_deps_T_1352; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1354 = {1'h0, entries_st_0_bits_deps_ex_12} + {1'h0, entries_st_0_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1355 = _pop_count_packed_deps_T_1354; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1356 = {1'h0, entries_st_0_bits_deps_ex_14} + {1'h0, entries_st_0_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1357 = _pop_count_packed_deps_T_1356; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1358 = {1'h0, _pop_count_packed_deps_T_1355} + {1'h0, _pop_count_packed_deps_T_1357}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1359 = _pop_count_packed_deps_T_1358; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1360 = {1'h0, _pop_count_packed_deps_T_1353} + {1'h0, _pop_count_packed_deps_T_1359}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1361 = _pop_count_packed_deps_T_1360; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1362 = {1'h0, _pop_count_packed_deps_T_1347} + {1'h0, _pop_count_packed_deps_T_1361}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1363 = _pop_count_packed_deps_T_1362; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1364 = {2'h0, _pop_count_packed_deps_T_1333} + {1'h0, _pop_count_packed_deps_T_1363}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1365 = _pop_count_packed_deps_T_1364[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1366 = {1'h0, entries_st_0_bits_deps_st_0} + {1'h0, entries_st_0_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1367 = _pop_count_packed_deps_T_1366; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1368 = {1'h0, entries_st_0_bits_deps_st_2} + {1'h0, entries_st_0_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1369 = _pop_count_packed_deps_T_1368; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1370 = {1'h0, _pop_count_packed_deps_T_1367} + {1'h0, _pop_count_packed_deps_T_1369}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1371 = _pop_count_packed_deps_T_1370; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1372 = {1'h0, _pop_count_packed_deps_T_1365} + {3'h0, _pop_count_packed_deps_T_1371}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1373 = _pop_count_packed_deps_T_1372[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1374 = entries_st_0_valid ? _pop_count_packed_deps_T_1373 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_24 = _pop_count_packed_deps_T_1374; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1375 = {1'h0, entries_st_1_bits_deps_ld_0} + {1'h0, entries_st_1_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1376 = _pop_count_packed_deps_T_1375; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1377 = {1'h0, entries_st_1_bits_deps_ld_2} + {1'h0, entries_st_1_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1378 = _pop_count_packed_deps_T_1377; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1379 = {1'h0, _pop_count_packed_deps_T_1376} + {1'h0, _pop_count_packed_deps_T_1378}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1380 = _pop_count_packed_deps_T_1379; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1381 = {1'h0, entries_st_1_bits_deps_ld_4} + {1'h0, entries_st_1_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1382 = _pop_count_packed_deps_T_1381; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1383 = {1'h0, entries_st_1_bits_deps_ld_6} + {1'h0, entries_st_1_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1384 = _pop_count_packed_deps_T_1383; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1385 = {1'h0, _pop_count_packed_deps_T_1382} + {1'h0, _pop_count_packed_deps_T_1384}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1386 = _pop_count_packed_deps_T_1385; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1387 = {1'h0, _pop_count_packed_deps_T_1380} + {1'h0, _pop_count_packed_deps_T_1386}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1388 = _pop_count_packed_deps_T_1387; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1389 = {1'h0, entries_st_1_bits_deps_ex_0} + {1'h0, entries_st_1_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1390 = _pop_count_packed_deps_T_1389; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1391 = {1'h0, entries_st_1_bits_deps_ex_2} + {1'h0, entries_st_1_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1392 = _pop_count_packed_deps_T_1391; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1393 = {1'h0, _pop_count_packed_deps_T_1390} + {1'h0, _pop_count_packed_deps_T_1392}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1394 = _pop_count_packed_deps_T_1393; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1395 = {1'h0, entries_st_1_bits_deps_ex_4} + {1'h0, entries_st_1_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1396 = _pop_count_packed_deps_T_1395; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1397 = {1'h0, entries_st_1_bits_deps_ex_6} + {1'h0, entries_st_1_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1398 = _pop_count_packed_deps_T_1397; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1399 = {1'h0, _pop_count_packed_deps_T_1396} + {1'h0, _pop_count_packed_deps_T_1398}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1400 = _pop_count_packed_deps_T_1399; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1401 = {1'h0, _pop_count_packed_deps_T_1394} + {1'h0, _pop_count_packed_deps_T_1400}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1402 = _pop_count_packed_deps_T_1401; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1403 = {1'h0, entries_st_1_bits_deps_ex_8} + {1'h0, entries_st_1_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1404 = _pop_count_packed_deps_T_1403; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1405 = {1'h0, entries_st_1_bits_deps_ex_10} + {1'h0, entries_st_1_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1406 = _pop_count_packed_deps_T_1405; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1407 = {1'h0, _pop_count_packed_deps_T_1404} + {1'h0, _pop_count_packed_deps_T_1406}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1408 = _pop_count_packed_deps_T_1407; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1409 = {1'h0, entries_st_1_bits_deps_ex_12} + {1'h0, entries_st_1_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1410 = _pop_count_packed_deps_T_1409; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1411 = {1'h0, entries_st_1_bits_deps_ex_14} + {1'h0, entries_st_1_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1412 = _pop_count_packed_deps_T_1411; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1413 = {1'h0, _pop_count_packed_deps_T_1410} + {1'h0, _pop_count_packed_deps_T_1412}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1414 = _pop_count_packed_deps_T_1413; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1415 = {1'h0, _pop_count_packed_deps_T_1408} + {1'h0, _pop_count_packed_deps_T_1414}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1416 = _pop_count_packed_deps_T_1415; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1417 = {1'h0, _pop_count_packed_deps_T_1402} + {1'h0, _pop_count_packed_deps_T_1416}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1418 = _pop_count_packed_deps_T_1417; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1419 = {2'h0, _pop_count_packed_deps_T_1388} + {1'h0, _pop_count_packed_deps_T_1418}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1420 = _pop_count_packed_deps_T_1419[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1421 = {1'h0, entries_st_1_bits_deps_st_0} + {1'h0, entries_st_1_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1422 = _pop_count_packed_deps_T_1421; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1423 = {1'h0, entries_st_1_bits_deps_st_2} + {1'h0, entries_st_1_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1424 = _pop_count_packed_deps_T_1423; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1425 = {1'h0, _pop_count_packed_deps_T_1422} + {1'h0, _pop_count_packed_deps_T_1424}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1426 = _pop_count_packed_deps_T_1425; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1427 = {1'h0, _pop_count_packed_deps_T_1420} + {3'h0, _pop_count_packed_deps_T_1426}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1428 = _pop_count_packed_deps_T_1427[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1429 = entries_st_1_valid ? _pop_count_packed_deps_T_1428 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_25 = _pop_count_packed_deps_T_1429; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1430 = {1'h0, entries_st_2_bits_deps_ld_0} + {1'h0, entries_st_2_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1431 = _pop_count_packed_deps_T_1430; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1432 = {1'h0, entries_st_2_bits_deps_ld_2} + {1'h0, entries_st_2_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1433 = _pop_count_packed_deps_T_1432; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1434 = {1'h0, _pop_count_packed_deps_T_1431} + {1'h0, _pop_count_packed_deps_T_1433}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1435 = _pop_count_packed_deps_T_1434; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1436 = {1'h0, entries_st_2_bits_deps_ld_4} + {1'h0, entries_st_2_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1437 = _pop_count_packed_deps_T_1436; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1438 = {1'h0, entries_st_2_bits_deps_ld_6} + {1'h0, entries_st_2_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1439 = _pop_count_packed_deps_T_1438; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1440 = {1'h0, _pop_count_packed_deps_T_1437} + {1'h0, _pop_count_packed_deps_T_1439}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1441 = _pop_count_packed_deps_T_1440; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1442 = {1'h0, _pop_count_packed_deps_T_1435} + {1'h0, _pop_count_packed_deps_T_1441}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1443 = _pop_count_packed_deps_T_1442; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1444 = {1'h0, entries_st_2_bits_deps_ex_0} + {1'h0, entries_st_2_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1445 = _pop_count_packed_deps_T_1444; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1446 = {1'h0, entries_st_2_bits_deps_ex_2} + {1'h0, entries_st_2_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1447 = _pop_count_packed_deps_T_1446; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1448 = {1'h0, _pop_count_packed_deps_T_1445} + {1'h0, _pop_count_packed_deps_T_1447}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1449 = _pop_count_packed_deps_T_1448; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1450 = {1'h0, entries_st_2_bits_deps_ex_4} + {1'h0, entries_st_2_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1451 = _pop_count_packed_deps_T_1450; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1452 = {1'h0, entries_st_2_bits_deps_ex_6} + {1'h0, entries_st_2_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1453 = _pop_count_packed_deps_T_1452; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1454 = {1'h0, _pop_count_packed_deps_T_1451} + {1'h0, _pop_count_packed_deps_T_1453}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1455 = _pop_count_packed_deps_T_1454; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1456 = {1'h0, _pop_count_packed_deps_T_1449} + {1'h0, _pop_count_packed_deps_T_1455}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1457 = _pop_count_packed_deps_T_1456; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1458 = {1'h0, entries_st_2_bits_deps_ex_8} + {1'h0, entries_st_2_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1459 = _pop_count_packed_deps_T_1458; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1460 = {1'h0, entries_st_2_bits_deps_ex_10} + {1'h0, entries_st_2_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1461 = _pop_count_packed_deps_T_1460; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1462 = {1'h0, _pop_count_packed_deps_T_1459} + {1'h0, _pop_count_packed_deps_T_1461}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1463 = _pop_count_packed_deps_T_1462; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1464 = {1'h0, entries_st_2_bits_deps_ex_12} + {1'h0, entries_st_2_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1465 = _pop_count_packed_deps_T_1464; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1466 = {1'h0, entries_st_2_bits_deps_ex_14} + {1'h0, entries_st_2_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1467 = _pop_count_packed_deps_T_1466; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1468 = {1'h0, _pop_count_packed_deps_T_1465} + {1'h0, _pop_count_packed_deps_T_1467}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1469 = _pop_count_packed_deps_T_1468; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1470 = {1'h0, _pop_count_packed_deps_T_1463} + {1'h0, _pop_count_packed_deps_T_1469}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1471 = _pop_count_packed_deps_T_1470; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1472 = {1'h0, _pop_count_packed_deps_T_1457} + {1'h0, _pop_count_packed_deps_T_1471}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1473 = _pop_count_packed_deps_T_1472; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1474 = {2'h0, _pop_count_packed_deps_T_1443} + {1'h0, _pop_count_packed_deps_T_1473}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1475 = _pop_count_packed_deps_T_1474[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1476 = {1'h0, entries_st_2_bits_deps_st_0} + {1'h0, entries_st_2_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1477 = _pop_count_packed_deps_T_1476; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1478 = {1'h0, entries_st_2_bits_deps_st_2} + {1'h0, entries_st_2_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1479 = _pop_count_packed_deps_T_1478; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1480 = {1'h0, _pop_count_packed_deps_T_1477} + {1'h0, _pop_count_packed_deps_T_1479}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1481 = _pop_count_packed_deps_T_1480; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1482 = {1'h0, _pop_count_packed_deps_T_1475} + {3'h0, _pop_count_packed_deps_T_1481}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1483 = _pop_count_packed_deps_T_1482[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1484 = entries_st_2_valid ? _pop_count_packed_deps_T_1483 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_26 = _pop_count_packed_deps_T_1484; // @[ReservationStation.scala:513:{38,59}]
wire [1:0] _pop_count_packed_deps_T_1485 = {1'h0, entries_st_3_bits_deps_ld_0} + {1'h0, entries_st_3_bits_deps_ld_1}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1486 = _pop_count_packed_deps_T_1485; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1487 = {1'h0, entries_st_3_bits_deps_ld_2} + {1'h0, entries_st_3_bits_deps_ld_3}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1488 = _pop_count_packed_deps_T_1487; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1489 = {1'h0, _pop_count_packed_deps_T_1486} + {1'h0, _pop_count_packed_deps_T_1488}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1490 = _pop_count_packed_deps_T_1489; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1491 = {1'h0, entries_st_3_bits_deps_ld_4} + {1'h0, entries_st_3_bits_deps_ld_5}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1492 = _pop_count_packed_deps_T_1491; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1493 = {1'h0, entries_st_3_bits_deps_ld_6} + {1'h0, entries_st_3_bits_deps_ld_7}; // @[ReservationStation.scala:119:23, :514:13]
wire [1:0] _pop_count_packed_deps_T_1494 = _pop_count_packed_deps_T_1493; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1495 = {1'h0, _pop_count_packed_deps_T_1492} + {1'h0, _pop_count_packed_deps_T_1494}; // @[ReservationStation.scala:514:13]
wire [2:0] _pop_count_packed_deps_T_1496 = _pop_count_packed_deps_T_1495; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1497 = {1'h0, _pop_count_packed_deps_T_1490} + {1'h0, _pop_count_packed_deps_T_1496}; // @[ReservationStation.scala:514:13]
wire [3:0] _pop_count_packed_deps_T_1498 = _pop_count_packed_deps_T_1497; // @[ReservationStation.scala:514:13]
wire [1:0] _pop_count_packed_deps_T_1499 = {1'h0, entries_st_3_bits_deps_ex_0} + {1'h0, entries_st_3_bits_deps_ex_1}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1500 = _pop_count_packed_deps_T_1499; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1501 = {1'h0, entries_st_3_bits_deps_ex_2} + {1'h0, entries_st_3_bits_deps_ex_3}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1502 = _pop_count_packed_deps_T_1501; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1503 = {1'h0, _pop_count_packed_deps_T_1500} + {1'h0, _pop_count_packed_deps_T_1502}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1504 = _pop_count_packed_deps_T_1503; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1505 = {1'h0, entries_st_3_bits_deps_ex_4} + {1'h0, entries_st_3_bits_deps_ex_5}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1506 = _pop_count_packed_deps_T_1505; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1507 = {1'h0, entries_st_3_bits_deps_ex_6} + {1'h0, entries_st_3_bits_deps_ex_7}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1508 = _pop_count_packed_deps_T_1507; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1509 = {1'h0, _pop_count_packed_deps_T_1506} + {1'h0, _pop_count_packed_deps_T_1508}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1510 = _pop_count_packed_deps_T_1509; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1511 = {1'h0, _pop_count_packed_deps_T_1504} + {1'h0, _pop_count_packed_deps_T_1510}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1512 = _pop_count_packed_deps_T_1511; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1513 = {1'h0, entries_st_3_bits_deps_ex_8} + {1'h0, entries_st_3_bits_deps_ex_9}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1514 = _pop_count_packed_deps_T_1513; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1515 = {1'h0, entries_st_3_bits_deps_ex_10} + {1'h0, entries_st_3_bits_deps_ex_11}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1516 = _pop_count_packed_deps_T_1515; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1517 = {1'h0, _pop_count_packed_deps_T_1514} + {1'h0, _pop_count_packed_deps_T_1516}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1518 = _pop_count_packed_deps_T_1517; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1519 = {1'h0, entries_st_3_bits_deps_ex_12} + {1'h0, entries_st_3_bits_deps_ex_13}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1520 = _pop_count_packed_deps_T_1519; // @[ReservationStation.scala:514:40]
wire [1:0] _pop_count_packed_deps_T_1521 = {1'h0, entries_st_3_bits_deps_ex_14} + {1'h0, entries_st_3_bits_deps_ex_15}; // @[ReservationStation.scala:119:23, :514:40]
wire [1:0] _pop_count_packed_deps_T_1522 = _pop_count_packed_deps_T_1521; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1523 = {1'h0, _pop_count_packed_deps_T_1520} + {1'h0, _pop_count_packed_deps_T_1522}; // @[ReservationStation.scala:514:40]
wire [2:0] _pop_count_packed_deps_T_1524 = _pop_count_packed_deps_T_1523; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1525 = {1'h0, _pop_count_packed_deps_T_1518} + {1'h0, _pop_count_packed_deps_T_1524}; // @[ReservationStation.scala:514:40]
wire [3:0] _pop_count_packed_deps_T_1526 = _pop_count_packed_deps_T_1525; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1527 = {1'h0, _pop_count_packed_deps_T_1512} + {1'h0, _pop_count_packed_deps_T_1526}; // @[ReservationStation.scala:514:40]
wire [4:0] _pop_count_packed_deps_T_1528 = _pop_count_packed_deps_T_1527; // @[ReservationStation.scala:514:40]
wire [5:0] _pop_count_packed_deps_T_1529 = {2'h0, _pop_count_packed_deps_T_1498} + {1'h0, _pop_count_packed_deps_T_1528}; // @[ReservationStation.scala:514:{13,30,40}]
wire [4:0] _pop_count_packed_deps_T_1530 = _pop_count_packed_deps_T_1529[4:0]; // @[ReservationStation.scala:514:30]
wire [1:0] _pop_count_packed_deps_T_1531 = {1'h0, entries_st_3_bits_deps_st_0} + {1'h0, entries_st_3_bits_deps_st_1}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1532 = _pop_count_packed_deps_T_1531; // @[ReservationStation.scala:514:67]
wire [1:0] _pop_count_packed_deps_T_1533 = {1'h0, entries_st_3_bits_deps_st_2} + {1'h0, entries_st_3_bits_deps_st_3}; // @[ReservationStation.scala:119:23, :514:67]
wire [1:0] _pop_count_packed_deps_T_1534 = _pop_count_packed_deps_T_1533; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1535 = {1'h0, _pop_count_packed_deps_T_1532} + {1'h0, _pop_count_packed_deps_T_1534}; // @[ReservationStation.scala:514:67]
wire [2:0] _pop_count_packed_deps_T_1536 = _pop_count_packed_deps_T_1535; // @[ReservationStation.scala:514:67]
wire [5:0] _pop_count_packed_deps_T_1537 = {1'h0, _pop_count_packed_deps_T_1530} + {3'h0, _pop_count_packed_deps_T_1536}; // @[ReservationStation.scala:514:{30,57,67}]
wire [4:0] _pop_count_packed_deps_T_1538 = _pop_count_packed_deps_T_1537[4:0]; // @[ReservationStation.scala:514:57]
wire [4:0] _pop_count_packed_deps_T_1539 = entries_st_3_valid ? _pop_count_packed_deps_T_1538 : 5'h0; // @[ReservationStation.scala:119:23, :513:59, :514:57]
wire [4:0] pop_count_packed_deps_27 = _pop_count_packed_deps_T_1539; // @[ReservationStation.scala:513:{38,59}]
wire _min_pop_count_T = pop_count_packed_deps_0 < pop_count_packed_deps_1; // @[Util.scala:109:12]
wire [4:0] _min_pop_count_T_1 = _min_pop_count_T ? pop_count_packed_deps_0 : pop_count_packed_deps_1; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_2 = _min_pop_count_T_1 < pop_count_packed_deps_2; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_3 = _min_pop_count_T_2 ? _min_pop_count_T_1 : pop_count_packed_deps_2; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_4 = _min_pop_count_T_3 < pop_count_packed_deps_3; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_5 = _min_pop_count_T_4 ? _min_pop_count_T_3 : pop_count_packed_deps_3; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_6 = _min_pop_count_T_5 < pop_count_packed_deps_4; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_7 = _min_pop_count_T_6 ? _min_pop_count_T_5 : pop_count_packed_deps_4; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_8 = _min_pop_count_T_7 < pop_count_packed_deps_5; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_9 = _min_pop_count_T_8 ? _min_pop_count_T_7 : pop_count_packed_deps_5; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_10 = _min_pop_count_T_9 < pop_count_packed_deps_6; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_11 = _min_pop_count_T_10 ? _min_pop_count_T_9 : pop_count_packed_deps_6; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_12 = _min_pop_count_T_11 < pop_count_packed_deps_7; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_13 = _min_pop_count_T_12 ? _min_pop_count_T_11 : pop_count_packed_deps_7; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_14 = _min_pop_count_T_13 < pop_count_packed_deps_8; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_15 = _min_pop_count_T_14 ? _min_pop_count_T_13 : pop_count_packed_deps_8; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_16 = _min_pop_count_T_15 < pop_count_packed_deps_9; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_17 = _min_pop_count_T_16 ? _min_pop_count_T_15 : pop_count_packed_deps_9; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_18 = _min_pop_count_T_17 < pop_count_packed_deps_10; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_19 = _min_pop_count_T_18 ? _min_pop_count_T_17 : pop_count_packed_deps_10; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_20 = _min_pop_count_T_19 < pop_count_packed_deps_11; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_21 = _min_pop_count_T_20 ? _min_pop_count_T_19 : pop_count_packed_deps_11; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_22 = _min_pop_count_T_21 < pop_count_packed_deps_12; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_23 = _min_pop_count_T_22 ? _min_pop_count_T_21 : pop_count_packed_deps_12; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_24 = _min_pop_count_T_23 < pop_count_packed_deps_13; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_25 = _min_pop_count_T_24 ? _min_pop_count_T_23 : pop_count_packed_deps_13; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_26 = _min_pop_count_T_25 < pop_count_packed_deps_14; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_27 = _min_pop_count_T_26 ? _min_pop_count_T_25 : pop_count_packed_deps_14; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_28 = _min_pop_count_T_27 < pop_count_packed_deps_15; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_29 = _min_pop_count_T_28 ? _min_pop_count_T_27 : pop_count_packed_deps_15; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_30 = _min_pop_count_T_29 < pop_count_packed_deps_16; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_31 = _min_pop_count_T_30 ? _min_pop_count_T_29 : pop_count_packed_deps_16; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_32 = _min_pop_count_T_31 < pop_count_packed_deps_17; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_33 = _min_pop_count_T_32 ? _min_pop_count_T_31 : pop_count_packed_deps_17; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_34 = _min_pop_count_T_33 < pop_count_packed_deps_18; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_35 = _min_pop_count_T_34 ? _min_pop_count_T_33 : pop_count_packed_deps_18; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_36 = _min_pop_count_T_35 < pop_count_packed_deps_19; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_37 = _min_pop_count_T_36 ? _min_pop_count_T_35 : pop_count_packed_deps_19; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_38 = _min_pop_count_T_37 < pop_count_packed_deps_20; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_39 = _min_pop_count_T_38 ? _min_pop_count_T_37 : pop_count_packed_deps_20; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_40 = _min_pop_count_T_39 < pop_count_packed_deps_21; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_41 = _min_pop_count_T_40 ? _min_pop_count_T_39 : pop_count_packed_deps_21; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_42 = _min_pop_count_T_41 < pop_count_packed_deps_22; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_43 = _min_pop_count_T_42 ? _min_pop_count_T_41 : pop_count_packed_deps_22; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_44 = _min_pop_count_T_43 < pop_count_packed_deps_23; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_45 = _min_pop_count_T_44 ? _min_pop_count_T_43 : pop_count_packed_deps_23; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_46 = _min_pop_count_T_45 < pop_count_packed_deps_24; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_47 = _min_pop_count_T_46 ? _min_pop_count_T_45 : pop_count_packed_deps_24; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_48 = _min_pop_count_T_47 < pop_count_packed_deps_25; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_49 = _min_pop_count_T_48 ? _min_pop_count_T_47 : pop_count_packed_deps_25; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_50 = _min_pop_count_T_49 < pop_count_packed_deps_26; // @[Util.scala:109:{8,12}]
wire [4:0] _min_pop_count_T_51 = _min_pop_count_T_50 ? _min_pop_count_T_49 : pop_count_packed_deps_26; // @[Util.scala:109:{8,12}]
wire _min_pop_count_T_52 = _min_pop_count_T_51 < pop_count_packed_deps_27; // @[Util.scala:109:{8,12}]
wire [4:0] min_pop_count = _min_pop_count_T_52 ? _min_pop_count_T_51 : pop_count_packed_deps_27; // @[Util.scala:109:{8,12}]
reg [15:0] cycles_since_issue; // @[ReservationStation.scala:520:35]
wire [16:0] _cycles_since_issue_T = {1'h0, cycles_since_issue} + 17'h1; // @[ReservationStation.scala:520:35, :525:46]
wire [15:0] _cycles_since_issue_T_1 = _cycles_since_issue_T[15:0]; // @[ReservationStation.scala:525:46]
reg [20:0] cntr_value; // @[Counter.scala:61:40]
wire wrap = cntr_value == 21'h1E847F; // @[Counter.scala:61:40, :73:24]
wire [21:0] _value_T = {1'h0, cntr_value} + 22'h1; // @[Counter.scala:61:40, :77:24]
wire [20:0] _value_T_1 = _value_T[20:0]; // @[Counter.scala:77:24] |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File L2MemHelperLatencyInjection.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.{Printable}
import chisel3.reflect.DataMirror
import freechips.rocketchip.tile._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig, TLBPTWIO, TLB, MStatus, PRV}
import freechips.rocketchip.util.DecoupledHelper
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.rocket.{RAS}
import freechips.rocketchip.tilelink._
class L2MemHelperLatencyInjection(printInfo: String = "", numOutstandingReqs: Int = 32, queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModule {
val numOutstandingRequestsAllowed = numOutstandingReqs
val tlTagBits = log2Ceil(numOutstandingRequestsAllowed)
lazy val module = new L2MemHelperLatencyInjectionModule(this, printInfo, queueRequests, queueResponses, printWriteBytes)
val masterNode = TLClientNode(Seq(TLClientPortParameters(
Seq(TLClientParameters(name = printInfo, sourceId = IdRange(0,
numOutstandingRequestsAllowed)))
)))
}
class L2MemHelperLatencyInjectionModule(outer: L2MemHelperLatencyInjection, printInfo: String = "", queueRequests: Boolean = false, queueResponses: Boolean = false, printWriteBytes: Boolean = false)(implicit p: Parameters) extends LazyModuleImp(outer)
with HasCoreParameters
with MemoryOpConstants {
val io = IO(new Bundle {
val userif = Flipped(new L2MemHelperBundle)
val latency_inject_cycles = Input(UInt(64.W))
val sfence = Input(Bool())
val ptw = new TLBPTWIO
val status = Flipped(Valid(new MStatus))
})
val (dmem, edge) = outer.masterNode.out.head
val request_input = Wire(Decoupled(new L2ReqInternal))
if (!queueRequests) {
request_input <> io.userif.req
} else {
val requestQueue = Module(new Queue(new L2ReqInternal, 4))
request_input <> requestQueue.io.deq
requestQueue.io.enq <> io.userif.req
}
val response_output = Wire(Decoupled(new L2RespInternal))
if (!queueResponses) {
io.userif.resp <> response_output
} else {
val responseQueue = Module(new Queue(new L2RespInternal, 4))
responseQueue.io.enq <> response_output
io.userif.resp <> responseQueue.io.deq
}
val status = Reg(new MStatus)
when (io.status.valid) {
CompressAccelLogger.logInfo(printInfo + " setting status.dprv to: %x compare %x\n", io.status.bits.dprv, PRV.M.U)
status := io.status.bits
}
val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), p(CompressAccelTLB).get)(edge, p))
tlb.io.req.valid := request_input.valid
tlb.io.req.bits.vaddr := request_input.bits.addr
tlb.io.req.bits.size := request_input.bits.size
tlb.io.req.bits.cmd := request_input.bits.cmd
tlb.io.req.bits.passthrough := false.B
val tlb_ready = tlb.io.req.ready && !tlb.io.resp.miss
tlb.io.req.bits.prv := DontCare
tlb.io.req.bits.v := DontCare
tlb.io.sfence.bits.hv := DontCare
tlb.io.sfence.bits.hg := DontCare
io.ptw <> tlb.io.ptw
tlb.io.ptw.status := status
tlb.io.sfence.valid := io.sfence
tlb.io.sfence.bits.rs1 := false.B
tlb.io.sfence.bits.rs2 := false.B
tlb.io.sfence.bits.addr := 0.U
tlb.io.sfence.bits.asid := 0.U
tlb.io.kill := false.B
val outstanding_req_addr = Module(new Queue(new L2InternalTracking, outer.numOutstandingRequestsAllowed * 4))
val tags_for_issue_Q = Module(new Queue(UInt(outer.tlTagBits.W), outer.numOutstandingRequestsAllowed * 2))
tags_for_issue_Q.io.enq.valid := false.B
tags_for_issue_Q.io.enq.bits := DontCare
val tags_init_reg = RegInit(0.U((outer.tlTagBits+1).W))
when (tags_init_reg =/= (outer.numOutstandingRequestsAllowed).U) {
tags_for_issue_Q.io.enq.bits := tags_init_reg
tags_for_issue_Q.io.enq.valid := true.B
when (tags_for_issue_Q.io.enq.ready) {
CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q init with value %d\n", tags_for_issue_Q.io.enq.bits)
tags_init_reg := tags_init_reg + 1.U
}
}
val addr_mask_check = (1.U(64.W) << request_input.bits.size) - 1.U
val assertcheck = RegNext((!request_input.valid) || ((request_input.bits.addr & addr_mask_check) === 0.U))
when (!assertcheck) {
CompressAccelLogger.logInfo(printInfo + " L2IF: access addr must be aligned to write width\n")
}
assert(assertcheck,
printInfo + " L2IF: access addr must be aligned to write width\n")
val global_memop_accepted = RegInit(0.U(64.W))
when (io.userif.req.fire) {
global_memop_accepted := global_memop_accepted + 1.U
}
val global_memop_sent = RegInit(0.U(64.W))
val global_memop_ackd = RegInit(0.U(64.W))
val global_memop_resp_to_user = RegInit(0.U(64.W))
io.userif.no_memops_inflight := global_memop_accepted === global_memop_ackd
val free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) < (1 << outer.tlTagBits).U
val assert_free_outstanding_op_slots = (global_memop_sent - global_memop_ackd) <= (1 << outer.tlTagBits).U
when (!assert_free_outstanding_op_slots) {
CompressAccelLogger.logInfo(printInfo + " L2IF: Too many outstanding requests for tag count.\n")
}
assert(assert_free_outstanding_op_slots,
printInfo + " L2IF: Too many outstanding requests for tag count.\n")
when (request_input.fire) {
global_memop_sent := global_memop_sent + 1.U
}
val sendtag = tags_for_issue_Q.io.deq.bits
val cur_cycle = RegInit(0.U(64.W))
cur_cycle := cur_cycle + 1.U
val release_cycle_q_depth = 2 * outer.numOutstandingRequestsAllowed
val request_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth))
// val req_release_cycle_q = Module(new Queue(UInt(64.W), release_cycle_q_depth, flow=true))
// val req_q = Module(new Queue(DataMirror.internal.chiselTypeClone[TLBundleA](dmem.a.bits), release_cycle_q_depth, flow=true))
// req_release_cycle_q.io.enq.bits := cur_cycle + io.latency_inject_cycles
request_latency_injection_q.io.latency_cycles := io.latency_inject_cycles
request_latency_injection_q.io.enq.bits := DontCare
when (request_input.bits.cmd === M_XRD) {
val (legal, bundle) = edge.Get(fromSource=sendtag,
toAddress=tlb.io.resp.paddr,
lgSize=request_input.bits.size)
request_latency_injection_q.io.enq.bits := bundle
// dmem.a.bits := bundle
} .elsewhen (request_input.bits.cmd === M_XWR) {
val (legal, bundle) = edge.Put(fromSource=sendtag,
toAddress=tlb.io.resp.paddr,
lgSize=request_input.bits.size,
data=request_input.bits.data << ((request_input.bits.addr(4, 0) << 3)))
request_latency_injection_q.io.enq.bits := bundle
// dmem.a.bits := bundle
} .elsewhen (request_input.valid) {
CompressAccelLogger.logInfo(printInfo + " ERR")
assert(false.B, "ERR")
}
val tl_resp_queues = Seq.fill(outer.numOutstandingRequestsAllowed)(
Module(new Queue(new L2RespInternal, 4, flow=true)).io)
// val current_request_tag_has_response_space = tl_resp_queues(tags_for_issue_Q.io.deq.bits).enq.ready
val current_request_tag_has_response_space = tl_resp_queues.zipWithIndex.map({ case (q, idx) =>
q.enq.ready && (idx.U === tags_for_issue_Q.io.deq.bits)
}).reduce(_ || _)
val fire_req = DecoupledHelper(
request_input.valid,
request_latency_injection_q.io.enq.ready,
tlb_ready,
outstanding_req_addr.io.enq.ready,
free_outstanding_op_slots,
tags_for_issue_Q.io.deq.valid,
current_request_tag_has_response_space
)
outstanding_req_addr.io.enq.bits.addrindex := request_input.bits.addr & 0x1F.U
outstanding_req_addr.io.enq.bits.tag := sendtag
request_latency_injection_q.io.enq.valid := fire_req.fire(request_latency_injection_q.io.enq.ready)
request_input.ready := fire_req.fire(request_input.valid)
outstanding_req_addr.io.enq.valid := fire_req.fire(outstanding_req_addr.io.enq.ready)
tags_for_issue_Q.io.deq.ready := fire_req.fire(tags_for_issue_Q.io.deq.valid)
dmem.a <> request_latency_injection_q.io.deq
when (dmem.a.fire) {
when (request_input.bits.cmd === M_XRD) {
CompressAccelLogger.logInfo(printInfo + " L2IF: req(read) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, opnum: %d, sendtag: %d\n",
request_input.bits.addr,
tlb.io.resp.paddr,
request_input.bits.size,
global_memop_sent,
sendtag)
}
}
when (fire_req.fire) {
when (request_input.bits.cmd === M_XWR) {
CompressAccelLogger.logCritical(printInfo + " L2IF: req(write) vaddr: 0x%x, paddr: 0x%x, wid: 0x%x, data: 0x%x, opnum: %d, sendtag: %d\n",
request_input.bits.addr,
tlb.io.resp.paddr,
request_input.bits.size,
request_input.bits.data,
global_memop_sent,
sendtag)
if (printWriteBytes) {
for (i <- 0 until 32) {
when (i.U < (1.U << request_input.bits.size)) {
CompressAccelLogger.logInfo("WRITE_BYTE ADDR: 0x%x BYTE: 0x%x " + printInfo + "\n", request_input.bits.addr + i.U, (request_input.bits.data >> (i*8).U)(7, 0))
}
}
}
}
}
val response_latency_injection_q = Module(new LatencyInjectionQueue(DataMirror.internal.chiselTypeClone[TLBundleD](dmem.d.bits), release_cycle_q_depth))
response_latency_injection_q.io.latency_cycles := io.latency_inject_cycles
response_latency_injection_q.io.enq <> dmem.d
// val selectQready = tl_resp_queues(response_latency_injection_q.io.deq.bits.source).enq.ready
val selectQready = tl_resp_queues.zipWithIndex.map({ case(q, idx) =>
q.enq.ready && (idx.U === response_latency_injection_q.io.deq.bits.source)
}).reduce(_ || _)
val fire_actual_mem_resp = DecoupledHelper(
selectQready,
response_latency_injection_q.io.deq.valid,
tags_for_issue_Q.io.enq.ready
)
when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready)) {
tags_for_issue_Q.io.enq.valid := true.B
tags_for_issue_Q.io.enq.bits := response_latency_injection_q.io.deq.bits.source
}
when (fire_actual_mem_resp.fire(tags_for_issue_Q.io.enq.ready) &&
tags_for_issue_Q.io.enq.valid) {
CompressAccelLogger.logInfo(printInfo + " tags_for_issue_Q add back tag %d\n", tags_for_issue_Q.io.enq.bits)
}
response_latency_injection_q.io.deq.ready := fire_actual_mem_resp.fire(response_latency_injection_q.io.deq.valid)
for (i <- 0 until outer.numOutstandingRequestsAllowed) {
tl_resp_queues(i).enq.valid := fire_actual_mem_resp.fire(selectQready) && (response_latency_injection_q.io.deq.bits.source === i.U)
tl_resp_queues(i).enq.bits.data := response_latency_injection_q.io.deq.bits.data
}
// val currentQueue = tl_resp_queues(outstanding_req_addr.io.deq.bits.tag)
// val queueValid = currentQueue.deq.valid
val queueValid = tl_resp_queues.zipWithIndex.map({ case(q, idx) =>
q.deq.valid && (idx.U === outstanding_req_addr.io.deq.bits.tag)
}).reduce(_ || _)
val fire_user_resp = DecoupledHelper(
queueValid,
response_output.ready,
outstanding_req_addr.io.deq.valid
)
// val resultdata = currentQueue.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3)
val resultdata = tl_resp_queues.zipWithIndex.map({ case(q, idx) =>
val is_current_q = (idx.U === outstanding_req_addr.io.deq.bits.tag)
val data = Wire(q.deq.bits.data.cloneType)
when (is_current_q) {
data := q.deq.bits.data >> (outstanding_req_addr.io.deq.bits.addrindex << 3)
} .otherwise {
data := 0.U
}
data
}).reduce(_ | _)
response_output.bits.data := resultdata
response_output.valid := fire_user_resp.fire(response_output.ready)
outstanding_req_addr.io.deq.ready := fire_user_resp.fire(outstanding_req_addr.io.deq.valid)
for (i <- 0 until outer.numOutstandingRequestsAllowed) {
tl_resp_queues(i).deq.ready := fire_user_resp.fire(queueValid) && (outstanding_req_addr.io.deq.bits.tag === i.U)
}
when (dmem.d.fire) {
when (edge.hasData(dmem.d.bits)) {
CompressAccelLogger.logInfo(printInfo + " L2IF: resp(read) data: 0x%x, opnum: %d, gettag: %d\n",
dmem.d.bits.data,
global_memop_ackd,
dmem.d.bits.source)
} .otherwise {
CompressAccelLogger.logInfo(printInfo + " L2IF: resp(write) opnum: %d, gettag: %d\n",
global_memop_ackd,
dmem.d.bits.source)
}
}
when (response_output.fire) {
CompressAccelLogger.logInfo(printInfo + " L2IF: realresp() data: 0x%x, opnum: %d, gettag: %d\n",
resultdata,
global_memop_resp_to_user,
outstanding_req_addr.io.deq.bits.tag)
}
when (response_latency_injection_q.io.deq.fire) {
global_memop_ackd := global_memop_ackd + 1.U
}
when (response_output.fire) {
global_memop_resp_to_user := global_memop_resp_to_user + 1.U
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Util.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.{Printable}
import freechips.rocketchip.tile._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig}
import freechips.rocketchip.util.DecoupledHelper
import freechips.rocketchip.rocket.constants.MemoryOpConstants
object CompressAccelLogger {
def logInfo(format: String, args: Bits*)(implicit p: Parameters) {
val loginfo_cycles = RegInit(0.U(64.W))
loginfo_cycles := loginfo_cycles + 1.U
printf("cy: %d, ", loginfo_cycles)
printf(Printable.pack(format, args:_*))
}
def logCritical(format: String, args: Bits*)(implicit p: Parameters) {
val loginfo_cycles = RegInit(0.U(64.W))
loginfo_cycles := loginfo_cycles + 1.U
if (p(CompressAccelPrintfEnable)) {
printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles))
printf(midas.targetutils.SynthesizePrintf(format, args:_*))
} else {
printf("cy: %d, ", loginfo_cycles)
printf(Printable.pack(format, args:_*))
}
}
def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) {
}
}
object CompressAccelParams {
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File annotations.scala:
// See LICENSE for license details.
package midas.targetutils
import chisel3.{
dontTouch,
fromBooleanToLiteral,
when,
Bits,
Bool,
Clock,
Data,
MemBase,
Module,
Printable,
RegNext,
Reset,
UInt,
Wire,
WireDefault,
}
import chisel3.printf.Printf
import chisel3.experimental.{annotate, requireIsHardware, BaseModule, ChiselAnnotation}
import firrtl.RenameMap
import firrtl.annotations.{
Annotation,
ComponentName,
HasSerializationHints,
InstanceTarget,
ModuleTarget,
ReferenceTarget,
SingleTargetAnnotation,
}
/** These are consumed by [[midas.passes.AutoILATransform]] to directly instantiate an ILA at the top of simulator's
* design hierarchy (the PlatformShim level).
*/
case class FpgaDebugAnnotation(target: Data) extends ChiselAnnotation {
def toFirrtl = FirrtlFpgaDebugAnnotation(target.toNamed)
}
case class FirrtlFpgaDebugAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] {
def duplicate(n: ComponentName) = this.copy(target = n)
}
object FpgaDebug {
def apply(targets: Data*): Unit = {
targets.foreach { requireIsHardware(_, "Target passed to FpgaDebug:") }
targets.map({ t => annotate(FpgaDebugAnnotation(t)) })
}
}
private[midas] class ReferenceTargetRenamer(renames: RenameMap) {
// TODO: determine order for multiple renames, or just check of == 1 rename?
def exactRename(rt: ReferenceTarget): ReferenceTarget = {
val renameMatches = renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt })
assert(
renameMatches.length <= 1,
s"${rt} should be renamed exactly once (or not at all). Suggested renames: ${renameMatches}",
)
renameMatches.headOption.getOrElse(rt)
}
def apply(rt: ReferenceTarget): Seq[ReferenceTarget] = {
renames.get(rt).getOrElse(Seq(rt)).collect({ case rt: ReferenceTarget => rt })
}
}
private[midas] case class SynthPrintfAnnotation(
target: ReferenceTarget
) extends firrtl.annotations.SingleTargetAnnotation[ReferenceTarget] {
def duplicate(newTarget: ReferenceTarget) = this.copy(newTarget)
}
object SynthesizePrintf {
/** Annotates a chisel printf as a candidate for synthesis. The printf is only synthesized if Printf synthesis is
* enabled in Golden Gate.
*
* See: https://docs.fires.im/en/stable/search.html?q=Printf+Synthesis&check_keywords=yes&area=default
*
* @param printf
* The printf statement to be synthesized.
*
* @return
* The original input, so that this annotator may be applied inline if desired.
*/
def apply(printf: Printf): Printf = {
annotate(new ChiselAnnotation {
def toFirrtl = SynthPrintfAnnotation(printf.toTarget)
})
printf
}
private def generateAnnotations(format: String, args: Seq[Bits], name: Option[String]): Printable = {
Module.currentModule.getOrElse(throw new RuntimeException("Cannot annotate a printf outside of a Module"))
// To preserve the behavior of the printf parameter annotator, generate a
// secondary printf and annotate that, instead of the user's printf, which
// will be given an empty string. This will be removed with the apply methods in 1.15.
val printf = SynthesizePrintf(chisel3.printf(Printable.pack(format, args: _*)))
name.foreach { n => printf.suggestName(n) }
Printable.pack("")
}
/** Annotates* a printf by intercepting the parameters to a chisel printf, and returning a printable. As a side
* effect, this function generates a ChiselSynthPrintfAnnotation with the format string and references to each of the
* args.
*
* *Note: this isn't actually annotating the statement but instead the arguments. This is a vestige from earlier
* versions of chisel / firrtl in which print statements were unnamed, and thus not referenceable from annotations.
*
* @param format
* The format string for the printf
* @param args
* Hardware references to populate the format string.
*/
@deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14")
def apply(format: String, args: Bits*): Printable = generateAnnotations(format, args, None)
/** Like the other apply method, but provides an optional name which can be used by synthesized hardware / bridge.
* Generally, users deploy the nameless form.
*
* @param name
* A descriptive name for this printf instance.
* @param format
* The format string for the printf
* @param args
* Hardware references to populate the format string.
*/
@deprecated("This method will be removed. Annotate the printf statement directly", "FireSim 1.14")
def apply(name: String, format: String, args: Bits*): Printable =
generateAnnotations(format, args, Some(name))
}
/** A mixed-in ancestor trait for all FAME annotations, useful for type-casing.
*/
trait FAMEAnnotation {
this: Annotation =>
}
/** This labels an instance so that it is extracted as a separate FAME model.
*/
case class FAMEModelAnnotation(target: BaseModule) extends ChiselAnnotation {
def toFirrtl: FirrtlFAMEModelAnnotation = {
val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName)
FirrtlFAMEModelAnnotation(parent.instOf(target.instanceName, target.name))
}
}
case class FirrtlFAMEModelAnnotation(
target: InstanceTarget
) extends SingleTargetAnnotation[InstanceTarget]
with FAMEAnnotation {
def targets = Seq(target)
def duplicate(n: InstanceTarget) = this.copy(n)
}
/** This specifies that the module should be automatically multi-threaded (Chisel annotator).
*/
case class EnableModelMultiThreadingAnnotation(target: BaseModule) extends ChiselAnnotation {
def toFirrtl: FirrtlEnableModelMultiThreadingAnnotation = {
val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName)
FirrtlEnableModelMultiThreadingAnnotation(parent.instOf(target.instanceName, target.name))
}
}
/** This specifies that the module should be automatically multi-threaded (FIRRTL annotation).
*/
case class FirrtlEnableModelMultiThreadingAnnotation(
target: InstanceTarget
) extends SingleTargetAnnotation[InstanceTarget]
with FAMEAnnotation {
def targets = Seq(target)
def duplicate(n: InstanceTarget) = this.copy(n)
}
/** This labels a target Mem so that it is extracted and replaced with a separate model.
*/
case class MemModelAnnotation[T <: Data](target: MemBase[T]) extends ChiselAnnotation {
def toFirrtl = FirrtlMemModelAnnotation(target.toNamed.toTarget)
}
case class FirrtlMemModelAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] {
def duplicate(rt: ReferenceTarget) = this.copy(target = rt)
}
case class ExcludeInstanceAssertsAnnotation(target: (String, String)) extends firrtl.annotations.NoTargetAnnotation {
def duplicate(n: (String, String)) = this.copy(target = n)
}
// TODO: Actually use a real target and not strings.
object ExcludeInstanceAsserts {
def apply(target: (String, String)): ChiselAnnotation =
new ChiselAnnotation {
def toFirrtl = ExcludeInstanceAssertsAnnotation(target)
}
}
sealed trait PerfCounterOpType
object PerfCounterOps {
/** Takes the annotated UInt and adds it to an accumulation register generated in the bridge
*/
case object Accumulate extends PerfCounterOpType
/** Takes the annotated UInt and exposes it directly to the driver NB: Fields longer than 64b are not supported, and
* must be divided into smaller segments that are sepearate annotated
*/
case object Identity extends PerfCounterOpType
}
/** AutoCounter annotations. Do not emit the FIRRTL annotations unless you are writing a target transformation, use the
* Chisel-side [[PerfCounter]] object instead.
*/
case class AutoCounterFirrtlAnnotation(
target: ReferenceTarget,
clock: ReferenceTarget,
reset: ReferenceTarget,
label: String,
description: String,
opType: PerfCounterOpType = PerfCounterOps.Accumulate,
coverGenerated: Boolean = false,
) extends firrtl.annotations.Annotation
with HasSerializationHints {
def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = {
val renamer = new ReferenceTargetRenamer(renames)
val renamedTarget = renamer.exactRename(target)
val renamedClock = renamer.exactRename(clock)
val renamedReset = renamer.exactRename(reset)
Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset))
}
// The AutoCounter tranform will reject this annotation if it's not enclosed
def shouldBeIncluded(modList: Seq[String]): Boolean = !coverGenerated || modList.contains(target.module)
def enclosingModule(): String = target.module
def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, enclosingModule())
def typeHints: Seq[Class[_]] = Seq(opType.getClass)
}
case class AutoCounterCoverModuleFirrtlAnnotation(target: ModuleTarget)
extends SingleTargetAnnotation[ModuleTarget]
with FAMEAnnotation {
def duplicate(n: ModuleTarget) = this.copy(target = n)
}
case class AutoCounterCoverModuleAnnotation(target: ModuleTarget) extends ChiselAnnotation {
def toFirrtl = AutoCounterCoverModuleFirrtlAnnotation(target)
}
object PerfCounter {
private def emitAnnotation(
target: UInt,
clock: Clock,
reset: Reset,
label: String,
description: String,
opType: PerfCounterOpType,
): Unit = {
requireIsHardware(target, "Target passed to PerfCounter:")
requireIsHardware(clock, "Clock passed to PerfCounter:")
requireIsHardware(reset, "Reset passed to PerfCounter:")
annotate(new ChiselAnnotation {
def toFirrtl =
AutoCounterFirrtlAnnotation(target.toTarget, clock.toTarget, reset.toTarget, label, description, opType)
})
}
/** Labels a signal as an event for which an host-side counter (an "AutoCounter") should be generated). Events can be
* multi-bit to encode multiple occurances in a cycle (e.g., the number of instructions retired in a superscalar
* processor). NB: Golden Gate will not generate the coutner unless AutoCounter is enabled in your the platform
* config. See the docs.fires.im for end-to-end usage information.
*
* @param target
* The number of occurances of the event (in the current cycle)
*
* @param clock
* The clock to which this event is sychronized.
*
* @param reset
* If the event is asserted while under the provide reset, it is not counted. TODO: This should be made optional.
*
* @param label
* A verilog-friendly identifier for the event signal
*
* @param description
* A human-friendly description of the event.
*
* @param opType
* Defines how the bridge should be aggregated into a performance counter.
*/
def apply(
target: UInt,
clock: Clock,
reset: Reset,
label: String,
description: String,
opType: PerfCounterOpType = PerfCounterOps.Accumulate,
): Unit =
emitAnnotation(target, clock, reset, label, description, opType)
/** A simplified variation of the full apply method above that uses the implicit clock and reset.
*/
def apply(target: UInt, label: String, description: String): Unit =
emitAnnotation(target, Module.clock, Module.reset, label, description, PerfCounterOps.Accumulate)
/** Passes the annotated UInt through to the driver without accumulation. Use cases:
* - Custom accumulation / counting logic not supported by the driver
* - Providing runtime metadata along side standard accumulation registers
*
* Note: Under reset, the passthrough value is set to 0. This keeps event handling uniform in the transform.
*/
def identity(target: UInt, label: String, description: String): Unit = {
require(
target.getWidth <= 64,
s"""|PerfCounter.identity can only accept fields <= 64b wide. Provided target for label:
| $label
|was ${target.getWidth}b.""".stripMargin,
)
emitAnnotation(target, Module.clock, Module.reset, label, description, opType = PerfCounterOps.Identity)
}
}
case class PlusArgFirrtlAnnotation(
target: InstanceTarget
) extends SingleTargetAnnotation[InstanceTarget]
with FAMEAnnotation {
def targets = Seq(target)
def duplicate(n: InstanceTarget) = this.copy(n)
}
object PlusArg {
private def emitAnnotation(
target: BaseModule
): Unit = {
annotate(new ChiselAnnotation {
def toFirrtl = {
val parent = ModuleTarget(target.toNamed.circuit.name, target.parentModName)
PlusArgFirrtlAnnotation(parent.instOf(target.instanceName, target.name))
}
})
}
/** Labels a Rocket Chip 'plusarg_reader' module to synthesize. Must be of the type found in
* https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/PlusArg.scala
*
* @param target
* The 'plusarg_reader' module to synthesize
*/
def apply(target: BaseModule): Unit = {
emitAnnotation(target)
}
}
// Need serialization utils to be upstreamed to FIRRTL before i can use these.
//sealed trait TriggerSourceType
//case object Credit extends TriggerSourceType
//case object Debit extends TriggerSourceType
case class TriggerSourceAnnotation(
target: ReferenceTarget,
clock: ReferenceTarget,
reset: Option[ReferenceTarget],
sourceType: Boolean,
) extends Annotation
with FAMEAnnotation {
def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = {
val renamer = new ReferenceTargetRenamer(renames)
val renamedTarget = renamer.exactRename(target)
val renamedClock = renamer.exactRename(clock)
val renamedReset = reset.map(renamer.exactRename)
Seq(this.copy(target = renamedTarget, clock = renamedClock, reset = renamedReset))
}
def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module)
def enclosingModule(): String = target.module
}
case class TriggerSinkAnnotation(
target: ReferenceTarget,
clock: ReferenceTarget,
) extends Annotation
with FAMEAnnotation {
def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = {
val renamer = new ReferenceTargetRenamer(renames)
val renamedTarget = renamer.exactRename(target)
val renamedClock = renamer.exactRename(clock)
Seq(this.copy(target = renamedTarget, clock = renamedClock))
}
def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module)
}
object TriggerSource {
private def annotateTrigger(tpe: Boolean)(target: Bool, reset: Option[Bool]): Unit = {
// Hack: Create dummy nodes until chisel-side instance annotations have been improved
val clock = WireDefault(Module.clock)
reset.map(dontTouch.apply)
requireIsHardware(target, "Target passed to TriggerSource:")
reset.foreach { requireIsHardware(_, "Reset passed to TriggerSource:") }
annotate(new ChiselAnnotation {
def toFirrtl =
TriggerSourceAnnotation(target.toNamed.toTarget, clock.toNamed.toTarget, reset.map(_.toTarget), tpe)
})
}
def annotateCredit = annotateTrigger(true) _
def annotateDebit = annotateTrigger(false) _
/** Methods to annotate a Boolean as a trigger credit or debit. Credits and debits issued while the module's implicit
* reset is asserted are not counted.
*/
def credit(credit: Bool): Unit = annotateCredit(credit, Some(Module.reset.asBool))
def debit(debit: Bool): Unit = annotateDebit(debit, Some(Module.reset.asBool))
def apply(creditSig: Bool, debitSig: Bool): Unit = {
credit(creditSig)
debit(debitSig)
}
/** Variations of the above methods that count credits and debits provided while the implicit reset is asserted.
*/
def creditEvenUnderReset(credit: Bool): Unit = annotateCredit(credit, None)
def debitEvenUnderReset(debit: Bool): Unit = annotateDebit(debit, None)
def evenUnderReset(creditSig: Bool, debitSig: Bool): Unit = {
creditEvenUnderReset(creditSig)
debitEvenUnderReset(debitSig)
}
/** Level sensitive trigger sources. Implemented using [[credit]] and [[debit]]. Note: This generated hardware in your
* target design.
*
* @param src
* Enables the trigger when asserted. If no other credits have been issued since (e.g., a second level-sensitive
* enable was asserted), the trigger is disabled when src is desasserted.
*/
def levelSensitiveEnable(src: Bool): Unit = {
val srcLast = RegNext(src)
credit(src && !srcLast)
debit(!src && srcLast)
}
}
object TriggerSink {
/** Marks a bool as receiving the global trigger signal.
*
* @param target
* A Bool node that will be driven with the trigger
*
* @param noSourceDefault
* The value that the trigger signal should take on if no trigger soruces are found in the target. This is a
* temporary parameter required while this apply method generates a wire. Otherwise this can be punted to the
* target's RTL.
*/
def apply(target: Bool, noSourceDefault: => Bool = true.B): Unit = {
// Hack: Create dummy nodes until chisel-side instance annotations have been improved
val targetWire = WireDefault(noSourceDefault)
val clock = Module.clock
target := targetWire
// Both the provided node and the generated one need to be dontTouched to stop
// constProp from optimizing the down stream logic(?)
dontTouch(target)
annotate(new ChiselAnnotation {
def toFirrtl = TriggerSinkAnnotation(targetWire.toTarget, clock.toTarget)
})
}
/** Syntatic sugar for a when context that is predicated by a trigger sink. Example usage:
* {{{
* TriggerSink.whenEnabled {
* printf(<...>)
* }
* }}}
*
* @param noSourceDefault
* See [[TriggerSink.apply]].
*/
def whenEnabled(noSourceDefault: => Bool = true.B)(elaborator: => Unit): Unit = {
val sinkEnable = Wire(Bool())
apply(sinkEnable, noSourceDefault)
when(sinkEnable) { elaborator }
}
}
case class RoCCBusyFirrtlAnnotation(
target: ReferenceTarget,
ready: ReferenceTarget,
valid: ReferenceTarget,
) extends firrtl.annotations.Annotation
with FAMEAnnotation {
def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = {
val renamer = new ReferenceTargetRenamer(renames)
val renamedReady = renamer.exactRename(ready)
val renamedValid = renamer.exactRename(valid)
val renamedTarget = renamer.exactRename(target)
Seq(this.copy(target = renamedTarget, ready = renamedReady, valid = renamedValid))
}
def enclosingModuleTarget(): ModuleTarget = ModuleTarget(target.circuit, target.module)
def enclosingModule(): String = target.module
}
object MakeRoCCBusyLatencyInsensitive {
def apply(
target: Bool,
ready: Bool,
valid: Bool,
): Unit = {
requireIsHardware(target, "Target passed to ..:")
requireIsHardware(ready, "Ready passed to ..:")
requireIsHardware(valid, "Valid passed to ..:")
annotate(new ChiselAnnotation {
def toFirrtl = RoCCBusyFirrtlAnnotation(target.toNamed.toTarget, ready.toNamed.toTarget, valid.toNamed.toTarget)
})
}
}
case class FirrtlPartWrapperParentAnnotation(
target: InstanceTarget
) extends SingleTargetAnnotation[InstanceTarget]
with FAMEAnnotation {
def targets = Seq(target)
def duplicate(n: InstanceTarget) = this.copy(n)
}
case class FirrtlPortToNeighborRouterIdxAnno(
target: ReferenceTarget,
extractNeighborIdx: Int,
removeNeighborIdx: Int,
) extends firrtl.annotations.Annotation
with FAMEAnnotation {
def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = {
val renamer = new ReferenceTargetRenamer(renames)
val renameTarget = renamer.exactRename(target)
Seq(this.copy(target = renameTarget))
}
}
case class FirrtlCombLogicInsideModuleAnno(
target: ReferenceTarget
) extends firrtl.annotations.Annotation
with FAMEAnnotation {
def update(renames: RenameMap): Seq[firrtl.annotations.Annotation] = {
val renamer = new ReferenceTargetRenamer(renames)
val renameTarget = renamer.exactRename(target)
Seq(this.copy(target = renameTarget))
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module L2MemHelperLatencyInjection_10( // @[L2MemHelperLatencyInjection.scala:29:7]
input clock, // @[L2MemHelperLatencyInjection.scala:29:7]
input reset, // @[L2MemHelperLatencyInjection.scala:29:7]
input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_master_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_master_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_master_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_master_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_master_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_master_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_master_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_master_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_master_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_userif_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_userif_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_userif_req_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [2:0] io_userif_req_bits_size, // @[L2MemHelperLatencyInjection.scala:33:14]
input [255:0] io_userif_req_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_userif_req_bits_cmd, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_userif_resp_ready, // @[L2MemHelperLatencyInjection.scala:33:14]
output io_userif_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14]
output [255:0] io_userif_resp_bits_data, // @[L2MemHelperLatencyInjection.scala:33:14]
output io_userif_no_memops_inflight, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_latency_inject_cycles, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_sfence, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_req_ready, // @[L2MemHelperLatencyInjection.scala:33:14]
output io_ptw_req_valid, // @[L2MemHelperLatencyInjection.scala:33:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
output io_ptw_req_bits_bits_need_gpa, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_valid, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_ae_ptw, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_ae_final, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pf, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_gf, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_hr, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_hw, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_hx, // @[L2MemHelperLatencyInjection.scala:33:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[L2MemHelperLatencyInjection.scala:33:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_d, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_g, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_u, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_pte_v, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_resp_bits_level, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_homogeneous, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_gpa_valid, // @[L2MemHelperLatencyInjection.scala:33:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_resp_bits_gpa_is_pte, // @[L2MemHelperLatencyInjection.scala:33:14]
input [3:0] io_ptw_ptbr_mode, // @[L2MemHelperLatencyInjection.scala:33:14]
input [43:0] io_ptw_ptbr_ppn, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_debug, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_cease, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_wfi, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_status_isa, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_status_dprv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_dv, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_status_prv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_v, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_mpv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_gva, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_tsr, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_tw, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_tvm, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_mxr, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_sum, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_mprv, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_status_fs, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_status_mpp, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_spp, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_mpie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_spie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_mie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_status_sie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_hstatus_spvp, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_hstatus_spv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_hstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_debug, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_cease, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_wfi, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_gstatus_isa, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_gstatus_dprv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_dv, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_gstatus_prv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_v, // @[L2MemHelperLatencyInjection.scala:33:14]
input [22:0] io_ptw_gstatus_zero2, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_mpv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_gva, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_mbe, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_sbe, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_gstatus_sxl, // @[L2MemHelperLatencyInjection.scala:33:14]
input [7:0] io_ptw_gstatus_zero1, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_tsr, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_tw, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_tvm, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_mxr, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_sum, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_mprv, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_gstatus_fs, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_gstatus_mpp, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_gstatus_vs, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_spp, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_mpie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_ube, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_spie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_upie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_mie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_hie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_sie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_gstatus_uie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_0_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_0_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_0_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_0_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_0_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_0_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_1_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_1_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_1_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_1_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_1_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_1_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_2_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_2_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_2_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_2_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_2_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_2_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_3_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_3_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_3_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_3_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_3_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_3_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_4_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_4_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_4_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_4_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_4_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_4_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_5_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_5_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_5_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_5_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_5_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_5_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_6_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_6_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_6_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_6_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_6_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_6_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_7_cfg_l, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_7_cfg_x, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_7_cfg_w, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_pmp_7_cfg_r, // @[L2MemHelperLatencyInjection.scala:33:14]
input [29:0] io_ptw_pmp_7_addr, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_ptw_pmp_7_mask, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_0_ren, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_0_wen, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_1_ren, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_1_wen, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_2_ren, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_2_wen, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_3_ren, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_ptw_customCSRs_csrs_3_wen, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[L2MemHelperLatencyInjection.scala:33:14]
input [63:0] io_ptw_customCSRs_csrs_3_value, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_valid, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_debug, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_cease, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_wfi, // @[L2MemHelperLatencyInjection.scala:33:14]
input [31:0] io_status_bits_isa, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_dprv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_dv, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_prv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_v, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_sd, // @[L2MemHelperLatencyInjection.scala:33:14]
input [22:0] io_status_bits_zero2, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_mpv, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_gva, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_mbe, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_sbe, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_sxl, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_uxl, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_sd_rv32, // @[L2MemHelperLatencyInjection.scala:33:14]
input [7:0] io_status_bits_zero1, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_tsr, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_tw, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_tvm, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_mxr, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_sum, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_mprv, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_xs, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_fs, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_mpp, // @[L2MemHelperLatencyInjection.scala:33:14]
input [1:0] io_status_bits_vs, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_spp, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_mpie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_ube, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_spie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_upie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_mie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_hie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_sie, // @[L2MemHelperLatencyInjection.scala:33:14]
input io_status_bits_uie // @[L2MemHelperLatencyInjection.scala:33:14]
);
wire _response_latency_injection_q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:245:44]
wire [4:0] _response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44]
wire [255:0] _response_latency_injection_q_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:245:44]
wire _Queue4_L2RespInternal_31_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_31_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_31_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_30_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_30_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_30_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_29_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_29_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_29_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_28_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_28_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_28_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_27_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_27_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_27_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_26_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_26_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_26_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_25_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_25_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_25_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_24_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_24_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_24_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_23_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_23_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_23_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_22_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_22_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_22_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_21_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_21_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_21_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_20_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_20_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_20_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_19_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_19_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_19_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_18_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_18_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_18_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_17_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_17_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_17_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_16_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_16_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_16_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_15_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_15_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_15_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_14_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_14_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_14_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_13_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_13_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_13_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_12_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_12_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_12_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_11_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_11_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_11_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_10_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_10_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_10_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_9_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_9_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_9_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_8_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_8_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_8_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_7_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_7_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_7_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_6_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_6_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_6_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_5_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_5_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_5_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_4_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_4_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_4_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_3_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_3_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_3_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_2_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_2_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_2_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_1_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_1_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_1_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _Queue4_L2RespInternal_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:182:11]
wire [255:0] _Queue4_L2RespInternal_io_deq_bits_data; // @[L2MemHelperLatencyInjection.scala:182:11]
wire _request_latency_injection_q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:151:43]
wire _tags_for_issue_Q_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:94:32]
wire _tags_for_issue_Q_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:94:32]
wire [4:0] _tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32]
wire _outstanding_req_addr_io_enq_ready; // @[L2MemHelperLatencyInjection.scala:91:36]
wire _outstanding_req_addr_io_deq_valid; // @[L2MemHelperLatencyInjection.scala:91:36]
wire [4:0] _outstanding_req_addr_io_deq_bits_addrindex; // @[L2MemHelperLatencyInjection.scala:91:36]
wire [4:0] _outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36]
wire _tlb_io_req_ready; // @[L2MemHelperLatencyInjection.scala:68:19]
wire _tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19]
wire [31:0] _tlb_io_resp_paddr; // @[L2MemHelperLatencyInjection.scala:68:19]
wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[L2MemHelperLatencyInjection.scala:29:7]
wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [4:0] auto_master_out_d_bits_source_0 = auto_master_out_d_bits_source; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[L2MemHelperLatencyInjection.scala:29:7]
wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [255:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7]
wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_userif_req_valid_0 = io_userif_req_valid; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_userif_req_bits_addr_0 = io_userif_req_bits_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [2:0] io_userif_req_bits_size_0 = io_userif_req_bits_size; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [255:0] io_userif_req_bits_data_0 = io_userif_req_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_userif_req_bits_cmd_0 = io_userif_req_bits_cmd; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_userif_resp_ready_0 = io_userif_resp_ready; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_latency_inject_cycles_0 = io_latency_inject_cycles; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_sfence_0 = io_sfence; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_valid_0 = io_status_valid; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_debug_0 = io_status_bits_debug; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_cease_0 = io_status_bits_cease; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_wfi_0 = io_status_bits_wfi; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] io_status_bits_isa_0 = io_status_bits_isa; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_dprv_0 = io_status_bits_dprv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_dv_0 = io_status_bits_dv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_prv_0 = io_status_bits_prv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_v_0 = io_status_bits_v; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_sd_0 = io_status_bits_sd; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [22:0] io_status_bits_zero2_0 = io_status_bits_zero2; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_mpv_0 = io_status_bits_mpv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_gva_0 = io_status_bits_gva; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_mbe_0 = io_status_bits_mbe; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_sbe_0 = io_status_bits_sbe; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_sxl_0 = io_status_bits_sxl; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_uxl_0 = io_status_bits_uxl; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_sd_rv32_0 = io_status_bits_sd_rv32; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [7:0] io_status_bits_zero1_0 = io_status_bits_zero1; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_tsr_0 = io_status_bits_tsr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_tw_0 = io_status_bits_tw; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_tvm_0 = io_status_bits_tvm; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_mxr_0 = io_status_bits_mxr; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_sum_0 = io_status_bits_sum; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_mprv_0 = io_status_bits_mprv; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_xs_0 = io_status_bits_xs; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_fs_0 = io_status_bits_fs; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_mpp_0 = io_status_bits_mpp; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_status_bits_vs_0 = io_status_bits_vs; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_spp_0 = io_status_bits_spp; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_mpie_0 = io_status_bits_mpie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_ube_0 = io_status_bits_ube; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_spie_0 = io_status_bits_spie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_upie_0 = io_status_bits_upie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_mie_0 = io_status_bits_mie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_hie_0 = io_status_bits_hie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_sie_0 = io_status_bits_sie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_status_bits_uie_0 = io_status_bits_uie; // @[L2MemHelperLatencyInjection.scala:29:7]
wire _printf_T = reset; // @[annotations.scala:102:49]
wire _printf_T_2 = reset; // @[annotations.scala:102:49]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_mbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_sbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_ube = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_upie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_hie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_uie = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_hu = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire bundle_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _legal_T_125 = 1'h0; // @[Parameters.scala:684:29]
wire _legal_T_131 = 1'h0; // @[Parameters.scala:684:54]
wire bundle_1_corrupt = 1'h0; // @[Edges.scala:480:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_req_bits_valid = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_status_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_gstatus_sd = 1'h1; // @[L2MemHelperLatencyInjection.scala:29:7]
wire _legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _legal_T_63 = 1'h1; // @[Parameters.scala:92:28]
wire _legal_T_64 = 1'h1; // @[Parameters.scala:92:38]
wire _legal_T_65 = 1'h1; // @[Parameters.scala:92:33]
wire _legal_T_66 = 1'h1; // @[Parameters.scala:684:29]
wire _legal_T_73 = 1'h1; // @[Parameters.scala:92:28]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [2:0] bundle_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] bundle_1_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] bundle_1_param = 3'h0; // @[Edges.scala:480:17]
wire [255:0] bundle_data = 256'h0; // @[Edges.scala:460:17]
wire [2:0] bundle_opcode = 3'h4; // @[Edges.scala:460:17]
wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[MixedNode.scala:542:17]
wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [255:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [4:0] masterNodeOut_d_bits_source = auto_master_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [255:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire request_input_ready; // @[L2MemHelperLatencyInjection.scala:44:27]
wire request_input_valid = io_userif_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27]
wire [63:0] request_input_bits_addr = io_userif_req_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27]
wire [2:0] request_input_bits_size = io_userif_req_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27]
wire [255:0] request_input_bits_data = io_userif_req_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27]
wire request_input_bits_cmd = io_userif_req_bits_cmd_0; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27]
wire response_output_ready = io_userif_resp_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29]
wire response_output_valid; // @[L2MemHelperLatencyInjection.scala:53:29]
wire [255:0] response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:53:29]
wire _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:128:57]
wire [2:0] auto_master_out_a_bits_opcode_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [2:0] auto_master_out_a_bits_param_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [3:0] auto_master_out_a_bits_size_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [4:0] auto_master_out_a_bits_source_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] auto_master_out_a_bits_address_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [31:0] auto_master_out_a_bits_mask_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [255:0] auto_master_out_a_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire auto_master_out_a_bits_corrupt_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire auto_master_out_a_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire auto_master_out_d_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_userif_req_ready_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [255:0] io_userif_resp_bits_data_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_userif_resp_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_userif_no_memops_inflight_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[L2MemHelperLatencyInjection.scala:29:7]
wire io_ptw_req_valid_0; // @[L2MemHelperLatencyInjection.scala:29:7]
assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_opcode_0 = masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_param_0 = masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_size_0 = masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_source_0 = masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_mask_0 = masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_data_0 = masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_master_out_a_bits_corrupt_0 = masterNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_master_out_d_ready_0 = masterNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire _request_input_ready_T_4; // @[Misc.scala:26:53]
assign io_userif_req_ready_0 = request_input_ready; // @[L2MemHelperLatencyInjection.scala:29:7, :44:27]
wire _response_output_valid_T; // @[Misc.scala:26:53]
assign io_userif_resp_valid_0 = response_output_valid; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29]
wire [255:0] resultdata; // @[L2MemHelperLatencyInjection.scala:307:15]
assign io_userif_resp_bits_data_0 = response_output_bits_data; // @[L2MemHelperLatencyInjection.scala:29:7, :53:29]
reg status_debug; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_cease; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_wfi; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [31:0] status_isa; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_dprv; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_dv; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_prv; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_v; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_sd; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [22:0] status_zero2; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_mpv; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_gva; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_mbe; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_sbe; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_sxl; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_uxl; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_sd_rv32; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [7:0] status_zero1; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_tsr; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_tw; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_tvm; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_mxr; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_sum; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_mprv; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_xs; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_fs; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_mpp; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [1:0] status_vs; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_spp; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_mpie; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_ube; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_spie; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_upie; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_mie; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_hie; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_sie; // @[L2MemHelperLatencyInjection.scala:62:19]
reg status_uie; // @[L2MemHelperLatencyInjection.scala:62:19]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
wire _tlb_ready_T = ~_tlb_io_resp_miss; // @[L2MemHelperLatencyInjection.scala:68:19, :74:39]
wire tlb_ready = _tlb_io_req_ready & _tlb_ready_T; // @[L2MemHelperLatencyInjection.scala:68:19, :74:{36,39}]
reg [5:0] tags_init_reg; // @[L2MemHelperLatencyInjection.scala:98:30]
wire _T_4 = tags_init_reg != 6'h20; // @[L2MemHelperLatencyInjection.scala:98:30, :99:23]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
wire [6:0] _tags_init_reg_T = {1'h0, tags_init_reg} + 7'h1; // @[L2MemHelperLatencyInjection.scala:98:30, :104:38]
wire [5:0] _tags_init_reg_T_1 = _tags_init_reg_T[5:0]; // @[L2MemHelperLatencyInjection.scala:104:38]
wire [70:0] _addr_mask_check_T = 71'h1 << request_input_bits_size; // @[L2MemHelperLatencyInjection.scala:44:27, :108:36]
wire [71:0] _addr_mask_check_T_1 = {1'h0, _addr_mask_check_T} - 72'h1; // @[L2MemHelperLatencyInjection.scala:108:{36,64}]
wire [70:0] addr_mask_check = _addr_mask_check_T_1[70:0]; // @[L2MemHelperLatencyInjection.scala:108:64]
wire _assertcheck_T = ~request_input_valid; // @[L2MemHelperLatencyInjection.scala:44:27, :109:30]
wire [70:0] _assertcheck_T_1 = {7'h0, addr_mask_check[63:0] & request_input_bits_addr}; // @[L2MemHelperLatencyInjection.scala:44:27, :108:64, :109:81]
wire _assertcheck_T_2 = _assertcheck_T_1 == 71'h0; // @[L2MemHelperLatencyInjection.scala:108:64, :109:{81,100}]
wire _assertcheck_T_3 = _assertcheck_T | _assertcheck_T_2; // @[L2MemHelperLatencyInjection.scala:109:{30,52,100}]
reg assertcheck; // @[L2MemHelperLatencyInjection.scala:109:28]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
reg [63:0] global_memop_accepted; // @[L2MemHelperLatencyInjection.scala:117:38]
wire [64:0] _global_memop_accepted_T = {1'h0, global_memop_accepted} + 65'h1; // @[L2MemHelperLatencyInjection.scala:117:38, :119:52]
wire [63:0] _global_memop_accepted_T_1 = _global_memop_accepted_T[63:0]; // @[L2MemHelperLatencyInjection.scala:119:52]
reg [63:0] global_memop_sent; // @[L2MemHelperLatencyInjection.scala:122:34]
reg [63:0] global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:124:34]
reg [63:0] global_memop_resp_to_user; // @[L2MemHelperLatencyInjection.scala:126:42]
assign _io_userif_no_memops_inflight_T = global_memop_accepted == global_memop_ackd; // @[L2MemHelperLatencyInjection.scala:117:38, :124:34, :128:57]
assign io_userif_no_memops_inflight_0 = _io_userif_no_memops_inflight_T; // @[L2MemHelperLatencyInjection.scala:29:7, :128:57]
wire [64:0] _GEN = {1'h0, global_memop_sent}; // @[L2MemHelperLatencyInjection.scala:122:34, :130:54]
wire [64:0] _GEN_0 = {1'h0, global_memop_ackd}; // @[L2MemHelperLatencyInjection.scala:124:34, :130:54]
wire [64:0] _GEN_1 = _GEN - _GEN_0; // @[L2MemHelperLatencyInjection.scala:130:54]
wire [64:0] _free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:130:54]
assign _free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54]
wire [64:0] _assert_free_outstanding_op_slots_T; // @[L2MemHelperLatencyInjection.scala:131:61]
assign _assert_free_outstanding_op_slots_T = _GEN_1; // @[L2MemHelperLatencyInjection.scala:130:54, :131:61]
wire [63:0] _free_outstanding_op_slots_T_1 = _free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:130:54]
wire free_outstanding_op_slots = _free_outstanding_op_slots_T_1 < 64'h20; // @[L2MemHelperLatencyInjection.scala:130:{54,75}]
wire [63:0] _assert_free_outstanding_op_slots_T_1 = _assert_free_outstanding_op_slots_T[63:0]; // @[L2MemHelperLatencyInjection.scala:131:61]
wire assert_free_outstanding_op_slots = _assert_free_outstanding_op_slots_T_1 < 64'h21; // @[L2MemHelperLatencyInjection.scala:131:{61,82}]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
wire [64:0] _global_memop_sent_T = _GEN + 65'h1; // @[L2MemHelperLatencyInjection.scala:130:54, :140:44]
wire [63:0] _global_memop_sent_T_1 = _global_memop_sent_T[63:0]; // @[L2MemHelperLatencyInjection.scala:140:44]
reg [63:0] cur_cycle; // @[L2MemHelperLatencyInjection.scala:146:26]
wire [64:0] _cur_cycle_T = {1'h0, cur_cycle} + 65'h1; // @[L2MemHelperLatencyInjection.scala:146:26, :147:26]
wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[L2MemHelperLatencyInjection.scala:147:26]
wire [31:0] _GEN_2 = {_tlb_io_resp_paddr[31:14], _tlb_io_resp_paddr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_4; // @[Parameters.scala:137:31]
assign _legal_T_4 = _GEN_2; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_67; // @[Parameters.scala:137:31]
assign _legal_T_67 = _GEN_2; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_5 = {1'h0, _legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_6 = _legal_T_5 & 33'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_7 = _legal_T_6; // @[Parameters.scala:137:46]
wire _legal_T_8 = _legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_9 = _legal_T_8; // @[Parameters.scala:684:54]
wire _legal_T_62 = _legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _GEN_3 = request_input_bits_size != 3'h7; // @[Parameters.scala:92:38]
wire _legal_T_11; // @[Parameters.scala:92:38]
assign _legal_T_11 = _GEN_3; // @[Parameters.scala:92:38]
wire _legal_T_74; // @[Parameters.scala:92:38]
assign _legal_T_74 = _GEN_3; // @[Parameters.scala:92:38]
wire _legal_T_12 = _legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _legal_T_13 = _legal_T_12; // @[Parameters.scala:684:29]
wire [31:0] _legal_T_14; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_15 = {1'h0, _legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_16 = _legal_T_15 & 33'h9A012000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_17 = _legal_T_16; // @[Parameters.scala:137:46]
wire _legal_T_18 = _legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_4 = {_tlb_io_resp_paddr[31:17], _tlb_io_resp_paddr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_19; // @[Parameters.scala:137:31]
assign _legal_T_19 = _GEN_4; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_24; // @[Parameters.scala:137:31]
assign _legal_T_24 = _GEN_4; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_126; // @[Parameters.scala:137:31]
assign _legal_T_126 = _GEN_4; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_20 = {1'h0, _legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_21 = _legal_T_20 & 33'h98013000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_22 = _legal_T_21; // @[Parameters.scala:137:46]
wire _legal_T_23 = _legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_25 = {1'h0, _legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_26 = _legal_T_25 & 33'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_27 = _legal_T_26; // @[Parameters.scala:137:46]
wire _legal_T_28 = _legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_5 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_29; // @[Parameters.scala:137:31]
assign _legal_T_29 = _GEN_5; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_87; // @[Parameters.scala:137:31]
assign _legal_T_87 = _GEN_5; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_30 = {1'h0, _legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_31 = _legal_T_30 & 33'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_32 = _legal_T_31; // @[Parameters.scala:137:46]
wire _legal_T_33 = _legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_6 = {_tlb_io_resp_paddr[31:28], _tlb_io_resp_paddr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_34; // @[Parameters.scala:137:31]
assign _legal_T_34 = _GEN_6; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_39; // @[Parameters.scala:137:31]
assign _legal_T_39 = _GEN_6; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_97; // @[Parameters.scala:137:31]
assign _legal_T_97 = _GEN_6; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_102; // @[Parameters.scala:137:31]
assign _legal_T_102 = _GEN_6; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_35 = {1'h0, _legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_36 = _legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_37 = _legal_T_36; // @[Parameters.scala:137:46]
wire _legal_T_38 = _legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_40 = {1'h0, _legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_41 = _legal_T_40 & 33'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_42 = _legal_T_41; // @[Parameters.scala:137:46]
wire _legal_T_43 = _legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_7 = {_tlb_io_resp_paddr[31:29], _tlb_io_resp_paddr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_44; // @[Parameters.scala:137:31]
assign _legal_T_44 = _GEN_7; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_107; // @[Parameters.scala:137:31]
assign _legal_T_107 = _GEN_7; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_45 = {1'h0, _legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_46 = _legal_T_45 & 33'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_47 = _legal_T_46; // @[Parameters.scala:137:46]
wire _legal_T_48 = _legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _GEN_8 = _tlb_io_resp_paddr ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_49; // @[Parameters.scala:137:31]
assign _legal_T_49 = _GEN_8; // @[Parameters.scala:137:31]
wire [31:0] _legal_T_112; // @[Parameters.scala:137:31]
assign _legal_T_112 = _GEN_8; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_50 = {1'h0, _legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_51 = _legal_T_50 & 33'h90000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_52 = _legal_T_51; // @[Parameters.scala:137:46]
wire _legal_T_53 = _legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_54 = _legal_T_18 | _legal_T_23; // @[Parameters.scala:685:42]
wire _legal_T_55 = _legal_T_54 | _legal_T_28; // @[Parameters.scala:685:42]
wire _legal_T_56 = _legal_T_55 | _legal_T_33; // @[Parameters.scala:685:42]
wire _legal_T_57 = _legal_T_56 | _legal_T_38; // @[Parameters.scala:685:42]
wire _legal_T_58 = _legal_T_57 | _legal_T_43; // @[Parameters.scala:685:42]
wire _legal_T_59 = _legal_T_58 | _legal_T_48; // @[Parameters.scala:685:42]
wire _legal_T_60 = _legal_T_59 | _legal_T_53; // @[Parameters.scala:685:42]
wire _legal_T_61 = _legal_T_13 & _legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42]
wire legal = _legal_T_62 | _legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire [31:0] _a_mask_T; // @[Misc.scala:222:10]
wire [3:0] bundle_size; // @[Edges.scala:460:17]
wire [4:0] bundle_source; // @[Edges.scala:460:17]
wire [31:0] bundle_address; // @[Edges.scala:460:17]
wire [31:0] bundle_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_9 = {1'h0, request_input_bits_size}; // @[Edges.scala:463:15]
assign bundle_size = _GEN_9; // @[Edges.scala:460:17, :463:15]
wire [3:0] bundle_1_size; // @[Edges.scala:480:17]
assign bundle_1_size = _GEN_9; // @[Edges.scala:463:15, :480:17]
wire [4:0] _GEN_10 = {2'h0, request_input_bits_size}; // @[Misc.scala:202:34]
wire [4:0] _a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _a_mask_sizeOH_T = _GEN_10; // @[Misc.scala:202:34]
wire [4:0] _a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _a_mask_sizeOH_T_3 = _GEN_10; // @[Misc.scala:202:34]
wire [4:0] _a_mask_sizeOH_shiftAmount_T = _a_mask_sizeOH_T; // @[OneHot.scala:64:31]
wire [2:0] a_mask_sizeOH_shiftAmount = _a_mask_sizeOH_shiftAmount_T[2:0]; // @[OneHot.scala:64:{31,49}]
wire [7:0] _a_mask_sizeOH_T_1 = 8'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [4:0] _a_mask_sizeOH_T_2 = _a_mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] a_mask_sizeOH = {_a_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27]
wire _GEN_11 = request_input_bits_size > 3'h4; // @[Misc.scala:206:21]
wire a_mask_sub_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21]
assign a_mask_sub_sub_sub_sub_sub_0_1 = _GEN_11; // @[Misc.scala:206:21]
wire a_mask_sub_sub_sub_sub_sub_0_1_1; // @[Misc.scala:206:21]
assign a_mask_sub_sub_sub_sub_sub_0_1_1 = _GEN_11; // @[Misc.scala:206:21]
wire a_mask_sub_sub_sub_sub_size = a_mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_sub_bit = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[4]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire a_mask_sub_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_sub_acc_T = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _a_mask_sub_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_sub_size & a_mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire a_mask_sub_sub_sub_size = a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_bit = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_bit_1 = _tlb_io_resp_paddr[3]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_sub_nbit = ~a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_0_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_0_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_1_2 = a_mask_sub_sub_sub_sub_0_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_1 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_1_1 = a_mask_sub_sub_sub_sub_0_1 | _a_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_2_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_2_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_3_2 = a_mask_sub_sub_sub_sub_1_2 & a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_size & a_mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_3_1 = a_mask_sub_sub_sub_sub_1_1 | _a_mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_size = a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_bit = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_bit_1 = _tlb_io_resp_paddr[2]; // @[Misc.scala:210:26]
wire a_mask_sub_sub_nbit = ~a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_0_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T = a_mask_sub_sub_size & a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_0_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_1_2 = a_mask_sub_sub_sub_0_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_1 = a_mask_sub_sub_size & a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_1_1 = a_mask_sub_sub_sub_0_1 | _a_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_2_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_2 = a_mask_sub_sub_size & a_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_2_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_3_2 = a_mask_sub_sub_sub_1_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_3 = a_mask_sub_sub_size & a_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_3_1 = a_mask_sub_sub_sub_1_1 | _a_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_4_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_4 = a_mask_sub_sub_size & a_mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_4_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_5_2 = a_mask_sub_sub_sub_2_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_5 = a_mask_sub_sub_size & a_mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_5_1 = a_mask_sub_sub_sub_2_1 | _a_mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_6_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_6 = a_mask_sub_sub_size & a_mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_6_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_7_2 = a_mask_sub_sub_sub_3_2 & a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_7 = a_mask_sub_sub_size & a_mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_7_1 = a_mask_sub_sub_sub_3_1 | _a_mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_size = a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_bit = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26]
wire a_mask_sub_bit_1 = _tlb_io_resp_paddr[1]; // @[Misc.scala:210:26]
wire a_mask_sub_nbit = ~a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_0_2 = a_mask_sub_sub_0_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T = a_mask_sub_size & a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_0_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_1_2 = a_mask_sub_sub_0_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_1 = a_mask_sub_size & a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_1_1 = a_mask_sub_sub_0_1 | _a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_2_2 = a_mask_sub_sub_1_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_2 = a_mask_sub_size & a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_2_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_3_2 = a_mask_sub_sub_1_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_3 = a_mask_sub_size & a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_3_1 = a_mask_sub_sub_1_1 | _a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_4_2 = a_mask_sub_sub_2_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_4 = a_mask_sub_size & a_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_4_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_5_2 = a_mask_sub_sub_2_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_5 = a_mask_sub_size & a_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_5_1 = a_mask_sub_sub_2_1 | _a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_6_2 = a_mask_sub_sub_3_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_6 = a_mask_sub_size & a_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_6_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_7_2 = a_mask_sub_sub_3_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_7 = a_mask_sub_size & a_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_7_1 = a_mask_sub_sub_3_1 | _a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_8_2 = a_mask_sub_sub_4_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_8 = a_mask_sub_size & a_mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_8_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_9_2 = a_mask_sub_sub_4_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_9 = a_mask_sub_size & a_mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_9_1 = a_mask_sub_sub_4_1 | _a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_10_2 = a_mask_sub_sub_5_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_10 = a_mask_sub_size & a_mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_10_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_11_2 = a_mask_sub_sub_5_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_11 = a_mask_sub_size & a_mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_11_1 = a_mask_sub_sub_5_1 | _a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_12_2 = a_mask_sub_sub_6_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_12 = a_mask_sub_size & a_mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_12_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_13_2 = a_mask_sub_sub_6_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_13 = a_mask_sub_size & a_mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_13_1 = a_mask_sub_sub_6_1 | _a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_14_2 = a_mask_sub_sub_7_2 & a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_14 = a_mask_sub_size & a_mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_14_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_15_2 = a_mask_sub_sub_7_2 & a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_15 = a_mask_sub_size & a_mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_15_1 = a_mask_sub_sub_7_1 | _a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire a_mask_size = a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire a_mask_bit = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26]
wire a_mask_bit_1 = _tlb_io_resp_paddr[0]; // @[Misc.scala:210:26]
wire a_mask_nbit = ~a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire a_mask_eq = a_mask_sub_0_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T = a_mask_size & a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc = a_mask_sub_0_1 | _a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_1 = a_mask_sub_0_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_1 = a_mask_size & a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_1 = a_mask_sub_0_1 | _a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_2 = a_mask_sub_1_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_2 = a_mask_size & a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_2 = a_mask_sub_1_1 | _a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_3 = a_mask_sub_1_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_3 = a_mask_size & a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_3 = a_mask_sub_1_1 | _a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_4 = a_mask_sub_2_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_4 = a_mask_size & a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_4 = a_mask_sub_2_1 | _a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_5 = a_mask_sub_2_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_5 = a_mask_size & a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_5 = a_mask_sub_2_1 | _a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_6 = a_mask_sub_3_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_6 = a_mask_size & a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_6 = a_mask_sub_3_1 | _a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_7 = a_mask_sub_3_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_7 = a_mask_size & a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_7 = a_mask_sub_3_1 | _a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_8 = a_mask_sub_4_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_8 = a_mask_size & a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_8 = a_mask_sub_4_1 | _a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_9 = a_mask_sub_4_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_9 = a_mask_size & a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_9 = a_mask_sub_4_1 | _a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_10 = a_mask_sub_5_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_10 = a_mask_size & a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_10 = a_mask_sub_5_1 | _a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_11 = a_mask_sub_5_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_11 = a_mask_size & a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_11 = a_mask_sub_5_1 | _a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_12 = a_mask_sub_6_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_12 = a_mask_size & a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_12 = a_mask_sub_6_1 | _a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_13 = a_mask_sub_6_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_13 = a_mask_size & a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_13 = a_mask_sub_6_1 | _a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_14 = a_mask_sub_7_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_14 = a_mask_size & a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_14 = a_mask_sub_7_1 | _a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_15 = a_mask_sub_7_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_15 = a_mask_size & a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_15 = a_mask_sub_7_1 | _a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_16 = a_mask_sub_8_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_16 = a_mask_size & a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_16 = a_mask_sub_8_1 | _a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_17 = a_mask_sub_8_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_17 = a_mask_size & a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_17 = a_mask_sub_8_1 | _a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_18 = a_mask_sub_9_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_18 = a_mask_size & a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_18 = a_mask_sub_9_1 | _a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_19 = a_mask_sub_9_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_19 = a_mask_size & a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_19 = a_mask_sub_9_1 | _a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_20 = a_mask_sub_10_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_20 = a_mask_size & a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_20 = a_mask_sub_10_1 | _a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_21 = a_mask_sub_10_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_21 = a_mask_size & a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_21 = a_mask_sub_10_1 | _a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_22 = a_mask_sub_11_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_22 = a_mask_size & a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_22 = a_mask_sub_11_1 | _a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_23 = a_mask_sub_11_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_23 = a_mask_size & a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_23 = a_mask_sub_11_1 | _a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_24 = a_mask_sub_12_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_24 = a_mask_size & a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_24 = a_mask_sub_12_1 | _a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_25 = a_mask_sub_12_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_25 = a_mask_size & a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_25 = a_mask_sub_12_1 | _a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_26 = a_mask_sub_13_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_26 = a_mask_size & a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_26 = a_mask_sub_13_1 | _a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_27 = a_mask_sub_13_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_27 = a_mask_size & a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_27 = a_mask_sub_13_1 | _a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_28 = a_mask_sub_14_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_28 = a_mask_size & a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_28 = a_mask_sub_14_1 | _a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_29 = a_mask_sub_14_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_29 = a_mask_size & a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_29 = a_mask_sub_14_1 | _a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_30 = a_mask_sub_15_2 & a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_30 = a_mask_size & a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_30 = a_mask_sub_15_1 | _a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_31 = a_mask_sub_15_2 & a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_31 = a_mask_size & a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_31 = a_mask_sub_15_1 | _a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] a_mask_lo_lo_lo_lo = {a_mask_acc_1, a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_lo_hi = {a_mask_acc_3, a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_lo = {a_mask_lo_lo_lo_hi, a_mask_lo_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_lo_hi_lo = {a_mask_acc_5, a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_hi_hi = {a_mask_acc_7, a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_hi = {a_mask_lo_lo_hi_hi, a_mask_lo_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_lo = {a_mask_lo_lo_hi, a_mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_lo_lo = {a_mask_acc_9, a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_lo_hi = {a_mask_acc_11, a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_lo = {a_mask_lo_hi_lo_hi, a_mask_lo_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_hi_lo = {a_mask_acc_13, a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_hi_hi = {a_mask_acc_15, a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_hi = {a_mask_lo_hi_hi_hi, a_mask_lo_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_hi = {a_mask_lo_hi_hi, a_mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] a_mask_lo = {a_mask_lo_hi, a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_lo_lo = {a_mask_acc_17, a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_lo_hi = {a_mask_acc_19, a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_lo = {a_mask_hi_lo_lo_hi, a_mask_hi_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_hi_lo = {a_mask_acc_21, a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_hi_hi = {a_mask_acc_23, a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_hi = {a_mask_hi_lo_hi_hi, a_mask_hi_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_lo = {a_mask_hi_lo_hi, a_mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_lo_lo = {a_mask_acc_25, a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_lo_hi = {a_mask_acc_27, a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_lo = {a_mask_hi_hi_lo_hi, a_mask_hi_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_hi_lo = {a_mask_acc_29, a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_hi_hi = {a_mask_acc_31, a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_hi = {a_mask_hi_hi_hi_hi, a_mask_hi_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_hi = {a_mask_hi_hi_hi, a_mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] a_mask_hi = {a_mask_hi_hi, a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _a_mask_T = {a_mask_hi, a_mask_lo}; // @[Misc.scala:222:10]
assign bundle_mask = _a_mask_T; // @[Misc.scala:222:10]
wire [510:0] _T_31 = {255'h0, request_input_bits_data} << {503'h0, request_input_bits_addr[4:0], 3'h0}; // @[L2MemHelperLatencyInjection.scala:44:27, :172:{58,86}]
wire [32:0] _legal_T_68 = {1'h0, _legal_T_67}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_69 = _legal_T_68 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_70 = _legal_T_69; // @[Parameters.scala:137:46]
wire _legal_T_71 = _legal_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_72 = _legal_T_71; // @[Parameters.scala:684:54]
wire _legal_T_132 = _legal_T_72; // @[Parameters.scala:684:54, :686:26]
wire _legal_T_75 = _legal_T_74; // @[Parameters.scala:92:{33,38}]
wire _legal_T_76 = _legal_T_75; // @[Parameters.scala:684:29]
wire [31:0] _legal_T_77; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_78 = {1'h0, _legal_T_77}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_79 = _legal_T_78 & 33'h9A112000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_80 = _legal_T_79; // @[Parameters.scala:137:46]
wire _legal_T_81 = _legal_T_80 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _legal_T_82 = {_tlb_io_resp_paddr[31:21], _tlb_io_resp_paddr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_83 = {1'h0, _legal_T_82}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_84 = _legal_T_83 & 33'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_85 = _legal_T_84; // @[Parameters.scala:137:46]
wire _legal_T_86 = _legal_T_85 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_88 = {1'h0, _legal_T_87}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_89 = _legal_T_88 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_90 = _legal_T_89; // @[Parameters.scala:137:46]
wire _legal_T_91 = _legal_T_90 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _legal_T_92 = {_tlb_io_resp_paddr[31:26], _tlb_io_resp_paddr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [32:0] _legal_T_93 = {1'h0, _legal_T_92}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_94 = _legal_T_93 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_95 = _legal_T_94; // @[Parameters.scala:137:46]
wire _legal_T_96 = _legal_T_95 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_98 = {1'h0, _legal_T_97}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_99 = _legal_T_98 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_100 = _legal_T_99; // @[Parameters.scala:137:46]
wire _legal_T_101 = _legal_T_100 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_103 = {1'h0, _legal_T_102}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_104 = _legal_T_103 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_105 = _legal_T_104; // @[Parameters.scala:137:46]
wire _legal_T_106 = _legal_T_105 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_108 = {1'h0, _legal_T_107}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_109 = _legal_T_108 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_110 = _legal_T_109; // @[Parameters.scala:137:46]
wire _legal_T_111 = _legal_T_110 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [32:0] _legal_T_113 = {1'h0, _legal_T_112}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_114 = _legal_T_113 & 33'h90000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_115 = _legal_T_114; // @[Parameters.scala:137:46]
wire _legal_T_116 = _legal_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_117 = _legal_T_81 | _legal_T_86; // @[Parameters.scala:685:42]
wire _legal_T_118 = _legal_T_117 | _legal_T_91; // @[Parameters.scala:685:42]
wire _legal_T_119 = _legal_T_118 | _legal_T_96; // @[Parameters.scala:685:42]
wire _legal_T_120 = _legal_T_119 | _legal_T_101; // @[Parameters.scala:685:42]
wire _legal_T_121 = _legal_T_120 | _legal_T_106; // @[Parameters.scala:685:42]
wire _legal_T_122 = _legal_T_121 | _legal_T_111; // @[Parameters.scala:685:42]
wire _legal_T_123 = _legal_T_122 | _legal_T_116; // @[Parameters.scala:685:42]
wire _legal_T_124 = _legal_T_76 & _legal_T_123; // @[Parameters.scala:684:{29,54}, :685:42]
wire [32:0] _legal_T_127 = {1'h0, _legal_T_126}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _legal_T_128 = _legal_T_127 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _legal_T_129 = _legal_T_128; // @[Parameters.scala:137:46]
wire _legal_T_130 = _legal_T_129 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_T_133 = _legal_T_132 | _legal_T_124; // @[Parameters.scala:684:54, :686:26]
wire legal_1 = _legal_T_133; // @[Parameters.scala:686:26]
wire [31:0] _a_mask_T_1; // @[Misc.scala:222:10]
wire [4:0] bundle_1_source; // @[Edges.scala:480:17]
wire [31:0] bundle_1_address; // @[Edges.scala:480:17]
wire [31:0] bundle_1_mask; // @[Edges.scala:480:17]
wire [255:0] bundle_1_data; // @[Edges.scala:480:17]
wire [4:0] _a_mask_sizeOH_shiftAmount_T_1 = _a_mask_sizeOH_T_3; // @[OneHot.scala:64:31]
wire [2:0] a_mask_sizeOH_shiftAmount_1 = _a_mask_sizeOH_shiftAmount_T_1[2:0]; // @[OneHot.scala:64:{31,49}]
wire [7:0] _a_mask_sizeOH_T_4 = 8'h1 << a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [4:0] _a_mask_sizeOH_T_5 = _a_mask_sizeOH_T_4[4:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] a_mask_sizeOH_1 = {_a_mask_sizeOH_T_5[4:1], 1'h1}; // @[OneHot.scala:65:27]
wire a_mask_sub_sub_sub_sub_size_1 = a_mask_sizeOH_1[4]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire a_mask_sub_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_sub_acc_T_2 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _a_mask_sub_sub_sub_sub_acc_T_3 = a_mask_sub_sub_sub_sub_size_1 & a_mask_sub_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire a_mask_sub_sub_sub_size_1 = a_mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_sub_nbit_1 = ~a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_sub_0_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T_4 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_0_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_1_2_1 = a_mask_sub_sub_sub_sub_0_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_5 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_1_1_1 = a_mask_sub_sub_sub_sub_0_1_1 | _a_mask_sub_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_2_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_sub_acc_T_6 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_2_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_sub_3_2_1 = a_mask_sub_sub_sub_sub_1_2_1 & a_mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_sub_acc_T_7 = a_mask_sub_sub_sub_size_1 & a_mask_sub_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_sub_3_1_1 = a_mask_sub_sub_sub_sub_1_1_1 | _a_mask_sub_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_size_1 = a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_sub_nbit_1 = ~a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_sub_0_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_8 = a_mask_sub_sub_size_1 & a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_0_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_1_2_1 = a_mask_sub_sub_sub_0_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_9 = a_mask_sub_sub_size_1 & a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_1_1_1 = a_mask_sub_sub_sub_0_1_1 | _a_mask_sub_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_2_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_10 = a_mask_sub_sub_size_1 & a_mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_2_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_3_2_1 = a_mask_sub_sub_sub_1_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_11 = a_mask_sub_sub_size_1 & a_mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_3_1_1 = a_mask_sub_sub_sub_1_1_1 | _a_mask_sub_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_4_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_12 = a_mask_sub_sub_size_1 & a_mask_sub_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_4_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_5_2_1 = a_mask_sub_sub_sub_2_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_13 = a_mask_sub_sub_size_1 & a_mask_sub_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_5_1_1 = a_mask_sub_sub_sub_2_1_1 | _a_mask_sub_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_6_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_sub_acc_T_14 = a_mask_sub_sub_size_1 & a_mask_sub_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_6_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_sub_7_2_1 = a_mask_sub_sub_sub_3_2_1 & a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_sub_acc_T_15 = a_mask_sub_sub_size_1 & a_mask_sub_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_sub_7_1_1 = a_mask_sub_sub_sub_3_1_1 | _a_mask_sub_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_size_1 = a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire a_mask_sub_nbit_1 = ~a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_sub_0_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_16 = a_mask_sub_size_1 & a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_0_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_1_2_1 = a_mask_sub_sub_0_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_17 = a_mask_sub_size_1 & a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_1_1_1 = a_mask_sub_sub_0_1_1 | _a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_2_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_18 = a_mask_sub_size_1 & a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_2_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_3_2_1 = a_mask_sub_sub_1_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_19 = a_mask_sub_size_1 & a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_3_1_1 = a_mask_sub_sub_1_1_1 | _a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_4_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_20 = a_mask_sub_size_1 & a_mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_4_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_5_2_1 = a_mask_sub_sub_2_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_21 = a_mask_sub_size_1 & a_mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_5_1_1 = a_mask_sub_sub_2_1_1 | _a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_6_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_22 = a_mask_sub_size_1 & a_mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_6_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_7_2_1 = a_mask_sub_sub_3_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_23 = a_mask_sub_size_1 & a_mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_7_1_1 = a_mask_sub_sub_3_1_1 | _a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_8_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_24 = a_mask_sub_size_1 & a_mask_sub_8_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_8_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_9_2_1 = a_mask_sub_sub_4_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_25 = a_mask_sub_size_1 & a_mask_sub_9_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_9_1_1 = a_mask_sub_sub_4_1_1 | _a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_10_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_26 = a_mask_sub_size_1 & a_mask_sub_10_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_10_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_11_2_1 = a_mask_sub_sub_5_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_27 = a_mask_sub_size_1 & a_mask_sub_11_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_11_1_1 = a_mask_sub_sub_5_1_1 | _a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_12_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_28 = a_mask_sub_size_1 & a_mask_sub_12_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_12_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_13_2_1 = a_mask_sub_sub_6_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_29 = a_mask_sub_size_1 & a_mask_sub_13_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_13_1_1 = a_mask_sub_sub_6_1_1 | _a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_14_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_sub_acc_T_30 = a_mask_sub_size_1 & a_mask_sub_14_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_14_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire a_mask_sub_15_2_1 = a_mask_sub_sub_7_2_1 & a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_sub_acc_T_31 = a_mask_sub_size_1 & a_mask_sub_15_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_sub_15_1_1 = a_mask_sub_sub_7_1_1 | _a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire a_mask_size_1 = a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire a_mask_eq_32 = a_mask_sub_0_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_32 = a_mask_size_1 & a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_32 = a_mask_sub_0_1_1 | _a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_33 = a_mask_sub_0_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_33 = a_mask_size_1 & a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_33 = a_mask_sub_0_1_1 | _a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_34 = a_mask_sub_1_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_34 = a_mask_size_1 & a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_34 = a_mask_sub_1_1_1 | _a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_35 = a_mask_sub_1_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_35 = a_mask_size_1 & a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_35 = a_mask_sub_1_1_1 | _a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_36 = a_mask_sub_2_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_36 = a_mask_size_1 & a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_36 = a_mask_sub_2_1_1 | _a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_37 = a_mask_sub_2_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_37 = a_mask_size_1 & a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_37 = a_mask_sub_2_1_1 | _a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_38 = a_mask_sub_3_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_38 = a_mask_size_1 & a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_38 = a_mask_sub_3_1_1 | _a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_39 = a_mask_sub_3_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_39 = a_mask_size_1 & a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_39 = a_mask_sub_3_1_1 | _a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_40 = a_mask_sub_4_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_40 = a_mask_size_1 & a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_40 = a_mask_sub_4_1_1 | _a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_41 = a_mask_sub_4_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_41 = a_mask_size_1 & a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_41 = a_mask_sub_4_1_1 | _a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_42 = a_mask_sub_5_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_42 = a_mask_size_1 & a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_42 = a_mask_sub_5_1_1 | _a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_43 = a_mask_sub_5_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_43 = a_mask_size_1 & a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_43 = a_mask_sub_5_1_1 | _a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_44 = a_mask_sub_6_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_44 = a_mask_size_1 & a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_44 = a_mask_sub_6_1_1 | _a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_45 = a_mask_sub_6_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_45 = a_mask_size_1 & a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_45 = a_mask_sub_6_1_1 | _a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_46 = a_mask_sub_7_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_46 = a_mask_size_1 & a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_46 = a_mask_sub_7_1_1 | _a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_47 = a_mask_sub_7_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_47 = a_mask_size_1 & a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_47 = a_mask_sub_7_1_1 | _a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_48 = a_mask_sub_8_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_48 = a_mask_size_1 & a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_48 = a_mask_sub_8_1_1 | _a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_49 = a_mask_sub_8_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_49 = a_mask_size_1 & a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_49 = a_mask_sub_8_1_1 | _a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_50 = a_mask_sub_9_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_50 = a_mask_size_1 & a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_50 = a_mask_sub_9_1_1 | _a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_51 = a_mask_sub_9_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_51 = a_mask_size_1 & a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_51 = a_mask_sub_9_1_1 | _a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_52 = a_mask_sub_10_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_52 = a_mask_size_1 & a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_52 = a_mask_sub_10_1_1 | _a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_53 = a_mask_sub_10_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_53 = a_mask_size_1 & a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_53 = a_mask_sub_10_1_1 | _a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_54 = a_mask_sub_11_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_54 = a_mask_size_1 & a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_54 = a_mask_sub_11_1_1 | _a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_55 = a_mask_sub_11_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_55 = a_mask_size_1 & a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_55 = a_mask_sub_11_1_1 | _a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_56 = a_mask_sub_12_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_56 = a_mask_size_1 & a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_56 = a_mask_sub_12_1_1 | _a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_57 = a_mask_sub_12_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_57 = a_mask_size_1 & a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_57 = a_mask_sub_12_1_1 | _a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_58 = a_mask_sub_13_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_58 = a_mask_size_1 & a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_58 = a_mask_sub_13_1_1 | _a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_59 = a_mask_sub_13_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_59 = a_mask_size_1 & a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_59 = a_mask_sub_13_1_1 | _a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_60 = a_mask_sub_14_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_60 = a_mask_size_1 & a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_60 = a_mask_sub_14_1_1 | _a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_61 = a_mask_sub_14_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_61 = a_mask_size_1 & a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_61 = a_mask_sub_14_1_1 | _a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_62 = a_mask_sub_15_2_1 & a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _a_mask_acc_T_62 = a_mask_size_1 & a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_62 = a_mask_sub_15_1_1 | _a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire a_mask_eq_63 = a_mask_sub_15_2_1 & a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _a_mask_acc_T_63 = a_mask_size_1 & a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire a_mask_acc_63 = a_mask_sub_15_1_1 | _a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] a_mask_lo_lo_lo_lo_1 = {a_mask_acc_33, a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_lo_hi_1 = {a_mask_acc_35, a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_lo_1 = {a_mask_lo_lo_lo_hi_1, a_mask_lo_lo_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_lo_hi_lo_1 = {a_mask_acc_37, a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_lo_hi_hi_1 = {a_mask_acc_39, a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_lo_hi_1 = {a_mask_lo_lo_hi_hi_1, a_mask_lo_lo_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_lo_1 = {a_mask_lo_lo_hi_1, a_mask_lo_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_lo_lo_1 = {a_mask_acc_41, a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_lo_hi_1 = {a_mask_acc_43, a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_lo_1 = {a_mask_lo_hi_lo_hi_1, a_mask_lo_hi_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_lo_hi_hi_lo_1 = {a_mask_acc_45, a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_lo_hi_hi_hi_1 = {a_mask_acc_47, a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_lo_hi_hi_1 = {a_mask_lo_hi_hi_hi_1, a_mask_lo_hi_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_lo_hi_1 = {a_mask_lo_hi_hi_1, a_mask_lo_hi_lo_1}; // @[Misc.scala:222:10]
wire [15:0] a_mask_lo_1 = {a_mask_lo_hi_1, a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_lo_lo_1 = {a_mask_acc_49, a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_lo_hi_1 = {a_mask_acc_51, a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_lo_1 = {a_mask_hi_lo_lo_hi_1, a_mask_hi_lo_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_lo_hi_lo_1 = {a_mask_acc_53, a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_lo_hi_hi_1 = {a_mask_acc_55, a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_lo_hi_1 = {a_mask_hi_lo_hi_hi_1, a_mask_hi_lo_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_lo_1 = {a_mask_hi_lo_hi_1, a_mask_hi_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_lo_lo_1 = {a_mask_acc_57, a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_lo_hi_1 = {a_mask_acc_59, a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_lo_1 = {a_mask_hi_hi_lo_hi_1, a_mask_hi_hi_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] a_mask_hi_hi_hi_lo_1 = {a_mask_acc_61, a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] a_mask_hi_hi_hi_hi_1 = {a_mask_acc_63, a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] a_mask_hi_hi_hi_1 = {a_mask_hi_hi_hi_hi_1, a_mask_hi_hi_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] a_mask_hi_hi_1 = {a_mask_hi_hi_hi_1, a_mask_hi_hi_lo_1}; // @[Misc.scala:222:10]
wire [15:0] a_mask_hi_1 = {a_mask_hi_hi_1, a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _a_mask_T_1 = {a_mask_hi_1, a_mask_lo_1}; // @[Misc.scala:222:10]
assign bundle_1_mask = _a_mask_T_1; // @[Misc.scala:222:10]
assign bundle_1_data = _T_31[255:0]; // @[Edges.scala:480:17, :489:15]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
wire _current_request_tag_has_response_space_T = _tags_for_issue_Q_io_deq_bits == 5'h0; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_1 = _Queue4_L2RespInternal_io_enq_ready & _current_request_tag_has_response_space_T; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_2 = _tags_for_issue_Q_io_deq_bits == 5'h1; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _current_request_tag_has_response_space_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_4 = _tags_for_issue_Q_io_deq_bits == 5'h2; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _current_request_tag_has_response_space_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_6 = _tags_for_issue_Q_io_deq_bits == 5'h3; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _current_request_tag_has_response_space_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_8 = _tags_for_issue_Q_io_deq_bits == 5'h4; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _current_request_tag_has_response_space_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_10 = _tags_for_issue_Q_io_deq_bits == 5'h5; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _current_request_tag_has_response_space_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_12 = _tags_for_issue_Q_io_deq_bits == 5'h6; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _current_request_tag_has_response_space_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_14 = _tags_for_issue_Q_io_deq_bits == 5'h7; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _current_request_tag_has_response_space_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_16 = _tags_for_issue_Q_io_deq_bits == 5'h8; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _current_request_tag_has_response_space_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_18 = _tags_for_issue_Q_io_deq_bits == 5'h9; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _current_request_tag_has_response_space_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_20 = _tags_for_issue_Q_io_deq_bits == 5'hA; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _current_request_tag_has_response_space_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_22 = _tags_for_issue_Q_io_deq_bits == 5'hB; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _current_request_tag_has_response_space_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_24 = _tags_for_issue_Q_io_deq_bits == 5'hC; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _current_request_tag_has_response_space_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_26 = _tags_for_issue_Q_io_deq_bits == 5'hD; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _current_request_tag_has_response_space_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_28 = _tags_for_issue_Q_io_deq_bits == 5'hE; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _current_request_tag_has_response_space_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_30 = _tags_for_issue_Q_io_deq_bits == 5'hF; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _current_request_tag_has_response_space_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_32 = _tags_for_issue_Q_io_deq_bits == 5'h10; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _current_request_tag_has_response_space_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_34 = _tags_for_issue_Q_io_deq_bits == 5'h11; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _current_request_tag_has_response_space_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_36 = _tags_for_issue_Q_io_deq_bits == 5'h12; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _current_request_tag_has_response_space_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_38 = _tags_for_issue_Q_io_deq_bits == 5'h13; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _current_request_tag_has_response_space_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_40 = _tags_for_issue_Q_io_deq_bits == 5'h14; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _current_request_tag_has_response_space_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_42 = _tags_for_issue_Q_io_deq_bits == 5'h15; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _current_request_tag_has_response_space_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_44 = _tags_for_issue_Q_io_deq_bits == 5'h16; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _current_request_tag_has_response_space_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_46 = _tags_for_issue_Q_io_deq_bits == 5'h17; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _current_request_tag_has_response_space_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_48 = _tags_for_issue_Q_io_deq_bits == 5'h18; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _current_request_tag_has_response_space_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_50 = _tags_for_issue_Q_io_deq_bits == 5'h19; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _current_request_tag_has_response_space_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_52 = _tags_for_issue_Q_io_deq_bits == 5'h1A; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _current_request_tag_has_response_space_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_54 = _tags_for_issue_Q_io_deq_bits == 5'h1B; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _current_request_tag_has_response_space_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_56 = _tags_for_issue_Q_io_deq_bits == 5'h1C; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _current_request_tag_has_response_space_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_58 = _tags_for_issue_Q_io_deq_bits == 5'h1D; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _current_request_tag_has_response_space_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_60 = _tags_for_issue_Q_io_deq_bits == 5'h1E; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _current_request_tag_has_response_space_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_62 = &_tags_for_issue_Q_io_deq_bits; // @[L2MemHelperLatencyInjection.scala:94:32, :186:27]
wire _current_request_tag_has_response_space_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _current_request_tag_has_response_space_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :186:{17,27}]
wire _current_request_tag_has_response_space_T_64 = _current_request_tag_has_response_space_T_1 | _current_request_tag_has_response_space_T_3; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_65 = _current_request_tag_has_response_space_T_64 | _current_request_tag_has_response_space_T_5; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_66 = _current_request_tag_has_response_space_T_65 | _current_request_tag_has_response_space_T_7; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_67 = _current_request_tag_has_response_space_T_66 | _current_request_tag_has_response_space_T_9; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_68 = _current_request_tag_has_response_space_T_67 | _current_request_tag_has_response_space_T_11; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_69 = _current_request_tag_has_response_space_T_68 | _current_request_tag_has_response_space_T_13; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_70 = _current_request_tag_has_response_space_T_69 | _current_request_tag_has_response_space_T_15; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_71 = _current_request_tag_has_response_space_T_70 | _current_request_tag_has_response_space_T_17; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_72 = _current_request_tag_has_response_space_T_71 | _current_request_tag_has_response_space_T_19; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_73 = _current_request_tag_has_response_space_T_72 | _current_request_tag_has_response_space_T_21; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_74 = _current_request_tag_has_response_space_T_73 | _current_request_tag_has_response_space_T_23; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_75 = _current_request_tag_has_response_space_T_74 | _current_request_tag_has_response_space_T_25; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_76 = _current_request_tag_has_response_space_T_75 | _current_request_tag_has_response_space_T_27; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_77 = _current_request_tag_has_response_space_T_76 | _current_request_tag_has_response_space_T_29; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_78 = _current_request_tag_has_response_space_T_77 | _current_request_tag_has_response_space_T_31; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_79 = _current_request_tag_has_response_space_T_78 | _current_request_tag_has_response_space_T_33; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_80 = _current_request_tag_has_response_space_T_79 | _current_request_tag_has_response_space_T_35; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_81 = _current_request_tag_has_response_space_T_80 | _current_request_tag_has_response_space_T_37; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_82 = _current_request_tag_has_response_space_T_81 | _current_request_tag_has_response_space_T_39; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_83 = _current_request_tag_has_response_space_T_82 | _current_request_tag_has_response_space_T_41; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_84 = _current_request_tag_has_response_space_T_83 | _current_request_tag_has_response_space_T_43; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_85 = _current_request_tag_has_response_space_T_84 | _current_request_tag_has_response_space_T_45; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_86 = _current_request_tag_has_response_space_T_85 | _current_request_tag_has_response_space_T_47; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_87 = _current_request_tag_has_response_space_T_86 | _current_request_tag_has_response_space_T_49; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_88 = _current_request_tag_has_response_space_T_87 | _current_request_tag_has_response_space_T_51; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_89 = _current_request_tag_has_response_space_T_88 | _current_request_tag_has_response_space_T_53; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_90 = _current_request_tag_has_response_space_T_89 | _current_request_tag_has_response_space_T_55; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_91 = _current_request_tag_has_response_space_T_90 | _current_request_tag_has_response_space_T_57; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_92 = _current_request_tag_has_response_space_T_91 | _current_request_tag_has_response_space_T_59; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire _current_request_tag_has_response_space_T_93 = _current_request_tag_has_response_space_T_92 | _current_request_tag_has_response_space_T_61; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire current_request_tag_has_response_space = _current_request_tag_has_response_space_T_93 | _current_request_tag_has_response_space_T_63; // @[L2MemHelperLatencyInjection.scala:186:17, :187:15]
wire [63:0] _outstanding_req_addr_io_enq_bits_addrindex_T = {59'h0, request_input_bits_addr[4:0]}; // @[L2MemHelperLatencyInjection.scala:44:27, :200:73]
wire _request_latency_injection_q_io_enq_valid_T = request_input_valid & tlb_ready; // @[Misc.scala:26:53]
wire _request_latency_injection_q_io_enq_valid_T_1 = _request_latency_injection_q_io_enq_valid_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53]
wire _request_latency_injection_q_io_enq_valid_T_2 = _request_latency_injection_q_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _request_latency_injection_q_io_enq_valid_T_3 = _request_latency_injection_q_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53]
wire _request_latency_injection_q_io_enq_valid_T_4 = _request_latency_injection_q_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53]
wire _request_input_ready_T = _request_latency_injection_q_io_enq_ready & tlb_ready; // @[Misc.scala:26:53]
wire _request_input_ready_T_1 = _request_input_ready_T & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53]
wire _request_input_ready_T_2 = _request_input_ready_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _request_input_ready_T_3 = _request_input_ready_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53]
assign _request_input_ready_T_4 = _request_input_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53]
assign request_input_ready = _request_input_ready_T_4; // @[Misc.scala:26:53]
wire _T_45 = request_input_valid & _request_latency_injection_q_io_enq_ready; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T; // @[Misc.scala:26:53]
assign _outstanding_req_addr_io_enq_valid_T = _T_45; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T; // @[Misc.scala:26:53]
assign _tags_for_issue_Q_io_deq_ready_T = _T_45; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_1 = _outstanding_req_addr_io_enq_valid_T & tlb_ready; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_2 = _outstanding_req_addr_io_enq_valid_T_1 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_3 = _outstanding_req_addr_io_enq_valid_T_2 & _tags_for_issue_Q_io_deq_valid; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_enq_valid_T_4 = _outstanding_req_addr_io_enq_valid_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_1 = _tags_for_issue_Q_io_deq_ready_T & tlb_ready; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_2 = _tags_for_issue_Q_io_deq_ready_T_1 & _outstanding_req_addr_io_enq_ready; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_3 = _tags_for_issue_Q_io_deq_ready_T_2 & free_outstanding_op_slots; // @[Misc.scala:26:53]
wire _tags_for_issue_Q_io_deq_ready_T_4 = _tags_for_issue_Q_io_deq_ready_T_3 & current_request_tag_has_response_space; // @[Misc.scala:26:53]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:26:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:26:33, :27:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:27:38]
wire _printf_T_1 = ~_printf_T; // @[annotations.scala:102:49]
wire _printf_T_3 = ~_printf_T_2; // @[annotations.scala:102:49]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38]
wire _selectQready_T = _response_latency_injection_q_io_deq_bits_source == 5'h0; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_1 = _Queue4_L2RespInternal_io_enq_ready & _selectQready_T; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_2 = _response_latency_injection_q_io_deq_bits_source == 5'h1; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_3 = _Queue4_L2RespInternal_1_io_enq_ready & _selectQready_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_4 = _response_latency_injection_q_io_deq_bits_source == 5'h2; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_5 = _Queue4_L2RespInternal_2_io_enq_ready & _selectQready_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_6 = _response_latency_injection_q_io_deq_bits_source == 5'h3; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_7 = _Queue4_L2RespInternal_3_io_enq_ready & _selectQready_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_8 = _response_latency_injection_q_io_deq_bits_source == 5'h4; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_9 = _Queue4_L2RespInternal_4_io_enq_ready & _selectQready_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_10 = _response_latency_injection_q_io_deq_bits_source == 5'h5; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_11 = _Queue4_L2RespInternal_5_io_enq_ready & _selectQready_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_12 = _response_latency_injection_q_io_deq_bits_source == 5'h6; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_13 = _Queue4_L2RespInternal_6_io_enq_ready & _selectQready_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_14 = _response_latency_injection_q_io_deq_bits_source == 5'h7; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_15 = _Queue4_L2RespInternal_7_io_enq_ready & _selectQready_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_16 = _response_latency_injection_q_io_deq_bits_source == 5'h8; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_17 = _Queue4_L2RespInternal_8_io_enq_ready & _selectQready_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_18 = _response_latency_injection_q_io_deq_bits_source == 5'h9; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_19 = _Queue4_L2RespInternal_9_io_enq_ready & _selectQready_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_20 = _response_latency_injection_q_io_deq_bits_source == 5'hA; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_21 = _Queue4_L2RespInternal_10_io_enq_ready & _selectQready_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_22 = _response_latency_injection_q_io_deq_bits_source == 5'hB; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_23 = _Queue4_L2RespInternal_11_io_enq_ready & _selectQready_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_24 = _response_latency_injection_q_io_deq_bits_source == 5'hC; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_25 = _Queue4_L2RespInternal_12_io_enq_ready & _selectQready_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_26 = _response_latency_injection_q_io_deq_bits_source == 5'hD; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_27 = _Queue4_L2RespInternal_13_io_enq_ready & _selectQready_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_28 = _response_latency_injection_q_io_deq_bits_source == 5'hE; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_29 = _Queue4_L2RespInternal_14_io_enq_ready & _selectQready_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_30 = _response_latency_injection_q_io_deq_bits_source == 5'hF; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_31 = _Queue4_L2RespInternal_15_io_enq_ready & _selectQready_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_32 = _response_latency_injection_q_io_deq_bits_source == 5'h10; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_33 = _Queue4_L2RespInternal_16_io_enq_ready & _selectQready_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_34 = _response_latency_injection_q_io_deq_bits_source == 5'h11; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_35 = _Queue4_L2RespInternal_17_io_enq_ready & _selectQready_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_36 = _response_latency_injection_q_io_deq_bits_source == 5'h12; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_37 = _Queue4_L2RespInternal_18_io_enq_ready & _selectQready_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_38 = _response_latency_injection_q_io_deq_bits_source == 5'h13; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_39 = _Queue4_L2RespInternal_19_io_enq_ready & _selectQready_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_40 = _response_latency_injection_q_io_deq_bits_source == 5'h14; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_41 = _Queue4_L2RespInternal_20_io_enq_ready & _selectQready_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_42 = _response_latency_injection_q_io_deq_bits_source == 5'h15; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_43 = _Queue4_L2RespInternal_21_io_enq_ready & _selectQready_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_44 = _response_latency_injection_q_io_deq_bits_source == 5'h16; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_45 = _Queue4_L2RespInternal_22_io_enq_ready & _selectQready_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_46 = _response_latency_injection_q_io_deq_bits_source == 5'h17; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_47 = _Queue4_L2RespInternal_23_io_enq_ready & _selectQready_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_48 = _response_latency_injection_q_io_deq_bits_source == 5'h18; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_49 = _Queue4_L2RespInternal_24_io_enq_ready & _selectQready_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_50 = _response_latency_injection_q_io_deq_bits_source == 5'h19; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_51 = _Queue4_L2RespInternal_25_io_enq_ready & _selectQready_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_52 = _response_latency_injection_q_io_deq_bits_source == 5'h1A; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_53 = _Queue4_L2RespInternal_26_io_enq_ready & _selectQready_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_54 = _response_latency_injection_q_io_deq_bits_source == 5'h1B; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_55 = _Queue4_L2RespInternal_27_io_enq_ready & _selectQready_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_56 = _response_latency_injection_q_io_deq_bits_source == 5'h1C; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_57 = _Queue4_L2RespInternal_28_io_enq_ready & _selectQready_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_58 = _response_latency_injection_q_io_deq_bits_source == 5'h1D; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_59 = _Queue4_L2RespInternal_29_io_enq_ready & _selectQready_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_60 = _response_latency_injection_q_io_deq_bits_source == 5'h1E; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_61 = _Queue4_L2RespInternal_30_io_enq_ready & _selectQready_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_62 = &_response_latency_injection_q_io_deq_bits_source; // @[L2MemHelperLatencyInjection.scala:245:44, :253:27]
wire _selectQready_T_63 = _Queue4_L2RespInternal_31_io_enq_ready & _selectQready_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :253:{17,27}]
wire _selectQready_T_64 = _selectQready_T_1 | _selectQready_T_3; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_65 = _selectQready_T_64 | _selectQready_T_5; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_66 = _selectQready_T_65 | _selectQready_T_7; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_67 = _selectQready_T_66 | _selectQready_T_9; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_68 = _selectQready_T_67 | _selectQready_T_11; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_69 = _selectQready_T_68 | _selectQready_T_13; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_70 = _selectQready_T_69 | _selectQready_T_15; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_71 = _selectQready_T_70 | _selectQready_T_17; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_72 = _selectQready_T_71 | _selectQready_T_19; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_73 = _selectQready_T_72 | _selectQready_T_21; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_74 = _selectQready_T_73 | _selectQready_T_23; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_75 = _selectQready_T_74 | _selectQready_T_25; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_76 = _selectQready_T_75 | _selectQready_T_27; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_77 = _selectQready_T_76 | _selectQready_T_29; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_78 = _selectQready_T_77 | _selectQready_T_31; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_79 = _selectQready_T_78 | _selectQready_T_33; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_80 = _selectQready_T_79 | _selectQready_T_35; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_81 = _selectQready_T_80 | _selectQready_T_37; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_82 = _selectQready_T_81 | _selectQready_T_39; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_83 = _selectQready_T_82 | _selectQready_T_41; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_84 = _selectQready_T_83 | _selectQready_T_43; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_85 = _selectQready_T_84 | _selectQready_T_45; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_86 = _selectQready_T_85 | _selectQready_T_47; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_87 = _selectQready_T_86 | _selectQready_T_49; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_88 = _selectQready_T_87 | _selectQready_T_51; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_89 = _selectQready_T_88 | _selectQready_T_53; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_90 = _selectQready_T_89 | _selectQready_T_55; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_91 = _selectQready_T_90 | _selectQready_T_57; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_92 = _selectQready_T_91 | _selectQready_T_59; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _selectQready_T_93 = _selectQready_T_92 | _selectQready_T_61; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire selectQready = _selectQready_T_93 | _selectQready_T_63; // @[L2MemHelperLatencyInjection.scala:253:17, :254:15]
wire _T_377 = selectQready & _response_latency_injection_q_io_deq_valid; // @[Misc.scala:26:53]
wire tags_for_issue_Q_io_enq_valid = _T_377 | _T_4; // @[Misc.scala:26:53]
wire [4:0] tags_for_issue_Q_io_enq_bits = _T_377 ? _response_latency_injection_q_io_deq_bits_source : tags_init_reg[4:0]; // @[Misc.scala:26:53]
reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38]
wire _response_latency_injection_q_io_deq_ready_T = selectQready & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53]
wire _T_476 = _response_latency_injection_q_io_deq_valid & _tags_for_issue_Q_io_enq_ready; // @[Misc.scala:26:53]
wire _T_480 = _outstanding_req_addr_io_deq_bits_tag == 5'h0; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T = _T_480; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q = _T_480; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_1 = _Queue4_L2RespInternal_io_deq_valid & _queueValid_T; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_483 = _outstanding_req_addr_io_deq_bits_tag == 5'h1; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_2 = _T_483; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_1; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_1 = _T_483; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_3 = _Queue4_L2RespInternal_1_io_deq_valid & _queueValid_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_486 = _outstanding_req_addr_io_deq_bits_tag == 5'h2; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_4 = _T_486; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_2; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_2 = _T_486; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_5 = _Queue4_L2RespInternal_2_io_deq_valid & _queueValid_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_489 = _outstanding_req_addr_io_deq_bits_tag == 5'h3; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_6 = _T_489; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_3; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_3 = _T_489; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_7 = _Queue4_L2RespInternal_3_io_deq_valid & _queueValid_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_492 = _outstanding_req_addr_io_deq_bits_tag == 5'h4; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_8 = _T_492; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_4; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_4 = _T_492; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_9 = _Queue4_L2RespInternal_4_io_deq_valid & _queueValid_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_495 = _outstanding_req_addr_io_deq_bits_tag == 5'h5; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_10 = _T_495; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_5; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_5 = _T_495; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_11 = _Queue4_L2RespInternal_5_io_deq_valid & _queueValid_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_498 = _outstanding_req_addr_io_deq_bits_tag == 5'h6; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_12 = _T_498; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_6; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_6 = _T_498; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_13 = _Queue4_L2RespInternal_6_io_deq_valid & _queueValid_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_501 = _outstanding_req_addr_io_deq_bits_tag == 5'h7; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_14 = _T_501; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_7; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_7 = _T_501; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_15 = _Queue4_L2RespInternal_7_io_deq_valid & _queueValid_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_504 = _outstanding_req_addr_io_deq_bits_tag == 5'h8; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_16 = _T_504; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_8; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_8 = _T_504; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_17 = _Queue4_L2RespInternal_8_io_deq_valid & _queueValid_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_507 = _outstanding_req_addr_io_deq_bits_tag == 5'h9; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_18 = _T_507; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_9; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_9 = _T_507; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_19 = _Queue4_L2RespInternal_9_io_deq_valid & _queueValid_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_510 = _outstanding_req_addr_io_deq_bits_tag == 5'hA; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_20 = _T_510; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_10; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_10 = _T_510; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_21 = _Queue4_L2RespInternal_10_io_deq_valid & _queueValid_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_513 = _outstanding_req_addr_io_deq_bits_tag == 5'hB; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_22 = _T_513; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_11; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_11 = _T_513; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_23 = _Queue4_L2RespInternal_11_io_deq_valid & _queueValid_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_516 = _outstanding_req_addr_io_deq_bits_tag == 5'hC; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_24 = _T_516; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_12; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_12 = _T_516; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_25 = _Queue4_L2RespInternal_12_io_deq_valid & _queueValid_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_519 = _outstanding_req_addr_io_deq_bits_tag == 5'hD; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_26 = _T_519; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_13; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_13 = _T_519; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_27 = _Queue4_L2RespInternal_13_io_deq_valid & _queueValid_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_522 = _outstanding_req_addr_io_deq_bits_tag == 5'hE; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_28 = _T_522; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_14; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_14 = _T_522; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_29 = _Queue4_L2RespInternal_14_io_deq_valid & _queueValid_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_525 = _outstanding_req_addr_io_deq_bits_tag == 5'hF; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_30 = _T_525; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_15; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_15 = _T_525; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_31 = _Queue4_L2RespInternal_15_io_deq_valid & _queueValid_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_528 = _outstanding_req_addr_io_deq_bits_tag == 5'h10; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_32 = _T_528; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_16; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_16 = _T_528; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_33 = _Queue4_L2RespInternal_16_io_deq_valid & _queueValid_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_531 = _outstanding_req_addr_io_deq_bits_tag == 5'h11; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_34 = _T_531; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_17; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_17 = _T_531; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_35 = _Queue4_L2RespInternal_17_io_deq_valid & _queueValid_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_534 = _outstanding_req_addr_io_deq_bits_tag == 5'h12; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_36 = _T_534; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_18; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_18 = _T_534; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_37 = _Queue4_L2RespInternal_18_io_deq_valid & _queueValid_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_537 = _outstanding_req_addr_io_deq_bits_tag == 5'h13; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_38 = _T_537; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_19; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_19 = _T_537; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_39 = _Queue4_L2RespInternal_19_io_deq_valid & _queueValid_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_540 = _outstanding_req_addr_io_deq_bits_tag == 5'h14; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_40 = _T_540; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_20; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_20 = _T_540; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_41 = _Queue4_L2RespInternal_20_io_deq_valid & _queueValid_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_543 = _outstanding_req_addr_io_deq_bits_tag == 5'h15; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_42 = _T_543; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_21; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_21 = _T_543; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_43 = _Queue4_L2RespInternal_21_io_deq_valid & _queueValid_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_546 = _outstanding_req_addr_io_deq_bits_tag == 5'h16; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_44 = _T_546; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_22; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_22 = _T_546; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_45 = _Queue4_L2RespInternal_22_io_deq_valid & _queueValid_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_549 = _outstanding_req_addr_io_deq_bits_tag == 5'h17; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_46 = _T_549; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_23; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_23 = _T_549; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_47 = _Queue4_L2RespInternal_23_io_deq_valid & _queueValid_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_552 = _outstanding_req_addr_io_deq_bits_tag == 5'h18; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_48 = _T_552; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_24; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_24 = _T_552; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_49 = _Queue4_L2RespInternal_24_io_deq_valid & _queueValid_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_555 = _outstanding_req_addr_io_deq_bits_tag == 5'h19; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_50 = _T_555; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_25; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_25 = _T_555; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_51 = _Queue4_L2RespInternal_25_io_deq_valid & _queueValid_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_558 = _outstanding_req_addr_io_deq_bits_tag == 5'h1A; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_52 = _T_558; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_26; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_26 = _T_558; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_53 = _Queue4_L2RespInternal_26_io_deq_valid & _queueValid_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_561 = _outstanding_req_addr_io_deq_bits_tag == 5'h1B; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_54 = _T_561; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_27; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_27 = _T_561; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_55 = _Queue4_L2RespInternal_27_io_deq_valid & _queueValid_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_564 = _outstanding_req_addr_io_deq_bits_tag == 5'h1C; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_56 = _T_564; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_28; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_28 = _T_564; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_57 = _Queue4_L2RespInternal_28_io_deq_valid & _queueValid_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_567 = _outstanding_req_addr_io_deq_bits_tag == 5'h1D; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_58 = _T_567; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_29; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_29 = _T_567; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_59 = _Queue4_L2RespInternal_29_io_deq_valid & _queueValid_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _T_570 = _outstanding_req_addr_io_deq_bits_tag == 5'h1E; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:287:27]
assign _queueValid_T_60 = _T_570; // @[L2MemHelperLatencyInjection.scala:287:27]
wire resultdata_is_current_q_30; // @[L2MemHelperLatencyInjection.scala:299:31]
assign resultdata_is_current_q_30 = _T_570; // @[L2MemHelperLatencyInjection.scala:287:27, :299:31]
wire _queueValid_T_61 = _Queue4_L2RespInternal_30_io_deq_valid & _queueValid_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _queueValid_T_62 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27]
wire _queueValid_T_63 = _Queue4_L2RespInternal_31_io_deq_valid & _queueValid_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :287:{17,27}]
wire _queueValid_T_64 = _queueValid_T_1 | _queueValid_T_3; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_65 = _queueValid_T_64 | _queueValid_T_5; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_66 = _queueValid_T_65 | _queueValid_T_7; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_67 = _queueValid_T_66 | _queueValid_T_9; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_68 = _queueValid_T_67 | _queueValid_T_11; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_69 = _queueValid_T_68 | _queueValid_T_13; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_70 = _queueValid_T_69 | _queueValid_T_15; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_71 = _queueValid_T_70 | _queueValid_T_17; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_72 = _queueValid_T_71 | _queueValid_T_19; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_73 = _queueValid_T_72 | _queueValid_T_21; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_74 = _queueValid_T_73 | _queueValid_T_23; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_75 = _queueValid_T_74 | _queueValid_T_25; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_76 = _queueValid_T_75 | _queueValid_T_27; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_77 = _queueValid_T_76 | _queueValid_T_29; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_78 = _queueValid_T_77 | _queueValid_T_31; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_79 = _queueValid_T_78 | _queueValid_T_33; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_80 = _queueValid_T_79 | _queueValid_T_35; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_81 = _queueValid_T_80 | _queueValid_T_37; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_82 = _queueValid_T_81 | _queueValid_T_39; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_83 = _queueValid_T_82 | _queueValid_T_41; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_84 = _queueValid_T_83 | _queueValid_T_43; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_85 = _queueValid_T_84 | _queueValid_T_45; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_86 = _queueValid_T_85 | _queueValid_T_47; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_87 = _queueValid_T_86 | _queueValid_T_49; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_88 = _queueValid_T_87 | _queueValid_T_51; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_89 = _queueValid_T_88 | _queueValid_T_53; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_90 = _queueValid_T_89 | _queueValid_T_55; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_91 = _queueValid_T_90 | _queueValid_T_57; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_92 = _queueValid_T_91 | _queueValid_T_59; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire _queueValid_T_93 = _queueValid_T_92 | _queueValid_T_61; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire queueValid = _queueValid_T_93 | _queueValid_T_63; // @[L2MemHelperLatencyInjection.scala:287:17, :288:15]
wire [255:0] resultdata_data; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [7:0] _GEN_12 = {_outstanding_req_addr_io_deq_bits_addrindex, 3'h0}; // @[L2MemHelperLatencyInjection.scala:91:36, :302:78]
wire [7:0] _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_2 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_4 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_6 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_8 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_10 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_12 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_14 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_16 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_18 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_20 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_22 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_24 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_26 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_28 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_30 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_32 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_34 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_36 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_38 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_40 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_42 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_44 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_46 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_48 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_50 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_52 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_54 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_56 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_58 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_60 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [7:0] _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:302:78]
assign _resultdata_data_T_62 = _GEN_12; // @[L2MemHelperLatencyInjection.scala:302:78]
wire [255:0] _resultdata_data_T_1 = _Queue4_L2RespInternal_io_deq_bits_data >> _resultdata_data_T; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data = resultdata_is_current_q ? _resultdata_data_T_1 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_3 = _Queue4_L2RespInternal_1_io_deq_bits_data >> _resultdata_data_T_2; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_1 = resultdata_is_current_q_1 ? _resultdata_data_T_3 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_5 = _Queue4_L2RespInternal_2_io_deq_bits_data >> _resultdata_data_T_4; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_2 = resultdata_is_current_q_2 ? _resultdata_data_T_5 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_7 = _Queue4_L2RespInternal_3_io_deq_bits_data >> _resultdata_data_T_6; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_3 = resultdata_is_current_q_3 ? _resultdata_data_T_7 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_9 = _Queue4_L2RespInternal_4_io_deq_bits_data >> _resultdata_data_T_8; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_4 = resultdata_is_current_q_4 ? _resultdata_data_T_9 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_11 = _Queue4_L2RespInternal_5_io_deq_bits_data >> _resultdata_data_T_10; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_5 = resultdata_is_current_q_5 ? _resultdata_data_T_11 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_13 = _Queue4_L2RespInternal_6_io_deq_bits_data >> _resultdata_data_T_12; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_6 = resultdata_is_current_q_6 ? _resultdata_data_T_13 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_15 = _Queue4_L2RespInternal_7_io_deq_bits_data >> _resultdata_data_T_14; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_7 = resultdata_is_current_q_7 ? _resultdata_data_T_15 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_17 = _Queue4_L2RespInternal_8_io_deq_bits_data >> _resultdata_data_T_16; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_8 = resultdata_is_current_q_8 ? _resultdata_data_T_17 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_19 = _Queue4_L2RespInternal_9_io_deq_bits_data >> _resultdata_data_T_18; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_9 = resultdata_is_current_q_9 ? _resultdata_data_T_19 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_21 = _Queue4_L2RespInternal_10_io_deq_bits_data >> _resultdata_data_T_20; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_10 = resultdata_is_current_q_10 ? _resultdata_data_T_21 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_23 = _Queue4_L2RespInternal_11_io_deq_bits_data >> _resultdata_data_T_22; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_11 = resultdata_is_current_q_11 ? _resultdata_data_T_23 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_25 = _Queue4_L2RespInternal_12_io_deq_bits_data >> _resultdata_data_T_24; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_12 = resultdata_is_current_q_12 ? _resultdata_data_T_25 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_27 = _Queue4_L2RespInternal_13_io_deq_bits_data >> _resultdata_data_T_26; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_13 = resultdata_is_current_q_13 ? _resultdata_data_T_27 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_29 = _Queue4_L2RespInternal_14_io_deq_bits_data >> _resultdata_data_T_28; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_14 = resultdata_is_current_q_14 ? _resultdata_data_T_29 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_31 = _Queue4_L2RespInternal_15_io_deq_bits_data >> _resultdata_data_T_30; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_15 = resultdata_is_current_q_15 ? _resultdata_data_T_31 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_33 = _Queue4_L2RespInternal_16_io_deq_bits_data >> _resultdata_data_T_32; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_16 = resultdata_is_current_q_16 ? _resultdata_data_T_33 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_35 = _Queue4_L2RespInternal_17_io_deq_bits_data >> _resultdata_data_T_34; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_17 = resultdata_is_current_q_17 ? _resultdata_data_T_35 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_37 = _Queue4_L2RespInternal_18_io_deq_bits_data >> _resultdata_data_T_36; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_18 = resultdata_is_current_q_18 ? _resultdata_data_T_37 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_39 = _Queue4_L2RespInternal_19_io_deq_bits_data >> _resultdata_data_T_38; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_19 = resultdata_is_current_q_19 ? _resultdata_data_T_39 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_41 = _Queue4_L2RespInternal_20_io_deq_bits_data >> _resultdata_data_T_40; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_20 = resultdata_is_current_q_20 ? _resultdata_data_T_41 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_43 = _Queue4_L2RespInternal_21_io_deq_bits_data >> _resultdata_data_T_42; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_21 = resultdata_is_current_q_21 ? _resultdata_data_T_43 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_45 = _Queue4_L2RespInternal_22_io_deq_bits_data >> _resultdata_data_T_44; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_22 = resultdata_is_current_q_22 ? _resultdata_data_T_45 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_47 = _Queue4_L2RespInternal_23_io_deq_bits_data >> _resultdata_data_T_46; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_23 = resultdata_is_current_q_23 ? _resultdata_data_T_47 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_49 = _Queue4_L2RespInternal_24_io_deq_bits_data >> _resultdata_data_T_48; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_24 = resultdata_is_current_q_24 ? _resultdata_data_T_49 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_51 = _Queue4_L2RespInternal_25_io_deq_bits_data >> _resultdata_data_T_50; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_25 = resultdata_is_current_q_25 ? _resultdata_data_T_51 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_53 = _Queue4_L2RespInternal_26_io_deq_bits_data >> _resultdata_data_T_52; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_26 = resultdata_is_current_q_26 ? _resultdata_data_T_53 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_55 = _Queue4_L2RespInternal_27_io_deq_bits_data >> _resultdata_data_T_54; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_27 = resultdata_is_current_q_27 ? _resultdata_data_T_55 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_57 = _Queue4_L2RespInternal_28_io_deq_bits_data >> _resultdata_data_T_56; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_28 = resultdata_is_current_q_28 ? _resultdata_data_T_57 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_59 = _Queue4_L2RespInternal_29_io_deq_bits_data >> _resultdata_data_T_58; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_29 = resultdata_is_current_q_29 ? _resultdata_data_T_59 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_61 = _Queue4_L2RespInternal_30_io_deq_bits_data >> _resultdata_data_T_60; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_30 = resultdata_is_current_q_30 ? _resultdata_data_T_61 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire resultdata_is_current_q_31 = &_outstanding_req_addr_io_deq_bits_tag; // @[L2MemHelperLatencyInjection.scala:91:36, :287:27, :299:31]
wire [255:0] resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20]
wire [255:0] _resultdata_data_T_63 = _Queue4_L2RespInternal_31_io_deq_bits_data >> _resultdata_data_T_62; // @[L2MemHelperLatencyInjection.scala:182:11, :302:{31,78}]
assign resultdata_data_31 = resultdata_is_current_q_31 ? _resultdata_data_T_63 : 256'h0; // @[L2MemHelperLatencyInjection.scala:299:31, :300:20, :301:25, :302:{12,31}, :304:12]
wire [255:0] _resultdata_T = resultdata_data | resultdata_data_1; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_1 = _resultdata_T | resultdata_data_2; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_2 = _resultdata_T_1 | resultdata_data_3; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_3 = _resultdata_T_2 | resultdata_data_4; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_4 = _resultdata_T_3 | resultdata_data_5; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_5 = _resultdata_T_4 | resultdata_data_6; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_6 = _resultdata_T_5 | resultdata_data_7; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_7 = _resultdata_T_6 | resultdata_data_8; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_8 = _resultdata_T_7 | resultdata_data_9; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_9 = _resultdata_T_8 | resultdata_data_10; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_10 = _resultdata_T_9 | resultdata_data_11; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_11 = _resultdata_T_10 | resultdata_data_12; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_12 = _resultdata_T_11 | resultdata_data_13; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_13 = _resultdata_T_12 | resultdata_data_14; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_14 = _resultdata_T_13 | resultdata_data_15; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_15 = _resultdata_T_14 | resultdata_data_16; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_16 = _resultdata_T_15 | resultdata_data_17; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_17 = _resultdata_T_16 | resultdata_data_18; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_18 = _resultdata_T_17 | resultdata_data_19; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_19 = _resultdata_T_18 | resultdata_data_20; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_20 = _resultdata_T_19 | resultdata_data_21; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_21 = _resultdata_T_20 | resultdata_data_22; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_22 = _resultdata_T_21 | resultdata_data_23; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_23 = _resultdata_T_22 | resultdata_data_24; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_24 = _resultdata_T_23 | resultdata_data_25; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_25 = _resultdata_T_24 | resultdata_data_26; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_26 = _resultdata_T_25 | resultdata_data_27; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_27 = _resultdata_T_26 | resultdata_data_28; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_28 = _resultdata_T_27 | resultdata_data_29; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
wire [255:0] _resultdata_T_29 = _resultdata_T_28 | resultdata_data_30; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
assign resultdata = _resultdata_T_29 | resultdata_data_31; // @[L2MemHelperLatencyInjection.scala:300:20, :307:15]
assign response_output_bits_data = resultdata; // @[L2MemHelperLatencyInjection.scala:53:29, :307:15]
assign _response_output_valid_T = queueValid & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53]
assign response_output_valid = _response_output_valid_T; // @[Misc.scala:26:53]
wire _outstanding_req_addr_io_deq_ready_T = queueValid & response_output_ready; // @[Misc.scala:26:53]
wire _T_572 = response_output_ready & _outstanding_req_addr_io_deq_valid; // @[Misc.scala:26:53]
wire opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38]
wire _T_590 = response_output_ready & response_output_valid; // @[Decoupled.scala:51:35]
reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to the following Chisel files.
File OutputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class OutputCreditAlloc extends Bundle {
val alloc = Bool()
val tail = Bool()
}
class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams {
val occupied = Bool()
def available = !occupied
val flow = new FlowRoutingBundle
}
class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams {
val alloc = Bool()
val flow = new FlowRoutingBundle
}
class AbstractOutputUnitIO(
val inParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val cParam: BaseChannelParams
)(implicit val p: Parameters) extends Bundle with HasRouterInputParams {
val nodeId = cParam.srcId
val nVirtualChannels = cParam.nVirtualChannels
val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val credit_available = Output(Vec(nVirtualChannels, Bool()))
val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus))
val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc))
val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc))
}
abstract class AbstractOutputUnit(
val inParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val cParam: BaseChannelParams
)(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams {
val nodeId = cParam.srcId
def io: AbstractOutputUnitIO
}
class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = new Channel(cParam.asInstanceOf[ChannelParams])
}
val io = IO(new OutputUnitIO)
class OutputState(val bufferSize: Int) extends Bundle {
val occupied = Bool()
val c = UInt(log2Up(1+bufferSize).W)
val flow = new FlowRoutingBundle
}
val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) }))
(states zip io.channel_status).map { case (s,a) =>
a.occupied := s.occupied
a.flow := s.flow
}
io.out.flit := io.in
states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) {
when (io.out.vc_free(i)) {
assert(s.occupied)
s.occupied := false.B
}
} }
(states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) {
when (a.alloc) {
s.occupied := true.B
s.flow := a.flow
}
} }
(io.credit_available zip states).zipWithIndex.map { case ((c,s),i) =>
c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U)
}
states.zipWithIndex.map { case (s,i) =>
val free = io.out.credit_return(i)
val alloc = io.credit_alloc(i).alloc
if (cParam.virtualChannelParams(i).traversable) {
s.c := s.c +& free - alloc
}
}
when (reset.asBool) {
states.foreach(_.occupied := false.B)
states.foreach(s => s.c := s.bufferSize.U)
}
}
| module OutputUnit_52( // @[OutputUnit.scala:52:7]
input clock, // @[OutputUnit.scala:52:7]
input reset, // @[OutputUnit.scala:52:7]
input io_in_0_valid, // @[OutputUnit.scala:58:14]
input io_in_0_bits_head, // @[OutputUnit.scala:58:14]
input io_in_0_bits_tail, // @[OutputUnit.scala:58:14]
input [36:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14]
input io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
input io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
output io_credit_available_1, // @[OutputUnit.scala:58:14]
output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14]
input io_allocs_1_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14]
output io_out_flit_0_valid, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14]
output [36:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
input [1:0] io_out_credit_return, // @[OutputUnit.scala:58:14]
input [1:0] io_out_vc_free // @[OutputUnit.scala:58:14]
);
reg states_1_occupied; // @[OutputUnit.scala:66:19]
reg [1:0] states_1_c; // @[OutputUnit.scala:66:19] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_184( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File tage.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f2_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
us.suggestName(s"tage_u_${histLength}")
table.suggestName(s"tage_table_${histLength}")
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry))
val s2_req_rus = Wire(Vec(bankWidth*2, Bool()))
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f2_resp(w).valid := s2_req_rhits(w)
io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2))
io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
val wen = WireInit(doing_reset || io.update_mask.reduce(_||_))
val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid)
when (RegNext(wen) && singlePorted.B) {
s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry))
} .otherwise {
s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry)))
}
when (wen) {
val widx = Mux(doing_reset, reset_idx, update_idx)
val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt)))
val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt)
table.write(widx, wdata, wmask.asBools)
}
val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)})
val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_))
val u_rdata = if (singlePorted) {
us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid)
} else {
us.read(s1_hashed_idx, io.f1_req_valid)
}
s2_req_rus := u_rdata
when (update_u_wen) {
val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx))
val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools))
val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt))
us.write(widx, wdata, wmask.asBools)
}
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048,
singlePorted: Boolean = false
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc))
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f2_resps = VecInit(tables.map(_.io.f2_resp))
val f3_resps = RegNext(f2_resps)
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var s2_provided = false.B
var s2_provider = 0.U
var s2_alt_provided = false.B
var s2_alt_provider = 0.U
for (i <- 0 until tageNTables) {
val hit = f2_resps(i)(w).valid
s2_alt_provided = s2_alt_provided || (s2_provided && hit)
s2_provided = s2_provided || hit
s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider)
s2_provider = Mux(hit, i.U, s2_provider)
}
val s3_provided = RegNext(s2_provided)
val s3_provider = RegNext(s2_provider)
val s3_alt_provided = RegNext(s2_alt_provided)
val s3_alt_provider = RegNext(s2_alt_provider)
val prov = RegNext(f2_resps(s2_provider)(w).bits)
val alt = RegNext(f2_resps(s2_alt_provider)(w).bits)
io.resp.f3(w).taken := Mux(s3_provided,
Mux(prov.ctr === 3.U || prov.ctr === 4.U,
Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken),
prov.ctr(2)),
io.resp_in(0).f3(w).taken
)
f3_meta.provider(w).valid := s3_provided
f3_meta.provider(w).bits := s3_provider
f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := prov.u
f3_meta.provider_ctr(w) := prov.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
| module tage_table_2( // @[tage.scala:90:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [43:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [43:0] W0_data,
input [3:0] W0_mask
);
tage_table_2_ext tage_table_2_ext ( // @[tage.scala:90:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:90:27]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_202( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Pipeline.scala:
package gemmini
import chisel3._
import chisel3.util._
class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module {
val io = IO(new Bundle {
val in = Flipped(Decoupled(gen))
val out = Decoupled(gen)
val busy = Output(Bool())
})
require(comb.size == latency+1, "length of combinational is incorrect")
if (latency == 0) {
io.in.ready := io.out.ready
io.out.valid := io.in.valid
io.out.bits := comb.head(io.in.bits)
io.busy := io.in.valid
} else {
val stages = Reg(Vec(latency, gen))
val valids = RegInit(VecInit(Seq.fill(latency)(false.B)))
val stalling = VecInit(Seq.fill(latency)(false.B))
io.busy := io.in.valid || valids.reduce(_||_)
// Stall signals
io.in.ready := !stalling.head
stalling.last := valids.last && !io.out.ready
(stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) =>
s1 := v1 && s2
}
// Valid signals
// When the pipeline stage ahead of you isn't stalling, then make yourself invalid
io.out.valid := valids.last
when(io.out.ready) {
valids.last := false.B
}
(valids.init, stalling.tail).zipped.foreach { case (v1, s2) =>
when(!s2) {
v1 := false.B
}
}
// When the pipeline stage behind you is valid then become true
when(io.in.fire) {
valids.head := true.B
}
(valids.tail, valids.init).zipped.foreach { case (v2, v1) =>
when(v1) {
v2 := true.B
}
}
// Stages
when(io.in.fire) {
stages.head := comb.head(io.in.bits)
}
io.out.bits := comb.last(stages.last)
((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) =>
when(!s2) {
st2 := c1(st1)
}
}
}
}
object Pipeline {
def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)(comb))
p.io.in <> in
p.io.out
}
def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)())
p.io.in <> in
p.io.out
}
}
| module Pipeline_13( // @[Pipeline.scala:6:7]
input clock, // @[Pipeline.scala:6:7]
input reset, // @[Pipeline.scala:6:7]
output io_in_ready, // @[Pipeline.scala:7:14]
input io_in_valid, // @[Pipeline.scala:7:14]
input [6:0] io_in_bits_cmd_inst_funct, // @[Pipeline.scala:7:14]
input [63:0] io_in_bits_cmd_rs1, // @[Pipeline.scala:7:14]
input [63:0] io_in_bits_cmd_rs2, // @[Pipeline.scala:7:14]
input [69:0] io_in_bits_dram_addr, // @[Pipeline.scala:7:14]
input [63:0] io_in_bits_spad_addr, // @[Pipeline.scala:7:14]
input [15:0] io_in_bits_K, // @[Pipeline.scala:7:14]
input [15:0] io_in_bits_J, // @[Pipeline.scala:7:14]
input io_out_ready, // @[Pipeline.scala:7:14]
output io_out_valid, // @[Pipeline.scala:7:14]
output [6:0] io_out_bits_cmd_inst_funct, // @[Pipeline.scala:7:14]
output [4:0] io_out_bits_cmd_inst_rs2, // @[Pipeline.scala:7:14]
output [4:0] io_out_bits_cmd_inst_rs1, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_inst_xd, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_inst_xs1, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_inst_xs2, // @[Pipeline.scala:7:14]
output [4:0] io_out_bits_cmd_inst_rd, // @[Pipeline.scala:7:14]
output [6:0] io_out_bits_cmd_inst_opcode, // @[Pipeline.scala:7:14]
output [63:0] io_out_bits_cmd_rs1, // @[Pipeline.scala:7:14]
output [63:0] io_out_bits_cmd_rs2, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_debug, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_cease, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_wfi, // @[Pipeline.scala:7:14]
output [31:0] io_out_bits_cmd_status_isa, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_dprv, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_dv, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_prv, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_v, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_sd, // @[Pipeline.scala:7:14]
output [22:0] io_out_bits_cmd_status_zero2, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_mpv, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_gva, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_mbe, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_sbe, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_sxl, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_uxl, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_sd_rv32, // @[Pipeline.scala:7:14]
output [7:0] io_out_bits_cmd_status_zero1, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_tsr, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_tw, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_tvm, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_mxr, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_sum, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_mprv, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_xs, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_fs, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_mpp, // @[Pipeline.scala:7:14]
output [1:0] io_out_bits_cmd_status_vs, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_spp, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_mpie, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_ube, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_spie, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_upie, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_mie, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_hie, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_sie, // @[Pipeline.scala:7:14]
output io_out_bits_cmd_status_uie, // @[Pipeline.scala:7:14]
output [69:0] io_out_bits_dram_addr, // @[Pipeline.scala:7:14]
output [63:0] io_out_bits_spad_addr, // @[Pipeline.scala:7:14]
output [15:0] io_out_bits_K, // @[Pipeline.scala:7:14]
output [15:0] io_out_bits_J, // @[Pipeline.scala:7:14]
output io_busy // @[Pipeline.scala:7:14]
);
wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7]
wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[Pipeline.scala:6:7]
wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[Pipeline.scala:6:7]
wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[Pipeline.scala:6:7]
wire [69:0] io_in_bits_dram_addr_0 = io_in_bits_dram_addr; // @[Pipeline.scala:6:7]
wire [63:0] io_in_bits_spad_addr_0 = io_in_bits_spad_addr; // @[Pipeline.scala:6:7]
wire [15:0] io_in_bits_K_0 = io_in_bits_K; // @[Pipeline.scala:6:7]
wire [15:0] io_in_bits_J_0 = io_in_bits_J; // @[Pipeline.scala:6:7]
wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7]
wire [4:0] io_in_bits_cmd_inst_rs2 = 5'h0; // @[Pipeline.scala:6:7, :7:14]
wire [4:0] io_in_bits_cmd_inst_rs1 = 5'h0; // @[Pipeline.scala:6:7, :7:14]
wire [4:0] io_in_bits_cmd_inst_rd = 5'h0; // @[Pipeline.scala:6:7, :7:14]
wire [6:0] io_in_bits_cmd_inst_opcode = 7'h0; // @[Pipeline.scala:6:7, :7:14]
wire [31:0] io_in_bits_cmd_status_isa = 32'h0; // @[Pipeline.scala:6:7, :7:14]
wire [22:0] io_in_bits_cmd_status_zero2 = 23'h0; // @[Pipeline.scala:6:7, :7:14]
wire [7:0] io_in_bits_cmd_status_zero1 = 8'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_dprv = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_prv = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_sxl = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_uxl = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_xs = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_fs = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_mpp = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire [1:0] io_in_bits_cmd_status_vs = 2'h0; // @[Pipeline.scala:6:7, :7:14]
wire io_in_bits_cmd_inst_xd = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_inst_xs1 = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_inst_xs2 = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_debug = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_cease = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_wfi = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_dv = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_v = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_sd = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_mpv = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_gva = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_mbe = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_sbe = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_sd_rv32 = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_tsr = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_tw = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_tvm = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_mxr = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_sum = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_mprv = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_spp = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_mpie = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_ube = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_spie = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_upie = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_mie = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_hie = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_sie = 1'h0; // @[Pipeline.scala:6:7]
wire io_in_bits_cmd_status_uie = 1'h0; // @[Pipeline.scala:6:7]
wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33]
wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33]
wire _io_in_ready_T; // @[Pipeline.scala:27:20]
wire _io_busy_T_1; // @[Pipeline.scala:24:28]
wire io_in_ready_0; // @[Pipeline.scala:6:7]
wire [6:0] io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7]
wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7]
wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7]
wire [4:0] io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7]
wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7]
wire [31:0] io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7]
wire [22:0] io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7]
wire [7:0] io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7]
wire [1:0] io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7]
wire io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7]
wire [63:0] io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7]
wire [63:0] io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7]
wire [69:0] io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7]
wire [63:0] io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7]
wire [15:0] io_out_bits_K_0; // @[Pipeline.scala:6:7]
wire [15:0] io_out_bits_J_0; // @[Pipeline.scala:6:7]
wire io_out_valid_0; // @[Pipeline.scala:6:7]
wire io_busy_0; // @[Pipeline.scala:6:7]
reg [6:0] stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21]
reg [63:0] stages_0_cmd_rs1; // @[Pipeline.scala:21:21]
reg [63:0] stages_0_cmd_rs2; // @[Pipeline.scala:21:21]
reg [69:0] stages_0_dram_addr; // @[Pipeline.scala:21:21]
reg [63:0] stages_0_spad_addr; // @[Pipeline.scala:21:21]
reg [15:0] stages_0_K; // @[Pipeline.scala:21:21]
reg [15:0] stages_0_J; // @[Pipeline.scala:21:21]
reg [6:0] stages_1_cmd_inst_funct; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_funct_0 = stages_1_cmd_inst_funct; // @[Pipeline.scala:6:7, :21:21]
reg [4:0] stages_1_cmd_inst_rs2; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_rs2_0 = stages_1_cmd_inst_rs2; // @[Pipeline.scala:6:7, :21:21]
reg [4:0] stages_1_cmd_inst_rs1; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_rs1_0 = stages_1_cmd_inst_rs1; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_xd_0 = stages_1_cmd_inst_xd; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_xs1_0 = stages_1_cmd_inst_xs1; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_xs2_0 = stages_1_cmd_inst_xs2; // @[Pipeline.scala:6:7, :21:21]
reg [4:0] stages_1_cmd_inst_rd; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_rd_0 = stages_1_cmd_inst_rd; // @[Pipeline.scala:6:7, :21:21]
reg [6:0] stages_1_cmd_inst_opcode; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_inst_opcode_0 = stages_1_cmd_inst_opcode; // @[Pipeline.scala:6:7, :21:21]
reg [63:0] stages_1_cmd_rs1; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_rs1_0 = stages_1_cmd_rs1; // @[Pipeline.scala:6:7, :21:21]
reg [63:0] stages_1_cmd_rs2; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_rs2_0 = stages_1_cmd_rs2; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_debug; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_debug_0 = stages_1_cmd_status_debug; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_cease; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_cease_0 = stages_1_cmd_status_cease; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_wfi_0 = stages_1_cmd_status_wfi; // @[Pipeline.scala:6:7, :21:21]
reg [31:0] stages_1_cmd_status_isa; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_isa_0 = stages_1_cmd_status_isa; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_dprv; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_dprv_0 = stages_1_cmd_status_dprv; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_dv; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_dv_0 = stages_1_cmd_status_dv; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_prv; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_prv_0 = stages_1_cmd_status_prv; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_v; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_v_0 = stages_1_cmd_status_v; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_sd; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_sd_0 = stages_1_cmd_status_sd; // @[Pipeline.scala:6:7, :21:21]
reg [22:0] stages_1_cmd_status_zero2; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_zero2_0 = stages_1_cmd_status_zero2; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_mpv_0 = stages_1_cmd_status_mpv; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_gva; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_gva_0 = stages_1_cmd_status_gva; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_mbe_0 = stages_1_cmd_status_mbe; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_sbe_0 = stages_1_cmd_status_sbe; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_sxl; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_sxl_0 = stages_1_cmd_status_sxl; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_uxl; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_uxl_0 = stages_1_cmd_status_uxl; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_sd_rv32_0 = stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:6:7, :21:21]
reg [7:0] stages_1_cmd_status_zero1; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_zero1_0 = stages_1_cmd_status_zero1; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_tsr_0 = stages_1_cmd_status_tsr; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_tw; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_tw_0 = stages_1_cmd_status_tw; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_tvm_0 = stages_1_cmd_status_tvm; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_mxr_0 = stages_1_cmd_status_mxr; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_sum; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_sum_0 = stages_1_cmd_status_sum; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_mprv_0 = stages_1_cmd_status_mprv; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_xs; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_xs_0 = stages_1_cmd_status_xs; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_fs; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_fs_0 = stages_1_cmd_status_fs; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_mpp; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_mpp_0 = stages_1_cmd_status_mpp; // @[Pipeline.scala:6:7, :21:21]
reg [1:0] stages_1_cmd_status_vs; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_vs_0 = stages_1_cmd_status_vs; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_spp; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_spp_0 = stages_1_cmd_status_spp; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_mpie_0 = stages_1_cmd_status_mpie; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_ube; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_ube_0 = stages_1_cmd_status_ube; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_spie; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_spie_0 = stages_1_cmd_status_spie; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_upie; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_upie_0 = stages_1_cmd_status_upie; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_mie; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_mie_0 = stages_1_cmd_status_mie; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_hie; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_hie_0 = stages_1_cmd_status_hie; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_sie; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_sie_0 = stages_1_cmd_status_sie; // @[Pipeline.scala:6:7, :21:21]
reg stages_1_cmd_status_uie; // @[Pipeline.scala:21:21]
assign io_out_bits_cmd_status_uie_0 = stages_1_cmd_status_uie; // @[Pipeline.scala:6:7, :21:21]
reg [69:0] stages_1_dram_addr; // @[Pipeline.scala:21:21]
assign io_out_bits_dram_addr_0 = stages_1_dram_addr; // @[Pipeline.scala:6:7, :21:21]
reg [63:0] stages_1_spad_addr; // @[Pipeline.scala:21:21]
assign io_out_bits_spad_addr_0 = stages_1_spad_addr; // @[Pipeline.scala:6:7, :21:21]
reg [15:0] stages_1_K; // @[Pipeline.scala:21:21]
assign io_out_bits_K_0 = stages_1_K; // @[Pipeline.scala:6:7, :21:21]
reg [15:0] stages_1_J; // @[Pipeline.scala:21:21]
assign io_out_bits_J_0 = stages_1_J; // @[Pipeline.scala:6:7, :21:21]
reg valids_0; // @[Pipeline.scala:22:25]
reg valids_1; // @[Pipeline.scala:22:25]
assign io_out_valid_0 = valids_1; // @[Pipeline.scala:6:7, :22:25]
wire _stalling_0_T; // @[Pipeline.scala:30:16]
wire _stalling_1_T_1; // @[Pipeline.scala:28:34]
wire stalling_0; // @[Pipeline.scala:23:27]
wire stalling_1; // @[Pipeline.scala:23:27]
wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46]
assign _io_busy_T_1 = io_in_valid_0 | _io_busy_T; // @[Pipeline.scala:6:7, :24:{28,46}]
assign io_busy_0 = _io_busy_T_1; // @[Pipeline.scala:6:7, :24:28]
assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20]
assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20]
wire _stalling_1_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37]
assign _stalling_1_T_1 = valids_1 & _stalling_1_T; // @[Pipeline.scala:22:25, :28:{34,37}]
assign stalling_1 = _stalling_1_T_1; // @[Pipeline.scala:23:27, :28:34]
assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16]
assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16]
wire _T_2 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Pipeline.scala:6:7]
if (_T_2) begin // @[Decoupled.scala:51:35]
stages_0_cmd_inst_funct <= io_in_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_cmd_rs1 <= io_in_bits_cmd_rs1_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_cmd_rs2 <= io_in_bits_cmd_rs2_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_dram_addr <= io_in_bits_dram_addr_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_spad_addr <= io_in_bits_spad_addr_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_K <= io_in_bits_K_0; // @[Pipeline.scala:6:7, :21:21]
stages_0_J <= io_in_bits_J_0; // @[Pipeline.scala:6:7, :21:21]
end
if (stalling_1) begin // @[Pipeline.scala:23:27]
end
else begin // @[Pipeline.scala:23:27]
stages_1_cmd_inst_funct <= stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21]
stages_1_cmd_inst_rs2 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_inst_rs1 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_inst_rd <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_inst_opcode <= 7'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_rs1 <= stages_0_cmd_rs1; // @[Pipeline.scala:21:21]
stages_1_cmd_rs2 <= stages_0_cmd_rs2; // @[Pipeline.scala:21:21]
stages_1_cmd_status_isa <= 32'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_dprv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_prv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_zero2 <= 23'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_sxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_uxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_zero1 <= 8'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_xs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_fs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_mpp <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_cmd_status_vs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21]
stages_1_dram_addr <= stages_0_dram_addr; // @[Pipeline.scala:21:21]
stages_1_spad_addr <= stages_0_spad_addr; // @[Pipeline.scala:21:21]
stages_1_K <= stages_0_K; // @[Pipeline.scala:21:21]
stages_1_J <= stages_0_J; // @[Pipeline.scala:21:21]
end
stages_1_cmd_inst_xd <= stalling_1 & stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_inst_xs1 <= stalling_1 & stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_inst_xs2 <= stalling_1 & stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_debug <= stalling_1 & stages_1_cmd_status_debug; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_cease <= stalling_1 & stages_1_cmd_status_cease; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_wfi <= stalling_1 & stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_dv <= stalling_1 & stages_1_cmd_status_dv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_v <= stalling_1 & stages_1_cmd_status_v; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_sd <= stalling_1 & stages_1_cmd_status_sd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_mpv <= stalling_1 & stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_gva <= stalling_1 & stages_1_cmd_status_gva; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_mbe <= stalling_1 & stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_sbe <= stalling_1 & stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_sd_rv32 <= stalling_1 & stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_tsr <= stalling_1 & stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_tw <= stalling_1 & stages_1_cmd_status_tw; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_tvm <= stalling_1 & stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_mxr <= stalling_1 & stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_sum <= stalling_1 & stages_1_cmd_status_sum; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_mprv <= stalling_1 & stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_spp <= stalling_1 & stages_1_cmd_status_spp; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_mpie <= stalling_1 & stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_ube <= stalling_1 & stages_1_cmd_status_ube; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_spie <= stalling_1 & stages_1_cmd_status_spie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_upie <= stalling_1 & stages_1_cmd_status_upie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_mie <= stalling_1 & stages_1_cmd_status_mie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_hie <= stalling_1 & stages_1_cmd_status_hie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_sie <= stalling_1 & stages_1_cmd_status_sie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
stages_1_cmd_status_uie <= stalling_1 & stages_1_cmd_status_uie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13]
if (reset) begin // @[Pipeline.scala:6:7]
valids_0 <= 1'h0; // @[Pipeline.scala:22:25]
valids_1 <= 1'h0; // @[Pipeline.scala:22:25]
end
else begin // @[Pipeline.scala:6:7]
valids_0 <= _T_2 | stalling_1 & valids_0; // @[Decoupled.scala:51:35]
valids_1 <= valids_0 | ~io_out_ready_0 & valids_1; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12]
end
always @(posedge)
assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7]
assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_funct = io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_rs2 = io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_rs1 = io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_xd = io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_xs1 = io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_xs2 = io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_rd = io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_inst_opcode = io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_rs1 = io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_rs2 = io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_debug = io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_cease = io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_wfi = io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_isa = io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_dprv = io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_dv = io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_prv = io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_v = io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_sd = io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_zero2 = io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_mpv = io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_gva = io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_mbe = io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_sbe = io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_sxl = io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_uxl = io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_sd_rv32 = io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_zero1 = io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_tsr = io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_tw = io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_tvm = io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_mxr = io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_sum = io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_mprv = io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_xs = io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_fs = io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_mpp = io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_vs = io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_spp = io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_mpie = io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_ube = io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_spie = io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_upie = io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_mie = io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_hie = io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_sie = io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7]
assign io_out_bits_cmd_status_uie = io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7]
assign io_out_bits_dram_addr = io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7]
assign io_out_bits_spad_addr = io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7]
assign io_out_bits_K = io_out_bits_K_0; // @[Pipeline.scala:6:7]
assign io_out_bits_J = io_out_bits_J_0; // @[Pipeline.scala:6:7]
assign io_busy = io_busy_0; // @[Pipeline.scala:6:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_3( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_5_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_4_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_5_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_4_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_5_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_4_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & ~(|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & (|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module ClockCrossingReg_w120( // @[SynchronizerReg.scala:191:7]
input clock, // @[SynchronizerReg.scala:191:7]
input reset, // @[SynchronizerReg.scala:191:7]
input [119:0] io_d, // @[SynchronizerReg.scala:195:14]
output [119:0] io_q, // @[SynchronizerReg.scala:195:14]
input io_en // @[SynchronizerReg.scala:195:14]
);
wire [119:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7]
wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7]
wire [119:0] io_q_0; // @[SynchronizerReg.scala:191:7]
reg [119:0] cdc_reg; // @[SynchronizerReg.scala:201:76]
assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge clock) begin // @[SynchronizerReg.scala:191:7]
if (io_en_0) // @[SynchronizerReg.scala:191:7]
cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76]
always @(posedge)
assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_172( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_13( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_13 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_13 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_24 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_1( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_6 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_12 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_24 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T = 1'h1; // @[Parameters.scala:46:9]
wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_6 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_10 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_12 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [5:0] io_in_b_bits_source = 6'h20; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_23 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_uncommonBits_T_1 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _legal_source_T_15 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_20 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_21 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_22 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_23 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _legal_source_WIRE_1 = 6'h20; // @[Mux.scala:30:73]
wire [5:0] _uncommonBits_T_24 = 6'h20; // @[Parameters.scala:52:29]
wire [5:0] _uncommonBits_T_25 = 6'h20; // @[Parameters.scala:52:29]
wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T_1 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_3 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_5 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_7 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_9 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_11 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_13 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_18 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] b_first_beats1_decode = 8'h3; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [3:0] uncommonBits_22 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] uncommonBits_23 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] legal_source_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] legal_source_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] uncommonBits_24 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] uncommonBits_25 = 4'h0; // @[Parameters.scala:52:56]
wire [5:0] _legal_source_T_16 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_19 = 6'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_17 = 5'h0; // @[Mux.scala:30:73]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _legal_source_T_2 = 2'h2; // @[Parameters.scala:54:10]
wire [1:0] _legal_source_T_8 = 2'h2; // @[Parameters.scala:54:10]
wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = io_in_a_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_2 = io_in_a_bits_source_0[5:4]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_8 = io_in_a_bits_source_0[5:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = _source_ok_T_2 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_7 = _source_ok_T_5; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_9 = _source_ok_T_8 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_13 = _source_ok_T_11; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_13; // @[Parameters.scala:1138:31]
wire _source_ok_T_14 = io_in_a_bits_source_0 == 6'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_4 = _source_ok_T_14; // @[Parameters.scala:1138:31]
wire _source_ok_T_15 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_16 = _source_ok_T_15 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_17 = _source_ok_T_16 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_17 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_18 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire _source_ok_T_19 = io_in_d_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_19; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_20 = io_in_d_bits_source_0[5:4]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[5:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_21 = _source_ok_T_20 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_25 = _source_ok_T_23; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_d_bits_source_0 == 6'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_4 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_35 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38]
wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38]
wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38]
wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38]
wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38]
wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38]
wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38]
wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38]
wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38]
wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38]
wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38]
wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38]
wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38]
wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38]
wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38]
wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_36 = io_in_c_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_c_bits_source_0 == 6'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_1 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_38 = io_in_c_bits_source_0[5:4]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_44 = io_in_c_bits_source_0[5:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_39 = _source_ok_T_38 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = _source_ok_T_44 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = io_in_c_bits_source_0 == 6'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_4 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire _source_ok_T_51 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_53 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire [3:0] uncommonBits_26 = _uncommonBits_T_26[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_27 = _uncommonBits_T_27[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_30 = _uncommonBits_T_30[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_31 = _uncommonBits_T_31[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_32 = _uncommonBits_T_32[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_33 = _uncommonBits_T_33[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire _T_2765 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2765; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2765; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2839 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2839; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2839; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2839; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2839; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [7:0] b_first_counter; // @[Edges.scala:229:27]
wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2836 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2836; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2836; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [7:0] c_first_counter; // @[Edges.scala:229:27]
wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [5:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [34:0] inflight; // @[Monitor.scala:614:27]
reg [139:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [279:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [34:0] a_set; // @[Monitor.scala:626:34]
wire [34:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [139:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [279:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101]
wire [139:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [139:0] _a_opcode_lookup_T_6 = {136'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [139:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[139:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99]
wire [279:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [279:0] _a_size_lookup_T_6 = {272'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [279:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[279:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_20 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire _T_2691 = _T_2765 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2691 ? _a_set_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2691 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2691 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2691 ? _a_opcodes_set_T_1[139:0] : 140'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2691 ? _a_sizes_set_T_1[279:0] : 280'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [34:0] d_clr; // @[Monitor.scala:664:34]
wire [34:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [139:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [279:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46]
wire _T_2737 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_22 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2737 & ~d_release_ack ? _d_clr_wo_ready_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire _T_2706 = _T_2839 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2706 ? _d_clr_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2706 ? _d_opcodes_clr_T_5[139:0] : 140'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2706 ? _d_sizes_clr_T_5[279:0] : 280'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [34:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [34:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [34:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [139:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [139:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [139:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [279:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [279:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [279:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [34:0] inflight_1; // @[Monitor.scala:726:35]
reg [139:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [279:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [7:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [34:0] c_set; // @[Monitor.scala:738:34]
wire [34:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [139:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [279:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [139:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [139:0] _c_opcode_lookup_T_6 = {136'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [139:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[139:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [279:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [279:0] _c_size_lookup_T_6 = {272'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [279:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[279:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [63:0] _GEN_23 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire _T_2778 = _T_2836 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2778 ? _c_set_T[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2778 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2778 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [8:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2778 ? _c_opcodes_set_T_1[139:0] : 140'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [8:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [515:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2778 ? _c_sizes_set_T_1[279:0] : 280'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [34:0] d_clr_1; // @[Monitor.scala:774:34]
wire [34:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [139:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [279:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2809 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2809 & d_release_ack_1 ? _d_clr_wo_ready_T_1[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire _T_2791 = _T_2839 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2791 ? _d_clr_T_1[34:0] : 35'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2791 ? _d_opcodes_clr_T_11[139:0] : 140'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2791 ? _d_sizes_clr_T_11[279:0] : 280'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [34:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [34:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [34:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [139:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [139:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [139:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [279:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [279:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [279:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [15:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] d_set; // @[Monitor.scala:833:25]
wire _T_2845 = _T_2839 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [15:0] _GEN_24 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [15:0] _d_set_T = 16'h1 << _GEN_24; // @[OneHot.scala:58:35]
assign d_set = _T_2845 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [15:0] e_clr; // @[Monitor.scala:839:25]
wire [15:0] _GEN_25 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [15:0] _e_clr_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_266( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_10 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_477( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_221 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_180( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_316 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_150( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_117( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_134 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_69( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_7( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [3:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14]
output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [3:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [31:0] io_out_a_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7]
wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_23 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7]
.io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7]
.io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7]
.io_out_a_bits (io_out_a_0_bits),
.io_out_b_bits (io_out_b_0_bits_0),
.io_out_c_bits (io_out_c_0_bits_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7]
assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor_56( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File TLChannelCompactor.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLDToBeat_serial_tl_0_a64d64s8k8z8c( // @[TLChannelCompactor.scala:130:7]
input clock, // @[TLChannelCompactor.scala:130:7]
input reset, // @[TLChannelCompactor.scala:130:7]
output io_protocol_ready, // @[TLChannelCompactor.scala:40:14]
input io_protocol_valid, // @[TLChannelCompactor.scala:40:14]
input [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:40:14]
input [1:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_sink, // @[TLChannelCompactor.scala:40:14]
input io_protocol_bits_denied, // @[TLChannelCompactor.scala:40:14]
input [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:40:14]
input io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:40:14]
input io_beat_ready, // @[TLChannelCompactor.scala:40:14]
output io_beat_valid, // @[TLChannelCompactor.scala:40:14]
output [64:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_head, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_tail // @[TLChannelCompactor.scala:40:14]
);
wire _q_io_deq_valid; // @[TLChannelCompactor.scala:47:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TLChannelCompactor.scala:47:17]
wire [1:0] _q_io_deq_bits_param; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_source; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_sink; // @[TLChannelCompactor.scala:47:17]
wire _q_io_deq_bits_denied; // @[TLChannelCompactor.scala:47:17]
wire [63:0] _q_io_deq_bits_data; // @[TLChannelCompactor.scala:47:17]
wire _q_io_deq_bits_corrupt; // @[TLChannelCompactor.scala:47:17]
wire io_protocol_valid_0 = io_protocol_valid; // @[TLChannelCompactor.scala:130:7]
wire [2:0] io_protocol_bits_opcode_0 = io_protocol_bits_opcode; // @[TLChannelCompactor.scala:130:7]
wire [1:0] io_protocol_bits_param_0 = io_protocol_bits_param; // @[TLChannelCompactor.scala:130:7]
wire [7:0] io_protocol_bits_size_0 = io_protocol_bits_size; // @[TLChannelCompactor.scala:130:7]
wire [7:0] io_protocol_bits_source_0 = io_protocol_bits_source; // @[TLChannelCompactor.scala:130:7]
wire [7:0] io_protocol_bits_sink_0 = io_protocol_bits_sink; // @[TLChannelCompactor.scala:130:7]
wire io_protocol_bits_denied_0 = io_protocol_bits_denied; // @[TLChannelCompactor.scala:130:7]
wire [63:0] io_protocol_bits_data_0 = io_protocol_bits_data; // @[TLChannelCompactor.scala:130:7]
wire io_protocol_bits_corrupt_0 = io_protocol_bits_corrupt; // @[TLChannelCompactor.scala:130:7]
wire io_beat_ready_0 = io_beat_ready; // @[TLChannelCompactor.scala:130:7]
wire [64:0] _io_beat_bits_payload_T; // @[TLChannelCompactor.scala:66:33]
wire _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35]
wire _io_beat_bits_tail_T_2; // @[TLChannelCompactor.scala:65:35]
wire io_protocol_ready_0; // @[TLChannelCompactor.scala:130:7]
wire [64:0] io_beat_bits_payload_0; // @[TLChannelCompactor.scala:130:7]
wire io_beat_bits_head_0; // @[TLChannelCompactor.scala:130:7]
wire io_beat_bits_tail_0; // @[TLChannelCompactor.scala:130:7]
wire io_beat_valid_0; // @[TLChannelCompactor.scala:130:7]
wire has_body_opdata; // @[Edges.scala:106:36]
wire has_body; // @[TLChannelCompactor.scala:51:22]
wire _q_io_deq_ready_T_2; // @[TLChannelCompactor.scala:62:35]
wire _GEN = _q_io_deq_ready_T_2 & _q_io_deq_valid; // @[Decoupled.scala:51:35]
wire _head_T; // @[Decoupled.scala:51:35]
assign _head_T = _GEN; // @[Decoupled.scala:51:35]
wire _tail_T; // @[Decoupled.scala:51:35]
assign _tail_T = _GEN; // @[Decoupled.scala:51:35]
wire [266:0] _GEN_0 = 267'hFFF << _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17]
wire [266:0] _head_beats1_decode_T; // @[package.scala:243:71]
assign _head_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [266:0] _tail_beats1_decode_T; // @[package.scala:243:71]
assign _tail_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [11:0] _head_beats1_decode_T_1 = _head_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _head_beats1_decode_T_2 = ~_head_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] head_beats1_decode = _head_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire head_beats1_opdata = _q_io_deq_bits_opcode[0]; // @[TLChannelCompactor.scala:47:17]
wire tail_beats1_opdata = _q_io_deq_bits_opcode[0]; // @[TLChannelCompactor.scala:47:17]
assign has_body_opdata = _q_io_deq_bits_opcode[0]; // @[TLChannelCompactor.scala:47:17]
wire [8:0] head_beats1 = head_beats1_opdata ? head_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire [9:0] _head_counter1_T = {1'h0, head_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] head_counter1 = _head_counter1_T[8:0]; // @[Edges.scala:230:28]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _head_last_T = head_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _head_last_T_1 = head_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire head_last = _head_last_T | _head_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire head_done = head_last & _head_T; // @[Decoupled.scala:51:35]
wire [8:0] _head_count_T = ~head_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] head_count = head_beats1 & _head_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _head_counter_T = head ? head_beats1 : head_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _tail_beats1_decode_T_1 = _tail_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _tail_beats1_decode_T_2 = ~_tail_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] tail_beats1_decode = _tail_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire [8:0] tail_beats1 = tail_beats1_opdata ? tail_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
wire [9:0] _tail_counter1_T = {1'h0, tail_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] tail_counter1 = _tail_counter1_T[8:0]; // @[Edges.scala:230:28]
wire tail_first = tail_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _tail_last_T = tail_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _tail_last_T_1 = tail_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire tail = _tail_last_T | _tail_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire tail_done = tail & _tail_T; // @[Decoupled.scala:51:35]
wire [8:0] _tail_count_T = ~tail_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] tail_count = tail_beats1 & _tail_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _tail_counter_T = tail_first ? tail_beats1 : tail_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] body = {_q_io_deq_bits_data, _q_io_deq_bits_corrupt}; // @[TLChannelCompactor.scala:47:17, :57:18]
wire [15:0] const_lo_hi = {_q_io_deq_bits_source, _q_io_deq_bits_sink}; // @[TLChannelCompactor.scala:47:17, :58:18]
wire [16:0] const_lo = {const_lo_hi, _q_io_deq_bits_denied}; // @[TLChannelCompactor.scala:47:17, :58:18]
wire [4:0] const_hi_hi = {_q_io_deq_bits_opcode, _q_io_deq_bits_param}; // @[TLChannelCompactor.scala:47:17, :58:18]
wire [12:0] const_hi = {const_hi_hi, _q_io_deq_bits_size}; // @[TLChannelCompactor.scala:47:17, :58:18]
wire [29:0] const_0 = {const_hi, const_lo}; // @[TLChannelCompactor.scala:58:18]
reg is_body; // @[TLChannelCompactor.scala:60:24]
wire _q_io_deq_ready_T = ~has_body; // @[TLChannelCompactor.scala:51:22, :62:50]
wire _q_io_deq_ready_T_1 = is_body | _q_io_deq_ready_T; // @[TLChannelCompactor.scala:60:24, :62:{47,50}]
assign _q_io_deq_ready_T_2 = io_beat_ready_0 & _q_io_deq_ready_T_1; // @[TLChannelCompactor.scala:62:{35,47}, :130:7]
wire _io_beat_bits_head_T = ~is_body; // @[TLChannelCompactor.scala:60:24, :64:38]
assign _io_beat_bits_head_T_1 = head & _io_beat_bits_head_T; // @[TLChannelCompactor.scala:64:{35,38}]
assign io_beat_bits_head_0 = _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35, :130:7]
wire _io_beat_bits_tail_T = ~has_body; // @[TLChannelCompactor.scala:51:22, :62:50, :65:50]
wire _io_beat_bits_tail_T_1 = is_body | _io_beat_bits_tail_T; // @[TLChannelCompactor.scala:60:24, :65:{47,50}]
assign _io_beat_bits_tail_T_2 = tail & _io_beat_bits_tail_T_1; // @[TLChannelCompactor.scala:65:{35,47}]
assign io_beat_bits_tail_0 = _io_beat_bits_tail_T_2; // @[TLChannelCompactor.scala:65:35, :130:7]
assign _io_beat_bits_payload_T = is_body ? body : {35'h0, const_0}; // @[TLChannelCompactor.scala:57:18, :58:18, :60:24, :66:33]
assign io_beat_bits_payload_0 = _io_beat_bits_payload_T; // @[TLChannelCompactor.scala:66:33, :130:7]
assign has_body = has_body_opdata; // @[TLChannelCompactor.scala:51:22]
wire _T_2 = io_beat_ready_0 & io_beat_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TLChannelCompactor.scala:130:7]
if (reset) begin // @[TLChannelCompactor.scala:130:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TLChannelCompactor.scala:60:24]
end
else begin // @[TLChannelCompactor.scala:130:7]
if (_head_T) // @[Decoupled.scala:51:35]
head_counter <= _head_counter_T; // @[Edges.scala:229:27, :236:21]
if (_tail_T) // @[Decoupled.scala:51:35]
tail_counter <= _tail_counter_T; // @[Edges.scala:229:27, :236:21]
is_body <= ~(_T_2 & io_beat_bits_tail_0) & (_T_2 & io_beat_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge)
Queue1_TLBundleD_a64d64s8k8z8c q ( // @[TLChannelCompactor.scala:47:17]
.clock (clock),
.reset (reset),
.io_enq_ready (io_protocol_ready_0),
.io_enq_valid (io_protocol_valid_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_opcode (io_protocol_bits_opcode_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_param (io_protocol_bits_param_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_size (io_protocol_bits_size_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_source (io_protocol_bits_source_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_sink (io_protocol_bits_sink_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_denied (io_protocol_bits_denied_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_data (io_protocol_bits_data_0), // @[TLChannelCompactor.scala:130:7]
.io_enq_bits_corrupt (io_protocol_bits_corrupt_0), // @[TLChannelCompactor.scala:130:7]
.io_deq_ready (_q_io_deq_ready_T_2), // @[TLChannelCompactor.scala:62:35]
.io_deq_valid (_q_io_deq_valid),
.io_deq_bits_opcode (_q_io_deq_bits_opcode),
.io_deq_bits_param (_q_io_deq_bits_param),
.io_deq_bits_size (_q_io_deq_bits_size),
.io_deq_bits_source (_q_io_deq_bits_source),
.io_deq_bits_sink (_q_io_deq_bits_sink),
.io_deq_bits_denied (_q_io_deq_bits_denied),
.io_deq_bits_data (_q_io_deq_bits_data),
.io_deq_bits_corrupt (_q_io_deq_bits_corrupt)
); // @[TLChannelCompactor.scala:47:17]
assign io_beat_valid_0 = _q_io_deq_valid; // @[TLChannelCompactor.scala:47:17, :130:7]
assign io_protocol_ready = io_protocol_ready_0; // @[TLChannelCompactor.scala:130:7]
assign io_beat_valid = io_beat_valid_0; // @[TLChannelCompactor.scala:130:7]
assign io_beat_bits_payload = io_beat_bits_payload_0; // @[TLChannelCompactor.scala:130:7]
assign io_beat_bits_head = io_beat_bits_head_0; // @[TLChannelCompactor.scala:130:7]
assign io_beat_bits_tail = io_beat_bits_tail_0; // @[TLChannelCompactor.scala:130:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_211( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_454( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_198 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_5(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_24( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_5_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_4_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14]
input io_out_credit_available_5_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_4_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_12, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_13, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_16, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_17, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_5_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_4_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'hE; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_4 = {2'h0, {2{_route_buffer_io_enq_bits_flow_egress_node_id_T}}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0); // @[Mux.scala:30:73]
wire [2:0] _GEN_0 = {_route_buffer_io_enq_bits_flow_egress_node_T_4[3], _route_buffer_io_enq_bits_flow_egress_node_T_4[1:0]}; // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_0 == 3'h4; // @[Decoupled.scala:51:35]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_0 != 3'h4; // @[Decoupled.scala:51:35]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_7( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_75 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_81 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1339 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1339; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1339; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1412 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1412; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1412; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1412; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1265 = _T_1339 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1265 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1265 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1265 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1265 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1265 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1311 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1311 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1280 = _T_1412 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1280 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1280 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1280 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1383 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1383 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1365 = _T_1412 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1365 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1365 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1365 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File PMP.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class PMPConfig extends Bundle {
val l = Bool()
val res = UInt(2.W)
val a = UInt(2.W)
val x = Bool()
val w = Bool()
val r = Bool()
}
object PMP {
def lgAlign = 2
def apply(reg: PMPReg): PMP = {
val pmp = Wire(new PMP()(reg.p))
pmp.cfg := reg.cfg
pmp.addr := reg.addr
pmp.mask := pmp.computeMask
pmp
}
}
class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
val cfg = new PMPConfig
val addr = UInt((paddrBits - PMP.lgAlign).W)
def reset(): Unit = {
cfg.a := 0.U
cfg.l := 0.U
}
def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {
val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U
Mux(napot, addr | (mask >> 1), ~(~addr | mask))
}
def napot = cfg.a(1)
def torNotNAPOT = cfg.a(0)
def tor = !napot && torNotNAPOT
def cfgLocked = cfg.l
def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor
}
class PMP(implicit p: Parameters) extends PMPReg {
val mask = UInt(paddrBits.W)
import PMP._
def computeMask = {
val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)
Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)
}
private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)
private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U
if (lgMaxSize <= pmpGranularity.log2) {
eval(x, comparand, mask)
} else {
// break up the circuit; the MSB part will be CSE'd
val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)
val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)
val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))
msbMatch && lsbMatch
}
}
private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {
if (lgMaxSize <= pmpGranularity.log2) {
x < comparand
} else {
// break up the circuit; the MSB part will be CSE'd
val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)
val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U
val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)
msbsLess || (msbsEqual && lsbsLess)
}
}
private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =
!boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)
private def upperBoundMatch(x: UInt, lgMaxSize: Int) =
boundMatch(x, 0.U, lgMaxSize)
private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =
prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {
val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)
maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))
}
private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>
f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)
}
private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {
val beginsAfterLower = !(x < prev.comparand)
val beginsAfterUpper = !(x < comparand)
val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)
val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)
endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)
}
// returns whether this PMP completely contains, or contains none of, a page
def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =
Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))
// returns whether this matching PMP fully contains the access
def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {
val lsbMask = UIntToOH1(lgSize, lgMaxSize)
val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U
val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U
val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)
val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U
Mux(napot, pow2Aligned, rangeAligned)
}
// returns whether this PMP matches at least one byte of the access
def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =
Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))
}
class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
def apply(addr: UInt, pgLevel: UInt): Bool = {
pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>
(h && pmp.homogeneous(addr, pgLevel, prev), pmp)
}._1
}
}
class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module
with HasCoreParameters {
override def desiredName = s"PMPChecker_s${lgMaxSize}"
val io = IO(new Bundle {
val prv = Input(UInt(PRV.SZ.W))
val pmp = Input(Vec(nPMPs, new PMP))
val addr = Input(UInt(paddrBits.W))
val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))
val r = Output(Bool())
val w = Output(Bool())
val x = Output(Bool())
})
val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U
val pmp0 = WireInit(0.U.asTypeOf(new PMP))
pmp0.cfg.r := default
pmp0.cfg.w := default
pmp0.cfg.x := default
val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>
val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
val ignore = default && !pmp.cfg.l
val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty)
property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting")
property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting")
// Not including Write and no Read permission as the combination is reserved
for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty)
property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting")
for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) {
property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access")
property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit")
}
val cur = WireInit(pmp)
cur.cfg.r := aligned && (pmp.cfg.r || ignore)
cur.cfg.w := aligned && (pmp.cfg.w || ignore)
cur.cfg.x := aligned && (pmp.cfg.x || ignore)
Mux(hit, cur, prev)
}
io.r := res.cfg.r
io.w := res.cfg.w
io.x := res.cfg.x
}
File TLBPermissions.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder}
import freechips.rocketchip.tilelink.TLManagerParameters
case class TLBPermissions(
homogeneous: Bool, // if false, the below are undefined
r: Bool, // readable
w: Bool, // writeable
x: Bool, // executable
c: Bool, // cacheable
a: Bool, // arithmetic ops
l: Bool) // logical ops
object TLBPageLookup
{
private case class TLBFixedPermissions(
e: Boolean, // get-/put-effects
r: Boolean, // readable
w: Boolean, // writeable
x: Boolean, // executable
c: Boolean, // cacheable
a: Boolean, // arithmetic ops
l: Boolean) { // logical ops
val useful = r || w || x || c || a || l
}
private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = {
val permissions = managers.map { m =>
(m.address, TLBFixedPermissions(
e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType,
r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get
w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put
x = m.executable,
c = m.supportsAcquireB,
a = m.supportsArithmetic,
l = m.supportsLogical))
}
permissions
.filter(_._2.useful) // get rid of no-permission devices
.groupBy(_._2) // group by permission type
.mapValues(seq =>
AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions
.toMap
}
// Unmapped memory is considered to be inhomogeneous
def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = {
require (isPow2(xLen) && xLen >= 8)
require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8)
require (isPow2(pageSize) && pageSize >= cacheBlockBytes)
val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes)
val allSizes = TransferSizes(1, maxRequestBytes)
val amoSizes = TransferSizes(4, xLen/8)
val permissions = managers.foreach { m =>
require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}")
require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}")
require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}")
require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}")
require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)")
}
val grouped = groupRegions(managers)
.mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough
def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = {
val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) }
val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList)
// Find the minimal bits needed to distinguish between yes and no
val decisionMask = AddressDecoder(Seq(yes, no))
def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct)
val (yesf, nof) = (simplify(yes), simplify(no))
if (yesf.size < no.size) {
(x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _)
} else {
(x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _)
}
}
// Derive simplified property circuits (don't care when !homo)
val rfn = lowCostProperty(_.r)
val wfn = lowCostProperty(_.w)
val xfn = lowCostProperty(_.x)
val cfn = lowCostProperty(_.c)
val afn = lowCostProperty(_.a)
val lfn = lowCostProperty(_.l)
val homo = AddressSet.unify(grouped.values.flatten.toList)
(x: UInt) => TLBPermissions(
homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _),
r = rfn(x),
w = wfn(x),
x = xfn(x),
c = cfn(x),
a = afn(x),
l = lfn(x))
}
// Are all pageSize intervals of mapped regions homogeneous?
def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = {
groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize))
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File PTW.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
import chisel3.withClock
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ListBuffer
/** PTE request from TLB to PTW
*
* TLB send a PTE request to PTW when L1TLB miss
*/
class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(vpnBits.W)
val need_gpa = Bool()
val vstage1 = Bool()
val stage2 = Bool()
}
/** PTE info from L2TLB to TLB
*
* containing: target PTE, exceptions, two-satge tanslation info
*/
class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
/** ptw access exception */
val ae_ptw = Bool()
/** final access exception */
val ae_final = Bool()
/** page fault */
val pf = Bool()
/** guest page fault */
val gf = Bool()
/** hypervisor read */
val hr = Bool()
/** hypervisor write */
val hw = Bool()
/** hypervisor execute */
val hx = Bool()
/** PTE to refill L1TLB
*
* source: L2TLB
*/
val pte = new PTE
/** pte pglevel */
val level = UInt(log2Ceil(pgLevels).W)
/** fragmented_superpage support */
val fragmented_superpage = Bool()
/** homogeneous for both pma and pmp */
val homogeneous = Bool()
val gpa = Valid(UInt(vaddrBits.W))
val gpa_is_pte = Bool()
}
/** IO between TLB and PTW
*
* PTW receives :
* - PTE request
* - CSRs info
* - pmp results from PMP(in TLB)
*/
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val req = Decoupled(Valid(new PTWReq))
val resp = Flipped(Valid(new PTWResp))
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val customCSRs = Flipped(coreParams.customCSRs)
}
/** PTW performance statistics */
class PTWPerfEvents extends Bundle {
val l2miss = Bool()
val l2hit = Bool()
val pte_miss = Bool()
val pte_hit = Bool()
}
/** Datapath IO between PTW and Core
*
* PTW receives CSRs info, pmp checks, sfence instruction info
*
* PTW sends its performance statistics to core
*/
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val ptbr = Input(new PTBR())
val hgatp = Input(new PTBR())
val vsatp = Input(new PTBR())
val sfence = Flipped(Valid(new SFenceReq))
val status = Input(new MStatus())
val hstatus = Input(new HStatus())
val gstatus = Input(new MStatus())
val pmp = Input(Vec(nPMPs, new PMP))
val perf = Output(new PTWPerfEvents())
val customCSRs = Flipped(coreParams.customCSRs)
/** enable clock generated by ptw */
val clock_enabled = Output(Bool())
}
/** PTE template for transmission
*
* contains useful methods to check PTE attributes
* @see RV-priv spec 4.3.1 for pgae table entry format
*/
class PTE(implicit p: Parameters) extends CoreBundle()(p) {
val reserved_for_future = UInt(10.W)
val ppn = UInt(44.W)
val reserved_for_software = Bits(2.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** global mapping */
val g = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
/** valid bit */
val v = Bool()
/** return true if find a pointer to next level page table */
def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U
/** return true if find a leaf PTE */
def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a
/** user read */
def ur(dummy: Int = 0) = sr() && u
/** user write*/
def uw(dummy: Int = 0) = sw() && u
/** user execute */
def ux(dummy: Int = 0) = sx() && u
/** supervisor read */
def sr(dummy: Int = 0) = leaf() && r
/** supervisor write */
def sw(dummy: Int = 0) = leaf() && w && d
/** supervisor execute */
def sx(dummy: Int = 0) = leaf() && x
/** full permission: writable and executable in user mode */
def isFullPerm(dummy: Int = 0) = uw() && ux()
}
/** L2TLB PTE template
*
* contains tag bits
* @param nSets number of sets in L2TLB
* @see RV-priv spec 4.3.1 for page table entry format
*/
class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val idxBits = log2Ceil(nSets)
val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0)
val tag = UInt(tagBits.W)
val ppn = UInt(ppnBits.W)
/** dirty bit */
val d = Bool()
/** access bit */
val a = Bool()
/** user mode accessible */
val u = Bool()
/** whether the page is executable */
val x = Bool()
/** whether the page is writable */
val w = Bool()
/** whether the page is readable */
val r = Bool()
}
/** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC)
*
* It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb.
* Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process.
*
* ==Structure==
* - l2tlb : for leaf PTEs
* - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]]))
* - PLRU
* - pte_cache: for non-leaf PTEs
* - set-associative
* - LRU
* - s2_pte_cache: for non-leaf PTEs in 2-stage translation
* - set-associative
* - PLRU
*
* l2tlb Pipeline: 3 stage
* {{{
* stage 0 : read
* stage 1 : decode
* stage 2 : hit check
* }}}
* ==State Machine==
* s_ready: ready to reveive request from TLB
* s_req: request mem; pte_cache hit judge
* s_wait1: deal with l2tlb error
* s_wait2: final hit judge
* s_wait3: receive mem response
* s_fragment_superpage: for superpage PTE
*
* @note l2tlb hit happens in s_req or s_wait1
* @see RV-priv spec 4.3-4.6 for Virtual-Memory System
* @see RV-priv spec 8.5 for Two-Stage Address Translation
* @todo details in two-stage translation
*/
class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
/** to n TLB */
val requestor = Flipped(Vec(n, new TLBPTWIO))
/** to HellaCache */
val mem = new HellaCacheIO
/** to Core
*
* contains CSRs info and performance statistics
*/
val dpath = new DatapathPTWIO
})
val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8)
val state = RegInit(s_ready)
val l2_refill_wire = Wire(Bool())
/** Arbiter to arbite request from n TLB */
val arb = Module(new Arbiter(Valid(new PTWReq), n))
// use TLB req as arbitor's input
arb.io.in <> io.requestor.map(_.req)
// receive req only when s_ready and not in refill
arb.io.out.ready := (state === s_ready) && !l2_refill_wire
val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B)))
val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate
io.dpath.clock_enabled := usingVM.B && clock_en
val gated_clock =
if (!usingVM || !tileParams.dcache.get.clockGate) clock
else ClockGate(clock, clock_en, "ptw_clock_gate")
withClock (gated_clock) { // entering gated-clock domain
val invalidated = Reg(Bool())
/** current PTE level
* {{{
* 0 <= count <= pgLevel-1
* count = pgLevel - 1 : leaf PTE
* count < pgLevel - 1 : non-leaf PTE
* }}}
*/
val count = Reg(UInt(log2Ceil(pgLevels).W))
val resp_ae_ptw = Reg(Bool())
val resp_ae_final = Reg(Bool())
val resp_pf = Reg(Bool())
val resp_gf = Reg(Bool())
val resp_hr = Reg(Bool())
val resp_hw = Reg(Bool())
val resp_hx = Reg(Bool())
val resp_fragmented_superpage = Reg(Bool())
/** tlb request */
val r_req = Reg(new PTWReq)
/** current selected way in arbitor */
val r_req_dest = Reg(Bits())
// to respond to L1TLB : l2_hit
// to construct mem.req.addr
val r_pte = Reg(new PTE)
val r_hgatp = Reg(new PTBR)
// 2-stage pageLevel
val aux_count = Reg(UInt(log2Ceil(pgLevels).W))
/** pte for 2-stage translation */
val aux_pte = Reg(new PTE)
val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case
val stage2 = Reg(Bool())
val stage2_final = Reg(Bool())
val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels
/** 2-stage translation both enable */
val do_both_stages = r_req.vstage1 && r_req.stage2
val max_count = count max aux_count
val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr)
val mem_resp_valid = RegNext(io.mem.resp.valid)
val mem_resp_data = RegNext(io.mem.resp.bits.data)
io.mem.uncached_resp.map { resp =>
assert(!(resp.valid && io.mem.resp.valid))
resp.ready := true.B
when (resp.valid) {
mem_resp_valid := true.B
mem_resp_data := resp.bits.data
}
}
// construct pte from mem.resp
val (pte, invalid_paddr, invalid_gpa) = {
val tmp = mem_resp_data.asTypeOf(new PTE())
val res = WireDefault(tmp)
res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0))
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B }
}
(res,
Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U),
do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn))
}
// find non-leaf PTE, need traverse
val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U
/** address send to mem for enquerry */
val pte_addr = if (!usingVM) 0.U else {
val vpn_idxs = (0 until pgLevels).map { i =>
val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0)
(vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0)
}
val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U)
val vpn_idx = vpn_idxs(count) & mask
val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8)
val size = if (usingHypervisor) vaddrBits else paddrBits
//use r_pte.ppn as page table base address
//use vpn slice as offset
raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0)
}
/** stage2_pte_cache input addr */
val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else {
val vpn_idxs = (0 until pgLevels - 1).map { i =>
(r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0)
}
val vpn_idx = vpn_idxs(aux_count)
val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8)
raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0)
}
def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = {
(pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i)))
}
/** PTECache caches non-leaf PTE
* @param s2 true: 2-stage address translation
*/
def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) {
(false.B, 0.U)
} else {
val plru = new PseudoLRU(coreParams.nPTECacheEntries)
val valid = RegInit(0.U(coreParams.nPTECacheEntries.W))
val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W)))
// not include full pte, only ppn
val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W)))
val can_hit =
if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final
else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2)
val can_refill =
if (s2) do_both_stages && !stage2 && !stage2_final
else can_hit
val tag =
if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits))
else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits))
val hits = tags.map(_ === tag).asUInt & valid
val hit = hits.orR && can_hit
// refill with mem response
when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) {
val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid))
valid := valid | UIntToOH(r)
tags(r) := tag
data(r) := pte.ppn
plru.access(r)
}
// replace
when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U }
val lcount = if (s2) aux_count else count
for (i <- 0 until pgLevels-1) {
ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i")
}
(hit, Mux1H(hits, data))
}
// generate pte_cache
val (pte_cache_hit, pte_cache_data) = makePTECache(false)
// generate pte_cache with 2-stage translation
val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true)
// pte_cache hit or 2-stage pte_cache hit
val pte_hit = RegNext(false.B)
io.dpath.perf.pte_miss := false.B
io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit
assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),
"PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event")
// l2_refill happens when find the leaf pte
val l2_refill = RegNext(false.B)
l2_refill_wire := l2_refill
io.dpath.perf.l2miss := false.B
io.dpath.perf.l2hit := false.B
// l2tlb
val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else {
val code = new ParityCode
require(isPow2(coreParams.nL2TLBEntries))
require(isPow2(coreParams.nL2TLBWays))
require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays)
val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays
require(isPow2(nL2TLBSets))
val idxBits = log2Ceil(nL2TLBSets)
val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru")
val ram = DescribedSRAM(
name = "l2_tlb_ram",
desc = "L2 TLB",
size = nL2TLBSets,
data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W))
)
val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W)))
val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W))))
// use r_req to construct tag
val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits)
/** the valid vec for the selected set(including n ways) */
val r_valid_vec = valid.map(_(r_idx)).asUInt
val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W))
val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W))
r_valid_vec_q := r_valid_vec
// replacement way
r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U)
// refill with r_pte(leaf pte)
when (l2_refill && !invalidated) {
val entry = Wire(new L2TLBEntry(nL2TLBSets))
entry.ppn := r_pte.ppn
entry.d := r_pte.d
entry.a := r_pte.a
entry.u := r_pte.u
entry.x := r_pte.x
entry.w := r_pte.w
entry.r := r_pte.r
entry.tag := r_tag
// if all the way are valid, use plru to select one way to be replaced,
// otherwise use PriorityEncoderOH to select one
val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W)
ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools)
val mask = UIntToOH(r_idx)
for (way <- 0 until coreParams.nL2TLBWays) {
when (wmask(way)) {
valid(way) := valid(way) | mask
g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask)
}
}
}
// sfence happens
when (io.dpath.sfence.valid) {
val hg = usingHypervisor.B && io.dpath.sfence.bits.hg
for (way <- 0 until coreParams.nL2TLBWays) {
valid(way) :=
Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way),
0.U))
}
}
val s0_valid = !l2_refill && arb.io.out.fire
val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa
val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid)
val s2_valid = RegNext(s1_valid)
// read from tlb idx
val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid)
val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid)))
val s2_valid_vec = RegEnable(r_valid_vec, s1_valid)
val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid)
val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR
when (s2_valid && s2_error) { valid.foreach { _ := 0.U }}
// decode
val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets)))
val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag))
val s2_hit = s2_valid && s2_hit_vec.orR
io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR)
io.dpath.perf.l2hit := s2_hit
when (s2_hit) {
l2_plru.access(r_idx, OHToUInt(s2_hit_vec))
assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit")
}
val s2_pte = Wire(new PTE)
val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec)
s2_pte.ppn := s2_hit_entry.ppn
s2_pte.d := s2_hit_entry.d
s2_pte.a := s2_hit_entry.a
s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec)
s2_pte.u := s2_hit_entry.u
s2_pte.x := s2_hit_entry.x
s2_pte.w := s2_hit_entry.w
s2_pte.r := s2_hit_entry.r
s2_pte.v := true.B
s2_pte.reserved_for_future := 0.U
s2_pte.reserved_for_software := 0.U
for (way <- 0 until coreParams.nL2TLBWays) {
ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way")
}
(s2_hit, s2_error, s2_pte, Some(ram))
}
// if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk
invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready)
// mem request
io.mem.keep_clock_enabled := false.B
io.mem.req.valid := state === s_req || state === s_dummy1
io.mem.req.bits.phys := true.B
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.size := log2Ceil(xLen/8).U
io.mem.req.bits.signed := false.B
io.mem.req.bits.addr := pte_addr
io.mem.req.bits.idx.foreach(_ := pte_addr)
io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition
io.mem.req.bits.dv := do_both_stages && !stage2
io.mem.req.bits.tag := DontCare
io.mem.req.bits.no_resp := false.B
io.mem.req.bits.no_alloc := DontCare
io.mem.req.bits.no_xcpt := DontCare
io.mem.req.bits.data := DontCare
io.mem.req.bits.mask := DontCare
io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf
io.mem.s1_data := DontCare
io.mem.s2_kill := false.B
val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}")
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits))
if (pageGranularityPMPs && i == pgLevels - 1) {
require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned")
true.B
} else {
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous
}
}
val pmaHomogeneous = pmaPgLevelHomogeneous(count)
val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count)
val homogeneous = pmaHomogeneous && pmpHomogeneous
// response to tlb
for (i <- 0 until io.requestor.size) {
io.requestor(i).resp.valid := resp_valid(i)
io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw
io.requestor(i).resp.bits.ae_final := resp_ae_final
io.requestor(i).resp.bits.pf := resp_pf
io.requestor(i).resp.bits.gf := resp_gf
io.requestor(i).resp.bits.hr := resp_hr
io.requestor(i).resp.bits.hw := resp_hw
io.requestor(i).resp.bits.hx := resp_hx
io.requestor(i).resp.bits.pte := r_pte
io.requestor(i).resp.bits.level := max_count
io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B
io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B
io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa
io.requestor(i).resp.bits.gpa.bits :=
Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff)
io.requestor(i).resp.bits.gpa_is_pte := !stage2_final
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).hgatp := io.dpath.hgatp
io.requestor(i).vsatp := io.dpath.vsatp
io.requestor(i).customCSRs <> io.dpath.customCSRs
io.requestor(i).status := io.dpath.status
io.requestor(i).hstatus := io.dpath.hstatus
io.requestor(i).gstatus := io.dpath.gstatus
io.requestor(i).pmp := io.dpath.pmp
}
// control state machine
val next_state = WireDefault(state)
state := OptimizationBarrier(next_state)
val do_switch = WireDefault(false.B)
switch (state) {
is (s_ready) {
when (arb.io.out.fire) {
val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels
val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels
val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels
val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
r_req := arb.io.out.bits.bits
r_req_dest := arb.io.chosen
next_state := Mux(arb.io.out.bits.valid, s_req, s_ready)
stage2 := arb.io.out.bits.bits.stage2
stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1
count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U)
aux_pte.ppn := aux_ppn
aux_pte.reserved_for_future := 0.U
resp_ae_ptw := false.B
resp_ae_final := false.B
resp_pf := false.B
resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2
resp_hr := true.B
resp_hw := true.B
resp_hx := true.B
resp_fragmented_superpage := false.B
r_hgatp := io.dpath.hgatp
assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)
}
}
is (s_req) {
when(stage2 && count === r_hgatp_initial_count) {
gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr)
}
// pte_cache hit
when (stage2_pte_cache_hit) {
aux_count := aux_count + 1.U
aux_pte.ppn := stage2_pte_cache_data
aux_pte.reserved_for_future := 0.U
pte_hit := true.B
}.elsewhen (pte_cache_hit) {
count := count + 1.U
pte_hit := true.B
}.otherwise {
next_state := Mux(io.mem.req.ready, s_wait1, s_req)
}
when(resp_gf) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_wait1) {
// This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below
next_state := Mux(l2_hit, s_req, s_wait2)
}
is (s_wait2) {
next_state := s_wait3
io.dpath.perf.pte_miss := count < (pgLevels-1).U
when (io.mem.s2_xcpt.ae.ld) {
resp_ae_ptw := true.B
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
}
is (s_fragment_superpage) {
next_state := s_ready
resp_valid(r_req_dest) := true.B
when (!homogeneous) {
count := (pgLevels-1).U
resp_fragmented_superpage := true.B
}
when (do_both_stages) {
resp_fragmented_superpage := true.B
}
}
}
val merged_pte = {
val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U)
val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U))
val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn
val stage1_ppn = stage1_ppns(count)
makePTE(stage1_ppn & superpage_mask, aux_pte)
}
r_pte := OptimizationBarrier(
// l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB
Mux(l2_hit && !l2_error && !resp_gf, l2_pte,
// S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp
Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte),
// pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem
Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte),
// 2-stage translation
Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte),
// when mem respond, store mem.resp.pte
Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte),
// fragment_superpage
Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte),
// when tlb request come->request mem, use root address in satp(or vsatp,hgatp)
Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)),
r_pte))))))))
when (l2_hit && !l2_error && !resp_gf) {
assert(state === s_req || state === s_wait1)
next_state := s_ready
resp_valid(r_req_dest) := true.B
count := (pgLevels-1).U
}
when (mem_resp_valid) {
assert(state === s_wait3)
next_state := s_req
when (traverse) {
when (do_both_stages && !stage2) { do_switch := true.B }
count := count + 1.U
}.otherwise {
val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa)
val ae = pte.v && invalid_paddr
val pf = pte.v && pte.reserved_for_future =/= 0.U
val success = pte.v && !ae && !pf && !gf
when (do_both_stages && !stage2_final && success) {
when (stage2) {
stage2 := false.B
count := aux_count
}.otherwise {
stage2_final := true.B
do_switch := true.B
}
}.otherwise {
// find a leaf pte, start l2 refill
l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa &&
(!r_req.vstage1 && !r_req.stage2 ||
do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm())
count := max_count
when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) {
next_state := s_fragment_superpage
}.otherwise {
next_state := s_ready
resp_valid(r_req_dest) := true.B
}
resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table()
resp_ae_final := ae && pte.leaf()
resp_pf := pf && !stage2
resp_gf := gf || (pf && stage2)
resp_hr := !stage2 || (!pf && !gf && pte.ur())
resp_hw := !stage2 || (!pf && !gf && pte.uw())
resp_hx := !stage2 || (!pf && !gf && pte.ux())
}
}
}
when (io.mem.s2_nack) {
assert(state === s_wait2)
next_state := s_req
}
when (do_switch) {
aux_count := Mux(traverse, count + 1.U, count)
count := r_hgatp_initial_count
aux_pte := Mux(traverse, pte, {
val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn
makePTE(s1_ppns(count), pte)
})
stage2 := true.B
}
for (i <- 0 until pgLevels) {
val leaf = mem_resp_valid && !traverse && count === i.U
ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i")
ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i")
ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i")
ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i")
ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i")
if (i != pgLevels-1)
ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i")
}
ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep")
ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
} // leaving gated-clock domain
private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
/** Relace PTE.ppn with ppn */
private def makePTE(ppn: UInt, default: PTE) = {
val pte = WireDefault(default)
pte.ppn := ppn
pte
}
/** use hgatp and vpn to construct a new ppn */
private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits))
val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count))
val pte = WireDefault(default)
pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs)
pte
}
/** use hgatp and vpn to check for gpa out of range */
private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits))
idxs.extract(count) =/= 0.U
}
}
/** Mix-ins for constructing tiles that might have a PTW */
trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
val module: CanHavePTWModule
var nPTWPorts = 1
nDCachePorts += usingPTW.toInt
}
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
ptw.io.mem <> DontCare
if (outer.usingPTW) {
dcachePorts += ptw.io.mem
}
}
| module PTW_4( // @[PTW.scala:219:7]
input clock, // @[PTW.scala:219:7]
input reset, // @[PTW.scala:219:7]
output io_requestor_0_req_ready, // @[PTW.scala:220:14]
input io_requestor_0_req_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_0_resp_valid, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14]
output [15:0] io_requestor_0_ptbr_asid, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_0_status_debug, // @[PTW.scala:220:14]
output io_requestor_0_status_cease, // @[PTW.scala:220:14]
output io_requestor_0_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14]
output io_requestor_0_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14]
output io_requestor_0_status_v, // @[PTW.scala:220:14]
output io_requestor_0_status_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_0_status_zero2, // @[PTW.scala:220:14]
output io_requestor_0_status_mpv, // @[PTW.scala:220:14]
output io_requestor_0_status_gva, // @[PTW.scala:220:14]
output io_requestor_0_status_mbe, // @[PTW.scala:220:14]
output io_requestor_0_status_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_sxl, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_uxl, // @[PTW.scala:220:14]
output io_requestor_0_status_sd_rv32, // @[PTW.scala:220:14]
output [7:0] io_requestor_0_status_zero1, // @[PTW.scala:220:14]
output io_requestor_0_status_tsr, // @[PTW.scala:220:14]
output io_requestor_0_status_tw, // @[PTW.scala:220:14]
output io_requestor_0_status_tvm, // @[PTW.scala:220:14]
output io_requestor_0_status_mxr, // @[PTW.scala:220:14]
output io_requestor_0_status_sum, // @[PTW.scala:220:14]
output io_requestor_0_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_xs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_vs, // @[PTW.scala:220:14]
output io_requestor_0_status_spp, // @[PTW.scala:220:14]
output io_requestor_0_status_mpie, // @[PTW.scala:220:14]
output io_requestor_0_status_ube, // @[PTW.scala:220:14]
output io_requestor_0_status_spie, // @[PTW.scala:220:14]
output io_requestor_0_status_upie, // @[PTW.scala:220:14]
output io_requestor_0_status_mie, // @[PTW.scala:220:14]
output io_requestor_0_status_hie, // @[PTW.scala:220:14]
output io_requestor_0_status_sie, // @[PTW.scala:220:14]
output io_requestor_0_status_uie, // @[PTW.scala:220:14]
input io_mem_req_ready, // @[PTW.scala:220:14]
output io_mem_req_valid, // @[PTW.scala:220:14]
output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14]
output io_mem_req_bits_dv, // @[PTW.scala:220:14]
output io_mem_s1_kill, // @[PTW.scala:220:14]
input io_mem_s2_nack, // @[PTW.scala:220:14]
input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14]
input io_mem_s2_uncached, // @[PTW.scala:220:14]
input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14]
input io_mem_resp_valid, // @[PTW.scala:220:14]
input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14]
input [7:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14]
input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14]
input io_mem_resp_bits_signed, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14]
input io_mem_resp_bits_dv, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14]
input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14]
input io_mem_resp_bits_replay, // @[PTW.scala:220:14]
input io_mem_resp_bits_has_data, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14]
input io_mem_replay_next, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14]
input [39:0] io_mem_s2_gpa, // @[PTW.scala:220:14]
input io_mem_ordered, // @[PTW.scala:220:14]
input io_mem_store_pending, // @[PTW.scala:220:14]
input io_mem_perf_acquire, // @[PTW.scala:220:14]
input io_mem_perf_release, // @[PTW.scala:220:14]
input io_mem_perf_grant, // @[PTW.scala:220:14]
input io_mem_perf_tlbMiss, // @[PTW.scala:220:14]
input io_mem_perf_blocked, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14]
input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14]
input [15:0] io_dpath_ptbr_asid, // @[PTW.scala:220:14]
input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14]
input io_dpath_sfence_valid, // @[PTW.scala:220:14]
input io_dpath_status_debug, // @[PTW.scala:220:14]
input io_dpath_status_cease, // @[PTW.scala:220:14]
input io_dpath_status_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14]
input io_dpath_status_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14]
input io_dpath_status_v, // @[PTW.scala:220:14]
input io_dpath_status_sd, // @[PTW.scala:220:14]
input [22:0] io_dpath_status_zero2, // @[PTW.scala:220:14]
input io_dpath_status_mpv, // @[PTW.scala:220:14]
input io_dpath_status_gva, // @[PTW.scala:220:14]
input io_dpath_status_mbe, // @[PTW.scala:220:14]
input io_dpath_status_sbe, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_sxl, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_uxl, // @[PTW.scala:220:14]
input io_dpath_status_sd_rv32, // @[PTW.scala:220:14]
input [7:0] io_dpath_status_zero1, // @[PTW.scala:220:14]
input io_dpath_status_tsr, // @[PTW.scala:220:14]
input io_dpath_status_tw, // @[PTW.scala:220:14]
input io_dpath_status_tvm, // @[PTW.scala:220:14]
input io_dpath_status_mxr, // @[PTW.scala:220:14]
input io_dpath_status_sum, // @[PTW.scala:220:14]
input io_dpath_status_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_xs, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_vs, // @[PTW.scala:220:14]
input io_dpath_status_spp, // @[PTW.scala:220:14]
input io_dpath_status_mpie, // @[PTW.scala:220:14]
input io_dpath_status_ube, // @[PTW.scala:220:14]
input io_dpath_status_spie, // @[PTW.scala:220:14]
input io_dpath_status_upie, // @[PTW.scala:220:14]
input io_dpath_status_mie, // @[PTW.scala:220:14]
input io_dpath_status_hie, // @[PTW.scala:220:14]
input io_dpath_status_sie, // @[PTW.scala:220:14]
input io_dpath_status_uie, // @[PTW.scala:220:14]
output io_dpath_perf_pte_miss, // @[PTW.scala:220:14]
output io_dpath_clock_enabled // @[PTW.scala:220:14]
);
wire tmp_r; // @[PTW.scala:304:37]
wire tmp_w; // @[PTW.scala:304:37]
wire tmp_x; // @[PTW.scala:304:37]
wire tmp_u; // @[PTW.scala:304:37]
wire tmp_g; // @[PTW.scala:304:37]
wire tmp_a; // @[PTW.scala:304:37]
wire tmp_d; // @[PTW.scala:304:37]
wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37]
wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37]
wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25]
wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25]
wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_d; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_a; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_g; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_u; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_x; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_w; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_r; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_v; // @[package.scala:267:25]
wire [2:0] _state_barrier_io_y; // @[package.scala:267:25]
wire _arb_io_out_valid; // @[PTW.scala:236:19]
wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19]
wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19]
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7]
wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7]
wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7]
wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7]
wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7]
wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7]
wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7]
wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7]
wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7]
wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7]
wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7]
wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7]
wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7]
wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7]
wire [15:0] io_dpath_ptbr_asid_0 = io_dpath_ptbr_asid; // @[PTW.scala:219:7]
wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7]
wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7]
wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7]
wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7]
wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7]
wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7]
wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7]
wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7]
wire [22:0] io_dpath_status_zero2_0 = io_dpath_status_zero2; // @[PTW.scala:219:7]
wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7]
wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7]
wire io_dpath_status_mbe_0 = io_dpath_status_mbe; // @[PTW.scala:219:7]
wire io_dpath_status_sbe_0 = io_dpath_status_sbe; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_sxl_0 = io_dpath_status_sxl; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_uxl_0 = io_dpath_status_uxl; // @[PTW.scala:219:7]
wire io_dpath_status_sd_rv32_0 = io_dpath_status_sd_rv32; // @[PTW.scala:219:7]
wire [7:0] io_dpath_status_zero1_0 = io_dpath_status_zero1; // @[PTW.scala:219:7]
wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7]
wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7]
wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7]
wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7]
wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7]
wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_xs_0 = io_dpath_status_xs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_vs_0 = io_dpath_status_vs; // @[PTW.scala:219:7]
wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7]
wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7]
wire io_dpath_status_ube_0 = io_dpath_status_ube; // @[PTW.scala:219:7]
wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7]
wire io_dpath_status_upie_0 = io_dpath_status_upie; // @[PTW.scala:219:7]
wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7]
wire io_dpath_status_hie_0 = io_dpath_status_hie; // @[PTW.scala:219:7]
wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7]
wire io_dpath_status_uie_0 = io_dpath_status_uie; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spvp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_debug = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_cease = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_wfi = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_dv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_v = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mxr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sum = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mprv = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spp = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_uie = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs1 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs2 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_asid = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hg = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spvp = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_debug = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_cease = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_wfi = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_dv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_v = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_gva = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mxr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sum = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mprv = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spp = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_ube = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_upie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_hie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_uie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_hit = 1'h0; // @[PTW.scala:219:7]
wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35]
wire _io_dpath_perf_pte_hit_T_1 = 1'h0; // @[PTW.scala:394:36]
wire _io_dpath_perf_pte_hit_T_3 = 1'h0; // @[PTW.scala:394:57]
wire l2_pte_d = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_a = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_g = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_u = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_x = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_w = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_r = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_v = 1'h0; // @[PTW.scala:403:113]
wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40]
wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53]
wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71]
wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16]
wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29]
wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25]
wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58]
wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26]
wire _r_pte_T_7 = 1'h0; // @[PTW.scala:674:25]
wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26]
wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7]
wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7]
wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7]
wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60]
wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_109 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56]
wire _r_pte_T = 1'h1; // @[PTW.scala:670:19]
wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113]
wire [43:0] r_pte_pte_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] _r_pte_pte_ppn_T_1 = 44'h0; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_1_ppn = 44'h0; // @[PTW.scala:771:26]
wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19]
wire [41:0] _r_pte_pte_ppn_T = 42'h0; // @[PTW.scala:781:30]
wire [41:0] _r_pte_pte_ppn_T_2 = 42'h0; // @[PTW.scala:781:30]
wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30]
wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40]
wire [1:0] io_requestor_0_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_dprv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_prv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_sxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_fs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_mpp = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_vsxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_dprv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_prv = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_sxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_uxl = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_fs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_mpp = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42]
wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58]
wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44]
wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113]
wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45]
wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61]
wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46]
wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62]
wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46]
wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62]
wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27]
wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27]
wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44]
wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40]
wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27]
wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26]
wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26]
wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27]
wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_gstatus_isa = 32'h0; // @[PTW.scala:219:7]
wire [31:0] io_dpath_gstatus_isa = 32'h0; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40]
wire [22:0] io_requestor_0_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_dpath_gstatus_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_req_bits_tag = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_dpath_gstatus_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7]
wire [38:0] io_dpath_sfence_bits_addr = 39'h0; // @[PTW.scala:219:7]
wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58]
wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42]
wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58]
wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45]
wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61]
wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46]
wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62]
wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46]
wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62]
wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44]
wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113]
wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26]
wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26]
wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24]
wire [2:0] _next_state_T = 3'h1; // @[PTW.scala:593:26]
wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23]
wire [1:0] max_count; // @[PTW.scala:289:25]
wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39]
wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40]
wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51]
wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17]
wire [15:0] io_requestor_0_ptbr_asid_0 = io_dpath_ptbr_asid_0; // @[PTW.scala:219:7]
wire [15:0] satp_asid = io_dpath_ptbr_asid_0; // @[PTW.scala:219:7, :285:17]
wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17]
wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_0_status_zero2_0 = io_dpath_status_zero2_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mbe_0 = io_dpath_status_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sbe_0 = io_dpath_status_sbe_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_sxl_0 = io_dpath_status_sxl_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_uxl_0 = io_dpath_status_uxl_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_rv32_0 = io_dpath_status_sd_rv32_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_status_zero1_0 = io_dpath_status_zero1_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_xs_0 = io_dpath_status_xs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_vs_0 = io_dpath_status_vs_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_ube_0 = io_dpath_status_ube_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_upie_0 = io_dpath_status_upie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_hie_0 = io_dpath_status_hie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_uie_0 = io_dpath_status_uie_0; // @[PTW.scala:219:7]
wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39]
wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7]
wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7]
wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7]
wire io_mem_req_valid_0; // @[PTW.scala:219:7]
wire io_mem_s1_kill_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7]
wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7]
reg [2:0] state; // @[PTW.scala:233:22]
wire l2_refill_wire; // @[PTW.scala:234:28]
wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30]
wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46]
wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}]
reg resp_valid_0; // @[PTW.scala:242:27]
assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27]
wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24]
wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}]
wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}]
wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}]
wire clock_en = _clock_en_T_3; // @[PTW.scala:244:{74,99}]
assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39]
assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39]
reg invalidated; // @[PTW.scala:251:24]
reg [1:0] count; // @[PTW.scala:259:18]
wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21]
reg resp_ae_ptw; // @[PTW.scala:260:24]
assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
reg resp_ae_final; // @[PTW.scala:261:26]
assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
reg resp_pf; // @[PTW.scala:262:20]
assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
reg resp_gf; // @[PTW.scala:263:20]
assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
reg resp_hr; // @[PTW.scala:264:20]
assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
reg resp_hw; // @[PTW.scala:265:20]
assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
reg resp_hx; // @[PTW.scala:266:20]
assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
reg resp_fragmented_superpage; // @[PTW.scala:267:38]
reg [26:0] r_req_addr; // @[PTW.scala:270:18]
reg r_req_need_gpa; // @[PTW.scala:270:18]
assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
reg r_req_vstage1; // @[PTW.scala:270:18]
reg r_req_stage2; // @[PTW.scala:270:18]
reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
reg [43:0] r_pte_ppn; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
reg r_pte_d; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
reg r_pte_a; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
reg r_pte_g; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
reg r_pte_u; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
reg r_pte_x; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
reg r_pte_w; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
reg r_pte_r; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
reg r_pte_v; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
reg [1:0] aux_count; // @[PTW.scala:278:22]
wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20]
wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26]
reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20]
reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20]
wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26]
reg aux_pte_d; // @[PTW.scala:280:20]
wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26]
reg aux_pte_a; // @[PTW.scala:280:20]
wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26]
reg aux_pte_g; // @[PTW.scala:280:20]
wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26]
reg aux_pte_u; // @[PTW.scala:280:20]
wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26]
reg aux_pte_x; // @[PTW.scala:280:20]
wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26]
reg aux_pte_w; // @[PTW.scala:280:20]
wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26]
reg aux_pte_r; // @[PTW.scala:280:20]
wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26]
reg aux_pte_v; // @[PTW.scala:280:20]
wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26]
reg [11:0] gpa_pgoff; // @[PTW.scala:281:22]
reg stage2; // @[PTW.scala:282:19]
reg stage2_final; // @[PTW.scala:283:25]
wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26]
wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38]
wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25]
assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25]
assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31]
wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}]
wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12]
reg mem_resp_valid; // @[PTW.scala:292:31]
reg [63:0] mem_resp_data; // @[PTW.scala:293:30]
wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37]
wire [9:0] _tmp_T_10; // @[PTW.scala:304:37]
wire [43:0] _tmp_T_9; // @[PTW.scala:304:37]
wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26]
wire [1:0] _tmp_T_8; // @[PTW.scala:304:37]
wire _tmp_T_7; // @[PTW.scala:304:37]
wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_6; // @[PTW.scala:304:37]
wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_5; // @[PTW.scala:304:37]
wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_4; // @[PTW.scala:304:37]
wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_3; // @[PTW.scala:304:37]
wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_2; // @[PTW.scala:304:37]
wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_1; // @[PTW.scala:304:37]
wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26]
wire _tmp_T; // @[PTW.scala:304:37]
wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26]
wire [43:0] tmp_ppn; // @[PTW.scala:304:37]
wire tmp_v; // @[PTW.scala:304:37]
assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37]
assign tmp_v = _tmp_T; // @[PTW.scala:304:37]
assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37]
assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37]
assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37]
assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37]
assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37]
assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37]
assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37]
assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37]
assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37]
assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37]
assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37]
assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37]
assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37]
assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37]
assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37]
assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37]
assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37]
assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37]
assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37]
assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37]
wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26]
wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26]
wire [43:0] pte_ppn; // @[PTW.scala:305:26]
wire pte_v; // @[PTW.scala:305:26]
wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26]
wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38]
wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}]
wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54]
wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99]
wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}]
assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}]
assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}]
wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}]
wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58]
wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25]
wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26]
wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}]
wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}]
wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}]
wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}]
wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}]
wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}]
wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33]
wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}]
wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51]
wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}]
wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73]
wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}]
wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}]
wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}]
wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}]
wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40]
wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}]
wire _GEN = count == 2'h1; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T = _GEN; // @[package.scala:39:86]
wire _pmaHomogeneous_T; // @[package.scala:39:86]
assign _pmaHomogeneous_T = _GEN; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T = _GEN; // @[package.scala:39:86]
wire _aux_pte_T; // @[package.scala:39:86]
assign _aux_pte_T = _GEN; // @[package.scala:39:86]
wire _leaf_T_5; // @[PTW.scala:751:53]
assign _leaf_T_5 = _GEN; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}]
wire _T_129 = count == 2'h2; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T_2 = _T_129; // @[package.scala:39:86]
wire _pmaHomogeneous_T_2; // @[package.scala:39:86]
assign _pmaHomogeneous_T_2 = _T_129; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T_2 = _T_129; // @[package.scala:39:86]
wire _l2_refill_T; // @[PTW.scala:713:39]
assign _l2_refill_T = _T_129; // @[package.scala:39:86]
wire _aux_pte_T_2; // @[package.scala:39:86]
assign _aux_pte_T_2 = _T_129; // @[package.scala:39:86]
wire _leaf_T_8; // @[PTW.scala:751:53]
assign _leaf_T_8 = _T_129; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}]
wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}]
wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76]
wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36]
wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}]
wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}]
wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23]
wire _T_44 = state == 3'h1; // @[PTW.scala:233:22, :394:46]
wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46]
assign _io_dpath_perf_pte_hit_T = _T_44; // @[PTW.scala:394:46]
wire _io_mem_req_valid_T; // @[PTW.scala:515:29]
assign _io_mem_req_valid_T = _T_44; // @[PTW.scala:394:46, :515:29]
wire _r_pte_T_4; // @[PTW.scala:672:15]
assign _r_pte_T_4 = _T_44; // @[PTW.scala:394:46, :672:15]
wire _r_pte_T_6; // @[PTW.scala:674:15]
assign _r_pte_T_6 = _T_44; // @[PTW.scala:394:46, :674:15]
reg l2_refill; // @[PTW.scala:398:26]
assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26]
wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65]
wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}]
wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}]
wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48]
assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}]
assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39]
assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24]
wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43]
assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}]
assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40]
wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38]
wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}]
assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}]
assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51]
wire [55:0] _GEN_0 = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96]
wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T = _GEN_0; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_7 = _GEN_0; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_37 = _GEN_0; // @[PTW.scala:544:96]
wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80]
assign _pmpHomogeneous_T = _GEN_0; // @[PTW.scala:544:96, :548:80]
wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65]
wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}]
wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_98 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65]
wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_43 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_122 = _GEN_1; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_48 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_127 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_159; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_159 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_166; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_166 = _GEN_2; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:18], _pmaPgLevelHomogeneous_T_37[17:0] ^ 18'h20000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:18], _pmaPgLevelHomogeneous_T_37[17:0] ^ 18'h24000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_68 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_78; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_78 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_132; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_132 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_147 = _GEN_3; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_83 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_88 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_89 = {1'h0, _pmaPgLevelHomogeneous_T_88}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_4 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_93; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_93 = _GEN_4; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_137 = _GEN_4; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_152; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_152 = _GEN_4; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_94 = {1'h0, _pmaPgLevelHomogeneous_T_93}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_97 = _pmaPgLevelHomogeneous_T_96 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_99 = _pmaPgLevelHomogeneous_T_98 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_104 = _pmaPgLevelHomogeneous_T_103 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_104 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_106 = _pmaPgLevelHomogeneous_T_105 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107 | _pmaPgLevelHomogeneous_T_92; // @[TLBPermissions.scala:101:65]
wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_108 | _pmaPgLevelHomogeneous_T_97; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_115 = _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_116 = ~_pmaPgLevelHomogeneous_T_115; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_118 = {1'h0, _pmaPgLevelHomogeneous_T_117}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 & 57'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_120 = _pmaPgLevelHomogeneous_T_119; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_121 = _pmaPgLevelHomogeneous_T_120 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_121; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_123 = {1'h0, _pmaPgLevelHomogeneous_T_122}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 & 57'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_125 = _pmaPgLevelHomogeneous_T_124; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_126 = _pmaPgLevelHomogeneous_T_125 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_128 = {1'h0, _pmaPgLevelHomogeneous_T_127}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 & 57'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_129; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_133 = {1'h0, _pmaPgLevelHomogeneous_T_132}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 & 57'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_135 = _pmaPgLevelHomogeneous_T_134; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_136 = _pmaPgLevelHomogeneous_T_135 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_138 = {1'h0, _pmaPgLevelHomogeneous_T_137}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 & 57'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_140 = _pmaPgLevelHomogeneous_T_139; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_141 = _pmaPgLevelHomogeneous_T_140 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142 | _pmaPgLevelHomogeneous_T_126; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 | _pmaPgLevelHomogeneous_T_131; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_144 | _pmaPgLevelHomogeneous_T_136; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_141; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8E020000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_153 = {1'h0, _pmaPgLevelHomogeneous_T_152}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_154 = _pmaPgLevelHomogeneous_T_153 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_155 = _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 | _pmaPgLevelHomogeneous_T_156; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_160 = {1'h0, _pmaPgLevelHomogeneous_T_159}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_161 = _pmaPgLevelHomogeneous_T_160 & 57'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_162 = _pmaPgLevelHomogeneous_T_161; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_163 = _pmaPgLevelHomogeneous_T_162 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_164 = _pmaPgLevelHomogeneous_T_163; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_165 = ~_pmaPgLevelHomogeneous_T_164; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_167 = {1'h0, _pmaPgLevelHomogeneous_T_166}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_168 = _pmaPgLevelHomogeneous_T_167 & 57'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_169 = _pmaPgLevelHomogeneous_T_168; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_170 = _pmaPgLevelHomogeneous_T_169 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_171 = _pmaPgLevelHomogeneous_T_170; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_172 = ~_pmaPgLevelHomogeneous_T_171; // @[TLBPermissions.scala:87:{22,66}]
wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86]
wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}]
wire homogeneous = pmaHomogeneous; // @[package.scala:39:76]
assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :566:15]
wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _T_61 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60]
wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_61; // @[PTW.scala:566:60]
wire _gpa_pgoff_T; // @[PTW.scala:615:36]
assign _gpa_pgoff_T = _T_61; // @[PTW.scala:566:60, :615:36]
wire _l2_refill_T_7; // @[PTW.scala:715:40]
assign _l2_refill_T_7 = _T_61; // @[PTW.scala:566:60, :715:40]
wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :567:45]
assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
wire [2:0] next_state; // @[PTW.scala:579:31]
wire do_switch; // @[PTW.scala:581:30]
wire _T_27 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire _GEN_5 = ~(|state) & _T_27; // @[Decoupled.scala:51:35]
wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38]
wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58]
wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40]
wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40]
wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67]
wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}]
wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32]
wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32]
wire [2:0] _GEN_6 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24]
wire [2:0] _count_T_4; // @[PTW.scala:624:24]
assign _count_T_4 = _GEN_6; // @[PTW.scala:624:24]
wire [2:0] _count_T_6; // @[PTW.scala:696:22]
assign _count_T_6 = _GEN_6; // @[PTW.scala:624:24, :696:22]
wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38]
assign _aux_count_T_3 = _GEN_6; // @[PTW.scala:624:24, :741:38]
wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24]
wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26]
wire _T_36 = state == 3'h2; // @[PTW.scala:233:22, :583:18]
wire _T_37 = state == 3'h4; // @[PTW.scala:233:22, :583:18]
wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39]
wire _GEN_7 = _T_44 | _T_36; // @[PTW.scala:393:26, :394:46, :583:18]
assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_7) & _T_37 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}]
wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45]
wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86]
wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}]
wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64]
wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}]
wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64]
wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}]
wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}]
wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86]
wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76]
wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26]
wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32]
wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58]
wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27]
assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27]
wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26]
assign _r_pte_pte_ppn_T_3 = {42'h0, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:19]
assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29]
wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}]
wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}]
wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15]
wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43]
wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}]
wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65]
wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}]
wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}]
wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}]
wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76]
wire _r_pte_T_25 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26]
wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26]
wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26]
wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35]
wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35]
wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:8, :676:8]
wire [43:0] _r_pte_T_31_ppn = _r_pte_T_30_ppn; // @[PTW.scala:674:8, :676:8]
wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_d = _r_pte_T_30_d; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_a = _r_pte_T_30_a; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_g = _r_pte_T_30_g; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_u = _r_pte_T_30_u; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_x = _r_pte_T_30_x; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_w = _r_pte_T_30_w; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_r = _r_pte_T_30_r; // @[PTW.scala:674:8, :676:8]
wire _r_pte_T_31_v = _r_pte_T_30_v; // @[PTW.scala:674:8, :676:8]
wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8]
wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8]
wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8]
wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:8, :672:8]
wire [43:0] _r_pte_T_33_ppn = _r_pte_T_32_ppn; // @[PTW.scala:670:8, :672:8]
wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_d = _r_pte_T_32_d; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_a = _r_pte_T_32_a; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_g = _r_pte_T_32_g; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_u = _r_pte_T_32_u; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_x = _r_pte_T_32_x; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_w = _r_pte_T_32_w; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_r = _r_pte_T_32_r; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_v = _r_pte_T_32_v; // @[PTW.scala:670:8, :672:8]
wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22]
wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :566:15, :698:27]
wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}]
wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44]
wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}]
wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97]
wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}]
wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}]
wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}]
wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22]
wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49]
wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}]
wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30]
wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}]
wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37]
wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}]
wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44]
wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}]
wire _T_58 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :566:15, :701:41, :703:{28,45}]
assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_58 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21]
wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}]
wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61]
wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}]
wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12]
wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :714:30]
wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}]
wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}]
wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41]
wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}]
wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59]
wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44]
wire _GEN_8 = traverse | _T_58; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19]
wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36]
wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}]
wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26]
wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}]
wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}]
wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}]
wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}]
wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}]
wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}]
wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}]
wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29]
wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26]
wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}]
wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30]
wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}]
wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20]
wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32]
wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39]
wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}]
wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}]
wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}]
wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20]
wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32]
wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39]
wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}]
wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}]
wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}]
wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20]
wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32]
wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39]
wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}]
wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}]
wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_285( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4099:0] _c_sizes_set_T_1 = 4100'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [2055:0] c_sizes_set = 2056'h0; // @[Monitor.scala:741:34]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 9'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 9'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = io_in_d_bits_source_0 == 9'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire _source_ok_T_76 = io_in_d_bits_source_0 == 9'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[8:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2055:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [2055:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [11:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [2055:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [2055:0] _a_size_lookup_T_6 = {2048'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [2055:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[2055:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_3 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1653 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [11:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [4099:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[2055:0] : 2056'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [2055:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1668 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[2055:0] : 2056'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [2055:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [2055:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [2055:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [2055:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [2055:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [2055:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [2055:0] _c_size_lookup_T_6 = {2048'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [2055:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[2055:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [2055:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1753 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[2055:0] : 2056'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [2055:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [2055:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_6( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_6 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_6 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_6 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_197( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module FixedClockBroadcast_3( // @[ClockGroup.scala:104:9]
input auto_anon_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_clock_0 = auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire auto_anon_in_reset_0 = auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire anonIn_clock = auto_anon_in_clock_0; // @[ClockGroup.scala:104:9]
wire anonIn_reset = auto_anon_in_reset_0; // @[ClockGroup.scala:104:9]
wire x1_anonOut_1_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_1_reset; // @[MixedNode.scala:542:17]
wire x1_anonOut_clock; // @[MixedNode.scala:542:17]
wire x1_anonOut_reset; // @[MixedNode.scala:542:17]
wire anonOut_clock; // @[MixedNode.scala:542:17]
wire anonOut_reset; // @[MixedNode.scala:542:17]
wire auto_anon_out_2_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_2_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_1_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_1_reset_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_0_clock_0; // @[ClockGroup.scala:104:9]
wire auto_anon_out_0_reset_0; // @[ClockGroup.scala:104:9]
assign anonOut_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_1_clock = anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_anonOut_1_reset = anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_out_0_clock_0 = anonOut_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_reset_0 = anonOut_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_clock_0 = x1_anonOut_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_reset_0 = x1_anonOut_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_clock_0 = x1_anonOut_1_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_reset_0 = x1_anonOut_1_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_clock = auto_anon_out_2_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_2_reset = auto_anon_out_2_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_clock = auto_anon_out_1_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_reset = auto_anon_out_1_reset_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_clock = auto_anon_out_0_clock_0; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_reset = auto_anon_out_0_reset_0; // @[ClockGroup.scala:104:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
| module TLInterconnectCoupler_cbus_to_clint( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire tlOut_d_valid; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOut_a_ready; // @[MixedNode.scala:542:17]
wire auto_fragmenter_anon_out_a_ready_0 = auto_fragmenter_anon_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_valid_0 = auto_fragmenter_anon_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_d_bits_opcode_0 = auto_fragmenter_anon_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_d_bits_size_0 = auto_fragmenter_anon_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_fragmenter_anon_out_d_bits_source_0 = auto_fragmenter_anon_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_d_bits_data_0 = auto_fragmenter_anon_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [25:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlOut_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_sink = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_denied = 1'h0; // @[Fragmenter.scala:345:34]
wire tlIn_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_fragmenter_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[Fragmenter.scala:345:34]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [25:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [2:0] auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [11:0] auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [25:0] auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [25:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
TLFragmenter_CLINT fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (tlOut_a_ready),
.auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17]
.auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_d_valid (tlOut_d_valid),
.auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode),
.auto_anon_in_d_bits_size (tlOut_d_bits_size),
.auto_anon_in_d_bits_source (tlOut_d_bits_source),
.auto_anon_in_d_bits_data (tlOut_d_bits_data),
.auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_fragmenter_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt_0),
.auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_opcode (auto_fragmenter_anon_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7]
); // @[Fragmenter.scala:345:34]
assign auto_fragmenter_anon_out_a_valid = auto_fragmenter_anon_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_opcode = auto_fragmenter_anon_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_param = auto_fragmenter_anon_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_size = auto_fragmenter_anon_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_source = auto_fragmenter_anon_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_address = auto_fragmenter_anon_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_mask = auto_fragmenter_anon_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_data = auto_fragmenter_anon_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_a_bits_corrupt = auto_fragmenter_anon_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_fragmenter_anon_out_d_ready = auto_fragmenter_anon_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module cc_banks_1( // @[DescribedSRAM.scala:17:26]
input [13:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_38( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] _mask_sizeOH_T_3 = 3'h0; // @[Misc.scala:202:34]
wire [2:0] b_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _b_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _b_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire io_in_b_valid = 1'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _address_ok_T_4 = 1'h0; // @[Parameters.scala:137:59]
wire _address_ok_T_9 = 1'h0; // @[Parameters.scala:137:59]
wire _address_ok_WIRE_0 = 1'h0; // @[Parameters.scala:612:40]
wire _address_ok_WIRE_1 = 1'h0; // @[Parameters.scala:612:40]
wire address_ok = 1'h0; // @[Parameters.scala:636:64]
wire mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire mask_sub_sub_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire mask_sub_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire mask_eq_9 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_9 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_10 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_10 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_11 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_11 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_12 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_12 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_13 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_13 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_14 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_14 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_15 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_15 = 1'h0; // @[Misc.scala:215:29]
wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_12 = 1'h0; // @[Parameters.scala:54:10]
wire _b_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_first_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _b_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire b_first_done = 1'h0; // @[Edges.scala:233:22]
wire io_in_b_ready = 1'h1; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire is_aligned_1 = 1'h1; // @[Edges.scala:21:24]
wire mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_eq_8 = 1'h1; // @[Misc.scala:214:27]
wire _mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:67]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire b_first_beats1_opdata = 1'h1; // @[Edges.scala:97:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] b_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _b_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [31:0] io_in_b_bits_address = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _is_aligned_T_1 = 32'h0; // @[Edges.scala:21:16]
wire [4:0] io_in_b_bits_source = 5'h0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = 5'h0; // @[Parameters.scala:52:29]
wire [4:0] uncommonBits_9 = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] _legal_source_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29]
wire [4:0] legal_source_uncommonBits = 5'h0; // @[Parameters.scala:52:56]
wire [1:0] io_in_b_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h0; // @[OneHot.scala:64:49]
wire [1:0] mask_lo_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire [7:0] io_in_b_bits_mask = 8'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] _mask_sizeOH_T_5 = 3'h1; // @[OneHot.scala:65:27]
wire [2:0] mask_sizeOH_1 = 3'h1; // @[Misc.scala:202:81]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [5:0] is_aligned_mask_1 = 6'h0; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'h3F; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [7:0] mask_1 = 8'h1; // @[Misc.scala:222:10]
wire [3:0] mask_hi_1 = 4'h0; // @[Misc.scala:222:10]
wire [3:0] _mask_sizeOH_T_4 = 4'h1; // @[OneHot.scala:65:12]
wire [3:0] mask_lo_1 = 4'h1; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h1; // @[Misc.scala:222:10]
wire [32:0] _address_ok_T_6 = 33'h80000000; // @[Parameters.scala:137:41]
wire [32:0] _address_ok_T_7 = 33'h80000000; // @[Parameters.scala:137:46]
wire [32:0] _address_ok_T_8 = 33'h80000000; // @[Parameters.scala:137:46]
wire [31:0] _address_ok_T_5 = 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] _address_ok_T_1 = 33'h8000000; // @[Parameters.scala:137:41]
wire [32:0] _address_ok_T_2 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _address_ok_T_3 = 33'h8000000; // @[Parameters.scala:137:46]
wire [31:0] _address_ok_T = 32'h8000000; // @[Parameters.scala:137:31]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_16 = source_ok_uncommonBits_2 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_2_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_1 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [4:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}]
wire _T_1335 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1335; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1335; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_1409; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_2 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_2; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _T_1406 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_1406; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_1406; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [4:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_3 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_4 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_1261 = _T_1335 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1261 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1261 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1261 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_5 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_5; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_5; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1261 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1261 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_6 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_6; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_6; // @[Monitor.scala:673:46, :783:46]
wire _T_1307 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_7 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1307 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_1276 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1276 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1276 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1276 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] c_set; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [79:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [31:0] _GEN_8 = 32'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_8; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_1348 = _T_1406 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_1348 ? _c_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_1348 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_1348 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [7:0] _GEN_9 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [7:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_9; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_9; // @[Monitor.scala:767:79, :768:77]
wire [258:0] _c_opcodes_set_T_1 = {255'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_1348 ? _c_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [258:0] _c_sizes_set_T_1 = {255'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_1348 ? _c_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1379 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1379 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_1361 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1361 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1361 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1361 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [19:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_1415 = _T_1409 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_10 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_10; // @[OneHot.scala:58:35]
assign d_set = _T_1415 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_11; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_175( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Debug.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}
import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.rocket.{CSRs, Instructions}
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink.{TLAsyncCrossingSink, TLAsyncCrossingSource, TLBuffer, TLRegisterNode, TLXbar}
import freechips.rocketchip.util.{Annotated, AsyncBundle, AsyncQueueParams, AsyncResetSynchronizerShiftReg, FromAsyncBundle, ParameterizedBundle, ResetSynchronizerShiftReg, ToAsyncBundle}
import freechips.rocketchip.util.SeqBoolBitwiseOps
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.BooleanToAugmentedBoolean
object DsbBusConsts {
def sbAddrWidth = 12
def sbIdWidth = 10
}
object DsbRegAddrs{
// These are used by the ROM.
def HALTED = 0x100
def GOING = 0x104
def RESUMING = 0x108
def EXCEPTION = 0x10C
def WHERETO = 0x300
// This needs to be aligned for up to lq/sq
// This shows up in HartInfo, and needs to be aligned
// to enable up to LQ/SQ instructions.
def DATA = 0x380
// We want DATA to immediately follow PROGBUF so that we can
// use them interchangeably. Leave another slot if there is an
// implicit ebreak.
def PROGBUF(cfg:DebugModuleParams) = {
val tmp = DATA - (cfg.nProgramBufferWords * 4)
if (cfg.hasImplicitEbreak) (tmp - 4) else tmp
}
// This is unused if hasImpEbreak is false, and just points to the end of the PROGBUF.
def IMPEBREAK(cfg: DebugModuleParams) = { DATA - 4 }
// We want abstract to be immediately before PROGBUF
// because we auto-generate 2 (or 5) instructions.
def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - (cfg.nAbstractInstructions * 4)
def FLAGS = 0x400
def ROMBASE = 0x800
}
/** Enumerations used both in the hardware
* and in the configuration specification.
*/
object DebugModuleAccessType extends scala.Enumeration {
type DebugModuleAccessType = Value
val Access8Bit, Access16Bit, Access32Bit, Access64Bit, Access128Bit = Value
}
object DebugAbstractCommandError extends scala.Enumeration {
type DebugAbstractCommandError = Value
val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value
}
object DebugAbstractCommandType extends scala.Enumeration {
type DebugAbstractCommandType = Value
val AccessRegister, QuickAccess = Value
}
/** Parameters exposed to the top-level design, set based on
* external requirements, etc.
*
* This object checks that the parameters conform to the
* full specification. The implementation which receives this
* object can perform more checks on what that implementation
* actually supports.
* @param nComponents Number of components to support debugging.
* @param baseAddress Base offest for debugEntry and debugException
* @param nDMIAddrSize Size of the Debug Bus Address
* @param nAbstractDataWords Number of 32-bit words for Abstract Commands
* @param nProgamBufferWords Number of 32-bit words for Program Buffer
* @param hasBusMaster Whether or not a bus master should be included
* @param clockGate Whether or not to use dmactive as the clockgate for debug module
* @param maxSupportedSBAccess Maximum transaction size supported by System Bus Access logic.
* @param supportQuickAccess Whether or not to support the quick access command.
* @param supportHartArray Whether or not to implement the hart array register (if >1 hart).
* @param nHaltGroups Number of halt groups
* @param nExtTriggers Number of external triggers
* @param hasHartResets Feature to reset all the currently selected harts
* @param hasImplicitEbreak There is an additional RO program buffer word containing an ebreak
* @param crossingHasSafeReset Include "safe" logic in Async Crossings so that only one side needs to be reset.
*/
case class DebugModuleParams (
baseAddress : BigInt = BigInt(0),
nDMIAddrSize : Int = 7,
nProgramBufferWords: Int = 16,
nAbstractDataWords : Int = 4,
nScratch : Int = 1,
hasBusMaster : Boolean = false,
clockGate : Boolean = true,
maxSupportedSBAccess : Int = 32,
supportQuickAccess : Boolean = false,
supportHartArray : Boolean = true,
nHaltGroups : Int = 1,
nExtTriggers : Int = 0,
hasHartResets : Boolean = false,
hasImplicitEbreak : Boolean = false,
hasAuthentication : Boolean = false,
crossingHasSafeReset : Boolean = true
) {
require ((nDMIAddrSize >= 7) && (nDMIAddrSize <= 32), s"Legal DMIAddrSize is 7-32, not ${nDMIAddrSize}")
require ((nAbstractDataWords > 0) && (nAbstractDataWords <= 16), s"Legal nAbstractDataWords is 0-16, not ${nAbstractDataWords}")
require ((nProgramBufferWords >= 0) && (nProgramBufferWords <= 16), s"Legal nProgramBufferWords is 0-16, not ${nProgramBufferWords}")
require (nHaltGroups < 32, s"Legal nHaltGroups is 0-31, not ${nHaltGroups}")
require (nExtTriggers <= 16, s"Legal nExtTriggers is 0-16, not ${nExtTriggers}")
if (supportQuickAccess) {
// TODO: Check that quick access requirements are met.
}
def address = AddressSet(baseAddress, 0xFFF)
/** the base address of DM */
def atzero = (baseAddress == 0)
/** The number of generated instructions
*
* When the base address is not zero, we need more instruction also,
* more dscratch registers) to load/store memory mapped data register
* because they may no longer be directly addressible with x0 + 12-bit imm
*/
def nAbstractInstructions = if (atzero) 2 else 5
def debugEntry: BigInt = baseAddress + 0x800
def debugException: BigInt = baseAddress + 0x808
def nDscratch: Int = if (atzero) 1 else 2
}
object DefaultDebugModuleParams {
def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {
new DebugModuleParams().copy(
nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4),
maxSupportedSBAccess = xlen
)
}
}
case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams()))
/** Functional parameters exposed to the design configuration.
*
* hartIdToHartSel: For systems where hart ids are not 1:1 with hartsel, provide the mapping.
* hartSelToHartId: Provide inverse mapping of the above
*/
case class DebugModuleHartSelFuncs (
hartIdToHartSel : (UInt) => UInt = (x:UInt) => x,
hartSelToHartId : (UInt) => UInt = (x:UInt) => x
)
case object DebugModuleHartSelKey extends Field(DebugModuleHartSelFuncs())
class DebugExtTriggerOut (val nExtTriggers: Int) extends Bundle {
val req = Output(UInt(nExtTriggers.W))
val ack = Input(UInt(nExtTriggers.W))
}
class DebugExtTriggerIn (val nExtTriggers: Int) extends Bundle {
val req = Input(UInt(nExtTriggers.W))
val ack = Output(UInt(nExtTriggers.W))
}
class DebugExtTriggerIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val out = new DebugExtTriggerOut(p(DebugModuleKey).get.nExtTriggers)
val in = new DebugExtTriggerIn (p(DebugModuleKey).get.nExtTriggers)
}
class DebugAuthenticationIO () (implicit val p: Parameters) extends ParameterizedBundle()(p) {
val dmactive = Output(Bool())
val dmAuthWrite = Output(Bool())
val dmAuthRead = Output(Bool())
val dmAuthWdata = Output(UInt(32.W))
val dmAuthBusy = Input(Bool())
val dmAuthRdata = Input(UInt(32.W))
val dmAuthenticated = Input(Bool())
}
// *****************************************
// Module Interfaces
//
// *****************************************
/** Control signals for Inner, generated in Outer
* {{{
* run control: resumreq, ackhavereset, halt-on-reset mask
* hart select: hasel, hartsel and the hart array mask
* }}}
*/
class DebugInternalBundle (val nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** resume request */
val resumereq = Bool()
/** hart select */
val hartsel = UInt(10.W)
/** reset acknowledge */
val ackhavereset = Bool()
/** hart array enable */
val hasel = Bool()
/** hart array mask */
val hamask = Vec(nComponents, Bool())
/** halt-on-reset mask */
val hrmask = Vec(nComponents, Bool())
}
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p) {
/** debug availability status for all harts */
val debugUnavail = Input(Vec(nComponents, Bool()))
/** reset signal
*
* for every part of the hardware platform,
* including every hart, except for the DM and any
* logic required to access the DM
*/
val ndreset = Output(Bool())
/** reset signal for the DM itself */
val dmactive = Output(Bool())
/** dmactive acknowlege */
val dmactiveAck = Input(Bool())
}
// *****************************************
// Debug Module
//
// *****************************************
/** Parameterized version of the Debug Module defined in the
* RISC-V Debug Specification
*
* DebugModule is a slave to two asynchronous masters:
* The Debug Bus (DMI) -- This is driven by an external debugger
*
* The System Bus -- This services requests from the cores. Generally
* this interface should only be active at the request
* of the debugger, but the Debug Module may also
* provide the default MTVEC since it is mapped
* to address 0x0.
*
* DebugModule is responsible for control registers and RAM, and
* Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and
* the TL clock. Therefore, it is divided into "Outer" portion (running
* off dmiClock and dmiReset) and "Inner" (running off tl_clock and tl_reset).
* This allows DMCONTROL.haltreq, hartsel, hasel, hawindowsel, hawindow, dmactive,
* and ndreset to be modified even while the Core is in reset or not being clocked.
* Not all reads from the Debugger to the Debug Module will actually complete
* in these scenarios either, they will just block until tl_clock and tl_reset
* allow them to complete. This is not strictly necessary for
* proper debugger functionality.
*/
// Local reg mapper function : Notify when written, but give the value as well.
object WNotifyWire {
def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = {
RegField(n, 0.U, RegWriteFn((valid, data) => {
set := valid
value := data
true.B
}), Some(RegFieldDesc(name = name, desc = desc,
access = RegFieldAccessType.W)))
}
}
// Local reg mapper function : Notify when accessed either as read or write.
object RWNotify {
def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = {
RegField(n,
RegReadFn ((ready) => {rNotify := ready ; (true.B, rVal)}),
RegWriteFn((valid, data) => {
wNotify := valid
when (valid) {wVal := data}
true.B
}
), desc)
}
}
// Local reg mapper function : Notify with value when written, take read input as presented.
// This allows checking or correcting the write value before storing it in the register field.
object WNotifyVal {
def apply(n: Int, rVal: UInt, wVal: UInt, wNotify: Bool, desc: RegFieldDesc): RegField = {
RegField(n, rVal, RegWriteFn((valid, data) => {
wNotify := valid
wVal := data
true.B
}
), desc)
}
}
class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyModule {
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
val intnode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false)
val dmiNode = TLRegisterNode (
address = AddressSet.misaligned(DMI_DMCONTROL << 2, 4) ++
AddressSet.misaligned(DMI_HARTINFO << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOWSEL << 2, 4) ++
AddressSet.misaligned(DMI_HAWINDOW << 2, 4),
device = device,
beatBytes = 4,
executable = false
)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
require (intnode.edges.in.size == 0, "Debug Module does not accept interrupts")
val nComponents = intnode.out.size
def getNComponents = () => nComponents
val supportHartArray = cfg.supportHartArray && (nComponents > 1) // no hart array if only one hart
val io = IO(new Bundle {
/** structure for top-level Debug Module signals which aren't the bus interfaces. */
val ctrl = (new DebugCtrlBundle(nComponents))
/** control signals for Inner, generated in Outer */
val innerCtrl = new DecoupledIO(new DebugInternalBundle(nComponents))
/** debug interruption from Inner to Outer
*
* contains 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = cfg.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** authentication support */
val dmAuthenticated = cfg.hasAuthentication.option(Input(Bool()))
})
val omRegMap = withReset(reset.asAsyncReset) {
// FIXME: Instead of casting reset to ensure it is Async, assert/require reset.Type == AsyncReset (when this feature is available)
val dmAuthenticated = io.dmAuthenticated.map( dma =>
ResetSynchronizerShiftReg(in=dma, sync=3, name=Some("dmAuthenticated_sync"))).getOrElse(true.B)
//----DMCONTROL (The whole point of 'Outer' is to maintain this register on dmiClock (e.g. TCK) domain, so that it
// can be written even if 'Inner' is not being clocked or is in reset. This allows halting
// harts while the rest of the system is in reset. It doesn't really allow any other
// register accesses, which will keep returning 'busy' to the debugger interface.
val DMCONTROLReset = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLNxt = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val DMCONTROLReg = RegNext(next=DMCONTROLNxt, init=0.U.asTypeOf(DMCONTROLNxt)).suggestName("DMCONTROLReg")
val hartsel_mask = if (nComponents > 1) ((1 << p(MaxHartIdBits)) - 1).U else 0.U
val DMCONTROLWrData = WireInit(0.U.asTypeOf(new DMCONTROLFields()))
val dmactiveWrEn = WireInit(false.B)
val ndmresetWrEn = WireInit(false.B)
val clrresethaltreqWrEn = WireInit(false.B)
val setresethaltreqWrEn = WireInit(false.B)
val hartselloWrEn = WireInit(false.B)
val haselWrEn = WireInit(false.B)
val ackhaveresetWrEn = WireInit(false.B)
val hartresetWrEn = WireInit(false.B)
val resumereqWrEn = WireInit(false.B)
val haltreqWrEn = WireInit(false.B)
val dmactive = DMCONTROLReg.dmactive
DMCONTROLNxt := DMCONTROLReg
when (~dmactive) {
DMCONTROLNxt := DMCONTROLReset
} .otherwise {
when (dmAuthenticated && ndmresetWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset }
when (dmAuthenticated && hartselloWrEn) { DMCONTROLNxt.hartsello := DMCONTROLWrData.hartsello & hartsel_mask}
when (dmAuthenticated && haselWrEn) { DMCONTROLNxt.hasel := DMCONTROLWrData.hasel }
when (dmAuthenticated && hartresetWrEn) { DMCONTROLNxt.hartreset := DMCONTROLWrData.hartreset }
when (dmAuthenticated && haltreqWrEn) { DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq }
}
// Put this last to override its own effects.
when (dmactiveWrEn) {
DMCONTROLNxt.dmactive := DMCONTROLWrData.dmactive
}
//----HARTINFO
// DATA registers are mapped to memory. The dataaddr field of HARTINFO has only
// 12 bits and assumes the DM base is 0. If not at 0, then HARTINFO reads as 0
// (implying nonexistence according to the Debug Spec).
val HARTINFORdData = WireInit(0.U.asTypeOf(new HARTINFOFields()))
if (cfg.atzero) when (dmAuthenticated) {
HARTINFORdData.dataaccess := true.B
HARTINFORdData.datasize := cfg.nAbstractDataWords.U
HARTINFORdData.dataaddr := DsbRegAddrs.DATA.U
HARTINFORdData.nscratch := cfg.nScratch.U
}
//--------------------------------------------------------------
// Hart array mask and window
// hamask is hart array mask(1 bit per component), which doesn't include the hart selected by dmcontrol.hartsello
// HAWINDOWSEL selects a 32-bit slice of HAMASK to be visible for read/write in HAWINDOW
//--------------------------------------------------------------
val hamask = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
def haWindowSize = 32
// The following need to be declared even if supportHartArray is false due to reference
// at compile time by dmiNode.regmap
val HAWINDOWSELWrData = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELWrEn = WireInit(false.B)
val HAWINDOWRdData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrData = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAWINDOWWrEn = WireInit(false.B)
/** whether the hart is selected */
def hartSelected(hart: Int): Bool = {
((io.innerCtrl.bits.hartsel === hart.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(hart) else false.B))
}
val HAWINDOWSELNxt = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
val HAWINDOWSELReg = RegNext(next=HAWINDOWSELNxt, init=0.U.asTypeOf(HAWINDOWSELNxt))
if (supportHartArray) {
val HAWINDOWSELReset = WireInit(0.U.asTypeOf(new HAWINDOWSELFields()))
HAWINDOWSELNxt := HAWINDOWSELReg
when (~dmactive || ~dmAuthenticated) {
HAWINDOWSELNxt := HAWINDOWSELReset
} .otherwise {
when (HAWINDOWSELWrEn) {
// Unneeded upper bits of HAWINDOWSEL are tied to 0. Entire register is 0 if all harts fit in one window
if (nComponents > haWindowSize) {
HAWINDOWSELNxt.hawindowsel := HAWINDOWSELWrData.hawindowsel & ((1 << (log2Up(nComponents) - 5)) - 1).U
} else {
HAWINDOWSELNxt.hawindowsel := 0.U
}
}
}
val numHAMASKSlices = ((nComponents - 1)/haWindowSize)+1
HAWINDOWRdData.maskdata := 0.U // default, overridden below
// for each slice,use a hamaskReg to store the selection info
for (ii <- 0 until numHAMASKSlices) {
val sliceMask = if (nComponents > ((ii*haWindowSize) + haWindowSize-1)) (BigInt(1) << haWindowSize) - 1 // All harts in this slice exist
else (BigInt(1)<<(nComponents - (ii*haWindowSize))) - 1 // Partial last slice
val HAMASKRst = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKNxt = WireInit(0.U.asTypeOf(new HAWINDOWFields()))
val HAMASKReg = RegNext(next=HAMASKNxt, init=0.U.asTypeOf(HAMASKNxt))
when (ii.U === HAWINDOWSELReg.hawindowsel) {
HAWINDOWRdData.maskdata := HAMASKReg.asUInt & sliceMask.U
}
HAMASKNxt.maskdata := HAMASKReg.asUInt
when (~dmactive || ~dmAuthenticated) {
HAMASKNxt := HAMASKRst
}.otherwise {
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
HAMASKNxt.maskdata := HAWINDOWWrData.maskdata
}
}
// drive each slice of hamask with stored HAMASKReg or with new value being written
for (jj <- 0 until haWindowSize) {
if (((ii*haWindowSize) + jj) < nComponents) {
val tempWrData = HAWINDOWWrData.maskdata.asBools
val tempMaskReg = HAMASKReg.asUInt.asBools
when (HAWINDOWWrEn && (ii.U === HAWINDOWSELReg.hawindowsel)) {
hamask(ii*haWindowSize + jj) := tempWrData(jj)
}.otherwise {
hamask(ii*haWindowSize + jj) := tempMaskReg(jj)
}
}
}
}
}
//--------------------------------------------------------------
// Halt-on-reset
// hrmaskReg is current set of harts that should halt-on-reset
// Reset state (dmactive=0) is all zeroes
// Bits are set by writing 1 to DMCONTROL.setresethaltreq
// Bits are cleared by writing 1 to DMCONTROL.clrresethaltreq
// Spec says if both are 1, then clrresethaltreq is executed
// hrmask is the halt-on-reset mask which will be sent to inner
//--------------------------------------------------------------
val hrmask = Wire(Vec(nComponents, Bool()))
val hrmaskNxt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegNext(next=hrmaskNxt, init=0.U.asTypeOf(hrmaskNxt)).suggestName("hrmaskReg")
hrmaskNxt := hrmaskReg
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
hrmaskNxt(component) := false.B
}.elsewhen (clrresethaltreqWrEn && DMCONTROLWrData.clrresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := false.B
}.elsewhen (setresethaltreqWrEn && DMCONTROLWrData.setresethaltreq && hartSelected(component)) {
hrmaskNxt(component) := true.B
}
}
hrmask := hrmaskNxt
val dmControlRegFields = RegFieldGroup("dmcontrol", Some("debug module control register"), Seq(
WNotifyVal(1, DMCONTROLReg.dmactive & io.ctrl.dmactiveAck, DMCONTROLWrData.dmactive, dmactiveWrEn,
RegFieldDesc("dmactive", "debug module active", reset=Some(0))),
WNotifyVal(1, DMCONTROLReg.ndmreset, DMCONTROLWrData.ndmreset, ndmresetWrEn,
RegFieldDesc("ndmreset", "debug module reset output", reset=Some(0))),
WNotifyVal(1, 0.U, DMCONTROLWrData.clrresethaltreq, clrresethaltreqWrEn,
RegFieldDesc("clrresethaltreq", "clear reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, 0.U, DMCONTROLWrData.setresethaltreq, setresethaltreqWrEn,
RegFieldDesc("setresethaltreq", "set reset halt request", reset=Some(0), access=RegFieldAccessType.W)),
RegField(12),
if (nComponents > 1) WNotifyVal(p(MaxHartIdBits),
DMCONTROLReg.hartsello, DMCONTROLWrData.hartsello, hartselloWrEn,
RegFieldDesc("hartsello", "hart select low", reset=Some(0)))
else RegField(1),
if (nComponents > 1) RegField(10-p(MaxHartIdBits))
else RegField(9),
if (supportHartArray)
WNotifyVal(1, DMCONTROLReg.hasel, DMCONTROLWrData.hasel, haselWrEn,
RegFieldDesc("hasel", "hart array select", reset=Some(0)))
else RegField(1),
RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.ackhavereset, ackhaveresetWrEn,
RegFieldDesc("ackhavereset", "acknowledge reset", reset=Some(0), access=RegFieldAccessType.W)),
if (cfg.hasHartResets)
WNotifyVal(1, DMCONTROLReg.hartreset, DMCONTROLWrData.hartreset, hartresetWrEn,
RegFieldDesc("hartreset", "hart reset request", reset=Some(0)))
else RegField(1),
WNotifyVal(1, 0.U, DMCONTROLWrData.resumereq, resumereqWrEn,
RegFieldDesc("resumereq", "resume request", reset=Some(0), access=RegFieldAccessType.W)),
WNotifyVal(1, DMCONTROLReg.haltreq, DMCONTROLWrData.haltreq, haltreqWrEn, // Spec says W, but maintaining previous behavior
RegFieldDesc("haltreq", "halt request", reset=Some(0)))
))
val hartinfoRegFields = RegFieldGroup("dmi_hartinfo", Some("hart information"), Seq(
RegField.r(12, HARTINFORdData.dataaddr, RegFieldDesc("dataaddr", "data address", reset=Some(if (cfg.atzero) DsbRegAddrs.DATA else 0))),
RegField.r(4, HARTINFORdData.datasize, RegFieldDesc("datasize", "number of DATA registers", reset=Some(if (cfg.atzero) cfg.nAbstractDataWords else 0))),
RegField.r(1, HARTINFORdData.dataaccess, RegFieldDesc("dataaccess", "data access type", reset=Some(if (cfg.atzero) 1 else 0))),
RegField(3),
RegField.r(4, HARTINFORdData.nscratch, RegFieldDesc("nscratch", "number of scratch registers", reset=Some(if (cfg.atzero) cfg.nScratch else 0)))
))
//--------------------------------------------------------------
// DMI register decoder for Outer
//--------------------------------------------------------------
// regmap addresses are byte offsets from lowest address
def DMI_DMCONTROL_OFFSET = 0
def DMI_HARTINFO_OFFSET = ((DMI_HARTINFO - DMI_DMCONTROL) << 2)
def DMI_HAWINDOWSEL_OFFSET = ((DMI_HAWINDOWSEL - DMI_DMCONTROL) << 2)
def DMI_HAWINDOW_OFFSET = ((DMI_HAWINDOW - DMI_DMCONTROL) << 2)
val omRegMap = dmiNode.regmap(
DMI_DMCONTROL_OFFSET -> dmControlRegFields,
DMI_HARTINFO_OFFSET -> hartinfoRegFields,
DMI_HAWINDOWSEL_OFFSET -> (if (supportHartArray && (nComponents > 32)) Seq(
WNotifyVal(log2Up(nComponents)-5, HAWINDOWSELReg.hawindowsel, HAWINDOWSELWrData.hawindowsel, HAWINDOWSELWrEn,
RegFieldDesc("hawindowsel", "hart array window select", reset=Some(0)))) else Nil),
DMI_HAWINDOW_OFFSET -> (if (supportHartArray) Seq(
WNotifyVal(if (nComponents > 31) 32 else nComponents, HAWINDOWRdData.maskdata, HAWINDOWWrData.maskdata, HAWINDOWWrEn,
RegFieldDesc("hawindow", "hart array window", reset=Some(0), volatile=(nComponents > 32)))) else Nil)
)
//--------------------------------------------------------------
// Interrupt Registers
//--------------------------------------------------------------
val debugIntNxt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val debugIntRegs = RegNext(next=debugIntNxt, init=0.U.asTypeOf(debugIntNxt)).suggestName("debugIntRegs")
debugIntNxt := debugIntRegs
val (intnode_out, _) = intnode.out.unzip
for (component <- 0 until nComponents) {
intnode_out(component)(0) := debugIntRegs(component) | io.hgDebugInt(component)
}
// sends debug interruption to Core when dmcs.haltreq is set,
for (component <- 0 until nComponents) {
when (~dmactive || ~dmAuthenticated) {
debugIntNxt(component) := false.B
}. otherwise {
when (haltreqWrEn && ((DMCONTROLWrData.hartsello === component.U)
|| (if (supportHartArray) DMCONTROLWrData.hasel && hamask(component) else false.B))) {
debugIntNxt(component) := DMCONTROLWrData.haltreq
}
}
}
// Halt request registers are set & cleared by writes to DMCONTROL.haltreq
// resumereq also causes the core to execute a 'dret',
// so resumereq is passed through to Inner.
// hartsel/hasel/hamask must also be used by the DebugModule state machine,
// so it is passed to Inner.
// These registers ensure that requests to dmInner are not lost if inner clock isn't running or requests occur too close together.
// If the innerCtrl async queue is not ready, the notification will be posted and held until ready is received.
// Additional notifications that occur while one is already waiting update the pending data so that the last value written is sent.
// Volatile events resumereq and ackhavereset are registered when they occur and remain pending until ready is received.
val innerCtrlValid = Wire(Bool())
val innerCtrlValidReg = RegInit(false.B).suggestName("innerCtrlValidReg")
val innerCtrlResumeReqReg = RegInit(false.B).suggestName("innerCtrlResumeReqReg")
val innerCtrlAckHaveResetReg = RegInit(false.B).suggestName("innerCtrlAckHaveResetReg")
innerCtrlValid := hartselloWrEn | resumereqWrEn | ackhaveresetWrEn | setresethaltreqWrEn | clrresethaltreqWrEn | haselWrEn |
(HAWINDOWWrEn & supportHartArray.B)
innerCtrlValidReg := io.innerCtrl.valid & ~io.innerCtrl.ready // Hold innerctrl request until the async queue accepts it
innerCtrlResumeReqReg := io.innerCtrl.bits.resumereq & ~io.innerCtrl.ready // Hold resumereq until accepted
innerCtrlAckHaveResetReg := io.innerCtrl.bits.ackhavereset & ~io.innerCtrl.ready // Hold ackhavereset until accepted
io.innerCtrl.valid := innerCtrlValid | innerCtrlValidReg
io.innerCtrl.bits.hartsel := Mux(hartselloWrEn, DMCONTROLWrData.hartsello, DMCONTROLReg.hartsello)
io.innerCtrl.bits.resumereq := (resumereqWrEn & DMCONTROLWrData.resumereq) | innerCtrlResumeReqReg
io.innerCtrl.bits.ackhavereset := (ackhaveresetWrEn & DMCONTROLWrData.ackhavereset) | innerCtrlAckHaveResetReg
io.innerCtrl.bits.hrmask := hrmask
if (supportHartArray) {
io.innerCtrl.bits.hasel := Mux(haselWrEn, DMCONTROLWrData.hasel, DMCONTROLReg.hasel)
io.innerCtrl.bits.hamask := hamask
} else {
io.innerCtrl.bits.hasel := DontCare
io.innerCtrl.bits.hamask := DontCare
}
io.ctrl.ndreset := DMCONTROLReg.ndmreset
io.ctrl.dmactive := DMCONTROLReg.dmactive
// hart reset mechanism implementation
if (cfg.hasHartResets) {
val hartResetNxt = Wire(Vec(nComponents, Bool()))
val hartResetReg = RegNext(next=hartResetNxt, init=0.U.asTypeOf(hartResetNxt))
for (component <- 0 until nComponents) {
hartResetNxt(component) := DMCONTROLReg.hartreset & hartSelected(component)
io.hartResetReq.get(component) := hartResetReg(component)
}
}
omRegMap // FIXME: Remove this when withReset is removed
}}
}
// wrap a Outer with a DMIToTL, derived by dmi clock & reset
class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule {
val cfg = p(DebugModuleKey).get
val dmiXbar = LazyModule (new TLXbar(nameSuffix = Some("dmixbar")))
val dmi2tlOpt = (!p(ExportDebug).apb).option({
val dmi2tl = LazyModule(new DMIToTL())
dmiXbar.node := dmi2tl.node
dmi2tl
})
val apbNodeOpt = p(ExportDebug).apb.option({
val apb2tl = LazyModule(new APBToTL())
val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe))
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr), maxAtomic=0, maxTransfer=4)
val tlError = LazyModule(new TLError(tlErrorParams, buffer=false))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())
apbRegs.node := apbXbar.node
apb2tl.node := apbXbar.node
apb2tlBuffer.node := apb2tl.node
dmiXbar.node := apb2tlBuffer.node
tlError.node := dmiXbar.node
apbXbar.node
})
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode = IntSyncIdentityNode()
intnode :*= IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
val dmiBypass = LazyModule(new TLBusBypass(beatBytes=4, bufferError=false, maxAtomic=0, maxTransfer=4))
val dmiInnerNode = TLAsyncCrossingSource() := dmiBypass.node := dmiXbar.node
dmOuter.dmiNode := dmiXbar.node
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.intnode.edges.out.size
val io = IO(new Bundle {
val dmi_clock = Input(Clock())
val dmi_reset = Input(Reset())
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new DMIIO()(p)))
// Optional APB Interface is fully diplomatic so is not listed here.
val ctrl = new DebugCtrlBundle(nComponents)
/** conrol signals for Inner, generated in Outer */
val innerCtrl = new AsyncBundle(new DebugInternalBundle(nComponents), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
/** debug interruption generated in Inner */
val hgDebugInt = Input(Vec(nComponents, Bool()))
/** hart reset request to core */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Authentication signal from core */
val dmAuthenticated = p(DebugModuleKey).get.hasAuthentication.option(Input(Bool()))
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.dmi_clock
childReset := io.dmi_reset
override def provideImplicitClockToLazyChildren = true
withClockAndReset(childClock, childReset) {
dmi2tlOpt.foreach { _.module.io.dmi <> io.dmi.get }
val dmactiveAck = AsyncResetSynchronizerShiftReg(in=io.ctrl.dmactiveAck, sync=3, name=Some("dmactiveAckSync"))
dmiBypass.module.io.bypass := ~io.ctrl.dmactive | ~dmactiveAck
io.ctrl <> dmOuter.module.io.ctrl
dmOuter.module.io.ctrl.dmactiveAck := dmactiveAck // send synced version down to dmOuter
io.innerCtrl <> ToAsyncBundle(dmOuter.module.io.innerCtrl, AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset))
dmOuter.module.io.hgDebugInt := io.hgDebugInt
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}}
}
}
}
class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// For Shorter Register Names
import DMI_RegAddrs._
val cfg = p(DebugModuleKey).get
def getCfg = () => cfg
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
/** dmiNode address set */
val dmiNode = TLRegisterNode(
// Address is range 0 to 0x1FF except DMCONTROL, HARTINFO, HAWINDOWSEL, HAWINDOW which are handled by Outer
address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HARTINFO << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_HARTINFO + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_HARTINFO + 1) << 2))) ++
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),
device = device,
beatBytes = 4,
executable = false
)
val tlNode = TLRegisterNode(
address=Seq(cfg.address),
device=device,
beatBytes=beatBytes,
executable=true
)
val sb2tlOpt = cfg.hasBusMaster.option(LazyModule(new SBToTL()))
// If we want to support custom registers read through Abstract Commands,
// provide a place to bring them into the debug module. What this connects
// to is up to the implementation.
val customNode = new DebugCustomSink()
lazy val module = new Impl
class Impl extends LazyModuleImp(this){
val nComponents = getNComponents()
Annotated.params(this, cfg)
val supportHartArray = cfg.supportHartArray & (nComponents > 1)
val nExtTriggers = cfg.nExtTriggers
val nHaltGroups = if ((nComponents > 1) | (nExtTriggers > 0)) cfg.nHaltGroups
else 0 // no halt groups possible if single hart with no external triggers
val hartSelFuncs = if (getNComponents() > 1) p(DebugModuleHartSelKey) else DebugModuleHartSelFuncs(
hartIdToHartSel = (x) => 0.U,
hartSelToHartId = (x) => x
)
val io = IO(new Bundle {
/** dm reset signal passed in from Outer */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* it's generated by Outer and comes in
*/
val innerCtrl = Flipped(new DecoupledIO(new DebugInternalBundle(nComponents)))
/** debug unavail signal passed in from Outer*/
val debugUnavail = Input(Vec(nComponents, Bool()))
/** debug interruption from Inner to Outer
*
* contain 2 type of debug interruption causes:
* - halt group
* - halt-on-reset
*/
val hgDebugInt = Output(Vec(nComponents, Bool()))
/** interface for trigger */
val extTrigger = (nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug Authentication signals from core */
val auth = cfg.hasAuthentication.option(new DebugAuthenticationIO())
})
sb2tlOpt.map { sb =>
sb.module.clock := io.tl_clock
sb.module.reset := io.tl_reset
sb.module.rf_reset := io.tl_reset
}
//--------------------------------------------------------------
// Import constants for shorter variable names
//--------------------------------------------------------------
import DMI_RegAddrs._
import DsbRegAddrs._
import DsbBusConsts._
//--------------------------------------------------------------
// Sanity Check Configuration For this implementation.
//--------------------------------------------------------------
require (cfg.supportQuickAccess == false, "No Quick Access support yet")
require ((nHaltGroups > 0) || (nExtTriggers == 0), "External triggers require at least 1 halt group")
//--------------------------------------------------------------
// Register & Wire Declarations (which need to be pre-declared)
//--------------------------------------------------------------
// run control regs: tracking all the harts
// implements: see implementation-specific bits part
/** all harts halted status */
val haltedBitRegs = Reg(UInt(nComponents.W))
/** all harts resume request status */
val resumeReqRegs = Reg(UInt(nComponents.W))
/** all harts have reset status */
val haveResetBitRegs = Reg(UInt(nComponents.W))
// default is 1,after resume, resumeAcks get 0
/** all harts resume ack status */
val resumeAcks = Wire(UInt(nComponents.W))
// --- regmapper outputs
// hart state Id and En
// in Hart Bus Access ROM
val hartHaltedWrEn = Wire(Bool())
val hartHaltedId = Wire(UInt(sbIdWidth.W))
val hartGoingWrEn = Wire(Bool())
val hartGoingId = Wire(UInt(sbIdWidth.W))
val hartResumingWrEn = Wire(Bool())
val hartResumingId = Wire(UInt(sbIdWidth.W))
val hartExceptionWrEn = Wire(Bool())
val hartExceptionId = Wire(UInt(sbIdWidth.W))
// progbuf and abstract data: byte-addressable control logic
// AccessLegal is set only when state = waiting
// RdEn and WrEnMaybe : contrl signal drived by DMI bus
val dmiProgramBufferRdEn = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiProgramBufferAccessLegal = WireInit(false.B)
val dmiProgramBufferWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
val dmiAbstractDataRdEn = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
val dmiAbstractDataAccessLegal = WireInit(false.B)
val dmiAbstractDataWrEnMaybe = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
//--------------------------------------------------------------
// Registers coming from 'CONTROL' in Outer
//--------------------------------------------------------------
val dmAuthenticated = io.auth.map(a => a.dmAuthenticated).getOrElse(true.B)
val selectedHartReg = Reg(UInt(p(MaxHartIdBits).W))
// hamaskFull is a vector of all selected harts including hartsel, whether or not supportHartArray is true
val hamaskFull = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nComponents > 1) {
when (~io.dmactive) {
selectedHartReg := 0.U
}.elsewhen (io.innerCtrl.fire){
selectedHartReg := io.innerCtrl.bits.hartsel
}
}
if (supportHartArray) {
val hamaskZero = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
val hamaskReg = Reg(Vec(nComponents, Bool()))
when (~io.dmactive || ~dmAuthenticated) {
hamaskReg := hamaskZero
}.elsewhen (io.innerCtrl.fire){
hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero)
}
hamaskFull := hamaskReg
}
// Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello,
// so append it here
when (selectedHartReg < nComponents.U) {
hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B
}
io.innerCtrl.ready := true.B
// Construct a Vec from io.innerCtrl fields indicating whether each hart is being selected in this write
// A hart may be selected by hartsel field or by hart array
val hamaskWrSel = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
for (component <- 0 until nComponents ) {
hamaskWrSel(component) := ((io.innerCtrl.bits.hartsel === component.U) ||
(if (supportHartArray) io.innerCtrl.bits.hasel && io.innerCtrl.bits.hamask(component) else false.B))
}
//-------------------------------------
// Halt-on-reset logic
// hrmask is set in dmOuter and passed in
// Debug interrupt is generated when a reset occurs whose corresponding hrmask bit is set
// Debug interrupt is maintained until the hart enters halted state
//-------------------------------------
val hrReset = WireInit(VecInit(Seq.fill(nComponents) { false.B } ))
val hrDebugInt = Wire(Vec(nComponents, Bool()))
val hrmaskReg = RegInit(hrReset)
val hartIsInResetSync = Wire(Vec(nComponents, Bool()))
for (component <- 0 until nComponents) {
hartIsInResetSync(component) := AsyncResetSynchronizerShiftReg(io.hartIsInReset(component), 3, Some(s"debug_hartReset_$component"))
}
when (~io.dmactive || ~dmAuthenticated) {
hrmaskReg := hrReset
}.elsewhen (io.innerCtrl.fire){
hrmaskReg := io.innerCtrl.bits.hrmask
}
withReset(reset.asAsyncReset) { // ensure interrupt requests are negated at first clock edge
val hrDebugIntReg = RegInit(VecInit(Seq.fill(nComponents) { false.B } ))
when (~io.dmactive || ~dmAuthenticated) {
hrDebugIntReg := hrReset
}.otherwise {
hrDebugIntReg := hrmaskReg &
(hartIsInResetSync | // set debugInt during reset
(hrDebugIntReg & ~(haltedBitRegs.asBools))) // maintain until core halts
}
hrDebugInt := hrDebugIntReg
}
//--------------------------------------------------------------
// DMI Registers
//--------------------------------------------------------------
//----DMSTATUS
val DMSTATUSRdData = WireInit(0.U.asTypeOf(new DMSTATUSFields()))
DMSTATUSRdData.authenticated := dmAuthenticated
DMSTATUSRdData.version := 2.U // Version 0.13
io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy)
val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq
when (dmAuthenticated) {
DMSTATUSRdData.hasresethaltreq := true.B
DMSTATUSRdData.anynonexistent := (selectedHartReg >= nComponents.U) // only hartsel can be nonexistent
// all harts nonexistent if hartsel is out of range and there are no harts selected in the hart array
DMSTATUSRdData.allnonexistent := (selectedHartReg >= nComponents.U) & (~hamaskFull.reduce(_ | _))
when (~DMSTATUSRdData.allnonexistent) { // if no existent harts selected, all other status is false
DMSTATUSRdData.anyunavail := (io.debugUnavail & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyhavereset := (haveResetBitRegs.asBools & hamaskFull).reduce(_ | _)
DMSTATUSRdData.anyresumeack := (resumeAcks.asBools & hamaskFull).reduce(_ | _)
when (~DMSTATUSRdData.anynonexistent) { // if one hart is nonexistent, no 'all' status is set
DMSTATUSRdData.allunavail := (io.debugUnavail | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhalted := ((~io.debugUnavail & (haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allrunning := ((~io.debugUnavail & ~(haltedBitRegs.asBools)) | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allhavereset := (haveResetBitRegs.asBools | ~hamaskFull).reduce(_ & _)
DMSTATUSRdData.allresumeack := (resumeAcks.asBools | ~hamaskFull).reduce(_ & _)
}
}
//TODO
DMSTATUSRdData.confstrptrvalid := false.B
DMSTATUSRdData.impebreak := (cfg.hasImplicitEbreak).B
}
when(~io.dmactive || ~dmAuthenticated) {
haveResetBitRegs := 0.U
}.otherwise {
when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) {
haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt
}.otherwise {
haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt
}
}
//----DMCS2 (Halt Groups)
val DMCS2RdData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val DMCS2WrData = WireInit(0.U.asTypeOf(new DMCS2Fields()))
val hgselectWrEn = WireInit(false.B)
val hgwriteWrEn = WireInit(false.B)
val haltgroupWrEn = WireInit(false.B)
val exttriggerWrEn = WireInit(false.B)
val hgDebugInt = WireInit(VecInit(Seq.fill(nComponents) {false.B} ))
if (nHaltGroups > 0) withReset (reset.asAsyncReset) { // async reset ensures triggers don't falsely fire during startup
val hgBits = log2Up(nHaltGroups)
// hgParticipate: Each entry indicates which hg that entity belongs to (1 to nHartGroups). 0 means no hg assigned.
val hgParticipateHart = RegInit(VecInit(Seq.fill(nComponents)(0.U(hgBits.W))))
val hgParticipateTrig = if (nExtTriggers > 0) RegInit(VecInit(Seq.fill(nExtTriggers)(0.U(hgBits.W)))) else Nil
// assign group index to current seledcted harts
for (component <- 0 until nComponents) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateHart(component) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & ~DMCS2WrData.hgselect &
hamaskFull(component) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateHart(component) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
if (nExtTriggers > 0) {
val hgSelect = Reg(Bool())
when (~io.dmactive || ~dmAuthenticated) {
hgSelect := false.B
}.otherwise {
when (hgselectWrEn) {
hgSelect := DMCS2WrData.hgselect
}
}
// assign group index to trigger
for (trigger <- 0 until nExtTriggers) {
when (~io.dmactive || ~dmAuthenticated) {
hgParticipateTrig(trigger) := 0.U
}.otherwise {
when (haltgroupWrEn & DMCS2WrData.hgwrite & DMCS2WrData.hgselect &
(DMCS2WrData.exttrigger === trigger.U) & (DMCS2WrData.haltgroup <= nHaltGroups.U)) {
hgParticipateTrig(trigger) := DMCS2WrData.haltgroup
}
}
}
DMCS2RdData.hgselect := hgSelect
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(0)
}
// If there is only 1 ext trigger, then the exttrigger field is fixed at 0
// Otherwise, instantiate a register with only the number of bits required
if (nExtTriggers > 1) {
val trigBits = log2Up(nExtTriggers-1)
val hgExtTrigger = Reg(UInt(trigBits.W))
when (~io.dmactive || ~dmAuthenticated) {
hgExtTrigger := 0.U
}.otherwise {
when (exttriggerWrEn & (DMCS2WrData.exttrigger < nExtTriggers.U)) {
hgExtTrigger := DMCS2WrData.exttrigger
}
}
DMCS2RdData.exttrigger := hgExtTrigger
when (hgSelect) {
DMCS2RdData.haltgroup := hgParticipateTrig(hgExtTrigger)
}
}
}
// Halt group state machine
// IDLE: Go to FIRED when any hart in this hg writes to HALTED while its HaltedBitRegs=0
// or when any trigin assigned to this hg occurs
// FIRED: Back to IDLE when all harts in this hg have set their haltedBitRegs
// and all trig out in this hg have been acknowledged
val hgFired = RegInit (VecInit(Seq.fill(nHaltGroups+1) {false.B} ))
val hgHartFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to hart halting
val hgTrigFiring = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // which hg's are firing due to trig in
val hgHartsAllHalted = WireInit(VecInit(Seq.fill(nHaltGroups+1) {false.B} )) // in which hg's have all harts halted
val hgTrigsAllAcked = WireInit(VecInit(Seq.fill(nHaltGroups+1) { true.B} )) // in which hg's have all trigouts been acked
io.extTrigger.foreach {extTrigger =>
val extTriggerInReq = Wire(Vec(nExtTriggers, Bool()))
val extTriggerOutAck = Wire(Vec(nExtTriggers, Bool()))
extTriggerInReq := extTrigger.in.req.asBools
extTriggerOutAck := extTrigger.out.ack.asBools
val trigInReq = ResetSynchronizerShiftReg(in=extTriggerInReq, sync=3, name=Some("dm_extTriggerInReqSync"))
val trigOutAck = ResetSynchronizerShiftReg(in=extTriggerOutAck, sync=3, name=Some("dm_extTriggerOutAckSync"))
for (hg <- 1 to nHaltGroups) {
hgTrigFiring(hg) := (trigInReq & ~RegNext(trigInReq) & hgParticipateTrig.map(_ === hg.U)).reduce(_ | _)
hgTrigsAllAcked(hg) := (trigOutAck | hgParticipateTrig.map(_ =/= hg.U)).reduce(_ & _)
}
extTrigger.in.ack := trigInReq.asUInt
}
for (hg <- 1 to nHaltGroups) {
hgHartFiring(hg) := hartHaltedWrEn & ~haltedBitRegs(hartHaltedId) & (hgParticipateHart(hartSelFuncs.hartIdToHartSel(hartHaltedId)) === hg.U)
hgHartsAllHalted(hg) := (haltedBitRegs.asBools | hgParticipateHart.map(_ =/= hg.U)).reduce(_ & _)
when (~io.dmactive || ~dmAuthenticated) {
hgFired(hg) := false.B
}.elsewhen (~hgFired(hg) & (hgHartFiring(hg) | hgTrigFiring(hg))) {
hgFired(hg) := true.B
}.elsewhen ( hgFired(hg) & hgHartsAllHalted(hg) & hgTrigsAllAcked(hg)) {
hgFired(hg) := false.B
}
}
// For each hg that has fired, assert debug interrupt to each hart in that hg
for (component <- 0 until nComponents) {
hgDebugInt(component) := hgFired(hgParticipateHart(component))
}
// For each hg that has fired, assert trigger out for all external triggers in that hg
io.extTrigger.foreach {extTrigger =>
val extTriggerOutReq = RegInit(VecInit(Seq.fill(cfg.nExtTriggers) {false.B} ))
for (trig <- 0 until nExtTriggers) {
extTriggerOutReq(trig) := hgFired(hgParticipateTrig(trig))
}
extTrigger.out.req := extTriggerOutReq.asUInt
}
}
io.hgDebugInt := hgDebugInt | hrDebugInt
//----HALTSUM*
val numHaltedStatus = ((nComponents - 1) / 32) + 1
val haltedStatus = Wire(Vec(numHaltedStatus, Bits(32.W)))
for (ii <- 0 until numHaltedStatus) {
when (dmAuthenticated) {
haltedStatus(ii) := haltedBitRegs >> (ii*32)
}.otherwise {
haltedStatus(ii) := 0.U
}
}
val haltedSummary = Cat(haltedStatus.map(_.orR).reverse)
val HALTSUM1RdData = haltedSummary.asTypeOf(new HALTSUM1Fields())
val selectedHaltedStatus = Mux((selectedHartReg >> 5) > numHaltedStatus.U, 0.U, haltedStatus(selectedHartReg >> 5))
val HALTSUM0RdData = selectedHaltedStatus.asTypeOf(new HALTSUM0Fields())
// Since we only support 1024 harts, we don't implement HALTSUM2 or HALTSUM3
//----ABSTRACTCS
val ABSTRACTCSReset = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
ABSTRACTCSReset.datacount := cfg.nAbstractDataWords.U
ABSTRACTCSReset.progbufsize := cfg.nProgramBufferWords.U
val ABSTRACTCSReg = Reg(new ABSTRACTCSFields())
val ABSTRACTCSWrData = WireInit(0.U.asTypeOf(new ABSTRACTCSFields()))
val ABSTRACTCSRdData = WireInit(ABSTRACTCSReg)
val ABSTRACTCSRdEn = WireInit(false.B)
val ABSTRACTCSWrEnMaybe = WireInit(false.B)
val ABSTRACTCSWrEnLegal = WireInit(false.B)
val ABSTRACTCSWrEn = ABSTRACTCSWrEnMaybe && ABSTRACTCSWrEnLegal
// multiple error types
// find implement in the state machine part
val errorBusy = WireInit(false.B)
val errorException = WireInit(false.B)
val errorUnsupported = WireInit(false.B)
val errorHaltResume = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTCSReg := ABSTRACTCSReset
}.otherwise {
when (errorBusy){
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrBusy.id.U
}.elsewhen (errorException) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrException.id.U
}.elsewhen (errorUnsupported) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrNotSupported.id.U
}.elsewhen (errorHaltResume) {
ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U
}.otherwise {
//W1C
when (ABSTRACTCSWrEn){
ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);
}
}
}
// For busy, see below state machine.
val abstractCommandBusy = WireInit(true.B)
ABSTRACTCSRdData.busy := abstractCommandBusy
when (~dmAuthenticated) { // read value must be 0 when not authenticated
ABSTRACTCSRdData.datacount := 0.U
ABSTRACTCSRdData.progbufsize := 0.U
}
//---- ABSTRACTAUTO
// It is a mask indicating whether datai/probufi have the autoexcution permisson
// this part aims to produce 3 wires : autoexecData,autoexecProg,autoexec
// first two specify which reg supports autoexec
// autoexec is a control signal, meaning there is at least one enabled autoexec reg
// when autoexec is set, generate instructions using COMMAND register
val ABSTRACTAUTOReset = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTOReg = Reg(new ABSTRACTAUTOFields())
val ABSTRACTAUTOWrData = WireInit(0.U.asTypeOf(new ABSTRACTAUTOFields()))
val ABSTRACTAUTORdData = WireInit(ABSTRACTAUTOReg)
val ABSTRACTAUTORdEn = WireInit(false.B)
val autoexecdataWrEnMaybe = WireInit(false.B)
val autoexecprogbufWrEnMaybe = WireInit(false.B)
val ABSTRACTAUTOWrEnLegal = WireInit(false.B)
when (~io.dmactive || ~dmAuthenticated) {
ABSTRACTAUTOReg := ABSTRACTAUTOReset
}.otherwise {
when (autoexecprogbufWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecprogbuf := ABSTRACTAUTOWrData.autoexecprogbuf & ( (1 << cfg.nProgramBufferWords) - 1).U
}
when (autoexecdataWrEnMaybe && ABSTRACTAUTOWrEnLegal) {
ABSTRACTAUTOReg.autoexecdata := ABSTRACTAUTOWrData.autoexecdata & ( (1 << cfg.nAbstractDataWords) - 1).U
}
}
// Abstract Data access vector(byte-addressable)
val dmiAbstractDataAccessVec = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords * 4) {false.B} ))
dmiAbstractDataAccessVec := (dmiAbstractDataWrEnMaybe zip dmiAbstractDataRdEn).map{ case (r,w) => r | w}
// Program Buffer access vector(byte-addressable)
val dmiProgramBufferAccessVec = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords * 4) {false.B} ))
dmiProgramBufferAccessVec := (dmiProgramBufferWrEnMaybe zip dmiProgramBufferRdEn).map{ case (r,w) => r | w}
// at least one word access
val dmiAbstractDataAccess = dmiAbstractDataAccessVec.reduce(_ || _ )
val dmiProgramBufferAccess = dmiProgramBufferAccessVec.reduce(_ || _)
// This will take the shorter of the lists, which is what we want.
val autoexecData = WireInit(VecInit(Seq.fill(cfg.nAbstractDataWords) {false.B} ))
val autoexecProg = WireInit(VecInit(Seq.fill(cfg.nProgramBufferWords) {false.B} ))
(autoexecData zip ABSTRACTAUTOReg.autoexecdata.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiAbstractDataAccessVec(i * 4) && t._2 }
(autoexecProg zip ABSTRACTAUTOReg.autoexecprogbuf.asBools).zipWithIndex.foreach {case (t, i) => t._1 := dmiProgramBufferAccessVec(i * 4) && t._2}
val autoexec = autoexecData.reduce(_ || _) || autoexecProg.reduce(_ || _)
//---- COMMAND
val COMMANDReset = WireInit(0.U.asTypeOf(new COMMANDFields()))
val COMMANDReg = Reg(new COMMANDFields())
val COMMANDWrDataVal = WireInit(0.U(32.W))
val COMMANDWrData = WireInit(COMMANDWrDataVal.asTypeOf(new COMMANDFields()))
val COMMANDWrEnMaybe = WireInit(false.B)
val COMMANDWrEnLegal = WireInit(false.B)
val COMMANDRdEn = WireInit(false.B)
val COMMANDWrEn = COMMANDWrEnMaybe && COMMANDWrEnLegal
val COMMANDRdData = COMMANDReg
when (~io.dmactive || ~dmAuthenticated) {
COMMANDReg := COMMANDReset
}.otherwise {
when (COMMANDWrEn) {
COMMANDReg := COMMANDWrData
}
}
// --- Abstract Data
// These are byte addressible, s.t. the Processor can use
// byte-addressible instructions to store to them.
val abstractDataMem = Reg(Vec(cfg.nAbstractDataWords*4, UInt(8.W)))
val abstractDataNxt = WireInit(abstractDataMem)
// --- Program Buffer
// byte-addressible mem
val programBufferMem = Reg(Vec(cfg.nProgramBufferWords*4, UInt(8.W)))
val programBufferNxt = WireInit(programBufferMem)
//--------------------------------------------------------------
// These bits are implementation-specific bits set
// by harts executing code.
//--------------------------------------------------------------
// Run control logic
when (~io.dmactive || ~dmAuthenticated) {
haltedBitRegs := 0.U
resumeReqRegs := 0.U
}.otherwise {
//remove those harts in reset
resumeReqRegs := resumeReqRegs & ~(hartIsInResetSync.asUInt)
val hartHaltedIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartHaltedId))
val hartResumingIdIndex = UIntToOH(hartSelFuncs.hartIdToHartSel(hartResumingId))
val hartselIndex = UIntToOH(io.innerCtrl.bits.hartsel)
when (hartHaltedWrEn) {
// add those harts halting and remove those in reset
haltedBitRegs := (haltedBitRegs | hartHaltedIdIndex) & ~(hartIsInResetSync.asUInt)
}.elsewhen (hartResumingWrEn) {
// remove those harts in reset and those in resume
haltedBitRegs := (haltedBitRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}.otherwise {
// remove those harts in reset
haltedBitRegs := haltedBitRegs & ~(hartIsInResetSync.asUInt)
}
when (hartResumingWrEn) {
// remove those harts in resume and those in reset
resumeReqRegs := (resumeReqRegs & ~(hartResumingIdIndex)) & ~(hartIsInResetSync.asUInt)
}
when (resumereq) {
// set all sleceted harts to resumeReq, remove those in reset
resumeReqRegs := (resumeReqRegs | hamaskWrSel.asUInt) & ~(hartIsInResetSync.asUInt)
}
}
when (resumereq) {
// next cycle resumeAcls will be the negation of next cycle resumeReqRegs
resumeAcks := (~resumeReqRegs & ~(hamaskWrSel.asUInt))
}.otherwise {
resumeAcks := ~resumeReqRegs
}
//---- AUTHDATA
val authRdEnMaybe = WireInit(false.B)
val authWrEnMaybe = WireInit(false.B)
io.auth.map { a =>
a.dmactive := io.dmactive
a.dmAuthRead := authRdEnMaybe & ~a.dmAuthBusy
a.dmAuthWrite := authWrEnMaybe & ~a.dmAuthBusy
}
val dmstatusRegFields = RegFieldGroup("dmi_dmstatus", Some("debug module status register"), Seq(
RegField.r(4, DMSTATUSRdData.version, RegFieldDesc("version", "version", reset=Some(2))),
RegField.r(1, DMSTATUSRdData.confstrptrvalid, RegFieldDesc("confstrptrvalid", "confstrptrvalid", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.hasresethaltreq, RegFieldDesc("hasresethaltreq", "hasresethaltreq", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.authbusy, RegFieldDesc("authbusy", "authbusy", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.authenticated, RegFieldDesc("authenticated", "authenticated", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhalted, RegFieldDesc("anyhalted", "anyhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhalted, RegFieldDesc("allhalted", "allhalted", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyrunning, RegFieldDesc("anyrunning", "anyrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allrunning, RegFieldDesc("allrunning", "allrunning", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyunavail, RegFieldDesc("anyunavail", "anyunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allunavail, RegFieldDesc("allunavail", "allunavail", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anynonexistent, RegFieldDesc("anynonexistent", "anynonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allnonexistent, RegFieldDesc("allnonexistent", "allnonexistent", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.anyresumeack, RegFieldDesc("anyresumeack", "anyresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.allresumeack, RegFieldDesc("allresumeack", "allresumeack", reset=Some(1))),
RegField.r(1, DMSTATUSRdData.anyhavereset, RegFieldDesc("anyhavereset", "anyhavereset", reset=Some(0))),
RegField.r(1, DMSTATUSRdData.allhavereset, RegFieldDesc("allhavereset", "allhavereset", reset=Some(0))),
RegField(2),
RegField.r(1, DMSTATUSRdData.impebreak, RegFieldDesc("impebreak", "impebreak", reset=Some(if (cfg.hasImplicitEbreak) 1 else 0)))
))
val dmcs2RegFields = RegFieldGroup("dmi_dmcs2", Some("debug module control/status register 2"), Seq(
WNotifyVal(1, DMCS2RdData.hgselect, DMCS2WrData.hgselect, hgselectWrEn,
RegFieldDesc("hgselect", "select halt groups or external triggers", reset=Some(0), volatile=true)),
WNotifyVal(1, 0.U, DMCS2WrData.hgwrite, hgwriteWrEn,
RegFieldDesc("hgwrite", "write 1 to change halt groups", reset=None, access=RegFieldAccessType.W)),
WNotifyVal(5, DMCS2RdData.haltgroup, DMCS2WrData.haltgroup, haltgroupWrEn,
RegFieldDesc("haltgroup", "halt group", reset=Some(0), volatile=true)),
if (nExtTriggers > 1)
WNotifyVal(4, DMCS2RdData.exttrigger, DMCS2WrData.exttrigger, exttriggerWrEn,
RegFieldDesc("exttrigger", "external trigger select", reset=Some(0), volatile=true))
else RegField(4)
))
val abstractcsRegFields = RegFieldGroup("dmi_abstractcs", Some("abstract command control/status"), Seq(
RegField.r(4, ABSTRACTCSRdData.datacount, RegFieldDesc("datacount", "number of DATA registers", reset=Some(cfg.nAbstractDataWords))),
RegField(4),
WNotifyVal(3, ABSTRACTCSRdData.cmderr, ABSTRACTCSWrData.cmderr, ABSTRACTCSWrEnMaybe,
RegFieldDesc("cmderr", "command error", reset=Some(0), wrType=Some(RegFieldWrType.ONE_TO_CLEAR))),
RegField(1),
RegField.r(1, ABSTRACTCSRdData.busy, RegFieldDesc("busy", "busy", reset=Some(0))),
RegField(11),
RegField.r(5, ABSTRACTCSRdData.progbufsize, RegFieldDesc("progbufsize", "number of PROGBUF registers", reset=Some(cfg.nProgramBufferWords)))
))
val (sbcsFields, sbAddrFields, sbDataFields):
(Seq[RegField], Seq[Seq[RegField]], Seq[Seq[RegField]]) = sb2tlOpt.map{ sb2tl =>
SystemBusAccessModule(sb2tl, io.dmactive, dmAuthenticated)(p)
}.getOrElse((Seq.empty[RegField], Seq.fill[Seq[RegField]](4)(Seq.empty[RegField]), Seq.fill[Seq[RegField]](4)(Seq.empty[RegField])))
//--------------------------------------------------------------
// Program Buffer Access (DMI ... System Bus can override)
//--------------------------------------------------------------
val omRegMap = dmiNode.regmap(
(DMI_DMSTATUS << 2) -> dmstatusRegFields,
//TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields,
(DMI_DMCS2 << 2) -> (if (nHaltGroups > 0) dmcs2RegFields else Nil),
(DMI_HALTSUM0 << 2) -> RegFieldGroup("dmi_haltsum0", Some("Halt Summary 0"),
Seq(RegField.r(32, HALTSUM0RdData.asUInt, RegFieldDesc("dmi_haltsum0", "halt summary 0")))),
(DMI_HALTSUM1 << 2) -> RegFieldGroup("dmi_haltsum1", Some("Halt Summary 1"),
Seq(RegField.r(32, HALTSUM1RdData.asUInt, RegFieldDesc("dmi_haltsum1", "halt summary 1")))),
(DMI_ABSTRACTCS << 2) -> abstractcsRegFields,
(DMI_ABSTRACTAUTO<< 2) -> RegFieldGroup("dmi_abstractauto", Some("abstract command autoexec"), Seq(
WNotifyVal(cfg.nAbstractDataWords, ABSTRACTAUTORdData.autoexecdata, ABSTRACTAUTOWrData.autoexecdata, autoexecdataWrEnMaybe,
RegFieldDesc("autoexecdata", "abstract command data autoexec", reset=Some(0))),
RegField(16-cfg.nAbstractDataWords),
WNotifyVal(cfg.nProgramBufferWords, ABSTRACTAUTORdData.autoexecprogbuf, ABSTRACTAUTOWrData.autoexecprogbuf, autoexecprogbufWrEnMaybe,
RegFieldDesc("autoexecprogbuf", "abstract command progbuf autoexec", reset=Some(0))))),
(DMI_COMMAND << 2) -> RegFieldGroup("dmi_command", Some("Abstract Command Register"),
Seq(RWNotify(32, COMMANDRdData.asUInt, COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe,
Some(RegFieldDesc("dmi_command", "abstract command register", reset=Some(0), volatile=true))))),
(DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", Some("abstract command data registers"), abstractDataMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), abstractDataNxt(i),
dmiAbstractDataRdEn(i),
dmiAbstractDataWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_data_$i", s"abstract command data register $i", reset = Some(0), volatile=true)))}, false),
(DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", Some("abstract command progbuf registers"), programBufferMem.zipWithIndex.map{case (x, i) =>
RWNotify(8, Mux(dmAuthenticated, x, 0.U), programBufferNxt(i),
dmiProgramBufferRdEn(i),
dmiProgramBufferWrEnMaybe(i),
Some(RegFieldDesc(s"dmi_progbuf_$i", s"abstract command progbuf register $i", reset = Some(0))))}, false),
(DMI_AUTHDATA << 2) -> (if (cfg.hasAuthentication) RegFieldGroup("dmi_authdata", Some("authentication data exchange register"),
Seq(RWNotify(32, io.auth.get.dmAuthRdata, io.auth.get.dmAuthWdata, authRdEnMaybe, authWrEnMaybe,
Some(RegFieldDesc("authdata", "authentication data exchange", volatile=true))))) else Nil),
(DMI_SBCS << 2) -> sbcsFields,
(DMI_SBDATA0 << 2) -> sbDataFields(0),
(DMI_SBDATA1 << 2) -> sbDataFields(1),
(DMI_SBDATA2 << 2) -> sbDataFields(2),
(DMI_SBDATA3 << 2) -> sbDataFields(3),
(DMI_SBADDRESS0 << 2) -> sbAddrFields(0),
(DMI_SBADDRESS1 << 2) -> sbAddrFields(1),
(DMI_SBADDRESS2 << 2) -> sbAddrFields(2),
(DMI_SBADDRESS3 << 2) -> sbAddrFields(3)
)
// Abstract data mem is written by both the tile link interface and DMI...
abstractDataMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiAbstractDataWrEnMaybe(i) && dmiAbstractDataAccessLegal) {
x := abstractDataNxt(i)
}
}
// ... and also by custom register read (if implemented)
val (customs, customParams) = customNode.in.unzip
val needCustom = (customs.size > 0) && (customParams.head.addrs.size > 0)
def getNeedCustom = () => needCustom
if (needCustom) {
val (custom, customP) = customNode.in.head
require(customP.width % 8 == 0, s"Debug Custom width must be divisible by 8, not ${customP.width}")
val custom_data = custom.data.asBools
val custom_bytes = Seq.tabulate(customP.width/8){i => custom_data.slice(i*8, (i+1)*8).asUInt}
when (custom.ready && custom.valid) {
(abstractDataMem zip custom_bytes).zipWithIndex.foreach {case ((a, b), i) =>
a := b
}
}
}
programBufferMem.zipWithIndex.foreach { case (x, i) =>
when (dmAuthenticated && dmiProgramBufferWrEnMaybe(i) && dmiProgramBufferAccessLegal) {
x := programBufferNxt(i)
}
}
//--------------------------------------------------------------
// "Variable" ROM Generation
//--------------------------------------------------------------
val goReg = Reg(Bool())
val goAbstract = WireInit(false.B)
val goCustom = WireInit(false.B)
val jalAbstract = WireInit(Instructions.JAL.value.U.asTypeOf(new GeneratedUJ()))
jalAbstract.setImm(ABSTRACT(cfg) - WHERETO)
when (~io.dmactive){
goReg := false.B
}.otherwise {
when (goAbstract) {
goReg := true.B
}.elsewhen (hartGoingWrEn){
assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U)
goReg := false.B
}
}
class flagBundle extends Bundle {
val reserved = UInt(6.W)
val resume = Bool()
val go = Bool()
}
val flags = WireInit(VecInit(Seq.fill(1 << selectedHartReg.getWidth) {0.U.asTypeOf(new flagBundle())} ))
assert ((hartSelFuncs.hartSelToHartId(selectedHartReg) < flags.size.U),
s"HartSel to HartId Mapping is illegal for this Debug Implementation, because HartID must be < ${flags.size} for it to work.")
flags(hartSelFuncs.hartSelToHartId(selectedHartReg)).go := goReg
for (component <- 0 until nComponents) {
val componentSel = WireInit(component.U)
flags(hartSelFuncs.hartSelToHartId(componentSel)).resume := resumeReqRegs(component)
}
//----------------------------
// Abstract Command Decoding & Generation
//----------------------------
val accessRegisterCommandWr = WireInit(COMMANDWrData.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
/** real COMMAND*/
val accessRegisterCommandReg = WireInit(COMMANDReg.asUInt.asTypeOf(new ACCESS_REGISTERFields()))
// TODO: Quick Access
class GeneratedI extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedS extends Bundle {
val immhi = UInt(7.W)
val rs2 = UInt(5.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val immlo = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedCSR extends Bundle {
val imm = UInt(12.W)
val rs1 = UInt(5.W)
val funct3 = UInt(3.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
}
class GeneratedUJ extends Bundle {
val imm3 = UInt(1.W)
val imm0 = UInt(10.W)
val imm1 = UInt(1.W)
val imm2 = UInt(8.W)
val rd = UInt(5.W)
val opcode = UInt(7.W)
def setImm(imm: Int) : Unit = {
// TODO: Check bounds of imm.
require(imm % 2 == 0, "Immediate must be even for UJ encoding.")
val immWire = WireInit(imm.S(21.W))
val immBits = WireInit(VecInit(immWire.asBools))
imm0 := immBits.slice(1, 1 + 10).asUInt
imm1 := immBits.slice(11, 11 + 11).asUInt
imm2 := immBits.slice(12, 12 + 8).asUInt
imm3 := immBits.slice(20, 20 + 1).asUInt
}
}
require((cfg.atzero && cfg.nAbstractInstructions == 2) || (!cfg.atzero && cfg.nAbstractInstructions == 5),
"Mismatch between DebugModuleParams atzero and nAbstractInstructions")
val abstractGeneratedMem = Reg(Vec(cfg.nAbstractInstructions, (UInt(32.W))))
def abstractGeneratedI(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedI())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.LW.value.U.asTypeOf(new GeneratedI())).opcode
inst.rd := (accessRegisterCommandReg.regno & 0x1F.U)
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.imm := offset.U
inst.asUInt
}
def abstractGeneratedS(cfg: DebugModuleParams): UInt = {
val inst = Wire(new GeneratedS())
val offset = if (cfg.atzero) DATA else (DATA-0x800) & 0xFFF
val base = if (cfg.atzero) 0.U else Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U)
inst.opcode := (Instructions.SW.value.U.asTypeOf(new GeneratedS())).opcode
inst.immlo := (offset & 0x1F).U
inst.funct3 := accessRegisterCommandReg.size
inst.rs1 := base
inst.rs2 := (accessRegisterCommandReg.regno & 0x1F.U)
inst.immhi := (offset >> 5).U
inst.asUInt
}
def abstractGeneratedCSR: UInt = {
val inst = Wire(new GeneratedCSR())
val base = Mux(accessRegisterCommandReg.regno(0), 8.U, 9.U) // use s0 as base for odd regs, s1 as base for even regs
inst := (Instructions.CSRRW.value.U.asTypeOf(new GeneratedCSR()))
inst.imm := CSRs.dscratch1.U
inst.rs1 := base
inst.rd := base
inst.asUInt
}
val nop = Wire(new GeneratedI())
nop := Instructions.ADDI.value.U.asTypeOf(new GeneratedI())
nop.rd := 0.U
nop.rs1 := 0.U
nop.imm := 0.U
val isa = Wire(new GeneratedI())
isa := Instructions.ADDIW.value.U.asTypeOf(new GeneratedI())
isa.rd := 0.U
isa.rs1 := 0.U
isa.imm := 0.U
when (goAbstract) {
if (cfg.nAbstractInstructions == 2) {
// ABSTRACT(0): Transfer: LW or SW, else NOP
// ABSTRACT(1): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
} else {
// Entry: All regs in GPRs, dscratch1=offset 0x800 in DM
// ABSTRACT(0): CheckISA: ADDW or NOP (exception here if size=3 and not RV64)
// ABSTRACT(1): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(2): Transfer: LW, SW, LD, SD else NOP
// ABSTRACT(3): CSRRW s1,dscratch1,s1 or CSRRW s0,dscratch1,s0
// ABSTRACT(4): Postexec: NOP else EBREAK
abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer && accessRegisterCommandReg.size =/= 2.U, isa.asUInt, nop.asUInt)
abstractGeneratedMem(1) := abstractGeneratedCSR
abstractGeneratedMem(2) := Mux(accessRegisterCommandReg.transfer,
Mux(accessRegisterCommandReg.write, abstractGeneratedI(cfg), abstractGeneratedS(cfg)),
nop.asUInt
)
abstractGeneratedMem(3) := abstractGeneratedCSR
abstractGeneratedMem(4) := Mux(accessRegisterCommandReg.postexec,
nop.asUInt,
Instructions.EBREAK.value.U)
}
}
//--------------------------------------------------------------
// Drive Custom Access
//--------------------------------------------------------------
if (needCustom) {
val (custom, customP) = customNode.in.head
custom.addr := accessRegisterCommandReg.regno
custom.valid := goCustom
}
//--------------------------------------------------------------
// Hart Bus Access
//--------------------------------------------------------------
tlNode.regmap(
// This memory is writable.
HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn,
"debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")),
GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn,
"debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")),
RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn,
"debug_hart_resuming", "Debug ROM causes hart to write its hartID here when it leaves Debug Mode.")),
EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn,
"debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")),
DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"),
abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}),
PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"),
programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}),
// These sections are read-only.
IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U,
RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil},
WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))),
ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}),
FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
if (nComponents == 1) {
Seq.tabulate(1024) { i => RegField.r(8, flags(0).asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true)) }
} else {
flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))}
}),
ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"),
(if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>
RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
)
// Override System Bus accesses with dmactive reset.
when (~io.dmactive){
abstractDataMem.foreach {x => x := 0.U}
programBufferMem.foreach {x => x := 0.U}
}
//--------------------------------------------------------------
// Abstract Command State Machine
//--------------------------------------------------------------
object CtrlState extends scala.Enumeration {
type CtrlState = Value
val Waiting, CheckGenerate, Exec, Custom = Value
def apply( t : Value) : UInt = {
t.id.U(log2Up(values.size).W)
}
}
import CtrlState._
// This is not an initialization!
val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting)))
val hartHalted = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
val ctrlStateNxt = WireInit(ctrlStateReg)
//------------------------
// DMI Register Control and Status
abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))
ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
ABSTRACTAUTOWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
dmiAbstractDataAccessLegal := (ctrlStateReg === CtrlState(Waiting))
dmiProgramBufferAccessLegal := (ctrlStateReg === CtrlState(Waiting))
errorBusy := (ABSTRACTCSWrEnMaybe && ~ABSTRACTCSWrEnLegal) ||
(autoexecdataWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(autoexecprogbufWrEnMaybe && ~ABSTRACTAUTOWrEnLegal) ||
(COMMANDWrEnMaybe && ~COMMANDWrEnLegal) ||
(dmiAbstractDataAccess && ~dmiAbstractDataAccessLegal) ||
(dmiProgramBufferAccess && ~dmiProgramBufferAccessLegal)
// TODO: Maybe Quick Access
val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U)
val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister
val commandRegIsUnsupported = WireInit(true.B)
val commandRegBadHaltResume = WireInit(false.B)
// We only support abstract commands for GPRs and any custom registers, if specified.
val accessRegIsLegalSize = (accessRegisterCommandReg.size === 2.U) || (accessRegisterCommandReg.size === 3.U)
val accessRegIsGPR = (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U) && accessRegIsLegalSize
val accessRegIsCustom = if (needCustom) {
val (custom, customP) = customNode.in.head
customP.addrs.foldLeft(false.B){
(result, current) => result || (current.U === accessRegisterCommandReg.regno)}
} else false.B
when (commandRegIsAccessRegister) {
when (accessRegIsCustom && accessRegisterCommandReg.transfer && accessRegisterCommandReg.write === false.B) {
commandRegIsUnsupported := false.B
}.elsewhen (!accessRegisterCommandReg.transfer || accessRegIsGPR) {
commandRegIsUnsupported := false.B
commandRegBadHaltResume := ~hartHalted
}
}
val wrAccessRegisterCommand = COMMANDWrEn && commandWrIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
val regAccessRegisterCommand = autoexec && commandRegIsAccessRegister && (ABSTRACTCSReg.cmderr === 0.U)
//------------------------
// Variable ROM STATE MACHINE
// -----------------------
when (ctrlStateReg === CtrlState(Waiting)){
when (wrAccessRegisterCommand || regAccessRegisterCommand) {
ctrlStateNxt := CtrlState(CheckGenerate)
}.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type.
errorUnsupported := true.B
}.elsewhen (autoexec && commandRegIsUnsupported) {
errorUnsupported := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){
// We use this state to ensure that the COMMAND has been
// registered by the time that we need to use it, to avoid
// generating it directly from the COMMANDWrData.
// This 'commandRegIsUnsupported' is really just checking the
// AccessRegisterCommand parameters (regno)
when (commandRegIsUnsupported) {
errorUnsupported := true.B
ctrlStateNxt := CtrlState(Waiting)
}.elsewhen (commandRegBadHaltResume){
errorHaltResume := true.B
ctrlStateNxt := CtrlState(Waiting)
}.otherwise {
when(accessRegIsCustom) {
ctrlStateNxt := CtrlState(Custom)
}.otherwise {
ctrlStateNxt := CtrlState(Exec)
goAbstract := true.B
}
}
}.elsewhen (ctrlStateReg === CtrlState(Exec)) {
// We can't just look at 'hartHalted' here, because
// hartHaltedWrEn is overloaded to mean 'got an ebreak'
// which may have happened when we were already halted.
when(goReg === false.B && hartHaltedWrEn && (hartSelFuncs.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
ctrlStateNxt := CtrlState(Waiting)
}
when(hartExceptionWrEn) {
assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U)
ctrlStateNxt := CtrlState(Waiting)
errorException := true.B
}
}.elsewhen (ctrlStateReg === CtrlState(Custom)) {
assert(needCustom.B, "Should not be in custom state unless we need it.")
goCustom := true.B
val (custom, customP) = customNode.in.head
when (custom.ready && custom.valid) {
ctrlStateNxt := CtrlState(Waiting)
}
}
when (~io.dmactive || ~dmAuthenticated) {
ctrlStateReg := CtrlState(Waiting)
}.otherwise {
ctrlStateReg := ctrlStateNxt
}
assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),
"Unexpected EXCEPTION write: should only get it in Debug Module EXEC state")
}
}
// Wrapper around TL Debug Module Inner and an Async DMI Sink interface.
// Handles the synchronization of dmactive, which is used as a synchronous reset
// inside the Inner block.
// Also is the Sink side of hartsel & resumereq fields of DMCONTROL.
class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int, beatBytes: Int)(implicit p: Parameters) extends LazyModule{
val cfg = p(DebugModuleKey).get
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents, beatBytes))
val dmiXing = LazyModule(new TLAsyncCrossingSink(AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
val dmiNode = dmiXing.node
val tlNode = dmInner.tlNode
dmInner.dmiNode := dmiXing.node
// Require that there are no registers in TL interface, so that spurious
// processor accesses to the DM don't need to enable the clock. We don't
// require this property of the SBA, because the debugger is responsible for
// raising dmactive (hence enabling the clock) during these transactions.
require(dmInner.tlNode.concurrency == 0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
// Clock/reset domains:
// debug_clock / debug_reset = Debug inner domain
// tl_clock / tl_reset = tilelink domain (External: clock / reset)
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
// These are all asynchronous and come from Outer
/** reset signal for DM */
val dmactive = Input(Bool())
/** conrol signals for Inner
*
* generated in Outer
*/
val innerCtrl = Flipped(new AsyncBundle(new DebugInternalBundle(getNComponents()), AsyncQueueParams.singleton(safe=cfg.crossingHasSafeReset)))
// This comes from tlClk domain.
/** debug available status */
val debugUnavail = Input(Vec(getNComponents(), Bool()))
/** debug interruption*/
val hgDebugInt = Output(Vec(getNComponents(), Bool()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(getNComponents(), Bool()))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
val rf_reset = IO(Input(Reset())) // RF transform
childClock := io.debug_clock
childReset := io.debug_reset
override def provideImplicitClockToLazyChildren = true
val dmactive_synced = withClockAndReset(childClock, childReset) {
val dmactive_synced = AsyncResetSynchronizerShiftReg(in=io.dmactive, sync=3, name=Some("dmactiveSync"))
dmInner.module.clock := io.debug_clock
dmInner.module.reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.dmactive := dmactive_synced
dmInner.module.io.innerCtrl <> FromAsyncBundle(io.innerCtrl)
dmInner.module.io.debugUnavail := io.debugUnavail
io.hgDebugInt := dmInner.module.io.hgDebugInt
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
dmactive_synced
}
}
}
/** Create a version of the TLDebugModule which includes a synchronization interface
* internally for the DMI. This is no longer optional outside of this module
* because the Clock must run when tl_clock isn't running or tl_reset is asserted.
*/
class TLDebugModule(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("debug-controller", Seq("sifive,debug-013","riscv,debug-013")){
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val attach = Map(
"debug-attach" -> (
(if (p(ExportDebug).apb) Seq(ResourceString("apb")) else Seq()) ++
(if (p(ExportDebug).jtag) Seq(ResourceString("jtag")) else Seq()) ++
(if (p(ExportDebug).cjtag) Seq(ResourceString("cjtag")) else Seq()) ++
(if (p(ExportDebug).dmi) Seq(ResourceString("dmi")) else Seq())))
Description(name, mapping ++ attach)
}
}
val dmOuter : TLDebugModuleOuterAsync = LazyModule(new TLDebugModuleOuterAsync(device)(p))
val dmInner : TLDebugModuleInnerAsync = LazyModule(new TLDebugModuleInnerAsync(device, () => {dmOuter.dmOuter.intnode.edges.out.size}, beatBytes)(p))
val node = dmInner.tlNode
val intnode = dmOuter.intnode
val apbNodeOpt = dmOuter.apbNodeOpt
dmInner.dmiNode := dmOuter.dmiInnerNode
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val nComponents = dmOuter.dmOuter.intnode.edges.out.size
// Clock/reset domains:
// tl_clock / tl_reset = tilelink domain
// debug_clock / debug_reset = Inner debug (synchronous to tl_clock)
// apb_clock / apb_reset = Outer debug with APB
// dmiClock / dmiReset = Outer debug without APB
//
val io = IO(new Bundle {
val debug_clock = Input(Clock())
val debug_reset = Input(Reset())
val tl_clock = Input(Clock())
val tl_reset = Input(Reset())
/** Debug control signals generated in Outer */
val ctrl = new DebugCtrlBundle(nComponents)
/** Debug Module Interface bewteen DM and DTM
*
* The DTM provides access to one or more Debug Modules (DMs) using DMI
*/
val dmi = (!p(ExportDebug).apb).option(Flipped(new ClockedDMIIO()))
val apb_clock = p(ExportDebug).apb.option(Input(Clock()))
val apb_reset = p(ExportDebug).apb.option(Input(Reset()))
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
/** vector to indicate which hart is in reset
*
* dm receives it from core and sends it to Inner
*/
val hartIsInReset = Input(Vec(nComponents, Bool()))
/** hart reset request generated by hartreset-logic in Outer */
val hartResetReq = p(DebugModuleKey).get.hasHartResets.option(Output(Vec(nComponents, Bool())))
/** Debug Authentication signals from core */
val auth = p(DebugModuleKey).get.hasAuthentication.option(new DebugAuthenticationIO())
})
childClock := io.tl_clock
childReset := io.tl_reset
override def provideImplicitClockToLazyChildren = true
dmOuter.module.io.dmi.foreach { dmOuterDMI =>
dmOuterDMI <> io.dmi.get.dmi
dmOuter.module.io.dmi_reset := io.dmi.get.dmiReset
dmOuter.module.io.dmi_clock := io.dmi.get.dmiClock
dmOuter.module.rf_reset := io.dmi.get.dmiReset
}
(io.apb_clock zip io.apb_reset) foreach { case (c, r) =>
dmOuter.module.io.dmi_reset := r
dmOuter.module.io.dmi_clock := c
dmOuter.module.rf_reset := r
}
dmInner.module.rf_reset := io.debug_reset
dmInner.module.io.debug_clock := io.debug_clock
dmInner.module.io.debug_reset := io.debug_reset
dmInner.module.io.tl_clock := io.tl_clock
dmInner.module.io.tl_reset := io.tl_reset
dmInner.module.io.innerCtrl <> dmOuter.module.io.innerCtrl
dmInner.module.io.dmactive := dmOuter.module.io.ctrl.dmactive
dmInner.module.io.debugUnavail := io.ctrl.debugUnavail
dmOuter.module.io.hgDebugInt := dmInner.module.io.hgDebugInt
io.ctrl <> dmOuter.module.io.ctrl
io.extTrigger.foreach { x => dmInner.module.io.extTrigger.foreach {y => x <> y}}
dmInner.module.io.hartIsInReset := io.hartIsInReset
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.auth.foreach { x => dmOuter.module.io.dmAuthenticated.get := x.dmAuthenticated }
io.auth.foreach { x => dmInner.module.io.auth.foreach {y => x <> y}}
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLDebugModuleOuter( // @[Debug.scala:340:9]
input clock, // @[Debug.scala:340:9]
input reset, // @[Debug.scala:340:9]
output auto_dmi_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dmi_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_dmi_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_dmi_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_dmi_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_dmi_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_dmi_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_dmi_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_int_out_7_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_6_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_5_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_4_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_3_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_2_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25]
output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25]
output io_ctrl_ndreset, // @[Debug.scala:348:16]
output io_ctrl_dmactive, // @[Debug.scala:348:16]
input io_ctrl_dmactiveAck, // @[Debug.scala:348:16]
input io_innerCtrl_ready, // @[Debug.scala:348:16]
output io_innerCtrl_valid, // @[Debug.scala:348:16]
output io_innerCtrl_bits_resumereq, // @[Debug.scala:348:16]
output [9:0] io_innerCtrl_bits_hartsel, // @[Debug.scala:348:16]
output io_innerCtrl_bits_ackhavereset, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hasel, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_0, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_1, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_2, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_3, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_4, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_5, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_6, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hamask_7, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_0, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_1, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_2, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_3, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_4, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_5, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_6, // @[Debug.scala:348:16]
output io_innerCtrl_bits_hrmask_7, // @[Debug.scala:348:16]
input io_hgDebugInt_0, // @[Debug.scala:348:16]
input io_hgDebugInt_1, // @[Debug.scala:348:16]
input io_hgDebugInt_2, // @[Debug.scala:348:16]
input io_hgDebugInt_3, // @[Debug.scala:348:16]
input io_hgDebugInt_4, // @[Debug.scala:348:16]
input io_hgDebugInt_5, // @[Debug.scala:348:16]
input io_hgDebugInt_6, // @[Debug.scala:348:16]
input io_hgDebugInt_7 // @[Debug.scala:348:16]
);
wire out_woready_17; // @[RegisterRouter.scala:87:24]
wire out_woready_16; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_17; // @[RegisterRouter.scala:87:24]
wire out_roready_16; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_17; // @[RegisterRouter.scala:87:24]
wire out_wivalid_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_17; // @[RegisterRouter.scala:87:24]
wire out_rivalid_16; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [2:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire auto_dmi_in_a_valid_0 = auto_dmi_in_a_valid; // @[Debug.scala:340:9]
wire [2:0] auto_dmi_in_a_bits_opcode_0 = auto_dmi_in_a_bits_opcode; // @[Debug.scala:340:9]
wire [6:0] auto_dmi_in_a_bits_address_0 = auto_dmi_in_a_bits_address; // @[Debug.scala:340:9]
wire [31:0] auto_dmi_in_a_bits_data_0 = auto_dmi_in_a_bits_data; // @[Debug.scala:340:9]
wire auto_dmi_in_d_ready_0 = auto_dmi_in_d_ready; // @[Debug.scala:340:9]
wire io_ctrl_dmactiveAck_0 = io_ctrl_dmactiveAck; // @[Debug.scala:340:9]
wire io_innerCtrl_ready_0 = io_innerCtrl_ready; // @[Debug.scala:340:9]
wire io_hgDebugInt_0_0 = io_hgDebugInt_0; // @[Debug.scala:340:9]
wire io_hgDebugInt_1_0 = io_hgDebugInt_1; // @[Debug.scala:340:9]
wire io_hgDebugInt_2_0 = io_hgDebugInt_2; // @[Debug.scala:340:9]
wire io_hgDebugInt_3_0 = io_hgDebugInt_3; // @[Debug.scala:340:9]
wire io_hgDebugInt_4_0 = io_hgDebugInt_4; // @[Debug.scala:340:9]
wire io_hgDebugInt_5_0 = io_hgDebugInt_5; // @[Debug.scala:340:9]
wire io_hgDebugInt_6_0 = io_hgDebugInt_6; // @[Debug.scala:340:9]
wire io_hgDebugInt_7_0 = io_hgDebugInt_7; // @[Debug.scala:340:9]
wire [11:0] _HARTINFORdData_WIRE_dataaddr = 12'h0; // @[Debug.scala:418:47]
wire [3:0] _HARTINFORdData_WIRE_nscratch = 4'h0; // @[Debug.scala:418:47]
wire [3:0] _HARTINFORdData_WIRE_datasize = 4'h0; // @[Debug.scala:418:47]
wire [9:0] _DMCONTROLReset_WIRE_hartsello = 10'h0; // @[Debug.scala:377:47]
wire [9:0] _DMCONTROLReset_WIRE_hartselhi = 10'h0; // @[Debug.scala:377:47]
wire [9:0] DMCONTROLReset_hartsello = 10'h0; // @[Debug.scala:377:34]
wire [9:0] DMCONTROLReset_hartselhi = 10'h0; // @[Debug.scala:377:34]
wire [9:0] _DMCONTROLNxt_WIRE_hartsello = 10'h0; // @[Debug.scala:378:45]
wire [9:0] _DMCONTROLNxt_WIRE_hartselhi = 10'h0; // @[Debug.scala:378:45]
wire [9:0] _DMCONTROLReg_WIRE_hartsello = 10'h0; // @[Debug.scala:379:68]
wire [9:0] _DMCONTROLReg_WIRE_hartselhi = 10'h0; // @[Debug.scala:379:68]
wire [9:0] _DMCONTROLWrData_WIRE_hartsello = 10'h0; // @[Debug.scala:382:48]
wire [9:0] _DMCONTROLWrData_WIRE_hartselhi = 10'h0; // @[Debug.scala:382:48]
wire [9:0] DMCONTROLWrData_hartselhi = 10'h0; // @[Debug.scala:382:35]
wire [7:0] _HARTINFORdData_WIRE_reserved0 = 8'h0; // @[Debug.scala:418:47]
wire [7:0] HARTINFORdData_reserved0 = 8'h0; // @[Debug.scala:418:34]
wire [3:0] HARTINFORdData_nscratch = 4'h1; // @[OneHot.scala:58:35]
wire [3:0] HARTINFORdData_datasize = 4'h8; // @[Debug.scala:418:34]
wire [16:0] _HAWINDOWSELWrData_WIRE_reserved0 = 17'h0; // @[Debug.scala:437:50]
wire [16:0] HAWINDOWSELWrData_reserved0 = 17'h0; // @[Debug.scala:437:37]
wire [16:0] _HAWINDOWSELNxt_WIRE_reserved0 = 17'h0; // @[Debug.scala:450:47]
wire [16:0] _HAWINDOWSELReg_WIRE_reserved0 = 17'h0; // @[Debug.scala:451:72]
wire [16:0] _HAWINDOWSELReset_WIRE_reserved0 = 17'h0; // @[Debug.scala:454:51]
wire [16:0] HAWINDOWSELReset_reserved0 = 17'h0; // @[Debug.scala:454:38]
wire [14:0] _HAWINDOWSELWrData_WIRE_hawindowsel = 15'h0; // @[Debug.scala:437:50]
wire [14:0] HAWINDOWSELWrData_hawindowsel = 15'h0; // @[Debug.scala:437:37]
wire [14:0] _HAWINDOWSELNxt_WIRE_hawindowsel = 15'h0; // @[Debug.scala:450:47]
wire [14:0] _HAWINDOWSELReg_WIRE_hawindowsel = 15'h0; // @[Debug.scala:451:72]
wire [14:0] _HAWINDOWSELReset_WIRE_hawindowsel = 15'h0; // @[Debug.scala:454:51]
wire [14:0] HAWINDOWSELReset_hawindowsel = 15'h0; // @[Debug.scala:454:38]
wire [2:0] out_maskMatch = 3'h1; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo = 16'hFFFF; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi = 16'hFFFF; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo = 16'hFFFF; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi = 16'hFFFF; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask = 32'hFFFFFFFF; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask = 32'hFFFFFFFF; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_rimask_T_6 = 7'h7F; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_wimask_T_6 = 7'h7F; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_romask_T_6 = 7'h7F; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_womask_T_6 = 7'h7F; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_4 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_5 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_6 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_7 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_4 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_5 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_6 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_7 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_13 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_13 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_13 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_13 = 8'hFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_rimask_T_4 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_wimask_T_4 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_romask_T_4 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_womask_T_4 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_rimask_T_14 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_wimask_T_14 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_romask_T_14 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_womask_T_14 = 12'hFFF; // @[RegisterRouter.scala:87:24]
wire [11:0] HARTINFORdData_dataaddr = 12'h380; // @[Debug.scala:418:34]
wire [11:0] _out_T_151 = 12'h380; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_152 = 12'h380; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_prepend_T_12 = 12'h380; // @[RegisterRouter.scala:87:24]
wire [15:0] out_prepend_12 = 16'h8380; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_160 = 16'h8380; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_161 = 16'h8380; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_13 = 16'h8380; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_5 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_5 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_5 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_5 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_rimask_T_17 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_wimask_T_17 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_romask_T_17 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_womask_T_17 = 3'h7; // @[RegisterRouter.scala:87:24]
wire [16:0] out_prepend_13 = 17'h18380; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_169 = 17'h18380; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_T_170 = 17'h18380; // @[RegisterRouter.scala:87:24]
wire [16:0] _out_prepend_T_14 = 17'h18380; // @[RegisterRouter.scala:87:24]
wire [17:0] out_prepend_14 = 18'h18380; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_178 = 20'h18380; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_179 = 20'h18380; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_prepend_T_15 = 20'h18380; // @[RegisterRouter.scala:87:24]
wire [23:0] out_prepend_15 = 24'h118380; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_187 = 24'h118380; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_188 = 24'h118380; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_1 = 32'h118380; // @[MuxLiteral.scala:49:48]
wire [31:0] _HAWINDOWRdData_WIRE_maskdata = 32'h0; // @[Debug.scala:440:47]
wire [31:0] _HAWINDOWWrData_WIRE_maskdata = 32'h0; // @[Debug.scala:441:47]
wire [31:0] _HAMASKRst_WIRE_maskdata = 32'h0; // @[Debug.scala:475:46]
wire [31:0] HAMASKRst_maskdata = 32'h0; // @[Debug.scala:475:33]
wire [31:0] _HAMASKNxt_WIRE_maskdata = 32'h0; // @[Debug.scala:476:46]
wire [31:0] _HAMASKReg_WIRE_maskdata = 32'h0; // @[Debug.scala:477:66]
wire [31:0] _out_out_bits_data_WIRE_1_3 = 32'h0; // @[MuxLiteral.scala:49:48]
wire [31:0] dmiNodeIn_d_bits_d_data = 32'h0; // @[Edges.scala:792:17]
wire [1:0] auto_dmi_in_d_bits_param = 2'h0; // @[Debug.scala:340:9]
wire [1:0] dmiNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] _DMCONTROLReset_WIRE_reserved1 = 2'h0; // @[Debug.scala:377:47]
wire [1:0] DMCONTROLReset_reserved1 = 2'h0; // @[Debug.scala:377:34]
wire [1:0] _DMCONTROLNxt_WIRE_reserved1 = 2'h0; // @[Debug.scala:378:45]
wire [1:0] _DMCONTROLReg_WIRE_reserved1 = 2'h0; // @[Debug.scala:379:68]
wire [1:0] _DMCONTROLWrData_WIRE_reserved1 = 2'h0; // @[Debug.scala:382:48]
wire [1:0] DMCONTROLWrData_reserved1 = 2'h0; // @[Debug.scala:382:35]
wire [1:0] dmiNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire [3:0] auto_dmi_in_a_bits_mask = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] dmiNodeIn_a_bits_mask = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] in_bits_mask = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] out_front_bits_mask = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_rimask_T_15 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_wimask_T_15 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_romask_T_15 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_womask_T_15 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_rimask_T_18 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_wimask_T_18 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_romask_T_18 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire [3:0] _out_womask_T_18 = 4'hF; // @[RegisterRouter.scala:73:18, :87:24]
wire auto_dmi_in_a_bits_source = 1'h0; // @[Debug.scala:340:9]
wire auto_dmi_in_a_bits_corrupt = 1'h0; // @[Debug.scala:340:9]
wire auto_dmi_in_d_bits_source = 1'h0; // @[Debug.scala:340:9]
wire auto_dmi_in_d_bits_sink = 1'h0; // @[Debug.scala:340:9]
wire auto_dmi_in_d_bits_denied = 1'h0; // @[Debug.scala:340:9]
wire auto_dmi_in_d_bits_corrupt = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_0 = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_1 = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_2 = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_3 = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_4 = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_5 = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_6 = 1'h0; // @[Debug.scala:340:9]
wire io_ctrl_debugUnavail_7 = 1'h0; // @[Debug.scala:340:9]
wire dmiNodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire dmiNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _DMCONTROLReset_WIRE_haltreq = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_resumereq = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_hartreset = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_ackhavereset = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_reserved0 = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_hasel = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_setresethaltreq = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_clrresethaltreq = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_ndmreset = 1'h0; // @[Debug.scala:377:47]
wire _DMCONTROLReset_WIRE_dmactive = 1'h0; // @[Debug.scala:377:47]
wire DMCONTROLReset_haltreq = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_resumereq = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_hartreset = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_ackhavereset = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_reserved0 = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_hasel = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_setresethaltreq = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_clrresethaltreq = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_ndmreset = 1'h0; // @[Debug.scala:377:34]
wire DMCONTROLReset_dmactive = 1'h0; // @[Debug.scala:377:34]
wire _DMCONTROLNxt_WIRE_haltreq = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_resumereq = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_hartreset = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_ackhavereset = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_reserved0 = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_hasel = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_setresethaltreq = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_clrresethaltreq = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_ndmreset = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLNxt_WIRE_dmactive = 1'h0; // @[Debug.scala:378:45]
wire _DMCONTROLReg_WIRE_haltreq = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_resumereq = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_hartreset = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_ackhavereset = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_reserved0 = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_hasel = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_setresethaltreq = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_clrresethaltreq = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_ndmreset = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLReg_WIRE_dmactive = 1'h0; // @[Debug.scala:379:68]
wire _DMCONTROLWrData_WIRE_haltreq = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_resumereq = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_hartreset = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_ackhavereset = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_reserved0 = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_hasel = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_setresethaltreq = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_clrresethaltreq = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_ndmreset = 1'h0; // @[Debug.scala:382:48]
wire _DMCONTROLWrData_WIRE_dmactive = 1'h0; // @[Debug.scala:382:48]
wire DMCONTROLWrData_hartreset = 1'h0; // @[Debug.scala:382:35]
wire DMCONTROLWrData_reserved0 = 1'h0; // @[Debug.scala:382:35]
wire hartresetWrEn = 1'h0; // @[Debug.scala:391:39]
wire _HARTINFORdData_WIRE_dataaccess = 1'h0; // @[Debug.scala:418:47]
wire _hamask_WIRE_0 = 1'h0; // @[Debug.scala:432:34]
wire _hamask_WIRE_1 = 1'h0; // @[Debug.scala:432:34]
wire _hamask_WIRE_2 = 1'h0; // @[Debug.scala:432:34]
wire _hamask_WIRE_3 = 1'h0; // @[Debug.scala:432:34]
wire _hamask_WIRE_4 = 1'h0; // @[Debug.scala:432:34]
wire _hamask_WIRE_5 = 1'h0; // @[Debug.scala:432:34]
wire _hamask_WIRE_6 = 1'h0; // @[Debug.scala:432:34]
wire _hamask_WIRE_7 = 1'h0; // @[Debug.scala:432:34]
wire HAWINDOWSELWrEn = 1'h0; // @[Debug.scala:438:37]
wire _hrmaskReg_WIRE_0 = 1'h0; // @[Debug.scala:519:62]
wire _hrmaskReg_WIRE_1 = 1'h0; // @[Debug.scala:519:62]
wire _hrmaskReg_WIRE_2 = 1'h0; // @[Debug.scala:519:62]
wire _hrmaskReg_WIRE_3 = 1'h0; // @[Debug.scala:519:62]
wire _hrmaskReg_WIRE_4 = 1'h0; // @[Debug.scala:519:62]
wire _hrmaskReg_WIRE_5 = 1'h0; // @[Debug.scala:519:62]
wire _hrmaskReg_WIRE_6 = 1'h0; // @[Debug.scala:519:62]
wire _hrmaskReg_WIRE_7 = 1'h0; // @[Debug.scala:519:62]
wire in_bits_extra_tlrr_extra_source = 1'h0; // @[RegisterRouter.scala:73:18]
wire out_bits_extra_tlrr_extra_source = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_front_bits_extra_tlrr_extra_source = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_24 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_25 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_33 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_42 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_51 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_60 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_61 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_71 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_80 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_81 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_82 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_83 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_90 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_91 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_92 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_101 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_116 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_138 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_147 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_156 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_157 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_158 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_166 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_167 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_168 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_174 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_175 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_176 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_177 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_183 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_184 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_185 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_186 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire dmiNodeIn_d_bits_d_source = 1'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire _debugIntNxt_WIRE_0 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntNxt_WIRE_1 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntNxt_WIRE_2 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntNxt_WIRE_3 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntNxt_WIRE_4 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntNxt_WIRE_5 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntNxt_WIRE_6 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntNxt_WIRE_7 = 1'h0; // @[Debug.scala:599:39]
wire _debugIntRegs_WIRE_0 = 1'h0; // @[Debug.scala:600:67]
wire _debugIntRegs_WIRE_1 = 1'h0; // @[Debug.scala:600:67]
wire _debugIntRegs_WIRE_2 = 1'h0; // @[Debug.scala:600:67]
wire _debugIntRegs_WIRE_3 = 1'h0; // @[Debug.scala:600:67]
wire _debugIntRegs_WIRE_4 = 1'h0; // @[Debug.scala:600:67]
wire _debugIntRegs_WIRE_5 = 1'h0; // @[Debug.scala:600:67]
wire _debugIntRegs_WIRE_6 = 1'h0; // @[Debug.scala:600:67]
wire _debugIntRegs_WIRE_7 = 1'h0; // @[Debug.scala:600:67]
wire [1:0] auto_dmi_in_a_bits_size = 2'h2; // @[Debug.scala:340:9]
wire [1:0] auto_dmi_in_d_bits_size = 2'h2; // @[Debug.scala:340:9]
wire [1:0] dmiNodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17]
wire [1:0] dmiNodeIn_d_bits_size = 2'h2; // @[MixedNode.scala:551:17]
wire [1:0] in_bits_extra_tlrr_extra_size = 2'h2; // @[RegisterRouter.scala:73:18]
wire [1:0] out_bits_extra_tlrr_extra_size = 2'h2; // @[RegisterRouter.scala:87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = 2'h2; // @[RegisterRouter.scala:87:24]
wire [1:0] dmiNodeIn_d_bits_d_size = 2'h2; // @[Edges.scala:792:17]
wire [2:0] auto_dmi_in_a_bits_param = 3'h0; // @[Debug.scala:340:9]
wire [2:0] dmiNodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] _HARTINFORdData_WIRE_reserved1 = 3'h0; // @[Debug.scala:418:47]
wire [2:0] HARTINFORdData_reserved1 = 3'h0; // @[Debug.scala:418:34]
wire [2:0] dmiNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire dmiNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire HARTINFORdData_dataaccess = 1'h1; // @[Debug.scala:418:34]
wire _out_frontMask_T = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_16 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rimask_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wimask_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_romask_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_womask_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire dmiNodeIn_a_valid = auto_dmi_in_a_valid_0; // @[Debug.scala:340:9]
wire [2:0] dmiNodeIn_a_bits_opcode = auto_dmi_in_a_bits_opcode_0; // @[Debug.scala:340:9]
wire [6:0] dmiNodeIn_a_bits_address = auto_dmi_in_a_bits_address_0; // @[Debug.scala:340:9]
wire [31:0] dmiNodeIn_a_bits_data = auto_dmi_in_a_bits_data_0; // @[Debug.scala:340:9]
wire dmiNodeIn_d_ready = auto_dmi_in_d_ready_0; // @[Debug.scala:340:9]
wire dmiNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] dmiNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [31:0] dmiNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire x1_intnodeOut_6_0; // @[MixedNode.scala:542:17]
wire x1_intnodeOut_5_0; // @[MixedNode.scala:542:17]
wire x1_intnodeOut_4_0; // @[MixedNode.scala:542:17]
wire x1_intnodeOut_3_0; // @[MixedNode.scala:542:17]
wire x1_intnodeOut_2_0; // @[MixedNode.scala:542:17]
wire x1_intnodeOut_1_0; // @[MixedNode.scala:542:17]
wire x1_intnodeOut_0; // @[MixedNode.scala:542:17]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire _io_innerCtrl_valid_T; // @[Debug.scala:641:54]
wire _io_innerCtrl_bits_resumereq_T_1; // @[Debug.scala:643:83]
wire [9:0] _io_innerCtrl_bits_hartsel_T; // @[Debug.scala:642:42]
wire _io_innerCtrl_bits_ackhavereset_T_1; // @[Debug.scala:644:89]
wire _io_innerCtrl_bits_hasel_T; // @[Debug.scala:647:42]
wire hamask_0; // @[Debug.scala:432:26]
wire hamask_1; // @[Debug.scala:432:26]
wire hamask_2; // @[Debug.scala:432:26]
wire hamask_3; // @[Debug.scala:432:26]
wire hamask_4; // @[Debug.scala:432:26]
wire hamask_5; // @[Debug.scala:432:26]
wire hamask_6; // @[Debug.scala:432:26]
wire hamask_7; // @[Debug.scala:432:26]
wire hrmask_0; // @[Debug.scala:517:25]
wire hrmask_1; // @[Debug.scala:517:25]
wire hrmask_2; // @[Debug.scala:517:25]
wire hrmask_3; // @[Debug.scala:517:25]
wire hrmask_4; // @[Debug.scala:517:25]
wire hrmask_5; // @[Debug.scala:517:25]
wire hrmask_6; // @[Debug.scala:517:25]
wire hrmask_7; // @[Debug.scala:517:25]
wire auto_dmi_in_a_ready_0; // @[Debug.scala:340:9]
wire [2:0] auto_dmi_in_d_bits_opcode_0; // @[Debug.scala:340:9]
wire [31:0] auto_dmi_in_d_bits_data_0; // @[Debug.scala:340:9]
wire auto_dmi_in_d_valid_0; // @[Debug.scala:340:9]
wire auto_int_out_7_0_0; // @[Debug.scala:340:9]
wire auto_int_out_6_0_0; // @[Debug.scala:340:9]
wire auto_int_out_5_0_0; // @[Debug.scala:340:9]
wire auto_int_out_4_0_0; // @[Debug.scala:340:9]
wire auto_int_out_3_0_0; // @[Debug.scala:340:9]
wire auto_int_out_2_0_0; // @[Debug.scala:340:9]
wire auto_int_out_1_0_0; // @[Debug.scala:340:9]
wire auto_int_out_0_0_0; // @[Debug.scala:340:9]
wire io_ctrl_ndreset_0; // @[Debug.scala:340:9]
wire io_ctrl_dmactive_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_0_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_1_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_2_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_3_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_4_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_5_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_6_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hamask_7_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_0_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_1_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_2_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_3_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_4_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_5_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_6_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hrmask_7_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_resumereq_0; // @[Debug.scala:340:9]
wire [9:0] io_innerCtrl_bits_hartsel_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_ackhavereset_0; // @[Debug.scala:340:9]
wire io_innerCtrl_bits_hasel_0; // @[Debug.scala:340:9]
wire io_innerCtrl_valid_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T; // @[Debug.scala:605:60]
assign auto_int_out_0_0_0 = intnodeOut_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T_1; // @[Debug.scala:605:60]
assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T_2; // @[Debug.scala:605:60]
assign auto_int_out_2_0_0 = x1_intnodeOut_1_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T_3; // @[Debug.scala:605:60]
assign auto_int_out_3_0_0 = x1_intnodeOut_2_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T_4; // @[Debug.scala:605:60]
assign auto_int_out_4_0_0 = x1_intnodeOut_3_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T_5; // @[Debug.scala:605:60]
assign auto_int_out_5_0_0 = x1_intnodeOut_4_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T_6; // @[Debug.scala:605:60]
assign auto_int_out_6_0_0 = x1_intnodeOut_5_0; // @[Debug.scala:340:9]
wire _intnodeOut_0_T_7; // @[Debug.scala:605:60]
assign auto_int_out_7_0_0 = x1_intnodeOut_6_0; // @[Debug.scala:340:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_dmi_in_a_ready_0 = dmiNodeIn_a_ready; // @[Debug.scala:340:9]
wire in_valid = dmiNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [31:0] in_bits_data = dmiNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = dmiNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_dmi_in_d_valid_0 = dmiNodeIn_d_valid; // @[Debug.scala:340:9]
assign auto_dmi_in_d_bits_opcode_0 = dmiNodeIn_d_bits_opcode; // @[Debug.scala:340:9]
wire [31:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_dmi_in_d_bits_data_0 = dmiNodeIn_d_bits_data; // @[Debug.scala:340:9]
wire DMCONTROLNxt_haltreq; // @[Debug.scala:378:32]
wire DMCONTROLNxt_resumereq; // @[Debug.scala:378:32]
wire DMCONTROLNxt_hartreset; // @[Debug.scala:378:32]
wire DMCONTROLNxt_ackhavereset; // @[Debug.scala:378:32]
wire DMCONTROLNxt_reserved0; // @[Debug.scala:378:32]
wire DMCONTROLNxt_hasel; // @[Debug.scala:378:32]
wire [9:0] DMCONTROLNxt_hartsello; // @[Debug.scala:378:32]
wire [9:0] DMCONTROLNxt_hartselhi; // @[Debug.scala:378:32]
wire [1:0] DMCONTROLNxt_reserved1; // @[Debug.scala:378:32]
wire DMCONTROLNxt_setresethaltreq; // @[Debug.scala:378:32]
wire DMCONTROLNxt_clrresethaltreq; // @[Debug.scala:378:32]
wire DMCONTROLNxt_ndmreset; // @[Debug.scala:378:32]
wire DMCONTROLNxt_dmactive; // @[Debug.scala:378:32]
reg DMCONTROLReg_haltreq; // @[Debug.scala:379:31]
reg DMCONTROLReg_resumereq; // @[Debug.scala:379:31]
reg DMCONTROLReg_hartreset; // @[Debug.scala:379:31]
reg DMCONTROLReg_ackhavereset; // @[Debug.scala:379:31]
reg DMCONTROLReg_reserved0; // @[Debug.scala:379:31]
reg DMCONTROLReg_hasel; // @[Debug.scala:379:31]
reg [9:0] DMCONTROLReg_hartsello; // @[Debug.scala:379:31]
reg [9:0] DMCONTROLReg_hartselhi; // @[Debug.scala:379:31]
reg [1:0] DMCONTROLReg_reserved1; // @[Debug.scala:379:31]
reg DMCONTROLReg_setresethaltreq; // @[Debug.scala:379:31]
reg DMCONTROLReg_clrresethaltreq; // @[Debug.scala:379:31]
reg DMCONTROLReg_ndmreset; // @[Debug.scala:379:31]
assign io_ctrl_ndreset_0 = DMCONTROLReg_ndmreset; // @[Debug.scala:340:9, :379:31]
reg DMCONTROLReg_dmactive; // @[Debug.scala:379:31]
assign io_ctrl_dmactive_0 = DMCONTROLReg_dmactive; // @[Debug.scala:340:9, :379:31]
wire _out_T_122; // @[RegisterRouter.scala:87:24]
wire _out_T_113; // @[RegisterRouter.scala:87:24]
wire _out_T_95; // @[RegisterRouter.scala:87:24]
wire _out_T_75; // @[RegisterRouter.scala:87:24]
wire _out_T_37; // @[RegisterRouter.scala:87:24]
wire _out_T_28; // @[RegisterRouter.scala:87:24]
wire _out_T_17; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
wire DMCONTROLWrData_haltreq; // @[Debug.scala:382:35]
wire DMCONTROLWrData_resumereq; // @[Debug.scala:382:35]
wire DMCONTROLWrData_ackhavereset; // @[Debug.scala:382:35]
wire DMCONTROLWrData_hasel; // @[Debug.scala:382:35]
wire [9:0] DMCONTROLWrData_hartsello; // @[Debug.scala:382:35]
wire DMCONTROLWrData_setresethaltreq; // @[Debug.scala:382:35]
wire DMCONTROLWrData_clrresethaltreq; // @[Debug.scala:382:35]
wire DMCONTROLWrData_ndmreset; // @[Debug.scala:382:35]
wire DMCONTROLWrData_dmactive; // @[Debug.scala:382:35]
wire out_f_woready; // @[RegisterRouter.scala:87:24]
wire dmactiveWrEn; // @[Debug.scala:384:39]
wire out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire ndmresetWrEn; // @[Debug.scala:385:39]
wire out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire clrresethaltreqWrEn; // @[Debug.scala:386:39]
wire out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire setresethaltreqWrEn; // @[Debug.scala:387:39]
wire out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire hartselloWrEn; // @[Debug.scala:388:39]
wire out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire haselWrEn; // @[Debug.scala:389:39]
wire out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire ackhaveresetWrEn; // @[Debug.scala:390:39]
wire out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire resumereqWrEn; // @[Debug.scala:392:39]
wire out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire haltreqWrEn; // @[Debug.scala:393:39]
assign DMCONTROLNxt_resumereq = DMCONTROLReg_dmactive & DMCONTROLReg_resumereq; // @[Debug.scala:378:32, :379:31, :397:18, :398:22, :399:20]
assign DMCONTROLNxt_ackhavereset = DMCONTROLReg_dmactive & DMCONTROLReg_ackhavereset; // @[Debug.scala:378:32, :379:31, :397:18, :398:22, :399:20]
assign DMCONTROLNxt_reserved0 = DMCONTROLReg_dmactive & DMCONTROLReg_reserved0; // @[Debug.scala:378:32, :379:31, :397:18, :398:22, :399:20]
assign DMCONTROLNxt_hartselhi = DMCONTROLReg_dmactive ? DMCONTROLReg_hartselhi : 10'h0; // @[Debug.scala:378:32, :379:31, :397:18, :398:22, :399:20]
assign DMCONTROLNxt_reserved1 = DMCONTROLReg_dmactive ? DMCONTROLReg_reserved1 : 2'h0; // @[Debug.scala:378:32, :379:31, :397:18, :398:22, :399:20]
assign DMCONTROLNxt_setresethaltreq = DMCONTROLReg_dmactive & DMCONTROLReg_setresethaltreq; // @[Debug.scala:378:32, :379:31, :397:18, :398:22, :399:20]
assign DMCONTROLNxt_clrresethaltreq = DMCONTROLReg_dmactive & DMCONTROLReg_clrresethaltreq; // @[Debug.scala:378:32, :379:31, :397:18, :398:22, :399:20]
assign DMCONTROLNxt_ndmreset = DMCONTROLReg_dmactive & (ndmresetWrEn ? DMCONTROLWrData_ndmreset : DMCONTROLReg_ndmreset); // @[Debug.scala:378:32, :379:31, :382:35, :385:39, :397:18, :398:22, :399:20, :401:{47,75}]
wire [9:0] _DMCONTROLNxt_hartsello_T = {7'h0, DMCONTROLWrData_hartsello[2:0]}; // @[Debug.scala:382:35, :402:104]
assign DMCONTROLNxt_hartsello = DMCONTROLReg_dmactive ? (hartselloWrEn ? _DMCONTROLNxt_hartsello_T : DMCONTROLReg_hartsello) : 10'h0; // @[Debug.scala:378:32, :379:31, :388:39, :397:18, :398:22, :399:20, :402:{47,75,104}]
assign _io_innerCtrl_bits_hasel_T = haselWrEn ? DMCONTROLWrData_hasel : DMCONTROLReg_hasel; // @[Debug.scala:379:31, :382:35, :389:39, :397:18, :403:{47,75}, :647:42]
assign DMCONTROLNxt_hasel = DMCONTROLReg_dmactive & _io_innerCtrl_bits_hasel_T; // @[Debug.scala:378:32, :379:31, :398:22, :399:20, :403:47, :647:42]
assign DMCONTROLNxt_hartreset = DMCONTROLReg_dmactive & DMCONTROLReg_hartreset; // @[Debug.scala:378:32, :379:31, :398:22, :399:20, :404:47]
assign DMCONTROLNxt_haltreq = DMCONTROLReg_dmactive & (haltreqWrEn ? DMCONTROLWrData_haltreq : DMCONTROLReg_haltreq); // @[Debug.scala:378:32, :379:31, :382:35, :393:39, :397:18, :398:22, :399:20, :405:{47,75}]
assign DMCONTROLNxt_dmactive = dmactiveWrEn ? DMCONTROLWrData_dmactive : DMCONTROLReg_dmactive; // @[Debug.scala:378:32, :379:31, :382:35, :384:39, :398:22, :409:25, :410:29]
assign io_innerCtrl_bits_hamask_0_0 = hamask_0; // @[Debug.scala:340:9, :432:26]
assign io_innerCtrl_bits_hamask_1_0 = hamask_1; // @[Debug.scala:340:9, :432:26]
assign io_innerCtrl_bits_hamask_2_0 = hamask_2; // @[Debug.scala:340:9, :432:26]
assign io_innerCtrl_bits_hamask_3_0 = hamask_3; // @[Debug.scala:340:9, :432:26]
assign io_innerCtrl_bits_hamask_4_0 = hamask_4; // @[Debug.scala:340:9, :432:26]
assign io_innerCtrl_bits_hamask_5_0 = hamask_5; // @[Debug.scala:340:9, :432:26]
assign io_innerCtrl_bits_hamask_6_0 = hamask_6; // @[Debug.scala:340:9, :432:26]
assign io_innerCtrl_bits_hamask_7_0 = hamask_7; // @[Debug.scala:340:9, :432:26]
wire [31:0] HAWINDOWRdData_maskdata; // @[Debug.scala:440:34]
wire [31:0] _out_T_142 = HAWINDOWRdData_maskdata; // @[RegisterRouter.scala:87:24]
wire [31:0] HAWINDOWWrData_maskdata; // @[Debug.scala:441:34]
wire out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire HAWINDOWWrEn; // @[Debug.scala:442:34]
wire _innerCtrlValid_T_5 = HAWINDOWWrEn; // @[Debug.scala:442:34, :635:22]
wire [16:0] HAWINDOWSELNxt_reserved0; // @[Debug.scala:450:34]
wire [14:0] HAWINDOWSELNxt_hawindowsel; // @[Debug.scala:450:34]
reg [16:0] HAWINDOWSELReg_reserved0; // @[Debug.scala:451:33]
reg [14:0] HAWINDOWSELReg_hawindowsel; // @[Debug.scala:451:33]
assign HAWINDOWSELNxt_reserved0 = DMCONTROLReg_dmactive ? HAWINDOWSELReg_reserved0 : 17'h0; // @[Debug.scala:379:31, :450:34, :451:33, :456:22, :457:44, :458:24]
assign HAWINDOWSELNxt_hawindowsel = DMCONTROLReg_dmactive ? HAWINDOWSELReg_hawindowsel : 15'h0; // @[Debug.scala:379:31, :450:34, :451:33, :457:44, :458:24, :460:32]
wire [31:0] HAMASKNxt_maskdata; // @[Debug.scala:476:33]
reg [31:0] HAMASKReg_maskdata; // @[Debug.scala:477:32]
wire _T_30 = HAWINDOWSELReg_hawindowsel == 15'h0; // @[Debug.scala:451:33, :479:20]
wire [31:0] _HAWINDOWRdData_maskdata_T = {24'h0, HAMASKReg_maskdata[7:0]}; // @[Debug.scala:477:32, :480:55]
assign HAWINDOWRdData_maskdata = _T_30 ? _HAWINDOWRdData_maskdata_T : 32'h0; // @[Debug.scala:440:34, :470:31, :479:{20,52}, :480:{35,55}]
assign HAMASKNxt_maskdata = DMCONTROLReg_dmactive ? (HAWINDOWWrEn & _T_30 ? HAWINDOWWrData_maskdata : HAMASKReg_maskdata) : 32'h0; // @[Debug.scala:379:31, :441:34, :442:34, :476:33, :477:32, :479:20, :483:28, :484:46, :485:21, :487:{30,72}, :488:32]
wire tempWrData_0 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_0_1 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_0_2 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_0_3 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_0_4 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_0_5 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_0_6 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_0_7 = HAWINDOWWrData_maskdata[0]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1_1 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1_2 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1_3 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1_4 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1_5 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1_6 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_1_7 = HAWINDOWWrData_maskdata[1]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2_1 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2_2 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2_3 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2_4 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2_5 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2_6 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_2_7 = HAWINDOWWrData_maskdata[2]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3_1 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3_2 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3_3 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3_4 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3_5 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3_6 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_3_7 = HAWINDOWWrData_maskdata[3]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4_1 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4_2 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4_3 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4_4 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4_5 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4_6 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_4_7 = HAWINDOWWrData_maskdata[4]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5_1 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5_2 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5_3 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5_4 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5_5 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5_6 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_5_7 = HAWINDOWWrData_maskdata[5]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6_1 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6_2 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6_3 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6_4 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6_5 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6_6 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_6_7 = HAWINDOWWrData_maskdata[6]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7_1 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7_2 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7_3 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7_4 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7_5 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7_6 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_7_7 = HAWINDOWWrData_maskdata[7]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8_1 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8_2 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8_3 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8_4 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8_5 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8_6 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_8_7 = HAWINDOWWrData_maskdata[8]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9_1 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9_2 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9_3 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9_4 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9_5 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9_6 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_9_7 = HAWINDOWWrData_maskdata[9]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10_1 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10_2 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10_3 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10_4 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10_5 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10_6 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_10_7 = HAWINDOWWrData_maskdata[10]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11_1 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11_2 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11_3 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11_4 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11_5 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11_6 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_11_7 = HAWINDOWWrData_maskdata[11]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12_1 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12_2 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12_3 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12_4 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12_5 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12_6 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_12_7 = HAWINDOWWrData_maskdata[12]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13_1 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13_2 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13_3 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13_4 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13_5 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13_6 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_13_7 = HAWINDOWWrData_maskdata[13]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14_1 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14_2 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14_3 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14_4 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14_5 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14_6 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_14_7 = HAWINDOWWrData_maskdata[14]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15_1 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15_2 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15_3 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15_4 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15_5 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15_6 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_15_7 = HAWINDOWWrData_maskdata[15]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16_1 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16_2 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16_3 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16_4 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16_5 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16_6 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_16_7 = HAWINDOWWrData_maskdata[16]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17_1 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17_2 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17_3 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17_4 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17_5 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17_6 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_17_7 = HAWINDOWWrData_maskdata[17]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18_1 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18_2 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18_3 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18_4 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18_5 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18_6 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_18_7 = HAWINDOWWrData_maskdata[18]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19_1 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19_2 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19_3 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19_4 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19_5 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19_6 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_19_7 = HAWINDOWWrData_maskdata[19]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20_1 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20_2 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20_3 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20_4 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20_5 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20_6 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_20_7 = HAWINDOWWrData_maskdata[20]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21_1 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21_2 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21_3 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21_4 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21_5 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21_6 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_21_7 = HAWINDOWWrData_maskdata[21]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22_1 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22_2 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22_3 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22_4 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22_5 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22_6 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_22_7 = HAWINDOWWrData_maskdata[22]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23_1 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23_2 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23_3 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23_4 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23_5 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23_6 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_23_7 = HAWINDOWWrData_maskdata[23]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24_1 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24_2 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24_3 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24_4 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24_5 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24_6 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_24_7 = HAWINDOWWrData_maskdata[24]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25_1 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25_2 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25_3 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25_4 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25_5 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25_6 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_25_7 = HAWINDOWWrData_maskdata[25]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26_1 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26_2 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26_3 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26_4 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26_5 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26_6 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_26_7 = HAWINDOWWrData_maskdata[26]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27_1 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27_2 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27_3 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27_4 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27_5 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27_6 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_27_7 = HAWINDOWWrData_maskdata[27]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28_1 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28_2 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28_3 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28_4 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28_5 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28_6 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_28_7 = HAWINDOWWrData_maskdata[28]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29_1 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29_2 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29_3 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29_4 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29_5 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29_6 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_29_7 = HAWINDOWWrData_maskdata[29]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30_1 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30_2 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30_3 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30_4 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30_5 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30_6 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_30_7 = HAWINDOWWrData_maskdata[30]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31_1 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31_2 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31_3 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31_4 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31_5 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31_6 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempWrData_31_7 = HAWINDOWWrData_maskdata[31]; // @[Debug.scala:441:34, :495:54]
wire tempMaskReg_0 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_0_1 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_0_2 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_0_3 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_0_4 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_0_5 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_0_6 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_0_7 = HAMASKReg_maskdata[0]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1_1 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1_2 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1_3 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1_4 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1_5 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1_6 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_1_7 = HAMASKReg_maskdata[1]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2_1 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2_2 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2_3 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2_4 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2_5 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2_6 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_2_7 = HAMASKReg_maskdata[2]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3_1 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3_2 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3_3 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3_4 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3_5 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3_6 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_3_7 = HAMASKReg_maskdata[3]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4_1 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4_2 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4_3 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4_4 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4_5 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4_6 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_4_7 = HAMASKReg_maskdata[4]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5_1 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5_2 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5_3 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5_4 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5_5 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5_6 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_5_7 = HAMASKReg_maskdata[5]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6_1 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6_2 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6_3 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6_4 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6_5 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6_6 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_6_7 = HAMASKReg_maskdata[6]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7_1 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7_2 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7_3 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7_4 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7_5 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7_6 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_7_7 = HAMASKReg_maskdata[7]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8_1 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8_2 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8_3 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8_4 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8_5 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8_6 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_8_7 = HAMASKReg_maskdata[8]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9_1 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9_2 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9_3 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9_4 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9_5 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9_6 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_9_7 = HAMASKReg_maskdata[9]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10_1 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10_2 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10_3 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10_4 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10_5 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10_6 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_10_7 = HAMASKReg_maskdata[10]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11_1 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11_2 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11_3 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11_4 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11_5 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11_6 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_11_7 = HAMASKReg_maskdata[11]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12_1 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12_2 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12_3 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12_4 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12_5 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12_6 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_12_7 = HAMASKReg_maskdata[12]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13_1 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13_2 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13_3 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13_4 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13_5 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13_6 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_13_7 = HAMASKReg_maskdata[13]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14_1 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14_2 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14_3 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14_4 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14_5 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14_6 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_14_7 = HAMASKReg_maskdata[14]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15_1 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15_2 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15_3 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15_4 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15_5 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15_6 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_15_7 = HAMASKReg_maskdata[15]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16_1 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16_2 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16_3 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16_4 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16_5 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16_6 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_16_7 = HAMASKReg_maskdata[16]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17_1 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17_2 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17_3 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17_4 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17_5 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17_6 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_17_7 = HAMASKReg_maskdata[17]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18_1 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18_2 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18_3 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18_4 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18_5 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18_6 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_18_7 = HAMASKReg_maskdata[18]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19_1 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19_2 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19_3 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19_4 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19_5 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19_6 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_19_7 = HAMASKReg_maskdata[19]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20_1 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20_2 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20_3 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20_4 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20_5 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20_6 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_20_7 = HAMASKReg_maskdata[20]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21_1 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21_2 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21_3 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21_4 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21_5 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21_6 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_21_7 = HAMASKReg_maskdata[21]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22_1 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22_2 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22_3 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22_4 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22_5 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22_6 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_22_7 = HAMASKReg_maskdata[22]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23_1 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23_2 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23_3 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23_4 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23_5 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23_6 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_23_7 = HAMASKReg_maskdata[23]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24_1 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24_2 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24_3 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24_4 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24_5 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24_6 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_24_7 = HAMASKReg_maskdata[24]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25_1 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25_2 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25_3 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25_4 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25_5 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25_6 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_25_7 = HAMASKReg_maskdata[25]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26_1 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26_2 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26_3 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26_4 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26_5 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26_6 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_26_7 = HAMASKReg_maskdata[26]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27_1 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27_2 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27_3 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27_4 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27_5 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27_6 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_27_7 = HAMASKReg_maskdata[27]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28_1 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28_2 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28_3 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28_4 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28_5 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28_6 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_28_7 = HAMASKReg_maskdata[28]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29_1 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29_2 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29_3 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29_4 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29_5 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29_6 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_29_7 = HAMASKReg_maskdata[29]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30_1 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30_2 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30_3 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30_4 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30_5 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30_6 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_30_7 = HAMASKReg_maskdata[30]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31_1 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31_2 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31_3 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31_4 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31_5 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31_6 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
wire tempMaskReg_31_7 = HAMASKReg_maskdata[31]; // @[Debug.scala:477:32, :496:48]
assign hamask_0 = HAWINDOWWrEn & _T_30 ? tempWrData_0 : tempMaskReg_0; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
assign hamask_1 = HAWINDOWWrEn & _T_30 ? tempWrData_1_1 : tempMaskReg_1_1; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
assign hamask_2 = HAWINDOWWrEn & _T_30 ? tempWrData_2_2 : tempMaskReg_2_2; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
assign hamask_3 = HAWINDOWWrEn & _T_30 ? tempWrData_3_3 : tempMaskReg_3_3; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
assign hamask_4 = HAWINDOWWrEn & _T_30 ? tempWrData_4_4 : tempMaskReg_4_4; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
assign hamask_5 = HAWINDOWWrEn & _T_30 ? tempWrData_5_5 : tempMaskReg_5_5; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
assign hamask_6 = HAWINDOWWrEn & _T_30 ? tempWrData_6_6 : tempMaskReg_6_6; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
assign hamask_7 = HAWINDOWWrEn & _T_30 ? tempWrData_7_7 : tempMaskReg_7_7; // @[Debug.scala:432:26, :442:34, :479:20, :495:54, :496:48, :497:{32,74}, :498:44, :500:44]
wire hrmaskNxt_0; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_0_0 = hrmask_0; // @[Debug.scala:340:9, :517:25]
wire hrmaskNxt_1; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_1_0 = hrmask_1; // @[Debug.scala:340:9, :517:25]
wire hrmaskNxt_2; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_2_0 = hrmask_2; // @[Debug.scala:340:9, :517:25]
wire hrmaskNxt_3; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_3_0 = hrmask_3; // @[Debug.scala:340:9, :517:25]
wire hrmaskNxt_4; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_4_0 = hrmask_4; // @[Debug.scala:340:9, :517:25]
wire hrmaskNxt_5; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_5_0 = hrmask_5; // @[Debug.scala:340:9, :517:25]
wire hrmaskNxt_6; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_6_0 = hrmask_6; // @[Debug.scala:340:9, :517:25]
wire hrmaskNxt_7; // @[Debug.scala:518:25]
assign io_innerCtrl_bits_hrmask_7_0 = hrmask_7; // @[Debug.scala:340:9, :517:25]
assign hrmask_0 = hrmaskNxt_0; // @[Debug.scala:517:25, :518:25]
assign hrmask_1 = hrmaskNxt_1; // @[Debug.scala:517:25, :518:25]
assign hrmask_2 = hrmaskNxt_2; // @[Debug.scala:517:25, :518:25]
assign hrmask_3 = hrmaskNxt_3; // @[Debug.scala:517:25, :518:25]
assign hrmask_4 = hrmaskNxt_4; // @[Debug.scala:517:25, :518:25]
assign hrmask_5 = hrmaskNxt_5; // @[Debug.scala:517:25, :518:25]
assign hrmask_6 = hrmaskNxt_6; // @[Debug.scala:517:25, :518:25]
assign hrmask_7 = hrmaskNxt_7; // @[Debug.scala:517:25, :518:25]
reg hrmaskReg_0; // @[Debug.scala:519:28]
reg hrmaskReg_1; // @[Debug.scala:519:28]
reg hrmaskReg_2; // @[Debug.scala:519:28]
reg hrmaskReg_3; // @[Debug.scala:519:28]
reg hrmaskReg_4; // @[Debug.scala:519:28]
reg hrmaskReg_5; // @[Debug.scala:519:28]
reg hrmaskReg_6; // @[Debug.scala:519:28]
reg hrmaskReg_7; // @[Debug.scala:519:28]
wire _T_41 = io_innerCtrl_bits_hartsel_0 == 10'h0; // @[Debug.scala:340:9, :446:35]
wire _T_42 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_0_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_0 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_41 | _T_42)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_41 | _T_42) | hrmaskReg_0); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _T_54 = io_innerCtrl_bits_hartsel_0 == 10'h1; // @[Debug.scala:340:9, :446:35]
wire _T_55 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_1_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_1 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_54 | _T_55)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_54 | _T_55) | hrmaskReg_1); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _T_67 = io_innerCtrl_bits_hartsel_0 == 10'h2; // @[Debug.scala:340:9, :446:35]
wire _T_68 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_2_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_2 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_67 | _T_68)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_67 | _T_68) | hrmaskReg_2); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _T_80 = io_innerCtrl_bits_hartsel_0 == 10'h3; // @[Debug.scala:340:9, :446:35]
wire _T_81 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_3_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_3 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_80 | _T_81)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_80 | _T_81) | hrmaskReg_3); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _T_93 = io_innerCtrl_bits_hartsel_0 == 10'h4; // @[Debug.scala:340:9, :446:35]
wire _T_94 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_4_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_4 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_93 | _T_94)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_93 | _T_94) | hrmaskReg_4); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _T_106 = io_innerCtrl_bits_hartsel_0 == 10'h5; // @[Debug.scala:340:9, :446:35]
wire _T_107 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_5_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_5 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_106 | _T_107)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_106 | _T_107) | hrmaskReg_5); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _T_119 = io_innerCtrl_bits_hartsel_0 == 10'h6; // @[Debug.scala:340:9, :446:35]
wire _T_120 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_6_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_6 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_119 | _T_120)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_119 | _T_120) | hrmaskReg_6); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _T_132 = io_innerCtrl_bits_hartsel_0 == 10'h7; // @[Debug.scala:340:9, :446:35]
wire _T_133 = io_innerCtrl_bits_hasel_0 & io_innerCtrl_bits_hamask_7_0; // @[Debug.scala:340:9, :447:56]
assign hrmaskNxt_7 = ~(~DMCONTROLReg_dmactive | clrresethaltreqWrEn & DMCONTROLWrData_clrresethaltreq & (_T_132 | _T_133)) & (setresethaltreqWrEn & DMCONTROLWrData_setresethaltreq & (_T_132 | _T_133) | hrmaskReg_7); // @[Debug.scala:379:31, :382:35, :386:39, :387:39, :398:11, :446:{35,47}, :447:56, :518:25, :519:28, :521:15, :523:44, :524:30, :525:{39,74,102}, :526:30, :527:{39,74,102}, :528:30]
wire _out_T_15 = DMCONTROLReg_dmactive & io_ctrl_dmactiveAck_0; // @[RegisterRouter.scala:87:24]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [2:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [31:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = dmiNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [4:0] _in_bits_index_T = dmiNodeIn_a_bits_address[6:2]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[2:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _dmiNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign dmiNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [2:0] _GEN = out_front_bits_index & 3'h1; // @[RegisterRouter.scala:87:24]
wire [2:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN; // @[RegisterRouter.scala:87:24]
wire [2:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 3'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 3'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_T_2 = out_findex == 3'h1; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = out_bindex == 3'h1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire out_f_rivalid = out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_16 = out_rivalid_16; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_17 = out_rivalid_17; // @[RegisterRouter.scala:87:24]
wire out_rivalid_18; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_18 = out_rivalid_18; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_16 = out_wivalid_16; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_17 = out_wivalid_17; // @[RegisterRouter.scala:87:24]
wire out_wivalid_18; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_18 = out_wivalid_18; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8 = out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9 = out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10 = out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11 = out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12 = out_roready_12; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13 = out_roready_13; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14 = out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15 = out_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_16 = out_roready_16; // @[RegisterRouter.scala:87:24]
wire out_f_roready_17 = out_roready_17; // @[RegisterRouter.scala:87:24]
wire out_roready_18; // @[RegisterRouter.scala:87:24]
wire out_f_roready_18 = out_roready_18; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_f_woready = out_woready_0; // @[RegisterRouter.scala:87:24]
assign out_f_woready_1 = out_woready_1; // @[RegisterRouter.scala:87:24]
assign out_f_woready_2 = out_woready_2; // @[RegisterRouter.scala:87:24]
assign out_f_woready_3 = out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4; // @[RegisterRouter.scala:87:24]
assign out_f_woready_5 = out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6 = out_woready_6; // @[RegisterRouter.scala:87:24]
assign out_f_woready_7 = out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8 = out_woready_8; // @[RegisterRouter.scala:87:24]
assign out_f_woready_9 = out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10 = out_woready_10; // @[RegisterRouter.scala:87:24]
assign out_f_woready_11 = out_woready_11; // @[RegisterRouter.scala:87:24]
assign out_f_woready_12 = out_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_f_woready_13 = out_woready_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14 = out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15 = out_woready_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_16 = out_woready_16; // @[RegisterRouter.scala:87:24]
wire out_f_woready_17 = out_woready_17; // @[RegisterRouter.scala:87:24]
wire out_woready_18; // @[RegisterRouter.scala:87:24]
wire out_f_woready_18 = out_woready_18; // @[RegisterRouter.scala:87:24]
wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
assign dmactiveWrEn = out_f_woready; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_dmactive = _out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24]
assign ndmresetWrEn = out_f_woready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = out_f_woready_1; // @[RegisterRouter.scala:87:24]
assign _out_T_17 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_ndmreset = _out_T_17; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend = {DMCONTROLReg_ndmreset, _out_prepend_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_26 = out_prepend; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_27 = _out_T_26; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_prepend_T_1 = _out_T_27; // @[RegisterRouter.scala:87:24]
wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24]
assign clrresethaltreqWrEn = out_f_woready_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24]
assign _out_T_28 = out_front_bits_data[2]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_clrresethaltreq = _out_T_28; // @[RegisterRouter.scala:87:24]
wire [2:0] out_prepend_1 = {1'h0, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_35 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_prepend_T_2 = _out_T_36; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24]
assign setresethaltreqWrEn = out_f_woready_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = out_f_woready_3; // @[RegisterRouter.scala:87:24]
assign _out_T_37 = out_front_bits_data[3]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_setresethaltreq = _out_T_37; // @[RegisterRouter.scala:87:24]
wire [3:0] out_prepend_2 = {1'h0, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_44 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_45 = _out_T_44; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_prepend_T_3 = _out_T_45; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_46 = out_front_bits_data[15:4]; // @[RegisterRouter.scala:87:24]
wire [4:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_53 = {11'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_54 = _out_T_53; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_4 = _out_T_54; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
wire _out_T_57 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_58 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24]
assign hartselloWrEn = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_55 = out_front_bits_data[18:16]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_hartsello = {7'h0, _out_T_55}; // @[RegisterRouter.scala:87:24]
wire [25:0] out_prepend_4 = {DMCONTROLReg_hartsello, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [25:0] _out_T_64 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_T_65 = _out_T_64[18:0]; // @[RegisterRouter.scala:87:24]
wire [18:0] _out_prepend_T_5 = _out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_T_67 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
wire _out_T_68 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire [6:0] _out_T_66 = out_front_bits_data[25:19]; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_5 = {1'h0, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [25:0] _out_T_73 = {6'h0, out_prepend_5}; // @[RegisterRouter.scala:87:24]
wire [25:0] _out_T_74 = _out_T_73; // @[RegisterRouter.scala:87:24]
wire [25:0] _out_prepend_T_6 = _out_T_74; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
assign haselWrEn = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_79 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
assign _out_T_75 = out_front_bits_data[26]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_hasel = _out_T_75; // @[RegisterRouter.scala:87:24]
wire [26:0] out_prepend_6 = {DMCONTROLReg_hasel, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [26:0] _out_T_84 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [26:0] _out_T_85 = _out_T_84; // @[RegisterRouter.scala:87:24]
wire [26:0] _out_prepend_T_7 = _out_T_85; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = out_front_bits_data[27]; // @[RegisterRouter.scala:87:24]
wire [27:0] out_prepend_7 = {1'h0, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [27:0] _out_T_93 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [27:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24]
wire [27:0] _out_prepend_T_8 = _out_T_94; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
assign ackhaveresetWrEn = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
assign _out_T_95 = out_front_bits_data[28]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_ackhavereset = _out_T_95; // @[RegisterRouter.scala:87:24]
wire [28:0] out_prepend_8 = {1'h0, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_102 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_T_103 = _out_T_102; // @[RegisterRouter.scala:87:24]
wire [28:0] _out_prepend_T_9 = _out_T_103; // @[RegisterRouter.scala:87:24]
wire _out_T_105 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
wire _out_T_106 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire _out_T_104 = out_front_bits_data[29]; // @[RegisterRouter.scala:87:24]
wire [29:0] out_prepend_9 = {1'h0, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [29:0] _out_T_111 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [29:0] _out_T_112 = _out_T_111; // @[RegisterRouter.scala:87:24]
wire [29:0] _out_prepend_T_10 = _out_T_112; // @[RegisterRouter.scala:87:24]
wire _out_T_114 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
assign resumereqWrEn = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_115 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
assign _out_T_113 = out_front_bits_data[30]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_resumereq = _out_T_113; // @[RegisterRouter.scala:87:24]
wire [30:0] out_prepend_10 = {1'h0, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_120 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_121 = _out_T_120; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_prepend_T_11 = _out_T_121; // @[RegisterRouter.scala:87:24]
wire _out_T_123 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
wire _out_T_124 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_125 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
assign haltreqWrEn = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_126 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
assign _out_T_122 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24]
assign DMCONTROLWrData_haltreq = _out_T_122; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_11 = {DMCONTROLReg_haltreq, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_131 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_132 = _out_T_131; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_out_bits_data_WIRE_1_0 = _out_T_132; // @[MuxLiteral.scala:49:48]
wire _out_T_134 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
wire _out_T_135 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire _out_T_136 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24]
assign HAWINDOWWrEn = out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire _out_T_137 = out_f_woready_13; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_133 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
assign HAWINDOWWrData_maskdata = {24'h0, _out_T_133}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_143 = _out_T_142[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_145 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
wire _out_T_146 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire [11:0] _out_T_144 = out_front_bits_data[11:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_T_155 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_153 = out_front_bits_data[15:12]; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = out_f_roready_16; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = out_front_bits_data[16]; // @[RegisterRouter.scala:87:24]
wire _out_T_172 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24]
wire _out_T_173 = out_f_roready_17; // @[RegisterRouter.scala:87:24]
wire [2:0] _out_T_171 = out_front_bits_data[19:17]; // @[RegisterRouter.scala:87:24]
wire _out_T_181 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24]
wire _out_T_182 = out_f_roready_18; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_180 = out_front_bits_data[23:20]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_2, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_2, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_18 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_18 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_18 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_18 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [31:0] _out_out_bits_data_WIRE_1_2 = {24'h0, _out_T_143}; // @[MuxLiteral.scala:49:48]
wire [3:0][31:0] _GEN_5 = {{32'h0}, {_out_out_bits_data_WIRE_1_2}, {32'h118380}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [31:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 32'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign dmiNodeIn_d_bits_opcode = {2'h0, _dmiNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
wire debugIntNxt_0; // @[Debug.scala:599:31]
wire debugIntNxt_1; // @[Debug.scala:599:31]
wire debugIntNxt_2; // @[Debug.scala:599:31]
wire debugIntNxt_3; // @[Debug.scala:599:31]
wire debugIntNxt_4; // @[Debug.scala:599:31]
wire debugIntNxt_5; // @[Debug.scala:599:31]
wire debugIntNxt_6; // @[Debug.scala:599:31]
wire debugIntNxt_7; // @[Debug.scala:599:31]
reg debugIntRegs_0; // @[Debug.scala:600:31]
reg debugIntRegs_1; // @[Debug.scala:600:31]
reg debugIntRegs_2; // @[Debug.scala:600:31]
reg debugIntRegs_3; // @[Debug.scala:600:31]
reg debugIntRegs_4; // @[Debug.scala:600:31]
reg debugIntRegs_5; // @[Debug.scala:600:31]
reg debugIntRegs_6; // @[Debug.scala:600:31]
reg debugIntRegs_7; // @[Debug.scala:600:31]
assign _intnodeOut_0_T = debugIntRegs_0 | io_hgDebugInt_0_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign intnodeOut_0 = _intnodeOut_0_T; // @[Debug.scala:605:60]
assign _intnodeOut_0_T_1 = debugIntRegs_1 | io_hgDebugInt_1_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[Debug.scala:605:60]
assign _intnodeOut_0_T_2 = debugIntRegs_2 | io_hgDebugInt_2_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign x1_intnodeOut_1_0 = _intnodeOut_0_T_2; // @[Debug.scala:605:60]
assign _intnodeOut_0_T_3 = debugIntRegs_3 | io_hgDebugInt_3_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign x1_intnodeOut_2_0 = _intnodeOut_0_T_3; // @[Debug.scala:605:60]
assign _intnodeOut_0_T_4 = debugIntRegs_4 | io_hgDebugInt_4_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign x1_intnodeOut_3_0 = _intnodeOut_0_T_4; // @[Debug.scala:605:60]
assign _intnodeOut_0_T_5 = debugIntRegs_5 | io_hgDebugInt_5_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign x1_intnodeOut_4_0 = _intnodeOut_0_T_5; // @[Debug.scala:605:60]
assign _intnodeOut_0_T_6 = debugIntRegs_6 | io_hgDebugInt_6_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign x1_intnodeOut_5_0 = _intnodeOut_0_T_6; // @[Debug.scala:605:60]
assign _intnodeOut_0_T_7 = debugIntRegs_7 | io_hgDebugInt_7_0; // @[Debug.scala:340:9, :600:31, :605:60]
assign x1_intnodeOut_6_0 = _intnodeOut_0_T_7; // @[Debug.scala:605:60]
assign debugIntNxt_0 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h0 | DMCONTROLWrData_hasel & hamask_0) ? DMCONTROLWrData_haltreq : debugIntRegs_0); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
assign debugIntNxt_1 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h1 | DMCONTROLWrData_hasel & hamask_1) ? DMCONTROLWrData_haltreq : debugIntRegs_1); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
assign debugIntNxt_2 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h2 | DMCONTROLWrData_hasel & hamask_2) ? DMCONTROLWrData_haltreq : debugIntRegs_2); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
assign debugIntNxt_3 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h3 | DMCONTROLWrData_hasel & hamask_3) ? DMCONTROLWrData_haltreq : debugIntRegs_3); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
assign debugIntNxt_4 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h4 | DMCONTROLWrData_hasel & hamask_4) ? DMCONTROLWrData_haltreq : debugIntRegs_4); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
assign debugIntNxt_5 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h5 | DMCONTROLWrData_hasel & hamask_5) ? DMCONTROLWrData_haltreq : debugIntRegs_5); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
assign debugIntNxt_6 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h6 | DMCONTROLWrData_hasel & hamask_6) ? DMCONTROLWrData_haltreq : debugIntRegs_6); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
assign debugIntNxt_7 = DMCONTROLReg_dmactive & (haltreqWrEn & (DMCONTROLWrData_hartsello == 10'h7 | DMCONTROLWrData_hasel & hamask_7) ? DMCONTROLWrData_haltreq : debugIntRegs_7); // @[Debug.scala:379:31, :382:35, :393:39, :432:26, :599:31, :600:31, :602:17, :610:44, :611:32, :613:{27,58}, :614:{11,59,96}, :615:34]
wire _innerCtrlValid_T_6; // @[Debug.scala:634:128]
wire innerCtrlValid; // @[Debug.scala:629:30]
reg innerCtrlValidReg; // @[Debug.scala:630:36]
reg innerCtrlResumeReqReg; // @[Debug.scala:631:40]
reg innerCtrlAckHaveResetReg; // @[Debug.scala:632:43]
wire _innerCtrlValid_T = hartselloWrEn | resumereqWrEn; // @[Debug.scala:388:39, :392:39, :634:37]
wire _innerCtrlValid_T_1 = _innerCtrlValid_T | ackhaveresetWrEn; // @[Debug.scala:390:39, :634:{37,53}]
wire _innerCtrlValid_T_2 = _innerCtrlValid_T_1 | setresethaltreqWrEn; // @[Debug.scala:387:39, :634:{53,72}]
wire _innerCtrlValid_T_3 = _innerCtrlValid_T_2 | clrresethaltreqWrEn; // @[Debug.scala:386:39, :634:{72,94}]
wire _innerCtrlValid_T_4 = _innerCtrlValid_T_3 | haselWrEn; // @[Debug.scala:389:39, :634:{94,116}]
assign _innerCtrlValid_T_6 = _innerCtrlValid_T_4 | _innerCtrlValid_T_5; // @[Debug.scala:634:{116,128}, :635:22]
assign innerCtrlValid = _innerCtrlValid_T_6; // @[Debug.scala:629:30, :634:128]
wire _innerCtrlValidReg_T = ~io_innerCtrl_ready_0; // @[Debug.scala:340:9, :637:54]
wire _innerCtrlValidReg_T_1 = io_innerCtrl_valid_0 & _innerCtrlValidReg_T; // @[Debug.scala:340:9, :637:{52,54}]
wire _innerCtrlResumeReqReg_T = ~io_innerCtrl_ready_0; // @[Debug.scala:340:9, :637:54, :638:63]
wire _innerCtrlResumeReqReg_T_1 = io_innerCtrl_bits_resumereq_0 & _innerCtrlResumeReqReg_T; // @[Debug.scala:340:9, :638:{61,63}]
wire _innerCtrlAckHaveResetReg_T = ~io_innerCtrl_ready_0; // @[Debug.scala:340:9, :637:54, :639:66]
wire _innerCtrlAckHaveResetReg_T_1 = io_innerCtrl_bits_ackhavereset_0 & _innerCtrlAckHaveResetReg_T; // @[Debug.scala:340:9, :639:{64,66}]
assign _io_innerCtrl_valid_T = innerCtrlValid | innerCtrlValidReg; // @[Debug.scala:629:30, :630:36, :641:54]
assign io_innerCtrl_valid_0 = _io_innerCtrl_valid_T; // @[Debug.scala:340:9, :641:54]
assign _io_innerCtrl_bits_hartsel_T = hartselloWrEn ? DMCONTROLWrData_hartsello : DMCONTROLReg_hartsello; // @[Debug.scala:379:31, :382:35, :388:39, :642:42]
assign io_innerCtrl_bits_hartsel_0 = _io_innerCtrl_bits_hartsel_T; // @[Debug.scala:340:9, :642:42]
wire _io_innerCtrl_bits_resumereq_T = resumereqWrEn & DMCONTROLWrData_resumereq; // @[Debug.scala:382:35, :392:39, :643:54]
assign _io_innerCtrl_bits_resumereq_T_1 = _io_innerCtrl_bits_resumereq_T | innerCtrlResumeReqReg; // @[Debug.scala:631:40, :643:{54,83}]
assign io_innerCtrl_bits_resumereq_0 = _io_innerCtrl_bits_resumereq_T_1; // @[Debug.scala:340:9, :643:83]
wire _io_innerCtrl_bits_ackhavereset_T = ackhaveresetWrEn & DMCONTROLWrData_ackhavereset; // @[Debug.scala:382:35, :390:39, :644:57]
assign _io_innerCtrl_bits_ackhavereset_T_1 = _io_innerCtrl_bits_ackhavereset_T | innerCtrlAckHaveResetReg; // @[Debug.scala:632:43, :644:{57,89}]
assign io_innerCtrl_bits_ackhavereset_0 = _io_innerCtrl_bits_ackhavereset_T_1; // @[Debug.scala:340:9, :644:89]
assign io_innerCtrl_bits_hasel_0 = _io_innerCtrl_bits_hasel_T; // @[Debug.scala:340:9, :647:42]
always @(posedge clock or posedge reset) begin // @[Debug.scala:340:9]
if (reset) begin // @[Debug.scala:340:9]
DMCONTROLReg_haltreq <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_resumereq <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_hartreset <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_ackhavereset <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_reserved0 <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_hasel <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_hartsello <= 10'h0; // @[Debug.scala:379:31]
DMCONTROLReg_hartselhi <= 10'h0; // @[Debug.scala:379:31]
DMCONTROLReg_reserved1 <= 2'h0; // @[Debug.scala:379:31]
DMCONTROLReg_setresethaltreq <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_clrresethaltreq <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_ndmreset <= 1'h0; // @[Debug.scala:379:31]
DMCONTROLReg_dmactive <= 1'h0; // @[Debug.scala:379:31]
HAWINDOWSELReg_reserved0 <= 17'h0; // @[Debug.scala:451:33]
HAWINDOWSELReg_hawindowsel <= 15'h0; // @[Debug.scala:451:33]
HAMASKReg_maskdata <= 32'h0; // @[Debug.scala:477:32]
hrmaskReg_0 <= 1'h0; // @[Debug.scala:519:28]
hrmaskReg_1 <= 1'h0; // @[Debug.scala:519:28]
hrmaskReg_2 <= 1'h0; // @[Debug.scala:519:28]
hrmaskReg_3 <= 1'h0; // @[Debug.scala:519:28]
hrmaskReg_4 <= 1'h0; // @[Debug.scala:519:28]
hrmaskReg_5 <= 1'h0; // @[Debug.scala:519:28]
hrmaskReg_6 <= 1'h0; // @[Debug.scala:519:28]
hrmaskReg_7 <= 1'h0; // @[Debug.scala:519:28]
debugIntRegs_0 <= 1'h0; // @[Debug.scala:600:31]
debugIntRegs_1 <= 1'h0; // @[Debug.scala:600:31]
debugIntRegs_2 <= 1'h0; // @[Debug.scala:600:31]
debugIntRegs_3 <= 1'h0; // @[Debug.scala:600:31]
debugIntRegs_4 <= 1'h0; // @[Debug.scala:600:31]
debugIntRegs_5 <= 1'h0; // @[Debug.scala:600:31]
debugIntRegs_6 <= 1'h0; // @[Debug.scala:600:31]
debugIntRegs_7 <= 1'h0; // @[Debug.scala:600:31]
innerCtrlValidReg <= 1'h0; // @[Debug.scala:630:36]
innerCtrlResumeReqReg <= 1'h0; // @[Debug.scala:631:40]
innerCtrlAckHaveResetReg <= 1'h0; // @[Debug.scala:632:43]
end
else begin // @[Debug.scala:340:9]
DMCONTROLReg_haltreq <= DMCONTROLNxt_haltreq; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_resumereq <= DMCONTROLNxt_resumereq; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_hartreset <= DMCONTROLNxt_hartreset; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_ackhavereset <= DMCONTROLNxt_ackhavereset; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_reserved0 <= DMCONTROLNxt_reserved0; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_hasel <= DMCONTROLNxt_hasel; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_hartsello <= DMCONTROLNxt_hartsello; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_hartselhi <= DMCONTROLNxt_hartselhi; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_reserved1 <= DMCONTROLNxt_reserved1; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_setresethaltreq <= DMCONTROLNxt_setresethaltreq; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_clrresethaltreq <= DMCONTROLNxt_clrresethaltreq; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_ndmreset <= DMCONTROLNxt_ndmreset; // @[Debug.scala:378:32, :379:31]
DMCONTROLReg_dmactive <= DMCONTROLNxt_dmactive; // @[Debug.scala:378:32, :379:31]
HAWINDOWSELReg_reserved0 <= HAWINDOWSELNxt_reserved0; // @[Debug.scala:450:34, :451:33]
HAWINDOWSELReg_hawindowsel <= HAWINDOWSELNxt_hawindowsel; // @[Debug.scala:450:34, :451:33]
HAMASKReg_maskdata <= HAMASKNxt_maskdata; // @[Debug.scala:476:33, :477:32]
hrmaskReg_0 <= hrmaskNxt_0; // @[Debug.scala:518:25, :519:28]
hrmaskReg_1 <= hrmaskNxt_1; // @[Debug.scala:518:25, :519:28]
hrmaskReg_2 <= hrmaskNxt_2; // @[Debug.scala:518:25, :519:28]
hrmaskReg_3 <= hrmaskNxt_3; // @[Debug.scala:518:25, :519:28]
hrmaskReg_4 <= hrmaskNxt_4; // @[Debug.scala:518:25, :519:28]
hrmaskReg_5 <= hrmaskNxt_5; // @[Debug.scala:518:25, :519:28]
hrmaskReg_6 <= hrmaskNxt_6; // @[Debug.scala:518:25, :519:28]
hrmaskReg_7 <= hrmaskNxt_7; // @[Debug.scala:518:25, :519:28]
debugIntRegs_0 <= debugIntNxt_0; // @[Debug.scala:599:31, :600:31]
debugIntRegs_1 <= debugIntNxt_1; // @[Debug.scala:599:31, :600:31]
debugIntRegs_2 <= debugIntNxt_2; // @[Debug.scala:599:31, :600:31]
debugIntRegs_3 <= debugIntNxt_3; // @[Debug.scala:599:31, :600:31]
debugIntRegs_4 <= debugIntNxt_4; // @[Debug.scala:599:31, :600:31]
debugIntRegs_5 <= debugIntNxt_5; // @[Debug.scala:599:31, :600:31]
debugIntRegs_6 <= debugIntNxt_6; // @[Debug.scala:599:31, :600:31]
debugIntRegs_7 <= debugIntNxt_7; // @[Debug.scala:599:31, :600:31]
innerCtrlValidReg <= _innerCtrlValidReg_T_1; // @[Debug.scala:630:36, :637:52]
innerCtrlResumeReqReg <= _innerCtrlResumeReqReg_T_1; // @[Debug.scala:631:40, :638:61]
innerCtrlAckHaveResetReg <= _innerCtrlAckHaveResetReg_T_1; // @[Debug.scala:632:43, :639:64]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File TileResetSetter.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
// Currently only works if all tiles are already driven by independent clock groups
// TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should
// always put all tiles on independent clock groups
class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters)
extends LazyModule {
val device = new SimpleDevice("tile-reset-setter", Nil)
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
val clockNode = ClockGroupIdentityNode()
lazy val module = new LazyModuleImp(this) {
val nTiles = p(TilesLocated(InSubsystem)).size
require (nTiles <= 4096 / 4)
val tile_async_resets = Wire(Vec(nTiles, Reset()))
val r_tile_resets = (0 until nTiles).map({ i =>
tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842
withReset (tile_async_resets(i)) {
Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0)))
}
})
if (nTiles > 0)
tlNode.regmap((0 until nTiles).map({ i =>
i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
}): _*)
val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>
n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4)
})
(clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) =>
(o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) =>
oD.clock := iD.clock
oD.reset := iD.reset
for ((n, (rIn, rOut, addr)) <- tileMap) {
if (name.contains(n)) {
println(s"${addr.toString(16)}: Tile $name reset control")
// Async because the reset coming out of the AsyncResetRegVec is
// clocked to the bus this is attached to, not the clock in this
// clock bundle. We expect a ClockGroupResetSynchronizer downstream
// to synchronize the resets
// Also, this or enforces that the tiles come out of reset after the reset of the system
oD.reset := (rOut.asBool || iD.reset.asBool).asAsyncReset
rIn := iD.reset
}
}
}
}
}
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TileResetSetter( // @[TileResetSetter.scala:26:25]
input clock, // @[TileResetSetter.scala:26:25]
input reset, // @[TileResetSetter.scala:26:25]
input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25]
wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25]
wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25]
wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25]
wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24]
wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33]
wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38]
wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25]
wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25]
wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10]
wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24]
wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25]
wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}]
assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
TLMonitor_61 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15]
.clock (clock),
.io_d (_out_T_2), // @[RegisterRouter.scala:87:24]
.io_en (out_f_woready) // @[RegisterRouter.scala:87:24]
); // @[TileResetSetter.scala:33:15]
assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module rockettile_icache_data_arrays_1_3( // @[DescribedSRAM.scala:17:26]
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [255:0] RW0_wdata,
output [255:0] RW0_rdata,
input [7:0] RW0_wmask
);
rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_83( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [4:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [4:0] mask; // @[InputUnit.scala:250:21]
wire [4:0] _vcalloc_filter_T_3 = {3'h0, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {3'h0, vcalloc_vals_1, 6'h0}; // @[OneHot.scala:85:71]
wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_1; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to the following Chisel files.
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
| module Repeater_TLBundleA_a26d64s9k1z3u_1( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [8:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [25:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [8:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [25:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [8:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [25:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [8:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [25:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [8:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [25:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [8:0] saved_source; // @[Repeater.scala:21:18]
reg [25:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File TSIHarness.scala:
package testchipip.tsi
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.amba.axi4._
import testchipip.serdes._
import java.nio.ByteBuffer
import java.nio.file.{Files, Paths}
object TSIHarness {
def connectRAM(params: SerialTLParams, serdesser: TLSerdesser, port: DecoupledPhitIO, reset: Reset): SerialRAM = {
implicit val p: Parameters = serdesser.p
val ram = LazyModule(new SerialRAM(serdesser, params))
val module = Module(ram.module)
module.io.ser <> port
ram
}
def tieoff(serial: Option[DecoupledPhitIO]) {
serial.foreach { s =>
s.in.valid := false.B
s.in.bits := DontCare
s.out.ready := true.B
}
}
def tieoff(serial: DecoupledPhitIO) { tieoff(Some(serial)) }
}
object SerialTLROM {
def apply(romParams: ManagerROMParams, beatBytes: Int)(implicit p: Parameters): TLROM = {
lazy val romContents = {
val romData = romParams.contentFileName.map(n => Files.readAllBytes(Paths.get(n))).getOrElse(
Array(
0x1b, 0x05, 0x10, 0x00, // 0010051b addiw a0,zero,1
0x13, 0x15, 0xf5, 0x01, // 01f51513 slli a0,a0,0x1f (li a0, 0x8000_0000)
0x73, 0x10, 0x15, 0x34, // 34151073 csrw mepc,a0
0x37, 0x25, 0x00, 0x00, // 00002537 lui a0,0x2
0x1b, 0x05, 0x05, 0x80, // 8005051b addiw a0,a0,-2048
0x73, 0x20, 0x05, 0x30, // 30052073 csrs mstatus,a0
0x73, 0x25, 0x40, 0xf1, // f1402573 csrr a0,mhartid
0x73, 0x00, 0x20, 0x30 // 30200073 mret
).map(_.toByte)
)
val rom = ByteBuffer.wrap(romData)
rom.array()
}
val rom = LazyModule(new TLROM(romParams.address, romParams.size, romContents, true, beatBytes))
rom
}
}
class SerialRAM(tl_serdesser: TLSerdesser, params: SerialTLParams)(implicit p: Parameters) extends LazyModule {
val managerParams = tl_serdesser.module.client_edge.map(_.slave) // the managerParams are the chip-side clientParams
val clientParams = tl_serdesser.module.manager_edge.map(_.master) // The clientParams are the chip-side managerParams
val serdesser = LazyModule(new TLSerdesser(
tl_serdesser.flitWidth,
clientParams,
managerParams,
tl_serdesser.bundleParams,
nameSuffix = Some("SerialRAM")
))
// If if this serdesser expects a manager, connect tsi2tl
val tsi2tl = serdesser.managerNode.map { managerNode =>
val tsi2tl = LazyModule(new TSIToTileLink)
serdesser.managerNode.get := TLBuffer() := tsi2tl.node
tsi2tl
}
serdesser.clientNode.foreach { clientNode =>
val beatBytes = 8
val memParams = params.manager.get.memParams
val romParams = params.manager.get.romParams
val cohParams = params.manager.get.cohParams
val xbar = TLXbar()
val srams = memParams.map { memParams =>
AddressSet.misaligned(memParams.address, memParams.size).map { aset =>
LazyModule(new TLRAM(aset, beatBytes = beatBytes) { override lazy val desiredName = "SerialRAM_RAM" })
}
}.flatten
srams.foreach { s => (s.node
:= TLBuffer()
:= TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("SerialRAM_RAM"))
:= xbar)
}
val rom = romParams.map { romParams => SerialTLROM(romParams, beatBytes) }
rom.foreach { r => (r.node
:= TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("SerialRAM_ROM"))
:= xbar)
}
val cohrams = cohParams.map { cohParams =>
AddressSet.misaligned(cohParams.address, cohParams.size).map { aset =>
LazyModule(new TLRAM(aset, beatBytes = beatBytes) { override lazy val desiredName = "SerialRAM_COH" })
}
}.flatten
cohrams.foreach { s => (s.node
:= TLBuffer()
:= TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("SerialRAM_COH"))
:= TLBroadcast(p(CacheBlockBytes))
:= xbar)
}
xbar := clientNode
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val ser = new DecoupledPhitIO(params.phyParams.phitWidth)
val tsi = tsi2tl.map(_ => new TSIIO)
val tsi2tl_state = Output(UInt())
})
val phy = Module(new DecoupledSerialPhy(5, params.phyParams))
phy.io.outer_clock := clock
phy.io.outer_reset := reset
phy.io.inner_clock := clock
phy.io.inner_reset := reset
phy.io.outer_ser <> io.ser
for (i <- 0 until 5) {
serdesser.module.io.ser(i) <> phy.io.inner_ser(i)
}
io.tsi.foreach(_ <> tsi2tl.get.module.io.tsi)
io.tsi2tl_state := tsi2tl.map(_.module.io.state).getOrElse(0.U(1.W))
require(serdesser.module.mergedParams == tl_serdesser.module.mergedParams,
"Mismatch between chip-side diplomatic params and harness-side diplomatic params:\n" +
s"Harness-side params: ${serdesser.module.mergedParams}\n" +
s"Chip-side params: ${tl_serdesser.module.mergedParams}")
}
}
| module SerialRAM( // @[TSIHarness.scala:122:9]
input clock, // @[TSIHarness.scala:122:9]
input reset, // @[TSIHarness.scala:122:9]
output io_ser_in_ready, // @[TSIHarness.scala:123:16]
input io_ser_in_valid, // @[TSIHarness.scala:123:16]
input [31:0] io_ser_in_bits_phit, // @[TSIHarness.scala:123:16]
input io_ser_out_ready, // @[TSIHarness.scala:123:16]
output io_ser_out_valid, // @[TSIHarness.scala:123:16]
output [31:0] io_ser_out_bits_phit, // @[TSIHarness.scala:123:16]
output io_tsi_in_ready, // @[TSIHarness.scala:123:16]
input io_tsi_in_valid, // @[TSIHarness.scala:123:16]
input [31:0] io_tsi_in_bits, // @[TSIHarness.scala:123:16]
input io_tsi_out_ready, // @[TSIHarness.scala:123:16]
output io_tsi_out_valid, // @[TSIHarness.scala:123:16]
output [31:0] io_tsi_out_bits // @[TSIHarness.scala:123:16]
);
wire _phy_io_inner_ser_0_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_0_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_0_out_ready; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_1_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_1_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_2_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_2_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_2_out_ready; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_3_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_3_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_4_in_valid; // @[TSIHarness.scala:129:21]
wire [31:0] _phy_io_inner_ser_4_in_bits_flit; // @[TSIHarness.scala:129:21]
wire _phy_io_inner_ser_4_out_ready; // @[TSIHarness.scala:129:21]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [31:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _tsi2tl_auto_out_a_valid; // @[TSIHarness.scala:76:28]
wire [2:0] _tsi2tl_auto_out_a_bits_opcode; // @[TSIHarness.scala:76:28]
wire [3:0] _tsi2tl_auto_out_a_bits_size; // @[TSIHarness.scala:76:28]
wire [31:0] _tsi2tl_auto_out_a_bits_address; // @[TSIHarness.scala:76:28]
wire [7:0] _tsi2tl_auto_out_a_bits_mask; // @[TSIHarness.scala:76:28]
wire [63:0] _tsi2tl_auto_out_a_bits_data; // @[TSIHarness.scala:76:28]
wire _tsi2tl_auto_out_d_ready; // @[TSIHarness.scala:76:28]
wire _serdesser_auto_manager_in_a_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_valid; // @[TSIHarness.scala:66:29]
wire [2:0] _serdesser_auto_manager_in_d_bits_opcode; // @[TSIHarness.scala:66:29]
wire [1:0] _serdesser_auto_manager_in_d_bits_param; // @[TSIHarness.scala:66:29]
wire [3:0] _serdesser_auto_manager_in_d_bits_size; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_source; // @[TSIHarness.scala:66:29]
wire [2:0] _serdesser_auto_manager_in_d_bits_sink; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_denied; // @[TSIHarness.scala:66:29]
wire [63:0] _serdesser_auto_manager_in_d_bits_data; // @[TSIHarness.scala:66:29]
wire _serdesser_auto_manager_in_d_bits_corrupt; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_0_in_ready; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_0_out_bits_flit; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_1_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_2_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_2_out_valid; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_2_out_bits_flit; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_3_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_4_in_ready; // @[TSIHarness.scala:66:29]
wire _serdesser_io_ser_4_out_valid; // @[TSIHarness.scala:66:29]
wire [31:0] _serdesser_io_ser_4_out_bits_flit; // @[TSIHarness.scala:66:29]
wire io_ser_in_valid_0 = io_ser_in_valid; // @[TSIHarness.scala:122:9]
wire [31:0] io_ser_in_bits_phit_0 = io_ser_in_bits_phit; // @[TSIHarness.scala:122:9]
wire io_ser_out_ready_0 = io_ser_out_ready; // @[TSIHarness.scala:122:9]
wire io_tsi_in_valid_0 = io_tsi_in_valid; // @[TSIHarness.scala:122:9]
wire [31:0] io_tsi_in_bits_0 = io_tsi_in_bits; // @[TSIHarness.scala:122:9]
wire io_tsi_out_ready_0 = io_tsi_out_ready; // @[TSIHarness.scala:122:9]
wire io_ser_in_ready_0; // @[TSIHarness.scala:122:9]
wire [31:0] io_ser_out_bits_phit_0; // @[TSIHarness.scala:122:9]
wire io_ser_out_valid_0; // @[TSIHarness.scala:122:9]
wire io_tsi_in_ready_0; // @[TSIHarness.scala:122:9]
wire io_tsi_out_valid_0; // @[TSIHarness.scala:122:9]
wire [31:0] io_tsi_out_bits_0; // @[TSIHarness.scala:122:9]
wire [3:0] io_tsi2tl_state; // @[TSIHarness.scala:122:9]
TLSerdesser_SerialRAM serdesser ( // @[TSIHarness.scala:66:29]
.clock (clock),
.reset (reset),
.auto_manager_in_a_ready (_serdesser_auto_manager_in_a_ready),
.auto_manager_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_manager_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_manager_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_manager_in_d_valid (_serdesser_auto_manager_in_d_valid),
.auto_manager_in_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode),
.auto_manager_in_d_bits_param (_serdesser_auto_manager_in_d_bits_param),
.auto_manager_in_d_bits_size (_serdesser_auto_manager_in_d_bits_size),
.auto_manager_in_d_bits_source (_serdesser_auto_manager_in_d_bits_source),
.auto_manager_in_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink),
.auto_manager_in_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied),
.auto_manager_in_d_bits_data (_serdesser_auto_manager_in_d_bits_data),
.auto_manager_in_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt),
.io_ser_0_in_ready (_serdesser_io_ser_0_in_ready),
.io_ser_0_in_valid (_phy_io_inner_ser_0_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_0_out_ready (_phy_io_inner_ser_0_out_ready), // @[TSIHarness.scala:129:21]
.io_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit),
.io_ser_1_in_ready (_serdesser_io_ser_1_in_ready),
.io_ser_1_in_valid (_phy_io_inner_ser_1_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_2_in_ready (_serdesser_io_ser_2_in_ready),
.io_ser_2_in_valid (_phy_io_inner_ser_2_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_2_out_ready (_phy_io_inner_ser_2_out_ready), // @[TSIHarness.scala:129:21]
.io_ser_2_out_valid (_serdesser_io_ser_2_out_valid),
.io_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit),
.io_ser_3_in_ready (_serdesser_io_ser_3_in_ready),
.io_ser_3_in_valid (_phy_io_inner_ser_3_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_4_in_ready (_serdesser_io_ser_4_in_ready),
.io_ser_4_in_valid (_phy_io_inner_ser_4_in_valid), // @[TSIHarness.scala:129:21]
.io_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit), // @[TSIHarness.scala:129:21]
.io_ser_4_out_ready (_phy_io_inner_ser_4_out_ready), // @[TSIHarness.scala:129:21]
.io_ser_4_out_valid (_serdesser_io_ser_4_out_valid),
.io_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit)
); // @[TSIHarness.scala:66:29]
TSIToTileLink tsi2tl ( // @[TSIHarness.scala:76:28]
.clock (clock),
.reset (reset),
.auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_a_valid (_tsi2tl_auto_out_a_valid),
.auto_out_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode),
.auto_out_a_bits_size (_tsi2tl_auto_out_a_bits_size),
.auto_out_a_bits_address (_tsi2tl_auto_out_a_bits_address),
.auto_out_a_bits_mask (_tsi2tl_auto_out_a_bits_mask),
.auto_out_a_bits_data (_tsi2tl_auto_out_a_bits_data),
.auto_out_d_ready (_tsi2tl_auto_out_d_ready),
.auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28]
.io_tsi_in_ready (io_tsi_in_ready_0),
.io_tsi_in_valid (io_tsi_in_valid_0), // @[TSIHarness.scala:122:9]
.io_tsi_in_bits (io_tsi_in_bits_0), // @[TSIHarness.scala:122:9]
.io_tsi_out_ready (io_tsi_out_ready_0), // @[TSIHarness.scala:122:9]
.io_tsi_out_valid (io_tsi_out_valid_0),
.io_tsi_out_bits (io_tsi_out_bits_0),
.io_state (io_tsi2tl_state)
); // @[TSIHarness.scala:76:28]
TLBuffer_a32d64s1k3z4u_1 buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_tsi2tl_auto_out_a_valid), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_opcode (_tsi2tl_auto_out_a_bits_opcode), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_size (_tsi2tl_auto_out_a_bits_size), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_address (_tsi2tl_auto_out_a_bits_address), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_mask (_tsi2tl_auto_out_a_bits_mask), // @[TSIHarness.scala:76:28]
.auto_in_a_bits_data (_tsi2tl_auto_out_a_bits_data), // @[TSIHarness.scala:76:28]
.auto_in_d_ready (_tsi2tl_auto_out_d_ready), // @[TSIHarness.scala:76:28]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready (_serdesser_auto_manager_in_a_ready), // @[TSIHarness.scala:66:29]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_serdesser_auto_manager_in_d_valid), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_opcode (_serdesser_auto_manager_in_d_bits_opcode), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_param (_serdesser_auto_manager_in_d_bits_param), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_size (_serdesser_auto_manager_in_d_bits_size), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_source (_serdesser_auto_manager_in_d_bits_source), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_sink (_serdesser_auto_manager_in_d_bits_sink), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_denied (_serdesser_auto_manager_in_d_bits_denied), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_data (_serdesser_auto_manager_in_d_bits_data), // @[TSIHarness.scala:66:29]
.auto_out_d_bits_corrupt (_serdesser_auto_manager_in_d_bits_corrupt) // @[TSIHarness.scala:66:29]
); // @[Buffer.scala:75:28]
DecoupledSerialPhy_1 phy ( // @[TSIHarness.scala:129:21]
.io_outer_clock (clock),
.io_outer_reset (reset),
.io_inner_clock (clock),
.io_inner_reset (reset),
.io_outer_ser_in_ready (io_ser_in_ready_0),
.io_outer_ser_in_valid (io_ser_in_valid_0), // @[TSIHarness.scala:122:9]
.io_outer_ser_in_bits_phit (io_ser_in_bits_phit_0), // @[TSIHarness.scala:122:9]
.io_outer_ser_out_ready (io_ser_out_ready_0), // @[TSIHarness.scala:122:9]
.io_outer_ser_out_valid (io_ser_out_valid_0),
.io_outer_ser_out_bits_phit (io_ser_out_bits_phit_0),
.io_inner_ser_0_in_ready (_serdesser_io_ser_0_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_0_in_valid (_phy_io_inner_ser_0_in_valid),
.io_inner_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit),
.io_inner_ser_0_out_ready (_phy_io_inner_ser_0_out_ready),
.io_inner_ser_0_out_bits_flit (_serdesser_io_ser_0_out_bits_flit), // @[TSIHarness.scala:66:29]
.io_inner_ser_1_in_ready (_serdesser_io_ser_1_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_1_in_valid (_phy_io_inner_ser_1_in_valid),
.io_inner_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit),
.io_inner_ser_2_in_ready (_serdesser_io_ser_2_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_2_in_valid (_phy_io_inner_ser_2_in_valid),
.io_inner_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit),
.io_inner_ser_2_out_ready (_phy_io_inner_ser_2_out_ready),
.io_inner_ser_2_out_valid (_serdesser_io_ser_2_out_valid), // @[TSIHarness.scala:66:29]
.io_inner_ser_2_out_bits_flit (_serdesser_io_ser_2_out_bits_flit), // @[TSIHarness.scala:66:29]
.io_inner_ser_3_in_ready (_serdesser_io_ser_3_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_3_in_valid (_phy_io_inner_ser_3_in_valid),
.io_inner_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit),
.io_inner_ser_4_in_ready (_serdesser_io_ser_4_in_ready), // @[TSIHarness.scala:66:29]
.io_inner_ser_4_in_valid (_phy_io_inner_ser_4_in_valid),
.io_inner_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit),
.io_inner_ser_4_out_ready (_phy_io_inner_ser_4_out_ready),
.io_inner_ser_4_out_valid (_serdesser_io_ser_4_out_valid), // @[TSIHarness.scala:66:29]
.io_inner_ser_4_out_bits_flit (_serdesser_io_ser_4_out_bits_flit) // @[TSIHarness.scala:66:29]
); // @[TSIHarness.scala:129:21]
assign io_ser_in_ready = io_ser_in_ready_0; // @[TSIHarness.scala:122:9]
assign io_ser_out_valid = io_ser_out_valid_0; // @[TSIHarness.scala:122:9]
assign io_ser_out_bits_phit = io_ser_out_bits_phit_0; // @[TSIHarness.scala:122:9]
assign io_tsi_in_ready = io_tsi_in_ready_0; // @[TSIHarness.scala:122:9]
assign io_tsi_out_valid = io_tsi_out_valid_0; // @[TSIHarness.scala:122:9]
assign io_tsi_out_bits = io_tsi_out_bits_0; // @[TSIHarness.scala:122:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_78( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_78 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_78 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_130 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
File Configs.scala:
package saturn.rocket
import chisel3._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile._
import freechips.rocketchip.diplomacy._
import saturn.common._
import saturn.frontend.{EarlyVectorDecode}
class WithRocketVectorUnit(
vLen: Int = 128,
dLen: Int = 64,
params: VectorParams = VectorParams(),
cores: Option[Seq[Int]] = None,
useL1DCache: Boolean = true) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => {
val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true)
if (buildVector) tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(
vector = Some(RocketCoreVectorParams(
build = ((p: Parameters) => new SaturnRocketUnit()(p.alterPartial {
case VectorParamsKey => params.copy(dLen=dLen)
})),
vLen = vLen,
vfLen = 64,
vfh = true,
eLen = 64,
vMemDataBits = if (useL1DCache) dLen else 0,
decoder = ((p: Parameters) => {
val decoder = Module(new EarlyVectorDecode(params.supported_ex_insns)(p))
decoder
}),
useDCache = true,
issueVConfig = false,
vExts = Seq("zvbb")
)),
fpu = (if (params.useScalarFPFMA || params.useScalarFPMisc) { tp.tileParams.core.fpu.map(_.copy(
sfmaLatency = params.fmaPipeDepth - 1,
dfmaLatency = params.fmaPipeDepth - 1,
ifpuLatency = params.fmaPipeDepth - 1,
fpmuLatency = params.fmaPipeDepth - 1,
)) } else { tp.tileParams.core.fpu }).map(_.copy(minFLen = 16))
),
dcache = if (useL1DCache) tp.tileParams.dcache.map(_.copy(rowBits = dLen)) else tp.tileParams.dcache
)) else tp
}
case other => other
}
})
| module FPU( // @[FPU.scala:735:7]
input clock, // @[FPU.scala:735:7]
input reset, // @[FPU.scala:735:7]
input [31:0] io_inst, // @[FPU.scala:736:14]
input [63:0] io_fromint_data, // @[FPU.scala:736:14]
input [2:0] io_fcsr_rm, // @[FPU.scala:736:14]
output io_fcsr_flags_valid, // @[FPU.scala:736:14]
output [4:0] io_fcsr_flags_bits, // @[FPU.scala:736:14]
input [2:0] io_v_sew, // @[FPU.scala:736:14]
output [63:0] io_store_data, // @[FPU.scala:736:14]
output [63:0] io_toint_data, // @[FPU.scala:736:14]
input io_ll_resp_val, // @[FPU.scala:736:14]
input [2:0] io_ll_resp_type, // @[FPU.scala:736:14]
input [4:0] io_ll_resp_tag, // @[FPU.scala:736:14]
input [63:0] io_ll_resp_data, // @[FPU.scala:736:14]
input io_valid, // @[FPU.scala:736:14]
output io_fcsr_rdy, // @[FPU.scala:736:14]
output io_nack_mem, // @[FPU.scala:736:14]
output io_illegal_rm, // @[FPU.scala:736:14]
input io_killx, // @[FPU.scala:736:14]
input io_killm, // @[FPU.scala:736:14]
output io_dec_wen, // @[FPU.scala:736:14]
output io_dec_ren1, // @[FPU.scala:736:14]
output io_dec_ren2, // @[FPU.scala:736:14]
output io_dec_ren3, // @[FPU.scala:736:14]
output io_sboard_set, // @[FPU.scala:736:14]
output io_sboard_clr, // @[FPU.scala:736:14]
output [4:0] io_sboard_clra, // @[FPU.scala:736:14]
output io_cp_req_ready, // @[FPU.scala:736:14]
input io_cp_req_valid, // @[FPU.scala:736:14]
input io_cp_req_bits_ren2, // @[FPU.scala:736:14]
input [1:0] io_cp_req_bits_typeTagIn, // @[FPU.scala:736:14]
input [1:0] io_cp_req_bits_typeTagOut, // @[FPU.scala:736:14]
input io_cp_req_bits_fromint, // @[FPU.scala:736:14]
input io_cp_req_bits_toint, // @[FPU.scala:736:14]
input io_cp_req_bits_fastpipe, // @[FPU.scala:736:14]
input io_cp_req_bits_div, // @[FPU.scala:736:14]
input io_cp_req_bits_sqrt, // @[FPU.scala:736:14]
input io_cp_req_bits_wflags, // @[FPU.scala:736:14]
input [2:0] io_cp_req_bits_rm, // @[FPU.scala:736:14]
input [1:0] io_cp_req_bits_typ, // @[FPU.scala:736:14]
input [64:0] io_cp_req_bits_in1, // @[FPU.scala:736:14]
input [64:0] io_cp_req_bits_in2, // @[FPU.scala:736:14]
output io_cp_resp_valid, // @[FPU.scala:736:14]
output [64:0] io_cp_resp_bits_data // @[FPU.scala:736:14]
);
wire divSqrt_inFlight; // @[FPU.scala:1035:34, :1045:{27,46}]
wire [1:0] divSqrt_typeTag; // @[FPU.scala:1037:66, :1041:25]
wire [4:0] divSqrt_flags; // @[FPU.scala:1037:66, :1040:23]
wire [64:0] divSqrt_wdata; // @[FPU.scala:1037:66, :1039:23]
wire divSqrt_wen; // @[FPU.scala:1037:66, :1038:21]
wire io_cp_req_ready_0; // @[FPU.scala:991:{36,71}]
wire _divSqrt_2_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_2_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_2_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [64:0] _divSqrt_2_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_2_io_exceptionFlags; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_1_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [32:0] _divSqrt_1_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_1_io_exceptionFlags; // @[FPU.scala:1027:55]
wire _divSqrt_io_inReady; // @[FPU.scala:1027:55]
wire _divSqrt_io_outValid_div; // @[FPU.scala:1027:55]
wire _divSqrt_io_outValid_sqrt; // @[FPU.scala:1027:55]
wire [16:0] _divSqrt_io_out; // @[FPU.scala:1027:55]
wire [4:0] _divSqrt_io_exceptionFlags; // @[FPU.scala:1027:55]
wire [64:0] _hfma_io_out_bits_data; // @[FPU.scala:919:28]
wire [4:0] _hfma_io_out_bits_exc; // @[FPU.scala:919:28]
wire [64:0] _dfma_io_out_bits_data; // @[FPU.scala:913:28]
wire [4:0] _dfma_io_out_bits_exc; // @[FPU.scala:913:28]
wire [64:0] _fpmu_io_out_bits_data; // @[FPU.scala:891:20]
wire [4:0] _fpmu_io_out_bits_exc; // @[FPU.scala:891:20]
wire [64:0] _ifpu_io_out_bits_data; // @[FPU.scala:886:20]
wire [4:0] _ifpu_io_out_bits_exc; // @[FPU.scala:886:20]
wire _fpiu_io_out_valid; // @[FPU.scala:876:20]
wire [2:0] _fpiu_io_out_bits_in_rm; // @[FPU.scala:876:20]
wire [64:0] _fpiu_io_out_bits_in_in1; // @[FPU.scala:876:20]
wire [64:0] _fpiu_io_out_bits_in_in2; // @[FPU.scala:876:20]
wire _fpiu_io_out_bits_lt; // @[FPU.scala:876:20]
wire [63:0] _fpiu_io_out_bits_toint; // @[FPU.scala:876:20]
wire [4:0] _fpiu_io_out_bits_exc; // @[FPU.scala:876:20]
wire [64:0] _sfma_io_out_bits_data; // @[FPU.scala:872:20]
wire [4:0] _sfma_io_out_bits_exc; // @[FPU.scala:872:20]
wire [64:0] _regfile_ext_R0_data; // @[FPU.scala:818:20]
wire [64:0] _regfile_ext_R1_data; // @[FPU.scala:818:20]
wire [64:0] _regfile_ext_R2_data; // @[FPU.scala:818:20]
wire _v_decode_io_legal; // @[Configs.scala:33:35]
wire _v_decode_io_read_frs1; // @[Configs.scala:33:35]
wire _v_decode_io_write_frd; // @[Configs.scala:33:35]
wire _fp_decoder_io_sigs_wen; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_ren1; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_ren2; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_ren3; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_swap12; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_swap23; // @[FPU.scala:750:26]
wire [1:0] _fp_decoder_io_sigs_typeTagIn; // @[FPU.scala:750:26]
wire [1:0] _fp_decoder_io_sigs_typeTagOut; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_fromint; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_toint; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_fastpipe; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_fma; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_div; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_sqrt; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_wflags; // @[FPU.scala:750:26]
wire _fp_decoder_io_sigs_vec; // @[FPU.scala:750:26]
wire _GEN = _v_decode_io_legal & _v_decode_io_read_frs1; // @[Configs.scala:33:35]
wire id_ctrl_ren1 = _GEN | _fp_decoder_io_sigs_ren1; // @[FPU.scala:750:26, :752:25, :757:{29,55}, :758:20]
reg ex_reg_valid; // @[FPU.scala:767:29]
reg [31:0] ex_reg_inst; // @[FPU.scala:768:30]
reg ex_reg_ctrl_ren2; // @[FPU.scala:769:30]
reg ex_reg_ctrl_ren3; // @[FPU.scala:769:30]
reg ex_reg_ctrl_swap23; // @[FPU.scala:769:30]
reg [1:0] ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30]
reg [1:0] ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30]
reg ex_reg_ctrl_fromint; // @[FPU.scala:769:30]
reg ex_reg_ctrl_toint; // @[FPU.scala:769:30]
reg ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30]
reg ex_reg_ctrl_fma; // @[FPU.scala:769:30]
reg ex_reg_ctrl_div; // @[FPU.scala:769:30]
reg ex_reg_ctrl_sqrt; // @[FPU.scala:769:30]
reg ex_reg_ctrl_wflags; // @[FPU.scala:769:30]
reg ex_reg_ctrl_vec; // @[FPU.scala:769:30]
reg [4:0] ex_ra_0; // @[FPU.scala:770:31]
reg [4:0] ex_ra_1; // @[FPU.scala:770:31]
reg [4:0] ex_ra_2; // @[FPU.scala:770:31]
reg load_wb; // @[FPU.scala:773:24]
reg [1:0] load_wb_typeTag; // @[FPU.scala:774:34]
reg [63:0] load_wb_data; // @[FPU.scala:775:31]
reg [4:0] load_wb_tag; // @[FPU.scala:776:30]
wire req_valid = ex_reg_valid | io_cp_req_valid; // @[FPU.scala:767:29, :780:32]
wire ex_cp_valid = io_cp_req_ready_0 & io_cp_req_valid; // @[Decoupled.scala:51:35]
reg mem_cp_valid; // @[FPU.scala:782:29]
reg wb_cp_valid; // @[FPU.scala:783:28]
reg mem_reg_valid; // @[FPU.scala:784:30]
reg [31:0] mem_reg_inst; // @[FPU.scala:791:31]
reg wb_reg_valid; // @[FPU.scala:792:29]
wire ex_ctrl_ren3 = ~ex_cp_valid & ex_reg_ctrl_ren3; // @[Decoupled.scala:51:35]
wire [1:0] ex_ctrl_typeTagIn = ex_cp_valid ? io_cp_req_bits_typeTagIn : ex_reg_ctrl_typeTagIn; // @[Decoupled.scala:51:35]
wire [1:0] ex_ctrl_typeTagOut = ex_cp_valid ? io_cp_req_bits_typeTagOut : ex_reg_ctrl_typeTagOut; // @[Decoupled.scala:51:35]
wire ex_ctrl_fromint = ex_cp_valid ? io_cp_req_bits_fromint : ex_reg_ctrl_fromint; // @[Decoupled.scala:51:35]
wire ex_ctrl_toint = ex_cp_valid ? io_cp_req_bits_toint : ex_reg_ctrl_toint; // @[Decoupled.scala:51:35]
wire ex_ctrl_fastpipe = ex_cp_valid ? io_cp_req_bits_fastpipe : ex_reg_ctrl_fastpipe; // @[Decoupled.scala:51:35]
wire ex_ctrl_fma = ~ex_cp_valid & ex_reg_ctrl_fma; // @[Decoupled.scala:51:35]
wire ex_ctrl_div = ex_cp_valid ? io_cp_req_bits_div : ex_reg_ctrl_div; // @[Decoupled.scala:51:35]
wire ex_ctrl_sqrt = ex_cp_valid ? io_cp_req_bits_sqrt : ex_reg_ctrl_sqrt; // @[Decoupled.scala:51:35]
wire ex_ctrl_wflags = ex_cp_valid ? io_cp_req_bits_wflags : ex_reg_ctrl_wflags; // @[Decoupled.scala:51:35]
reg [1:0] mem_ctrl_typeTagOut; // @[FPU.scala:801:27]
reg mem_ctrl_fromint; // @[FPU.scala:801:27]
reg mem_ctrl_toint; // @[FPU.scala:801:27]
reg mem_ctrl_fastpipe; // @[FPU.scala:801:27]
reg mem_ctrl_fma; // @[FPU.scala:801:27]
reg mem_ctrl_div; // @[FPU.scala:801:27]
reg mem_ctrl_sqrt; // @[FPU.scala:801:27]
reg mem_ctrl_wflags; // @[FPU.scala:801:27]
reg mem_ctrl_vec; // @[FPU.scala:801:27]
reg wb_ctrl_toint; // @[FPU.scala:802:26]
wire [63:0] _wdata_T_6 = ((&load_wb_typeTag) | load_wb_typeTag == 2'h2 ? 64'h0 : load_wb_typeTag == 2'h1 ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000) | load_wb_data; // @[package.scala:39:{76,86}]
wire wdata_rawIn_isZeroExpIn = _wdata_T_6[62:52] == 11'h0; // @[FPU.scala:431:23]
wire [5:0] wdata_rawIn_normDist = _wdata_T_6[51] ? 6'h0 : _wdata_T_6[50] ? 6'h1 : _wdata_T_6[49] ? 6'h2 : _wdata_T_6[48] ? 6'h3 : _wdata_T_6[47] ? 6'h4 : _wdata_T_6[46] ? 6'h5 : _wdata_T_6[45] ? 6'h6 : _wdata_T_6[44] ? 6'h7 : _wdata_T_6[43] ? 6'h8 : _wdata_T_6[42] ? 6'h9 : _wdata_T_6[41] ? 6'hA : _wdata_T_6[40] ? 6'hB : _wdata_T_6[39] ? 6'hC : _wdata_T_6[38] ? 6'hD : _wdata_T_6[37] ? 6'hE : _wdata_T_6[36] ? 6'hF : _wdata_T_6[35] ? 6'h10 : _wdata_T_6[34] ? 6'h11 : _wdata_T_6[33] ? 6'h12 : _wdata_T_6[32] ? 6'h13 : _wdata_T_6[31] ? 6'h14 : _wdata_T_6[30] ? 6'h15 : _wdata_T_6[29] ? 6'h16 : _wdata_T_6[28] ? 6'h17 : _wdata_T_6[27] ? 6'h18 : _wdata_T_6[26] ? 6'h19 : _wdata_T_6[25] ? 6'h1A : _wdata_T_6[24] ? 6'h1B : _wdata_T_6[23] ? 6'h1C : _wdata_T_6[22] ? 6'h1D : _wdata_T_6[21] ? 6'h1E : _wdata_T_6[20] ? 6'h1F : _wdata_T_6[19] ? 6'h20 : _wdata_T_6[18] ? 6'h21 : _wdata_T_6[17] ? 6'h22 : _wdata_T_6[16] ? 6'h23 : _wdata_T_6[15] ? 6'h24 : _wdata_T_6[14] ? 6'h25 : _wdata_T_6[13] ? 6'h26 : _wdata_T_6[12] ? 6'h27 : _wdata_T_6[11] ? 6'h28 : _wdata_T_6[10] ? 6'h29 : _wdata_T_6[9] ? 6'h2A : _wdata_T_6[8] ? 6'h2B : _wdata_T_6[7] ? 6'h2C : _wdata_T_6[6] ? 6'h2D : _wdata_T_6[5] ? 6'h2E : _wdata_T_6[4] ? 6'h2F : _wdata_T_6[3] ? 6'h30 : _wdata_T_6[2] ? 6'h31 : {5'h19, ~(_wdata_T_6[1])}; // @[Mux.scala:50:70]
wire [114:0] _wdata_rawIn_subnormFract_T = {63'h0, _wdata_T_6[51:0]} << wdata_rawIn_normDist; // @[Mux.scala:50:70]
wire [11:0] _wdata_rawIn_adjustedExp_T_4 = (wdata_rawIn_isZeroExpIn ? {6'h3F, ~wdata_rawIn_normDist} : {1'h0, _wdata_T_6[62:52]}) + {10'h100, wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [51:0] _wdata_rawIn_out_sig_T_2 = wdata_rawIn_isZeroExpIn ? {_wdata_rawIn_subnormFract_T[50:0], 1'h0} : _wdata_T_6[51:0]; // @[FPU.scala:431:23]
wire [2:0] _wdata_T_8 = wdata_rawIn_isZeroExpIn & ~(|(_wdata_T_6[51:0])) ? 3'h0 : _wdata_rawIn_adjustedExp_T_4[11:9]; // @[FPU.scala:431:23, :735:7]
wire _GEN_0 = _wdata_T_8[0] | (&(_wdata_rawIn_adjustedExp_T_4[11:10])) & (|(_wdata_T_6[51:0])); // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn_1 = _wdata_T_6[30:23] == 8'h0; // @[FPU.scala:431:23]
wire [4:0] wdata_rawIn_normDist_1 = _wdata_T_6[22] ? 5'h0 : _wdata_T_6[21] ? 5'h1 : _wdata_T_6[20] ? 5'h2 : _wdata_T_6[19] ? 5'h3 : _wdata_T_6[18] ? 5'h4 : _wdata_T_6[17] ? 5'h5 : _wdata_T_6[16] ? 5'h6 : _wdata_T_6[15] ? 5'h7 : _wdata_T_6[14] ? 5'h8 : _wdata_T_6[13] ? 5'h9 : _wdata_T_6[12] ? 5'hA : _wdata_T_6[11] ? 5'hB : _wdata_T_6[10] ? 5'hC : _wdata_T_6[9] ? 5'hD : _wdata_T_6[8] ? 5'hE : _wdata_T_6[7] ? 5'hF : _wdata_T_6[6] ? 5'h10 : _wdata_T_6[5] ? 5'h11 : _wdata_T_6[4] ? 5'h12 : _wdata_T_6[3] ? 5'h13 : _wdata_T_6[2] ? 5'h14 : _wdata_T_6[1] ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [53:0] _wdata_rawIn_subnormFract_T_2 = {31'h0, _wdata_T_6[22:0]} << wdata_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [8:0] _wdata_rawIn_adjustedExp_T_9 = (wdata_rawIn_isZeroExpIn_1 ? {4'hF, ~wdata_rawIn_normDist_1} : {1'h0, _wdata_T_6[30:23]}) + {7'h20, wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [22:0] _wdata_rawIn_out_sig_T_6 = wdata_rawIn_isZeroExpIn_1 ? {_wdata_rawIn_subnormFract_T_2[21:0], 1'h0} : _wdata_T_6[22:0]; // @[FPU.scala:431:23]
wire [2:0] _wdata_T_17 = wdata_rawIn_isZeroExpIn_1 & ~(|(_wdata_T_6[22:0])) ? 3'h0 : _wdata_rawIn_adjustedExp_T_9[8:6]; // @[FPU.scala:431:23, :735:7]
wire _GEN_1 = _wdata_T_17[0] | (&(_wdata_rawIn_adjustedExp_T_9[8:7])) & (|(_wdata_T_6[22:0])); // @[FPU.scala:431:23]
wire wdata_rawIn_isZeroExpIn_2 = _wdata_T_6[14:10] == 5'h0; // @[FPU.scala:431:23]
wire [3:0] wdata_rawIn_normDist_2 = _wdata_T_6[9] ? 4'h0 : _wdata_T_6[8] ? 4'h1 : _wdata_T_6[7] ? 4'h2 : _wdata_T_6[6] ? 4'h3 : _wdata_T_6[5] ? 4'h4 : _wdata_T_6[4] ? 4'h5 : _wdata_T_6[3] ? 4'h6 : _wdata_T_6[2] ? 4'h7 : {3'h4, ~(_wdata_T_6[1])}; // @[Mux.scala:50:70]
wire [24:0] _wdata_rawIn_subnormFract_T_4 = {15'h0, _wdata_T_6[9:0]} << wdata_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [5:0] _wdata_rawIn_adjustedExp_T_14 = (wdata_rawIn_isZeroExpIn_2 ? {2'h3, ~wdata_rawIn_normDist_2} : {1'h0, _wdata_T_6[14:10]}) + {4'h4, wdata_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1}; // @[Mux.scala:50:70]
wire [2:0] _wdata_T_26 = wdata_rawIn_isZeroExpIn_2 & ~(|(_wdata_T_6[9:0])) ? 3'h0 : _wdata_rawIn_adjustedExp_T_14[5:3]; // @[FPU.scala:431:23, :735:7]
wire [60:0] _GEN_2 = (&{_wdata_T_8[2:1], _GEN_0}) ? {&(_wdata_rawIn_out_sig_T_2[51:32]), _wdata_rawIn_adjustedExp_T_4[7:1], _wdata_T_17[2], _wdata_rawIn_out_sig_T_2[51:32], _wdata_T_6[31], _wdata_T_17[1], _GEN_1, (&{_wdata_T_17[2:1], _GEN_1}) ? {&(_wdata_rawIn_out_sig_T_6[22:16]), _wdata_rawIn_adjustedExp_T_9[4:1], _wdata_T_26[2], _wdata_rawIn_out_sig_T_6[22:16], _wdata_T_6[15], _wdata_T_26[1], _wdata_T_26[0] | (&(_wdata_rawIn_adjustedExp_T_14[5:4])) & (|(_wdata_T_6[9:0])), _wdata_rawIn_adjustedExp_T_14[2:0], wdata_rawIn_isZeroExpIn_2 ? {_wdata_rawIn_subnormFract_T_4[8:0], 1'h0} : _wdata_T_6[9:0]} : {_wdata_rawIn_adjustedExp_T_9[5:0], _wdata_rawIn_out_sig_T_6}} : {_wdata_rawIn_adjustedExp_T_4[8:0], _wdata_rawIn_out_sig_T_2}; // @[FPU.scala:249:{25,56}, :336:26, :338:{8,42}, :339:8, :340:8, :343:8, :344:8, :431:23]
wire _hfma_io_in_valid_T = req_valid & ex_ctrl_fma; // @[FPU.scala:780:32, :800:20, :873:33]
wire hfma_io_in_bits_req_ren3 = ~ex_cp_valid & ex_reg_ctrl_ren3; // @[Decoupled.scala:51:35]
wire hfma_io_in_bits_req_swap23 = ~ex_cp_valid & ex_reg_ctrl_swap23; // @[Decoupled.scala:51:35]
wire [2:0] fpmu_io_in_bits_rm = ex_cp_valid ? io_cp_req_bits_rm : (&(ex_reg_inst[14:12])) ? io_fcsr_rm : ex_reg_inst[14:12]; // @[Decoupled.scala:51:35]
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = {_regfile_ext_R2_data[23], _regfile_ext_R2_data[14:13]}; // @[FPU.scala:276:18, :279:26, :358:14, :818:20]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {6'h0, _regfile_ext_R2_data[23], _regfile_ext_R2_data[14:10]} + 12'h7E0; // @[FPU.scala:276:18, :280:{31,50}, :358:14, :818:20]
wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = {_regfile_ext_R2_data[52], _regfile_ext_R2_data[30:29]}; // @[FPU.scala:276:18, :279:26, :358:14, :818:20]
wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {3'h0, _regfile_ext_R2_data[52], _regfile_ext_R2_data[30:23]} + 12'h700; // @[FPU.scala:276:18, :280:{31,50}, :358:14, :735:7, :818:20]
wire _fpiu_io_in_bits_req_in3_T_6 = ex_ctrl_typeTagIn == 2'h1; // @[package.scala:39:86]
wire _GEN_3 = (&ex_ctrl_typeTagIn) | ex_ctrl_typeTagIn == 2'h2; // @[package.scala:39:{76,86}]
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = {_regfile_ext_R1_data[23], _regfile_ext_R1_data[14:13]}; // @[FPU.scala:276:18, :279:26, :358:14, :818:20]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {6'h0, _regfile_ext_R1_data[23], _regfile_ext_R1_data[14:10]} + 12'h7E0; // @[FPU.scala:276:18, :280:{31,50}, :358:14, :818:20]
wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = {_regfile_ext_R1_data[52], _regfile_ext_R1_data[30:29]}; // @[FPU.scala:276:18, :279:26, :358:14, :818:20]
wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {3'h0, _regfile_ext_R1_data[52], _regfile_ext_R1_data[30:23]} + 12'h700; // @[FPU.scala:276:18, :280:{31,50}, :358:14, :735:7, :818:20]
wire fpmu_io_in_bits_ren2 = ex_cp_valid ? io_cp_req_bits_ren2 : ex_reg_ctrl_ren2; // @[Decoupled.scala:51:35]
wire [1:0] fpmu_io_in_bits_typeTagIn = ex_cp_valid ? io_cp_req_bits_typeTagIn : ex_reg_ctrl_typeTagIn; // @[Decoupled.scala:51:35]
wire [1:0] fpmu_io_in_bits_typeTagOut = ex_cp_valid ? io_cp_req_bits_typeTagOut : ex_reg_ctrl_typeTagOut; // @[Decoupled.scala:51:35]
wire fpmu_io_in_bits_wflags = ex_cp_valid ? io_cp_req_bits_wflags : ex_reg_ctrl_wflags; // @[Decoupled.scala:51:35]
wire [1:0] ifpu_io_in_bits_typ = ex_cp_valid ? io_cp_req_bits_typ : ex_reg_inst[21:20]; // @[Decoupled.scala:51:35]
wire [64:0] fpmu_io_in_bits_in1 = ex_cp_valid ? io_cp_req_bits_in1 : _GEN_3 | (_fpiu_io_in_bits_req_in3_T_6 | (&{_regfile_ext_R2_data[31], _regfile_ext_R2_data[52], _regfile_ext_R2_data[30:28]})) & (&(_regfile_ext_R2_data[64:60])) ? (_GEN_3 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in3_T_6 ? {_regfile_ext_R2_data[31], fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0 | fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5 ? {_regfile_ext_R2_data[52], _regfile_ext_R2_data[30:29], _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]} : _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, _regfile_ext_R2_data[22:0], 29'h0} : {_regfile_ext_R2_data[15], fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0 | fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5 ? {_regfile_ext_R2_data[23], _regfile_ext_R2_data[14:13], _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]} : _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, _regfile_ext_R2_data[9:0], 42'h0}) : 65'hE008000000000000; // @[Decoupled.scala:51:35]
wire [64:0] fpmu_io_in_bits_in2 = ex_cp_valid ? io_cp_req_bits_in2 : _GEN_3 | (_fpiu_io_in_bits_req_in3_T_6 | (&{_regfile_ext_R1_data[31], _regfile_ext_R1_data[52], _regfile_ext_R1_data[30:28]})) & (&(_regfile_ext_R1_data[64:60])) ? (_GEN_3 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in3_T_6 ? {_regfile_ext_R1_data[31], fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0 | fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5 ? {_regfile_ext_R1_data[52], _regfile_ext_R1_data[30:29], _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]} : _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, _regfile_ext_R1_data[22:0], 29'h0} : {_regfile_ext_R1_data[15], fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0 | fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5 ? {_regfile_ext_R1_data[23], _regfile_ext_R1_data[14:13], _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]} : _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, _regfile_ext_R1_data[9:0], 42'h0}) : 65'hE008000000000000; // @[Decoupled.scala:51:35]
wire _GEN_4 = _fpiu_io_out_valid & mem_cp_valid & mem_ctrl_toint; // @[FPU.scala:782:29, :801:27, :876:20, :881:{26,42}]
reg [4:0] divSqrt_waddr; // @[FPU.scala:898:26]
reg divSqrt_cp; // @[FPU.scala:899:23]
wire _divSqrt_io_inValid_T_2 = mem_ctrl_typeTagOut == 2'h1; // @[FPU.scala:801:27, :911:72]
wire _divSqrt_io_inValid_T_4 = mem_ctrl_typeTagOut == 2'h2; // @[FPU.scala:801:27, :916:78]
wire _divSqrt_io_inValid_T = mem_ctrl_typeTagOut == 2'h0; // @[FPU.scala:801:27, :922:78]
reg [1:0] wen; // @[FPU.scala:939:20]
reg [4:0] wbInfo_0_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_0_typeTag; // @[FPU.scala:940:19]
reg wbInfo_0_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_0_pipeid; // @[FPU.scala:940:19]
reg [4:0] wbInfo_1_rd; // @[FPU.scala:940:19]
reg [1:0] wbInfo_1_typeTag; // @[FPU.scala:940:19]
reg wbInfo_1_cp; // @[FPU.scala:940:19]
reg [2:0] wbInfo_1_pipeid; // @[FPU.scala:940:19]
reg write_port_busy; // @[FPU.scala:942:34]
wire [4:0] waddr = divSqrt_wen ? divSqrt_waddr : wbInfo_0_rd; // @[FPU.scala:898:26, :940:19, :963:18, :1037:66, :1038:21]
wire [1:0] wtypeTag = divSqrt_wen ? divSqrt_typeTag : wbInfo_0_typeTag; // @[FPU.scala:940:19, :965:21, :1037:66, :1038:21, :1041:25]
wire _wexc_T = wbInfo_0_pipeid == 3'h1; // @[package.scala:39:86]
wire _wexc_T_2 = wbInfo_0_pipeid == 3'h2; // @[package.scala:39:86]
wire _wexc_T_4 = wbInfo_0_pipeid == 3'h3; // @[package.scala:39:86]
wire _GEN_5 = (&wbInfo_0_pipeid) | wbInfo_0_pipeid == 3'h6 | wbInfo_0_pipeid == 3'h5 | wbInfo_0_pipeid == 3'h4; // @[package.scala:39:{76,86}]
wire [64:0] _wdata_T_53 = divSqrt_wen ? divSqrt_wdata : _GEN_5 ? _hfma_io_out_bits_data : _wexc_T_4 ? _dfma_io_out_bits_data : _wexc_T_2 ? _sfma_io_out_bits_data : _wexc_T ? _ifpu_io_out_bits_data : _fpmu_io_out_bits_data; // @[package.scala:39:{76,86}]
wire [64:0] wdata_1 = (&wtypeTag) | wtypeTag == 2'h2 ? _wdata_T_53 : wtypeTag == 2'h1 ? {12'hFFF, _wdata_T_53[31], 20'hFFFFF, _wdata_T_53[32], _wdata_T_53[30:0]} : {41'h1FFFFFFFFFF, _wdata_T_53[15], 7'h7F, _wdata_T_53[16], _wdata_T_53[14:0]}; // @[package.scala:39:{76,86}]
wire _GEN_6 = ~wbInfo_0_cp & wen[0] | divSqrt_wen; // @[FPU.scala:939:20, :940:19, :968:{10,24,30,35}, :1037:66, :1038:21] |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
| module BranchKillableQueue_7( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [11:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush // @[util.scala:463:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:504:34]
wire _io_enq_ready_T; // @[util.scala:543:21]
wire _io_deq_valid_T_1; // @[util.scala:548:42]
wire [31:0] out_uop_inst; // @[util.scala:545:19]
wire [31:0] out_uop_debug_inst; // @[util.scala:545:19]
wire out_uop_is_rvc; // @[util.scala:545:19]
wire [39:0] out_uop_debug_pc; // @[util.scala:545:19]
wire out_uop_iq_type_0; // @[util.scala:545:19]
wire out_uop_iq_type_1; // @[util.scala:545:19]
wire out_uop_iq_type_2; // @[util.scala:545:19]
wire out_uop_iq_type_3; // @[util.scala:545:19]
wire out_uop_fu_code_0; // @[util.scala:545:19]
wire out_uop_fu_code_1; // @[util.scala:545:19]
wire out_uop_fu_code_2; // @[util.scala:545:19]
wire out_uop_fu_code_3; // @[util.scala:545:19]
wire out_uop_fu_code_4; // @[util.scala:545:19]
wire out_uop_fu_code_5; // @[util.scala:545:19]
wire out_uop_fu_code_6; // @[util.scala:545:19]
wire out_uop_fu_code_7; // @[util.scala:545:19]
wire out_uop_fu_code_8; // @[util.scala:545:19]
wire out_uop_fu_code_9; // @[util.scala:545:19]
wire out_uop_iw_issued; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19]
wire [1:0] out_uop_iw_p1_speculative_child; // @[util.scala:545:19]
wire [1:0] out_uop_iw_p2_speculative_child; // @[util.scala:545:19]
wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19]
wire [1:0] out_uop_dis_col_sel; // @[util.scala:545:19]
wire [11:0] out_uop_br_mask; // @[util.scala:545:19]
wire [3:0] out_uop_br_tag; // @[util.scala:545:19]
wire [3:0] out_uop_br_type; // @[util.scala:545:19]
wire out_uop_is_sfb; // @[util.scala:545:19]
wire out_uop_is_fence; // @[util.scala:545:19]
wire out_uop_is_fencei; // @[util.scala:545:19]
wire out_uop_is_sfence; // @[util.scala:545:19]
wire out_uop_is_amo; // @[util.scala:545:19]
wire out_uop_is_eret; // @[util.scala:545:19]
wire out_uop_is_sys_pc2epc; // @[util.scala:545:19]
wire out_uop_is_rocc; // @[util.scala:545:19]
wire out_uop_is_mov; // @[util.scala:545:19]
wire [4:0] out_uop_ftq_idx; // @[util.scala:545:19]
wire out_uop_edge_inst; // @[util.scala:545:19]
wire [5:0] out_uop_pc_lob; // @[util.scala:545:19]
wire out_uop_taken; // @[util.scala:545:19]
wire out_uop_imm_rename; // @[util.scala:545:19]
wire [2:0] out_uop_imm_sel; // @[util.scala:545:19]
wire [4:0] out_uop_pimm; // @[util.scala:545:19]
wire [19:0] out_uop_imm_packed; // @[util.scala:545:19]
wire [1:0] out_uop_op1_sel; // @[util.scala:545:19]
wire [2:0] out_uop_op2_sel; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wen; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_toint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fma; // @[util.scala:545:19]
wire out_uop_fp_ctrl_div; // @[util.scala:545:19]
wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19]
wire out_uop_fp_ctrl_vec; // @[util.scala:545:19]
wire [5:0] out_uop_rob_idx; // @[util.scala:545:19]
wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19]
wire [3:0] out_uop_stq_idx; // @[util.scala:545:19]
wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19]
wire [6:0] out_uop_pdst; // @[util.scala:545:19]
wire [6:0] out_uop_prs1; // @[util.scala:545:19]
wire [6:0] out_uop_prs2; // @[util.scala:545:19]
wire [6:0] out_uop_prs3; // @[util.scala:545:19]
wire [4:0] out_uop_ppred; // @[util.scala:545:19]
wire out_uop_prs1_busy; // @[util.scala:545:19]
wire out_uop_prs2_busy; // @[util.scala:545:19]
wire out_uop_prs3_busy; // @[util.scala:545:19]
wire out_uop_ppred_busy; // @[util.scala:545:19]
wire [6:0] out_uop_stale_pdst; // @[util.scala:545:19]
wire out_uop_exception; // @[util.scala:545:19]
wire [63:0] out_uop_exc_cause; // @[util.scala:545:19]
wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19]
wire [1:0] out_uop_mem_size; // @[util.scala:545:19]
wire out_uop_mem_signed; // @[util.scala:545:19]
wire out_uop_uses_ldq; // @[util.scala:545:19]
wire out_uop_uses_stq; // @[util.scala:545:19]
wire out_uop_is_unique; // @[util.scala:545:19]
wire out_uop_flush_on_commit; // @[util.scala:545:19]
wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19]
wire out_uop_ldst_is_rs1; // @[util.scala:545:19]
wire [5:0] out_uop_ldst; // @[util.scala:545:19]
wire [5:0] out_uop_lrs1; // @[util.scala:545:19]
wire [5:0] out_uop_lrs2; // @[util.scala:545:19]
wire [5:0] out_uop_lrs3; // @[util.scala:545:19]
wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19]
wire out_uop_frs3_en; // @[util.scala:545:19]
wire out_uop_fcn_dw; // @[util.scala:545:19]
wire [4:0] out_uop_fcn_op; // @[util.scala:545:19]
wire out_uop_fp_val; // @[util.scala:545:19]
wire [2:0] out_uop_fp_rm; // @[util.scala:545:19]
wire [1:0] out_uop_fp_typ; // @[util.scala:545:19]
wire out_uop_xcpt_pf_if; // @[util.scala:545:19]
wire out_uop_xcpt_ae_if; // @[util.scala:545:19]
wire out_uop_xcpt_ma_if; // @[util.scala:545:19]
wire out_uop_bp_debug_if; // @[util.scala:545:19]
wire out_uop_bp_xcpt_if; // @[util.scala:545:19]
wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19]
wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19]
wire [63:0] out_data; // @[util.scala:545:19]
wire _io_empty_T_1; // @[util.scala:512:27]
wire _do_enq_T_6 = io_flush_0; // @[util.scala:458:7, :514:113]
wire _valids_0_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_1_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_2_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_3_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_4_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_5_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_6_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire _valids_7_T_5 = io_flush_0; // @[util.scala:458:7, :520:94]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [11:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty; // @[util.scala:458:7]
wire [2:0] io_count; // @[util.scala:458:7]
reg valids_0; // @[util.scala:504:26]
reg valids_1; // @[util.scala:504:26]
reg valids_2; // @[util.scala:504:26]
reg valids_3; // @[util.scala:504:26]
reg valids_4; // @[util.scala:504:26]
reg valids_5; // @[util.scala:504:26]
reg valids_6; // @[util.scala:504:26]
reg valids_7; // @[util.scala:504:26]
reg [31:0] uops_0_inst; // @[util.scala:505:22]
reg [31:0] uops_0_debug_inst; // @[util.scala:505:22]
reg uops_0_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_0_debug_pc; // @[util.scala:505:22]
reg uops_0_iq_type_0; // @[util.scala:505:22]
reg uops_0_iq_type_1; // @[util.scala:505:22]
reg uops_0_iq_type_2; // @[util.scala:505:22]
reg uops_0_iq_type_3; // @[util.scala:505:22]
reg uops_0_fu_code_0; // @[util.scala:505:22]
reg uops_0_fu_code_1; // @[util.scala:505:22]
reg uops_0_fu_code_2; // @[util.scala:505:22]
reg uops_0_fu_code_3; // @[util.scala:505:22]
reg uops_0_fu_code_4; // @[util.scala:505:22]
reg uops_0_fu_code_5; // @[util.scala:505:22]
reg uops_0_fu_code_6; // @[util.scala:505:22]
reg uops_0_fu_code_7; // @[util.scala:505:22]
reg uops_0_fu_code_8; // @[util.scala:505:22]
reg uops_0_fu_code_9; // @[util.scala:505:22]
reg uops_0_iw_issued; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_0_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_0_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_0_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_0_br_mask; // @[util.scala:505:22]
reg [3:0] uops_0_br_tag; // @[util.scala:505:22]
reg [3:0] uops_0_br_type; // @[util.scala:505:22]
reg uops_0_is_sfb; // @[util.scala:505:22]
reg uops_0_is_fence; // @[util.scala:505:22]
reg uops_0_is_fencei; // @[util.scala:505:22]
reg uops_0_is_sfence; // @[util.scala:505:22]
reg uops_0_is_amo; // @[util.scala:505:22]
reg uops_0_is_eret; // @[util.scala:505:22]
reg uops_0_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_0_is_rocc; // @[util.scala:505:22]
reg uops_0_is_mov; // @[util.scala:505:22]
reg [4:0] uops_0_ftq_idx; // @[util.scala:505:22]
reg uops_0_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_0_pc_lob; // @[util.scala:505:22]
reg uops_0_taken; // @[util.scala:505:22]
reg uops_0_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_0_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_0_pimm; // @[util.scala:505:22]
reg [19:0] uops_0_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_0_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_0_op2_sel; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_0_fp_ctrl_div; // @[util.scala:505:22]
reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_0_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_0_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_0_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_0_pdst; // @[util.scala:505:22]
reg [6:0] uops_0_prs1; // @[util.scala:505:22]
reg [6:0] uops_0_prs2; // @[util.scala:505:22]
reg [6:0] uops_0_prs3; // @[util.scala:505:22]
reg [4:0] uops_0_ppred; // @[util.scala:505:22]
reg uops_0_prs1_busy; // @[util.scala:505:22]
reg uops_0_prs2_busy; // @[util.scala:505:22]
reg uops_0_prs3_busy; // @[util.scala:505:22]
reg uops_0_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_0_stale_pdst; // @[util.scala:505:22]
reg uops_0_exception; // @[util.scala:505:22]
reg [63:0] uops_0_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_0_mem_size; // @[util.scala:505:22]
reg uops_0_mem_signed; // @[util.scala:505:22]
reg uops_0_uses_ldq; // @[util.scala:505:22]
reg uops_0_uses_stq; // @[util.scala:505:22]
reg uops_0_is_unique; // @[util.scala:505:22]
reg uops_0_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22]
reg uops_0_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_0_ldst; // @[util.scala:505:22]
reg [5:0] uops_0_lrs1; // @[util.scala:505:22]
reg [5:0] uops_0_lrs2; // @[util.scala:505:22]
reg [5:0] uops_0_lrs3; // @[util.scala:505:22]
reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22]
reg uops_0_frs3_en; // @[util.scala:505:22]
reg uops_0_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_0_fcn_op; // @[util.scala:505:22]
reg uops_0_fp_val; // @[util.scala:505:22]
reg [2:0] uops_0_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_0_fp_typ; // @[util.scala:505:22]
reg uops_0_xcpt_pf_if; // @[util.scala:505:22]
reg uops_0_xcpt_ae_if; // @[util.scala:505:22]
reg uops_0_xcpt_ma_if; // @[util.scala:505:22]
reg uops_0_bp_debug_if; // @[util.scala:505:22]
reg uops_0_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_1_inst; // @[util.scala:505:22]
reg [31:0] uops_1_debug_inst; // @[util.scala:505:22]
reg uops_1_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_1_debug_pc; // @[util.scala:505:22]
reg uops_1_iq_type_0; // @[util.scala:505:22]
reg uops_1_iq_type_1; // @[util.scala:505:22]
reg uops_1_iq_type_2; // @[util.scala:505:22]
reg uops_1_iq_type_3; // @[util.scala:505:22]
reg uops_1_fu_code_0; // @[util.scala:505:22]
reg uops_1_fu_code_1; // @[util.scala:505:22]
reg uops_1_fu_code_2; // @[util.scala:505:22]
reg uops_1_fu_code_3; // @[util.scala:505:22]
reg uops_1_fu_code_4; // @[util.scala:505:22]
reg uops_1_fu_code_5; // @[util.scala:505:22]
reg uops_1_fu_code_6; // @[util.scala:505:22]
reg uops_1_fu_code_7; // @[util.scala:505:22]
reg uops_1_fu_code_8; // @[util.scala:505:22]
reg uops_1_fu_code_9; // @[util.scala:505:22]
reg uops_1_iw_issued; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_1_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_1_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_1_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_1_br_mask; // @[util.scala:505:22]
reg [3:0] uops_1_br_tag; // @[util.scala:505:22]
reg [3:0] uops_1_br_type; // @[util.scala:505:22]
reg uops_1_is_sfb; // @[util.scala:505:22]
reg uops_1_is_fence; // @[util.scala:505:22]
reg uops_1_is_fencei; // @[util.scala:505:22]
reg uops_1_is_sfence; // @[util.scala:505:22]
reg uops_1_is_amo; // @[util.scala:505:22]
reg uops_1_is_eret; // @[util.scala:505:22]
reg uops_1_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_1_is_rocc; // @[util.scala:505:22]
reg uops_1_is_mov; // @[util.scala:505:22]
reg [4:0] uops_1_ftq_idx; // @[util.scala:505:22]
reg uops_1_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_1_pc_lob; // @[util.scala:505:22]
reg uops_1_taken; // @[util.scala:505:22]
reg uops_1_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_1_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_1_pimm; // @[util.scala:505:22]
reg [19:0] uops_1_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_1_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_1_op2_sel; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_1_fp_ctrl_div; // @[util.scala:505:22]
reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_1_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_1_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_1_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_1_pdst; // @[util.scala:505:22]
reg [6:0] uops_1_prs1; // @[util.scala:505:22]
reg [6:0] uops_1_prs2; // @[util.scala:505:22]
reg [6:0] uops_1_prs3; // @[util.scala:505:22]
reg [4:0] uops_1_ppred; // @[util.scala:505:22]
reg uops_1_prs1_busy; // @[util.scala:505:22]
reg uops_1_prs2_busy; // @[util.scala:505:22]
reg uops_1_prs3_busy; // @[util.scala:505:22]
reg uops_1_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_1_stale_pdst; // @[util.scala:505:22]
reg uops_1_exception; // @[util.scala:505:22]
reg [63:0] uops_1_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_1_mem_size; // @[util.scala:505:22]
reg uops_1_mem_signed; // @[util.scala:505:22]
reg uops_1_uses_ldq; // @[util.scala:505:22]
reg uops_1_uses_stq; // @[util.scala:505:22]
reg uops_1_is_unique; // @[util.scala:505:22]
reg uops_1_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22]
reg uops_1_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_1_ldst; // @[util.scala:505:22]
reg [5:0] uops_1_lrs1; // @[util.scala:505:22]
reg [5:0] uops_1_lrs2; // @[util.scala:505:22]
reg [5:0] uops_1_lrs3; // @[util.scala:505:22]
reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22]
reg uops_1_frs3_en; // @[util.scala:505:22]
reg uops_1_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_1_fcn_op; // @[util.scala:505:22]
reg uops_1_fp_val; // @[util.scala:505:22]
reg [2:0] uops_1_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_1_fp_typ; // @[util.scala:505:22]
reg uops_1_xcpt_pf_if; // @[util.scala:505:22]
reg uops_1_xcpt_ae_if; // @[util.scala:505:22]
reg uops_1_xcpt_ma_if; // @[util.scala:505:22]
reg uops_1_bp_debug_if; // @[util.scala:505:22]
reg uops_1_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_2_inst; // @[util.scala:505:22]
reg [31:0] uops_2_debug_inst; // @[util.scala:505:22]
reg uops_2_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_2_debug_pc; // @[util.scala:505:22]
reg uops_2_iq_type_0; // @[util.scala:505:22]
reg uops_2_iq_type_1; // @[util.scala:505:22]
reg uops_2_iq_type_2; // @[util.scala:505:22]
reg uops_2_iq_type_3; // @[util.scala:505:22]
reg uops_2_fu_code_0; // @[util.scala:505:22]
reg uops_2_fu_code_1; // @[util.scala:505:22]
reg uops_2_fu_code_2; // @[util.scala:505:22]
reg uops_2_fu_code_3; // @[util.scala:505:22]
reg uops_2_fu_code_4; // @[util.scala:505:22]
reg uops_2_fu_code_5; // @[util.scala:505:22]
reg uops_2_fu_code_6; // @[util.scala:505:22]
reg uops_2_fu_code_7; // @[util.scala:505:22]
reg uops_2_fu_code_8; // @[util.scala:505:22]
reg uops_2_fu_code_9; // @[util.scala:505:22]
reg uops_2_iw_issued; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_2_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_2_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_2_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_2_br_mask; // @[util.scala:505:22]
reg [3:0] uops_2_br_tag; // @[util.scala:505:22]
reg [3:0] uops_2_br_type; // @[util.scala:505:22]
reg uops_2_is_sfb; // @[util.scala:505:22]
reg uops_2_is_fence; // @[util.scala:505:22]
reg uops_2_is_fencei; // @[util.scala:505:22]
reg uops_2_is_sfence; // @[util.scala:505:22]
reg uops_2_is_amo; // @[util.scala:505:22]
reg uops_2_is_eret; // @[util.scala:505:22]
reg uops_2_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_2_is_rocc; // @[util.scala:505:22]
reg uops_2_is_mov; // @[util.scala:505:22]
reg [4:0] uops_2_ftq_idx; // @[util.scala:505:22]
reg uops_2_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_2_pc_lob; // @[util.scala:505:22]
reg uops_2_taken; // @[util.scala:505:22]
reg uops_2_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_2_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_2_pimm; // @[util.scala:505:22]
reg [19:0] uops_2_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_2_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_2_op2_sel; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_2_fp_ctrl_div; // @[util.scala:505:22]
reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_2_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_2_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_2_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_2_pdst; // @[util.scala:505:22]
reg [6:0] uops_2_prs1; // @[util.scala:505:22]
reg [6:0] uops_2_prs2; // @[util.scala:505:22]
reg [6:0] uops_2_prs3; // @[util.scala:505:22]
reg [4:0] uops_2_ppred; // @[util.scala:505:22]
reg uops_2_prs1_busy; // @[util.scala:505:22]
reg uops_2_prs2_busy; // @[util.scala:505:22]
reg uops_2_prs3_busy; // @[util.scala:505:22]
reg uops_2_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_2_stale_pdst; // @[util.scala:505:22]
reg uops_2_exception; // @[util.scala:505:22]
reg [63:0] uops_2_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_2_mem_size; // @[util.scala:505:22]
reg uops_2_mem_signed; // @[util.scala:505:22]
reg uops_2_uses_ldq; // @[util.scala:505:22]
reg uops_2_uses_stq; // @[util.scala:505:22]
reg uops_2_is_unique; // @[util.scala:505:22]
reg uops_2_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22]
reg uops_2_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_2_ldst; // @[util.scala:505:22]
reg [5:0] uops_2_lrs1; // @[util.scala:505:22]
reg [5:0] uops_2_lrs2; // @[util.scala:505:22]
reg [5:0] uops_2_lrs3; // @[util.scala:505:22]
reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22]
reg uops_2_frs3_en; // @[util.scala:505:22]
reg uops_2_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_2_fcn_op; // @[util.scala:505:22]
reg uops_2_fp_val; // @[util.scala:505:22]
reg [2:0] uops_2_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_2_fp_typ; // @[util.scala:505:22]
reg uops_2_xcpt_pf_if; // @[util.scala:505:22]
reg uops_2_xcpt_ae_if; // @[util.scala:505:22]
reg uops_2_xcpt_ma_if; // @[util.scala:505:22]
reg uops_2_bp_debug_if; // @[util.scala:505:22]
reg uops_2_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_3_inst; // @[util.scala:505:22]
reg [31:0] uops_3_debug_inst; // @[util.scala:505:22]
reg uops_3_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_3_debug_pc; // @[util.scala:505:22]
reg uops_3_iq_type_0; // @[util.scala:505:22]
reg uops_3_iq_type_1; // @[util.scala:505:22]
reg uops_3_iq_type_2; // @[util.scala:505:22]
reg uops_3_iq_type_3; // @[util.scala:505:22]
reg uops_3_fu_code_0; // @[util.scala:505:22]
reg uops_3_fu_code_1; // @[util.scala:505:22]
reg uops_3_fu_code_2; // @[util.scala:505:22]
reg uops_3_fu_code_3; // @[util.scala:505:22]
reg uops_3_fu_code_4; // @[util.scala:505:22]
reg uops_3_fu_code_5; // @[util.scala:505:22]
reg uops_3_fu_code_6; // @[util.scala:505:22]
reg uops_3_fu_code_7; // @[util.scala:505:22]
reg uops_3_fu_code_8; // @[util.scala:505:22]
reg uops_3_fu_code_9; // @[util.scala:505:22]
reg uops_3_iw_issued; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_3_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_3_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_3_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_3_br_mask; // @[util.scala:505:22]
reg [3:0] uops_3_br_tag; // @[util.scala:505:22]
reg [3:0] uops_3_br_type; // @[util.scala:505:22]
reg uops_3_is_sfb; // @[util.scala:505:22]
reg uops_3_is_fence; // @[util.scala:505:22]
reg uops_3_is_fencei; // @[util.scala:505:22]
reg uops_3_is_sfence; // @[util.scala:505:22]
reg uops_3_is_amo; // @[util.scala:505:22]
reg uops_3_is_eret; // @[util.scala:505:22]
reg uops_3_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_3_is_rocc; // @[util.scala:505:22]
reg uops_3_is_mov; // @[util.scala:505:22]
reg [4:0] uops_3_ftq_idx; // @[util.scala:505:22]
reg uops_3_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_3_pc_lob; // @[util.scala:505:22]
reg uops_3_taken; // @[util.scala:505:22]
reg uops_3_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_3_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_3_pimm; // @[util.scala:505:22]
reg [19:0] uops_3_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_3_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_3_op2_sel; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_3_fp_ctrl_div; // @[util.scala:505:22]
reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_3_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_3_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_3_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_3_pdst; // @[util.scala:505:22]
reg [6:0] uops_3_prs1; // @[util.scala:505:22]
reg [6:0] uops_3_prs2; // @[util.scala:505:22]
reg [6:0] uops_3_prs3; // @[util.scala:505:22]
reg [4:0] uops_3_ppred; // @[util.scala:505:22]
reg uops_3_prs1_busy; // @[util.scala:505:22]
reg uops_3_prs2_busy; // @[util.scala:505:22]
reg uops_3_prs3_busy; // @[util.scala:505:22]
reg uops_3_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_3_stale_pdst; // @[util.scala:505:22]
reg uops_3_exception; // @[util.scala:505:22]
reg [63:0] uops_3_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_3_mem_size; // @[util.scala:505:22]
reg uops_3_mem_signed; // @[util.scala:505:22]
reg uops_3_uses_ldq; // @[util.scala:505:22]
reg uops_3_uses_stq; // @[util.scala:505:22]
reg uops_3_is_unique; // @[util.scala:505:22]
reg uops_3_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22]
reg uops_3_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_3_ldst; // @[util.scala:505:22]
reg [5:0] uops_3_lrs1; // @[util.scala:505:22]
reg [5:0] uops_3_lrs2; // @[util.scala:505:22]
reg [5:0] uops_3_lrs3; // @[util.scala:505:22]
reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22]
reg uops_3_frs3_en; // @[util.scala:505:22]
reg uops_3_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_3_fcn_op; // @[util.scala:505:22]
reg uops_3_fp_val; // @[util.scala:505:22]
reg [2:0] uops_3_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_3_fp_typ; // @[util.scala:505:22]
reg uops_3_xcpt_pf_if; // @[util.scala:505:22]
reg uops_3_xcpt_ae_if; // @[util.scala:505:22]
reg uops_3_xcpt_ma_if; // @[util.scala:505:22]
reg uops_3_bp_debug_if; // @[util.scala:505:22]
reg uops_3_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_4_inst; // @[util.scala:505:22]
reg [31:0] uops_4_debug_inst; // @[util.scala:505:22]
reg uops_4_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_4_debug_pc; // @[util.scala:505:22]
reg uops_4_iq_type_0; // @[util.scala:505:22]
reg uops_4_iq_type_1; // @[util.scala:505:22]
reg uops_4_iq_type_2; // @[util.scala:505:22]
reg uops_4_iq_type_3; // @[util.scala:505:22]
reg uops_4_fu_code_0; // @[util.scala:505:22]
reg uops_4_fu_code_1; // @[util.scala:505:22]
reg uops_4_fu_code_2; // @[util.scala:505:22]
reg uops_4_fu_code_3; // @[util.scala:505:22]
reg uops_4_fu_code_4; // @[util.scala:505:22]
reg uops_4_fu_code_5; // @[util.scala:505:22]
reg uops_4_fu_code_6; // @[util.scala:505:22]
reg uops_4_fu_code_7; // @[util.scala:505:22]
reg uops_4_fu_code_8; // @[util.scala:505:22]
reg uops_4_fu_code_9; // @[util.scala:505:22]
reg uops_4_iw_issued; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_4_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_4_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_4_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_4_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_4_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_4_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_4_br_mask; // @[util.scala:505:22]
reg [3:0] uops_4_br_tag; // @[util.scala:505:22]
reg [3:0] uops_4_br_type; // @[util.scala:505:22]
reg uops_4_is_sfb; // @[util.scala:505:22]
reg uops_4_is_fence; // @[util.scala:505:22]
reg uops_4_is_fencei; // @[util.scala:505:22]
reg uops_4_is_sfence; // @[util.scala:505:22]
reg uops_4_is_amo; // @[util.scala:505:22]
reg uops_4_is_eret; // @[util.scala:505:22]
reg uops_4_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_4_is_rocc; // @[util.scala:505:22]
reg uops_4_is_mov; // @[util.scala:505:22]
reg [4:0] uops_4_ftq_idx; // @[util.scala:505:22]
reg uops_4_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_4_pc_lob; // @[util.scala:505:22]
reg uops_4_taken; // @[util.scala:505:22]
reg uops_4_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_4_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_4_pimm; // @[util.scala:505:22]
reg [19:0] uops_4_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_4_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_4_op2_sel; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_4_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_4_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_4_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_4_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_4_fp_ctrl_div; // @[util.scala:505:22]
reg uops_4_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_4_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_4_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_4_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_4_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_4_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_4_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_4_pdst; // @[util.scala:505:22]
reg [6:0] uops_4_prs1; // @[util.scala:505:22]
reg [6:0] uops_4_prs2; // @[util.scala:505:22]
reg [6:0] uops_4_prs3; // @[util.scala:505:22]
reg [4:0] uops_4_ppred; // @[util.scala:505:22]
reg uops_4_prs1_busy; // @[util.scala:505:22]
reg uops_4_prs2_busy; // @[util.scala:505:22]
reg uops_4_prs3_busy; // @[util.scala:505:22]
reg uops_4_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_4_stale_pdst; // @[util.scala:505:22]
reg uops_4_exception; // @[util.scala:505:22]
reg [63:0] uops_4_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_4_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_4_mem_size; // @[util.scala:505:22]
reg uops_4_mem_signed; // @[util.scala:505:22]
reg uops_4_uses_ldq; // @[util.scala:505:22]
reg uops_4_uses_stq; // @[util.scala:505:22]
reg uops_4_is_unique; // @[util.scala:505:22]
reg uops_4_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_4_csr_cmd; // @[util.scala:505:22]
reg uops_4_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_4_ldst; // @[util.scala:505:22]
reg [5:0] uops_4_lrs1; // @[util.scala:505:22]
reg [5:0] uops_4_lrs2; // @[util.scala:505:22]
reg [5:0] uops_4_lrs3; // @[util.scala:505:22]
reg [1:0] uops_4_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:505:22]
reg uops_4_frs3_en; // @[util.scala:505:22]
reg uops_4_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_4_fcn_op; // @[util.scala:505:22]
reg uops_4_fp_val; // @[util.scala:505:22]
reg [2:0] uops_4_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_4_fp_typ; // @[util.scala:505:22]
reg uops_4_xcpt_pf_if; // @[util.scala:505:22]
reg uops_4_xcpt_ae_if; // @[util.scala:505:22]
reg uops_4_xcpt_ma_if; // @[util.scala:505:22]
reg uops_4_bp_debug_if; // @[util.scala:505:22]
reg uops_4_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_4_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_4_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_5_inst; // @[util.scala:505:22]
reg [31:0] uops_5_debug_inst; // @[util.scala:505:22]
reg uops_5_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_5_debug_pc; // @[util.scala:505:22]
reg uops_5_iq_type_0; // @[util.scala:505:22]
reg uops_5_iq_type_1; // @[util.scala:505:22]
reg uops_5_iq_type_2; // @[util.scala:505:22]
reg uops_5_iq_type_3; // @[util.scala:505:22]
reg uops_5_fu_code_0; // @[util.scala:505:22]
reg uops_5_fu_code_1; // @[util.scala:505:22]
reg uops_5_fu_code_2; // @[util.scala:505:22]
reg uops_5_fu_code_3; // @[util.scala:505:22]
reg uops_5_fu_code_4; // @[util.scala:505:22]
reg uops_5_fu_code_5; // @[util.scala:505:22]
reg uops_5_fu_code_6; // @[util.scala:505:22]
reg uops_5_fu_code_7; // @[util.scala:505:22]
reg uops_5_fu_code_8; // @[util.scala:505:22]
reg uops_5_fu_code_9; // @[util.scala:505:22]
reg uops_5_iw_issued; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_5_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_5_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_5_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_5_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_5_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_5_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_5_br_mask; // @[util.scala:505:22]
reg [3:0] uops_5_br_tag; // @[util.scala:505:22]
reg [3:0] uops_5_br_type; // @[util.scala:505:22]
reg uops_5_is_sfb; // @[util.scala:505:22]
reg uops_5_is_fence; // @[util.scala:505:22]
reg uops_5_is_fencei; // @[util.scala:505:22]
reg uops_5_is_sfence; // @[util.scala:505:22]
reg uops_5_is_amo; // @[util.scala:505:22]
reg uops_5_is_eret; // @[util.scala:505:22]
reg uops_5_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_5_is_rocc; // @[util.scala:505:22]
reg uops_5_is_mov; // @[util.scala:505:22]
reg [4:0] uops_5_ftq_idx; // @[util.scala:505:22]
reg uops_5_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_5_pc_lob; // @[util.scala:505:22]
reg uops_5_taken; // @[util.scala:505:22]
reg uops_5_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_5_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_5_pimm; // @[util.scala:505:22]
reg [19:0] uops_5_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_5_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_5_op2_sel; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_5_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_5_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_5_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_5_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_5_fp_ctrl_div; // @[util.scala:505:22]
reg uops_5_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_5_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_5_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_5_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_5_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_5_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_5_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_5_pdst; // @[util.scala:505:22]
reg [6:0] uops_5_prs1; // @[util.scala:505:22]
reg [6:0] uops_5_prs2; // @[util.scala:505:22]
reg [6:0] uops_5_prs3; // @[util.scala:505:22]
reg [4:0] uops_5_ppred; // @[util.scala:505:22]
reg uops_5_prs1_busy; // @[util.scala:505:22]
reg uops_5_prs2_busy; // @[util.scala:505:22]
reg uops_5_prs3_busy; // @[util.scala:505:22]
reg uops_5_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_5_stale_pdst; // @[util.scala:505:22]
reg uops_5_exception; // @[util.scala:505:22]
reg [63:0] uops_5_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_5_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_5_mem_size; // @[util.scala:505:22]
reg uops_5_mem_signed; // @[util.scala:505:22]
reg uops_5_uses_ldq; // @[util.scala:505:22]
reg uops_5_uses_stq; // @[util.scala:505:22]
reg uops_5_is_unique; // @[util.scala:505:22]
reg uops_5_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_5_csr_cmd; // @[util.scala:505:22]
reg uops_5_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_5_ldst; // @[util.scala:505:22]
reg [5:0] uops_5_lrs1; // @[util.scala:505:22]
reg [5:0] uops_5_lrs2; // @[util.scala:505:22]
reg [5:0] uops_5_lrs3; // @[util.scala:505:22]
reg [1:0] uops_5_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:505:22]
reg uops_5_frs3_en; // @[util.scala:505:22]
reg uops_5_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_5_fcn_op; // @[util.scala:505:22]
reg uops_5_fp_val; // @[util.scala:505:22]
reg [2:0] uops_5_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_5_fp_typ; // @[util.scala:505:22]
reg uops_5_xcpt_pf_if; // @[util.scala:505:22]
reg uops_5_xcpt_ae_if; // @[util.scala:505:22]
reg uops_5_xcpt_ma_if; // @[util.scala:505:22]
reg uops_5_bp_debug_if; // @[util.scala:505:22]
reg uops_5_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_5_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_5_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_6_inst; // @[util.scala:505:22]
reg [31:0] uops_6_debug_inst; // @[util.scala:505:22]
reg uops_6_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_6_debug_pc; // @[util.scala:505:22]
reg uops_6_iq_type_0; // @[util.scala:505:22]
reg uops_6_iq_type_1; // @[util.scala:505:22]
reg uops_6_iq_type_2; // @[util.scala:505:22]
reg uops_6_iq_type_3; // @[util.scala:505:22]
reg uops_6_fu_code_0; // @[util.scala:505:22]
reg uops_6_fu_code_1; // @[util.scala:505:22]
reg uops_6_fu_code_2; // @[util.scala:505:22]
reg uops_6_fu_code_3; // @[util.scala:505:22]
reg uops_6_fu_code_4; // @[util.scala:505:22]
reg uops_6_fu_code_5; // @[util.scala:505:22]
reg uops_6_fu_code_6; // @[util.scala:505:22]
reg uops_6_fu_code_7; // @[util.scala:505:22]
reg uops_6_fu_code_8; // @[util.scala:505:22]
reg uops_6_fu_code_9; // @[util.scala:505:22]
reg uops_6_iw_issued; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_6_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_6_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_6_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_6_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_6_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_6_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_6_br_mask; // @[util.scala:505:22]
reg [3:0] uops_6_br_tag; // @[util.scala:505:22]
reg [3:0] uops_6_br_type; // @[util.scala:505:22]
reg uops_6_is_sfb; // @[util.scala:505:22]
reg uops_6_is_fence; // @[util.scala:505:22]
reg uops_6_is_fencei; // @[util.scala:505:22]
reg uops_6_is_sfence; // @[util.scala:505:22]
reg uops_6_is_amo; // @[util.scala:505:22]
reg uops_6_is_eret; // @[util.scala:505:22]
reg uops_6_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_6_is_rocc; // @[util.scala:505:22]
reg uops_6_is_mov; // @[util.scala:505:22]
reg [4:0] uops_6_ftq_idx; // @[util.scala:505:22]
reg uops_6_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_6_pc_lob; // @[util.scala:505:22]
reg uops_6_taken; // @[util.scala:505:22]
reg uops_6_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_6_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_6_pimm; // @[util.scala:505:22]
reg [19:0] uops_6_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_6_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_6_op2_sel; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_6_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_6_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_6_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_6_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_6_fp_ctrl_div; // @[util.scala:505:22]
reg uops_6_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_6_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_6_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_6_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_6_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_6_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_6_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_6_pdst; // @[util.scala:505:22]
reg [6:0] uops_6_prs1; // @[util.scala:505:22]
reg [6:0] uops_6_prs2; // @[util.scala:505:22]
reg [6:0] uops_6_prs3; // @[util.scala:505:22]
reg [4:0] uops_6_ppred; // @[util.scala:505:22]
reg uops_6_prs1_busy; // @[util.scala:505:22]
reg uops_6_prs2_busy; // @[util.scala:505:22]
reg uops_6_prs3_busy; // @[util.scala:505:22]
reg uops_6_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_6_stale_pdst; // @[util.scala:505:22]
reg uops_6_exception; // @[util.scala:505:22]
reg [63:0] uops_6_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_6_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_6_mem_size; // @[util.scala:505:22]
reg uops_6_mem_signed; // @[util.scala:505:22]
reg uops_6_uses_ldq; // @[util.scala:505:22]
reg uops_6_uses_stq; // @[util.scala:505:22]
reg uops_6_is_unique; // @[util.scala:505:22]
reg uops_6_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_6_csr_cmd; // @[util.scala:505:22]
reg uops_6_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_6_ldst; // @[util.scala:505:22]
reg [5:0] uops_6_lrs1; // @[util.scala:505:22]
reg [5:0] uops_6_lrs2; // @[util.scala:505:22]
reg [5:0] uops_6_lrs3; // @[util.scala:505:22]
reg [1:0] uops_6_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:505:22]
reg uops_6_frs3_en; // @[util.scala:505:22]
reg uops_6_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_6_fcn_op; // @[util.scala:505:22]
reg uops_6_fp_val; // @[util.scala:505:22]
reg [2:0] uops_6_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_6_fp_typ; // @[util.scala:505:22]
reg uops_6_xcpt_pf_if; // @[util.scala:505:22]
reg uops_6_xcpt_ae_if; // @[util.scala:505:22]
reg uops_6_xcpt_ma_if; // @[util.scala:505:22]
reg uops_6_bp_debug_if; // @[util.scala:505:22]
reg uops_6_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_6_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_6_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_7_inst; // @[util.scala:505:22]
reg [31:0] uops_7_debug_inst; // @[util.scala:505:22]
reg uops_7_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_7_debug_pc; // @[util.scala:505:22]
reg uops_7_iq_type_0; // @[util.scala:505:22]
reg uops_7_iq_type_1; // @[util.scala:505:22]
reg uops_7_iq_type_2; // @[util.scala:505:22]
reg uops_7_iq_type_3; // @[util.scala:505:22]
reg uops_7_fu_code_0; // @[util.scala:505:22]
reg uops_7_fu_code_1; // @[util.scala:505:22]
reg uops_7_fu_code_2; // @[util.scala:505:22]
reg uops_7_fu_code_3; // @[util.scala:505:22]
reg uops_7_fu_code_4; // @[util.scala:505:22]
reg uops_7_fu_code_5; // @[util.scala:505:22]
reg uops_7_fu_code_6; // @[util.scala:505:22]
reg uops_7_fu_code_7; // @[util.scala:505:22]
reg uops_7_fu_code_8; // @[util.scala:505:22]
reg uops_7_fu_code_9; // @[util.scala:505:22]
reg uops_7_iw_issued; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_7_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_7_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_7_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_7_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_7_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_7_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_7_br_mask; // @[util.scala:505:22]
reg [3:0] uops_7_br_tag; // @[util.scala:505:22]
reg [3:0] uops_7_br_type; // @[util.scala:505:22]
reg uops_7_is_sfb; // @[util.scala:505:22]
reg uops_7_is_fence; // @[util.scala:505:22]
reg uops_7_is_fencei; // @[util.scala:505:22]
reg uops_7_is_sfence; // @[util.scala:505:22]
reg uops_7_is_amo; // @[util.scala:505:22]
reg uops_7_is_eret; // @[util.scala:505:22]
reg uops_7_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_7_is_rocc; // @[util.scala:505:22]
reg uops_7_is_mov; // @[util.scala:505:22]
reg [4:0] uops_7_ftq_idx; // @[util.scala:505:22]
reg uops_7_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_7_pc_lob; // @[util.scala:505:22]
reg uops_7_taken; // @[util.scala:505:22]
reg uops_7_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_7_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_7_pimm; // @[util.scala:505:22]
reg [19:0] uops_7_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_7_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_7_op2_sel; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_7_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_7_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_7_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_7_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_7_fp_ctrl_div; // @[util.scala:505:22]
reg uops_7_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_7_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_7_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_7_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_7_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_7_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_7_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_7_pdst; // @[util.scala:505:22]
reg [6:0] uops_7_prs1; // @[util.scala:505:22]
reg [6:0] uops_7_prs2; // @[util.scala:505:22]
reg [6:0] uops_7_prs3; // @[util.scala:505:22]
reg [4:0] uops_7_ppred; // @[util.scala:505:22]
reg uops_7_prs1_busy; // @[util.scala:505:22]
reg uops_7_prs2_busy; // @[util.scala:505:22]
reg uops_7_prs3_busy; // @[util.scala:505:22]
reg uops_7_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_7_stale_pdst; // @[util.scala:505:22]
reg uops_7_exception; // @[util.scala:505:22]
reg [63:0] uops_7_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_7_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_7_mem_size; // @[util.scala:505:22]
reg uops_7_mem_signed; // @[util.scala:505:22]
reg uops_7_uses_ldq; // @[util.scala:505:22]
reg uops_7_uses_stq; // @[util.scala:505:22]
reg uops_7_is_unique; // @[util.scala:505:22]
reg uops_7_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_7_csr_cmd; // @[util.scala:505:22]
reg uops_7_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_7_ldst; // @[util.scala:505:22]
reg [5:0] uops_7_lrs1; // @[util.scala:505:22]
reg [5:0] uops_7_lrs2; // @[util.scala:505:22]
reg [5:0] uops_7_lrs3; // @[util.scala:505:22]
reg [1:0] uops_7_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:505:22]
reg uops_7_frs3_en; // @[util.scala:505:22]
reg uops_7_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_7_fcn_op; // @[util.scala:505:22]
reg uops_7_fp_val; // @[util.scala:505:22]
reg [2:0] uops_7_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_7_fp_typ; // @[util.scala:505:22]
reg uops_7_xcpt_pf_if; // @[util.scala:505:22]
reg uops_7_xcpt_ae_if; // @[util.scala:505:22]
reg uops_7_xcpt_ma_if; // @[util.scala:505:22]
reg uops_7_bp_debug_if; // @[util.scala:505:22]
reg uops_7_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_7_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_7_debug_tsrc; // @[util.scala:505:22]
reg [2:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [2:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:509:29]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}]
assign io_empty = _io_empty_T_1; // @[util.scala:458:7, :512:27]
wire _GEN = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26]
wire full; // @[util.scala:513:26]
assign full = _GEN; // @[util.scala:513:26]
wire _io_count_T; // @[util.scala:553:34]
assign _io_count_T = _GEN; // @[util.scala:513:26, :553:34]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire [11:0] _do_enq_T_1 = io_brupdate_b1_mispredict_mask_0 & io_enq_bits_uop_br_mask_0; // @[util.scala:126:51, :458:7]
wire _do_enq_T_2 = |_do_enq_T_1; // @[util.scala:126:{51,59}]
wire _do_enq_T_3 = _do_enq_T_2; // @[util.scala:61:61, :126:59]
wire _do_enq_T_4 = ~_do_enq_T_3; // @[util.scala:61:61, :514:42]
wire _do_enq_T_5 = _do_enq_T & _do_enq_T_4; // @[Decoupled.scala:51:35]
wire _do_enq_T_7 = ~_do_enq_T_6; // @[util.scala:514:{102,113}]
wire _do_enq_T_8 = _do_enq_T_5 & _do_enq_T_7; // @[util.scala:514:{39,99,102}]
wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}]
wire [7:0] _GEN_0 = {{valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:515:44]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}]
wire _do_deq_T_2 = ~io_empty; // @[util.scala:458:7, :515:71]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}]
wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}]
wire [11:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:126:{51,59}]
wire _valids_0_T_2 = _valids_0_T_1; // @[util.scala:61:61, :126:59]
wire _valids_0_T_3 = ~_valids_0_T_2; // @[util.scala:61:61, :520:34]
wire _valids_0_T_4 = valids_0 & _valids_0_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_0_T_6 = ~_valids_0_T_5; // @[util.scala:520:{83,94}]
wire _valids_0_T_7 = _valids_0_T_4 & _valids_0_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:126:{51,59}]
wire _valids_1_T_2 = _valids_1_T_1; // @[util.scala:61:61, :126:59]
wire _valids_1_T_3 = ~_valids_1_T_2; // @[util.scala:61:61, :520:34]
wire _valids_1_T_4 = valids_1 & _valids_1_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_1_T_6 = ~_valids_1_T_5; // @[util.scala:520:{83,94}]
wire _valids_1_T_7 = _valids_1_T_4 & _valids_1_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:126:{51,59}]
wire _valids_2_T_2 = _valids_2_T_1; // @[util.scala:61:61, :126:59]
wire _valids_2_T_3 = ~_valids_2_T_2; // @[util.scala:61:61, :520:34]
wire _valids_2_T_4 = valids_2 & _valids_2_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_2_T_6 = ~_valids_2_T_5; // @[util.scala:520:{83,94}]
wire _valids_2_T_7 = _valids_2_T_4 & _valids_2_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:126:{51,59}]
wire _valids_3_T_2 = _valids_3_T_1; // @[util.scala:61:61, :126:59]
wire _valids_3_T_3 = ~_valids_3_T_2; // @[util.scala:61:61, :520:34]
wire _valids_3_T_4 = valids_3 & _valids_3_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_3_T_6 = ~_valids_3_T_5; // @[util.scala:520:{83,94}]
wire _valids_3_T_7 = _valids_3_T_4 & _valids_3_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:126:{51,59}]
wire _valids_4_T_2 = _valids_4_T_1; // @[util.scala:61:61, :126:59]
wire _valids_4_T_3 = ~_valids_4_T_2; // @[util.scala:61:61, :520:34]
wire _valids_4_T_4 = valids_4 & _valids_4_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_4_T_6 = ~_valids_4_T_5; // @[util.scala:520:{83,94}]
wire _valids_4_T_7 = _valids_4_T_4 & _valids_4_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:126:{51,59}]
wire _valids_5_T_2 = _valids_5_T_1; // @[util.scala:61:61, :126:59]
wire _valids_5_T_3 = ~_valids_5_T_2; // @[util.scala:61:61, :520:34]
wire _valids_5_T_4 = valids_5 & _valids_5_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_5_T_6 = ~_valids_5_T_5; // @[util.scala:520:{83,94}]
wire _valids_5_T_7 = _valids_5_T_4 & _valids_5_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:126:{51,59}]
wire _valids_6_T_2 = _valids_6_T_1; // @[util.scala:61:61, :126:59]
wire _valids_6_T_3 = ~_valids_6_T_2; // @[util.scala:61:61, :520:34]
wire _valids_6_T_4 = valids_6 & _valids_6_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_6_T_6 = ~_valids_6_T_5; // @[util.scala:520:{83,94}]
wire _valids_6_T_7 = _valids_6_T_4 & _valids_6_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:126:{51,59}]
wire _valids_7_T_2 = _valids_7_T_1; // @[util.scala:61:61, :126:59]
wire _valids_7_T_3 = ~_valids_7_T_2; // @[util.scala:61:61, :520:34]
wire _valids_7_T_4 = valids_7 & _valids_7_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_7_T_6 = ~_valids_7_T_5; // @[util.scala:520:{83,94}]
wire _valids_7_T_7 = _valids_7_T_4 & _valids_7_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23, :458:7]
wire [11:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:93:{25,27}, :458:7]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [3:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [3:0] _value_T = _GEN_2 + 4'h1; // @[Counter.scala:77:24]
wire [2:0] _value_T_1 = _value_T[2:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [3:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [3:0] _value_T_2 = _GEN_3 + 4'h1; // @[Counter.scala:77:24]
wire [2:0] _value_T_3 = _value_T_2[2:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19]
wire [7:0][31:0] _GEN_4 = {{uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][31:0] _GEN_5 = {{uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_6 = {{uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rvc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][39:0] _GEN_7 = {{uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_pc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_8 = {{uops_7_iq_type_0}, {uops_6_iq_type_0}, {uops_5_iq_type_0}, {uops_4_iq_type_0}, {uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_0 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_9 = {{uops_7_iq_type_1}, {uops_6_iq_type_1}, {uops_5_iq_type_1}, {uops_4_iq_type_1}, {uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_1 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_10 = {{uops_7_iq_type_2}, {uops_6_iq_type_2}, {uops_5_iq_type_2}, {uops_4_iq_type_2}, {uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_2 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_11 = {{uops_7_iq_type_3}, {uops_6_iq_type_3}, {uops_5_iq_type_3}, {uops_4_iq_type_3}, {uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_3 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_12 = {{uops_7_fu_code_0}, {uops_6_fu_code_0}, {uops_5_fu_code_0}, {uops_4_fu_code_0}, {uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_0 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_13 = {{uops_7_fu_code_1}, {uops_6_fu_code_1}, {uops_5_fu_code_1}, {uops_4_fu_code_1}, {uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_1 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_14 = {{uops_7_fu_code_2}, {uops_6_fu_code_2}, {uops_5_fu_code_2}, {uops_4_fu_code_2}, {uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_2 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_15 = {{uops_7_fu_code_3}, {uops_6_fu_code_3}, {uops_5_fu_code_3}, {uops_4_fu_code_3}, {uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_3 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_16 = {{uops_7_fu_code_4}, {uops_6_fu_code_4}, {uops_5_fu_code_4}, {uops_4_fu_code_4}, {uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_4 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_17 = {{uops_7_fu_code_5}, {uops_6_fu_code_5}, {uops_5_fu_code_5}, {uops_4_fu_code_5}, {uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_5 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_18 = {{uops_7_fu_code_6}, {uops_6_fu_code_6}, {uops_5_fu_code_6}, {uops_4_fu_code_6}, {uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_6 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_19 = {{uops_7_fu_code_7}, {uops_6_fu_code_7}, {uops_5_fu_code_7}, {uops_4_fu_code_7}, {uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_7 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_20 = {{uops_7_fu_code_8}, {uops_6_fu_code_8}, {uops_5_fu_code_8}, {uops_4_fu_code_8}, {uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_8 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_21 = {{uops_7_fu_code_9}, {uops_6_fu_code_9}, {uops_5_fu_code_9}, {uops_4_fu_code_9}, {uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_9 = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_22 = {{uops_7_iw_issued}, {uops_6_iw_issued}, {uops_5_iw_issued}, {uops_4_iw_issued}, {uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_23 = {{uops_7_iw_issued_partial_agen}, {uops_6_iw_issued_partial_agen}, {uops_5_iw_issued_partial_agen}, {uops_4_iw_issued_partial_agen}, {uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_agen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_24 = {{uops_7_iw_issued_partial_dgen}, {uops_6_iw_issued_partial_dgen}, {uops_5_iw_issued_partial_dgen}, {uops_4_iw_issued_partial_dgen}, {uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_dgen = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_25 = {{uops_7_iw_p1_speculative_child}, {uops_6_iw_p1_speculative_child}, {uops_5_iw_p1_speculative_child}, {uops_4_iw_p1_speculative_child}, {uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_26 = {{uops_7_iw_p2_speculative_child}, {uops_6_iw_p2_speculative_child}, {uops_5_iw_p2_speculative_child}, {uops_4_iw_p2_speculative_child}, {uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_speculative_child = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_27 = {{uops_7_iw_p1_bypass_hint}, {uops_6_iw_p1_bypass_hint}, {uops_5_iw_p1_bypass_hint}, {uops_4_iw_p1_bypass_hint}, {uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_28 = {{uops_7_iw_p2_bypass_hint}, {uops_6_iw_p2_bypass_hint}, {uops_5_iw_p2_bypass_hint}, {uops_4_iw_p2_bypass_hint}, {uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_29 = {{uops_7_iw_p3_bypass_hint}, {uops_6_iw_p3_bypass_hint}, {uops_5_iw_p3_bypass_hint}, {uops_4_iw_p3_bypass_hint}, {uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p3_bypass_hint = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_30 = {{uops_7_dis_col_sel}, {uops_6_dis_col_sel}, {uops_5_dis_col_sel}, {uops_4_dis_col_sel}, {uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_dis_col_sel = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][11:0] _GEN_31 = {{uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_mask = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_32 = {{uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_tag = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_33 = {{uops_7_br_type}, {uops_6_br_type}, {uops_5_br_type}, {uops_4_br_type}, {uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_type = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_34 = {{uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfb = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_35 = {{uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fence = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_36 = {{uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fencei = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_37 = {{uops_7_is_sfence}, {uops_6_is_sfence}, {uops_5_is_sfence}, {uops_4_is_sfence}, {uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfence = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_38 = {{uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_amo = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_39 = {{uops_7_is_eret}, {uops_6_is_eret}, {uops_5_is_eret}, {uops_4_is_eret}, {uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_eret = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_40 = {{uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sys_pc2epc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_41 = {{uops_7_is_rocc}, {uops_6_is_rocc}, {uops_5_is_rocc}, {uops_4_is_rocc}, {uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rocc = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_42 = {{uops_7_is_mov}, {uops_6_is_mov}, {uops_5_is_mov}, {uops_4_is_mov}, {uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_mov = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_43 = {{uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ftq_idx = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_44 = {{uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_edge_inst = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_45 = {{uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21]
assign out_uop_pc_lob = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_46 = {{uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21]
assign out_uop_taken = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_47 = {{uops_7_imm_rename}, {uops_6_imm_rename}, {uops_5_imm_rename}, {uops_4_imm_rename}, {uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_rename = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_48 = {{uops_7_imm_sel}, {uops_6_imm_sel}, {uops_5_imm_sel}, {uops_4_imm_sel}, {uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_sel = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_49 = {{uops_7_pimm}, {uops_6_pimm}, {uops_5_pimm}, {uops_4_pimm}, {uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21]
assign out_uop_pimm = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][19:0] _GEN_50 = {{uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_packed = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_51 = {{uops_7_op1_sel}, {uops_6_op1_sel}, {uops_5_op1_sel}, {uops_4_op1_sel}, {uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op1_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_52 = {{uops_7_op2_sel}, {uops_6_op2_sel}, {uops_5_op2_sel}, {uops_4_op2_sel}, {uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op2_sel = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_53 = {{uops_7_fp_ctrl_ldst}, {uops_6_fp_ctrl_ldst}, {uops_5_fp_ctrl_ldst}, {uops_4_fp_ctrl_ldst}, {uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ldst = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_54 = {{uops_7_fp_ctrl_wen}, {uops_6_fp_ctrl_wen}, {uops_5_fp_ctrl_wen}, {uops_4_fp_ctrl_wen}, {uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wen = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_55 = {{uops_7_fp_ctrl_ren1}, {uops_6_fp_ctrl_ren1}, {uops_5_fp_ctrl_ren1}, {uops_4_fp_ctrl_ren1}, {uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren1 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_56 = {{uops_7_fp_ctrl_ren2}, {uops_6_fp_ctrl_ren2}, {uops_5_fp_ctrl_ren2}, {uops_4_fp_ctrl_ren2}, {uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren2 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_57 = {{uops_7_fp_ctrl_ren3}, {uops_6_fp_ctrl_ren3}, {uops_5_fp_ctrl_ren3}, {uops_4_fp_ctrl_ren3}, {uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren3 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_58 = {{uops_7_fp_ctrl_swap12}, {uops_6_fp_ctrl_swap12}, {uops_5_fp_ctrl_swap12}, {uops_4_fp_ctrl_swap12}, {uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap12 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_59 = {{uops_7_fp_ctrl_swap23}, {uops_6_fp_ctrl_swap23}, {uops_5_fp_ctrl_swap23}, {uops_4_fp_ctrl_swap23}, {uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap23 = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_60 = {{uops_7_fp_ctrl_typeTagIn}, {uops_6_fp_ctrl_typeTagIn}, {uops_5_fp_ctrl_typeTagIn}, {uops_4_fp_ctrl_typeTagIn}, {uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagIn = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_61 = {{uops_7_fp_ctrl_typeTagOut}, {uops_6_fp_ctrl_typeTagOut}, {uops_5_fp_ctrl_typeTagOut}, {uops_4_fp_ctrl_typeTagOut}, {uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagOut = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_62 = {{uops_7_fp_ctrl_fromint}, {uops_6_fp_ctrl_fromint}, {uops_5_fp_ctrl_fromint}, {uops_4_fp_ctrl_fromint}, {uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fromint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_63 = {{uops_7_fp_ctrl_toint}, {uops_6_fp_ctrl_toint}, {uops_5_fp_ctrl_toint}, {uops_4_fp_ctrl_toint}, {uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_toint = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_64 = {{uops_7_fp_ctrl_fastpipe}, {uops_6_fp_ctrl_fastpipe}, {uops_5_fp_ctrl_fastpipe}, {uops_4_fp_ctrl_fastpipe}, {uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fastpipe = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_65 = {{uops_7_fp_ctrl_fma}, {uops_6_fp_ctrl_fma}, {uops_5_fp_ctrl_fma}, {uops_4_fp_ctrl_fma}, {uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fma = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_66 = {{uops_7_fp_ctrl_div}, {uops_6_fp_ctrl_div}, {uops_5_fp_ctrl_div}, {uops_4_fp_ctrl_div}, {uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_div = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_67 = {{uops_7_fp_ctrl_sqrt}, {uops_6_fp_ctrl_sqrt}, {uops_5_fp_ctrl_sqrt}, {uops_4_fp_ctrl_sqrt}, {uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_sqrt = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_68 = {{uops_7_fp_ctrl_wflags}, {uops_6_fp_ctrl_wflags}, {uops_5_fp_ctrl_wflags}, {uops_4_fp_ctrl_wflags}, {uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wflags = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_69 = {{uops_7_fp_ctrl_vec}, {uops_6_fp_ctrl_vec}, {uops_5_fp_ctrl_vec}, {uops_4_fp_ctrl_vec}, {uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_vec = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_70 = {{uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rob_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_71 = {{uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][3:0] _GEN_72 = {{uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_stq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_73 = {{uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rxq_idx = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][6:0] _GEN_74 = {{uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_pdst = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][6:0] _GEN_75 = {{uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][6:0] _GEN_76 = {{uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][6:0] _GEN_77 = {{uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3 = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_78 = {{uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_79 = {{uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_80 = {{uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_81 = {{uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_82 = {{uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred_busy = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][6:0] _GEN_83 = {{uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_stale_pdst = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_84 = {{uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21]
assign out_uop_exception = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][63:0] _GEN_85 = {{uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21]
assign out_uop_exc_cause = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_86 = {{uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_cmd = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_87 = {{uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_size = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_88 = {{uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_signed = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_89 = {{uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_ldq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_90 = {{uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_stq = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_91 = {{uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_unique = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_92 = {{uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21]
assign out_uop_flush_on_commit = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_93 = {{uops_7_csr_cmd}, {uops_6_csr_cmd}, {uops_5_csr_cmd}, {uops_4_csr_cmd}, {uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_csr_cmd = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_94 = {{uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst_is_rs1 = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_95 = {{uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_96 = {{uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_97 = {{uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][5:0] _GEN_98 = {{uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs3 = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_99 = {{uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_dst_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_100 = {{uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_101 = {{uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2_rtype = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_102 = {{uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21]
assign out_uop_frs3_en = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_103 = {{uops_7_fcn_dw}, {uops_6_fcn_dw}, {uops_5_fcn_dw}, {uops_4_fcn_dw}, {uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_dw = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][4:0] _GEN_104 = {{uops_7_fcn_op}, {uops_6_fcn_op}, {uops_5_fcn_op}, {uops_4_fcn_op}, {uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_op = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_105 = {{uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_val = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_106 = {{uops_7_fp_rm}, {uops_6_fp_rm}, {uops_5_fp_rm}, {uops_4_fp_rm}, {uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_rm = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][1:0] _GEN_107 = {{uops_7_fp_typ}, {uops_6_fp_typ}, {uops_5_fp_typ}, {uops_4_fp_typ}, {uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_typ = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_108 = {{uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_pf_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_109 = {{uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ae_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_110 = {{uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ma_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_111 = {{uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_debug_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0] _GEN_112 = {{uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_xcpt_if = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_113 = {{uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_fsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40]
wire [7:0][2:0] _GEN_114 = {{uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_tsrc = _GEN_114[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty; // @[util.scala:458:7, :515:71, :548:32]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:515:44, :548:{32,42}]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42]
wire [3:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [2:0] ptr_diff = _ptr_diff_T[2:0]; // @[util.scala:551:34]
wire [3:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:551:34, :553:{22,34}]
assign io_count = _io_count_T_1[2:0]; // @[util.scala:458:7, :553:{16,22}]
wire _GEN_115 = enq_ptr_value == 3'h0; // @[Counter.scala:61:40]
wire _GEN_116 = do_enq & _GEN_115; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_117 = enq_ptr_value == 3'h1; // @[Counter.scala:61:40]
wire _GEN_118 = do_enq & _GEN_117; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_119 = enq_ptr_value == 3'h2; // @[Counter.scala:61:40]
wire _GEN_120 = do_enq & _GEN_119; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_121 = enq_ptr_value == 3'h3; // @[Counter.scala:61:40]
wire _GEN_122 = do_enq & _GEN_121; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_123 = enq_ptr_value == 3'h4; // @[Counter.scala:61:40]
wire _GEN_124 = do_enq & _GEN_123; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_125 = enq_ptr_value == 3'h5; // @[Counter.scala:61:40]
wire _GEN_126 = do_enq & _GEN_125; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_127 = enq_ptr_value == 3'h6; // @[Counter.scala:61:40]
wire _GEN_128 = do_enq & _GEN_127; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_129 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:458:7]
if (reset) begin // @[util.scala:458:7]
valids_0 <= 1'h0; // @[util.scala:504:26]
valids_1 <= 1'h0; // @[util.scala:504:26]
valids_2 <= 1'h0; // @[util.scala:504:26]
valids_3 <= 1'h0; // @[util.scala:504:26]
valids_4 <= 1'h0; // @[util.scala:504:26]
valids_5 <= 1'h0; // @[util.scala:504:26]
valids_6 <= 1'h0; // @[util.scala:504:26]
valids_7 <= 1'h0; // @[util.scala:504:26]
enq_ptr_value <= 3'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 3'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:509:29]
end
else begin // @[util.scala:458:7]
valids_0 <= ~(do_deq & deq_ptr_value == 3'h0) & (_GEN_116 | _valids_0_T_7); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 3'h1) & (_GEN_118 | _valids_1_T_7); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 3'h2) & (_GEN_120 | _valids_2_T_7); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 3'h3) & (_GEN_122 | _valids_3_T_7); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 3'h4) & (_GEN_124 | _valids_4_T_7); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 3'h5) & (_GEN_126 | _valids_5_T_7); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 3'h6) & (_GEN_128 | _valids_6_T_7); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_129 | _valids_7_T_7); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:514:26]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:515:26]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18]
maybe_full <= do_enq; // @[util.scala:509:29, :514:26]
end
if (_GEN_116) begin // @[util.scala:520:18, :526:19, :528:35]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_115) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_0) // @[util.scala:504:26]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_118) begin // @[util.scala:520:18, :526:19, :528:35]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_117) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_1) // @[util.scala:504:26]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_120) begin // @[util.scala:520:18, :526:19, :528:35]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_119) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_2) // @[util.scala:504:26]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_122) begin // @[util.scala:520:18, :526:19, :528:35]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_121) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_3) // @[util.scala:504:26]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_124) begin // @[util.scala:520:18, :526:19, :528:35]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_4_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_4_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_4_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_4_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_4_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_4_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_4_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_4_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_4_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_4_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_4_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_4_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_4_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_4_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_4_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_4_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_4_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_4_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_123) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_4) // @[util.scala:504:26]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_126) begin // @[util.scala:520:18, :526:19, :528:35]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_5_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_5_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_5_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_5_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_5_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_5_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_5_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_5_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_5_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_5_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_5_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_5_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_5_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_5_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_5_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_5_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_5_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_5_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_125) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_5) // @[util.scala:504:26]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_128) begin // @[util.scala:520:18, :526:19, :528:35]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_6_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_6_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_6_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_6_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_6_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_6_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_6_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_6_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_6_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_6_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_6_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_6_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_6_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_6_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_6_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_6_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_6_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_6_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_127) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_6) // @[util.scala:504:26]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_129) begin // @[util.scala:520:18, :526:19, :528:35]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_7_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_7_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_7_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_7_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_7_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_7_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_7_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_7_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_7_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_7_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_7_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_7_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_7_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_7_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_7_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_7_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_7_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_7_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_7) // @[util.scala:504:26]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:97:21, :505:22]
always @(posedge)
ram_8x64 ram_ext ( // @[util.scala:503:22]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (out_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:514:26]
.W0_clk (clock),
.W0_data (io_enq_bits_data_0) // @[util.scala:458:7]
); // @[util.scala:503:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
| module PE_192( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tilelink.scala:
package constellation.protocol
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.soc.{CanAttachToGlobalNoC}
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import scala.collection.immutable.{ListMap}
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLMasterToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 2))
a.io.protocol <> io.tilelink.a
io.tilelink.b <> b.io.protocol
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
e.io.protocol <> io.tilelink.e
io.flits.a <> a.io.flit
b.io.flit <> io.flits.b
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
io.flits.e <> e.io.flit
}
class TLMasterACDToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val a = Decoupled(new IngressFlit(flitWidth))
val c = Decoupled(new IngressFlit(flitWidth))
val d = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val a = Module(new TLAToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0, sourceStart))
val c = Module(new TLCToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 1, sourceStart))
val d = Module(new TLDFromNoC(edgeIn, wideBundle, sourceSize))
a.io.protocol <> io.tilelink.a
c.io.protocol <> io.tilelink.c
io.tilelink.d <> d.io.protocol
io.flits.a <> a.io.flit
io.flits.c <> c.io.flit
d.io.flit <> io.flits.d
}
class TLMasterBEToNoC(
edgeIn: TLEdge, edgesOut: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
slaveToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = Flipped(new TLBundle(wideBundle))
val flits = new Bundle {
val b = Flipped(Decoupled(new EgressFlit(flitWidth)))
val e = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val b = Module(new TLBFromNoC(edgeIn, wideBundle, sourceSize))
val e = Module(new TLEToNoC(edgeIn, edgesOut, wideBundle, (i) => slaveToEgressOffset(i) + 0))
io.tilelink.b <> b.io.protocol
e.io.protocol <> io.tilelink.e
b.io.flit <> io.flits.b
io.flits.e <> e.io.flit
}
class TLSlaveToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val b = Decoupled(new IngressFlit(flitWidth))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 1, sourceStart))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
io.tilelink.a <> a.io.protocol
b.io.protocol <> io.tilelink.b
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
io.tilelink.e <> e.io.protocol
a.io.flit <> io.flits.a
io.flits.b <> b.io.flit
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
e.io.flit <> io.flits.e
}
class TLSlaveACDToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val a = Flipped(Decoupled(new EgressFlit(flitWidth)))
val c = Flipped(Decoupled(new EgressFlit(flitWidth)))
val d = Decoupled(new IngressFlit(flitWidth))
}
})
io.tilelink := DontCare
val a = Module(new TLAFromNoC(edgeOut, wideBundle))
val c = Module(new TLCFromNoC(edgeOut, wideBundle))
val d = Module(new TLDToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0, sourceStart))
io.tilelink.a <> a.io.protocol
io.tilelink.c <> c.io.protocol
d.io.protocol <> io.tilelink.d
a.io.flit <> io.flits.a
c.io.flit <> io.flits.c
io.flits.d <> d.io.flit
}
class TLSlaveBEToNoC(
edgeOut: TLEdge, edgesIn: Seq[TLEdge],
sourceStart: Int, sourceSize: Int,
wideBundle: TLBundleParameters,
masterToEgressOffset: Int => Int,
flitWidth: Int
)(implicit p: Parameters) extends Module {
val io = IO(new Bundle {
val tilelink = new TLBundle(wideBundle)
val flits = new Bundle {
val b = Decoupled(new IngressFlit(flitWidth))
val e = Flipped(Decoupled(new EgressFlit(flitWidth)))
}
})
io.tilelink := DontCare
val b = Module(new TLBToNoC(edgeOut, edgesIn, wideBundle, (i) => masterToEgressOffset(i) + 0))
val e = Module(new TLEFromNoC(edgeOut, wideBundle, sourceSize))
b.io.protocol <> io.tilelink.b
io.tilelink.e <> e.io.protocol
io.flits.b <> b.io.flit
e.io.flit <> io.flits.e
}
class TileLinkInterconnectInterface(edgesIn: Seq[TLEdge], edgesOut: Seq[TLEdge])(implicit val p: Parameters) extends Bundle {
val in = MixedVec(edgesIn.map { e => Flipped(new TLBundle(e.bundle)) })
val out = MixedVec(edgesOut.map { e => new TLBundle(e.bundle) })
}
trait TileLinkProtocolParams extends ProtocolParams with TLFieldHelper {
def edgesIn: Seq[TLEdge]
def edgesOut: Seq[TLEdge]
def edgeInNodes: Seq[Int]
def edgeOutNodes: Seq[Int]
require(edgesIn.size == edgeInNodes.size && edgesOut.size == edgeOutNodes.size)
def wideBundle = TLBundleParameters.union(edgesIn.map(_.bundle) ++ edgesOut.map(_.bundle))
def genBundle = new TLBundle(wideBundle)
def inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
def outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
val vNetBlocking = (blocker: Int, blockee: Int) => blocker < blockee
def genIO()(implicit p: Parameters): Data = new TileLinkInterconnectInterface(edgesIn, edgesOut)
}
object TLConnect {
def apply[T <: TLBundleBase](l: DecoupledIO[T], r: DecoupledIO[T]) = {
l.valid := r.valid
r.ready := l.ready
l.bits.squeezeAll.waiveAll :<>= r.bits.squeezeAll.waiveAll
}
}
// BEGIN: TileLinkProtocolParams
case class TileLinkABCDEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]
) extends TileLinkProtocolParams {
// END: TileLinkProtocolParams
val minPayloadWidth = minTLPayloadWidth(new TLBundle(wideBundle))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(3) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (3) {u})).flatten
val nVirtualNetworks = 5
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 3 + 0 , oi * 3 + 0 + edgesIn.size * 2, 4)) else None) ++ // A
(if (probe ) Some(FlowParams(oi * 2 + 0 + edgesIn.size * 3, ii * 2 + 0 , 3)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 3 + 1 , oi * 3 + 1 + edgesIn.size * 2, 2)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 2 + 1 + edgesIn.size * 3, ii * 2 + 1 , 1)) else None) ++ // D
(if (release ) Some(FlowParams(ii * 3 + 2 , oi * 3 + 2 + edgesIn.size * 2, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master = Module(new TLMasterToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 3 + edgesIn.size * 2 + egressOffset,
minPayloadWidth
))
nif_master.io.tilelink := DontCare
nif_master.io.tilelink.a.valid := false.B
nif_master.io.tilelink.c.valid := false.B
nif_master.io.tilelink.e.valid := false.B
TLConnect(nif_master.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master.io.tilelink.b)
TLConnect(nif_master.io.tilelink.c, protocol.in(i).c)
TLConnect(nif_master.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 3 + 0).flit <> nif_master.io.flits.a
ingresses(i * 3 + 1).flit <> nif_master.io.flits.c
ingresses(i * 3 + 2).flit <> nif_master.io.flits.e
nif_master.io.flits.b <> egresses(i * 2 + 0).flit
nif_master.io.flits.d <> egresses(i * 2 + 1).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave = Module(new TLSlaveToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 2 + egressOffset,
minPayloadWidth
))
nif_slave.io.tilelink := DontCare
nif_slave.io.tilelink.b.valid := false.B
nif_slave.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave.io.tilelink.a)
TLConnect(nif_slave.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(nif_slave.io.tilelink.b, protocol.out(i).b)
TLConnect(protocol.out(i).c, nif_slave.io.tilelink.c)
TLConnect(protocol.out(i).e, nif_slave.io.tilelink.e)
}
ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b
ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d
nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit
nif_slave.io.flits.c <> egresses(i * 3 + 1 + edgesIn.size * 2).flit
nif_slave.io.flits.e <> egresses(i * 3 + 2 + edgesIn.size * 2).flit
}
} }
}
}
case class TileLinkACDProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.a, genBundle.c, genBundle.d).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(2) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (2) {u})).flatten
val nVirtualNetworks = 3
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val reachable = edgeIn.client.clients.exists { c => edgeOut.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)
}}
}}
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (reachable) Some(FlowParams(ii * 2 + 0 , oi * 2 + 0 + edgesIn.size * 1, 2)) else None) ++ // A
(if (release ) Some(FlowParams(ii * 2 + 1 , oi * 2 + 1 + edgesIn.size * 1, 1)) else None) ++ // C
(if (reachable) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 2, ii * 1 + 0 , 0)) else None)) // D
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_acd = Module(new TLMasterACDToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 2 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_acd.io.tilelink := DontCare
nif_master_acd.io.tilelink.a.valid := false.B
nif_master_acd.io.tilelink.c.valid := false.B
nif_master_acd.io.tilelink.e.valid := false.B
TLConnect(nif_master_acd.io.tilelink.a, protocol.in(i).a)
TLConnect(protocol.in(i).d, nif_master_acd.io.tilelink.d)
if (protocol.in(i).params.hasBCE) {
TLConnect(nif_master_acd.io.tilelink.c, protocol.in(i).c)
}
ingresses(i * 2 + 0).flit <> nif_master_acd.io.flits.a
ingresses(i * 2 + 1).flit <> nif_master_acd.io.flits.c
nif_master_acd.io.flits.d <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_acd = Module(new TLSlaveACDToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_acd.io.tilelink := DontCare
nif_slave_acd.io.tilelink.b.valid := false.B
nif_slave_acd.io.tilelink.d.valid := false.B
TLConnect(protocol.out(i).a, nif_slave_acd.io.tilelink.a)
TLConnect(nif_slave_acd.io.tilelink.d, protocol.out(i).d)
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).c, nif_slave_acd.io.tilelink.c)
}
ingresses(i * 1 + 0 + edgesIn.size * 2).flit <> nif_slave_acd.io.flits.d
nif_slave_acd.io.flits.a <> egresses(i * 2 + 0 + edgesIn.size * 1).flit
nif_slave_acd.io.flits.c <> egresses(i * 2 + 1 + edgesIn.size * 1).flit
}
}}
}
}
case class TileLinkBEProtocolParams(
edgesIn: Seq[TLEdge],
edgesOut: Seq[TLEdge],
edgeInNodes: Seq[Int],
edgeOutNodes: Seq[Int]) extends TileLinkProtocolParams {
val minPayloadWidth = minTLPayloadWidth(Seq(genBundle.b, genBundle.e).map(_.bits))
val ingressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val egressNodes = (edgeInNodes.map(u => Seq.fill(1) (u)) ++ edgeOutNodes.map(u => Seq.fill (1) {u})).flatten
val nVirtualNetworks = 2
val flows = edgesIn.zipWithIndex.map { case (edgeIn, ii) => edgesOut.zipWithIndex.map { case (edgeOut, oi) =>
val probe = edgeIn.client.anySupportProbe && edgeOut.manager.managers.exists(_.regionType >= RegionType.TRACKED)
val release = edgeIn.client.anySupportProbe && edgeOut.manager.anySupportAcquireB
( (if (probe ) Some(FlowParams(oi * 1 + 0 + edgesIn.size * 1, ii * 1 + 0 , 1)) else None) ++ // B
(if (release ) Some(FlowParams(ii * 1 + 0 , oi * 1 + 0 + edgesIn.size * 1, 0)) else None)) // E
}}.flatten.flatten
def interface(terminals: NoCTerminalIO,
ingressOffset: Int, egressOffset: Int, protocol: Data)(implicit p: Parameters) = {
val ingresses = terminals.ingress
val egresses = terminals.egress
protocol match { case protocol: TileLinkInterconnectInterface => {
protocol := DontCare
edgesIn.zipWithIndex.map { case (e,i) =>
val nif_master_be = Module(new TLMasterBEToNoC(
e, edgesOut, inputIdRanges(i).start, inputIdRanges(i).size,
wideBundle,
(s) => s * 1 + edgesIn.size * 1 + egressOffset,
minPayloadWidth
))
nif_master_be.io.tilelink := DontCare
nif_master_be.io.tilelink.a.valid := false.B
nif_master_be.io.tilelink.c.valid := false.B
nif_master_be.io.tilelink.e.valid := false.B
if (protocol.in(i).params.hasBCE) {
TLConnect(protocol.in(i).b, nif_master_be.io.tilelink.b)
TLConnect(nif_master_be.io.tilelink.e, protocol.in(i).e)
}
ingresses(i * 1 + 0).flit <> nif_master_be.io.flits.e
nif_master_be.io.flits.b <> egresses(i * 1 + 0).flit
}
edgesOut.zipWithIndex.map { case (e,i) =>
val nif_slave_be = Module(new TLSlaveBEToNoC(
e, edgesIn, outputIdRanges(i).start, outputIdRanges(i).size,
wideBundle,
(s) => s * 1 + egressOffset,
minPayloadWidth
))
nif_slave_be.io.tilelink := DontCare
nif_slave_be.io.tilelink.b.valid := false.B
nif_slave_be.io.tilelink.d.valid := false.B
if (protocol.out(i).params.hasBCE) {
TLConnect(protocol.out(i).e, nif_slave_be.io.tilelink.e)
TLConnect(nif_slave_be.io.tilelink.b, protocol.out(i).b)
}
ingresses(i * 1 + 0 + edgesIn.size * 1).flit <> nif_slave_be.io.flits.b
nif_slave_be.io.flits.e <> egresses(i * 1 + 0 + edgesIn.size * 1).flit
}
}}
}
}
abstract class TLNoCLike(implicit p: Parameters) extends LazyModule {
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"TLNoC (data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
// TileLink NoC does not preserve FIFO-ness, masters to this NoC should instantiate FIFOFixers
port.managers map { manager => manager.v1copy(fifoId = None) }
}
)
}
)
}
abstract class TLNoCModuleImp(outer: LazyModule) extends LazyModuleImp(outer) {
val edgesIn: Seq[TLEdge]
val edgesOut: Seq[TLEdge]
val nodeMapping: DiplomaticNetworkNodeMapping
val nocName: String
lazy val inNames = nodeMapping.genUniqueName(edgesIn.map(_.master.masters.map(_.name)))
lazy val outNames = nodeMapping.genUniqueName(edgesOut.map(_.slave.slaves.map(_.name)))
lazy val edgeInNodes = nodeMapping.getNodesIn(inNames)
lazy val edgeOutNodes = nodeMapping.getNodesOut(outNames)
def printNodeMappings() {
println(s"Constellation: TLNoC $nocName inwards mapping:")
for ((n, i) <- inNames zip edgeInNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
println(s"Constellation: TLNoC $nocName outwards mapping:")
for ((n, i) <- outNames zip edgeOutNodes) {
val node = i.map(_.toString).getOrElse("X")
println(s" $node <- $n")
}
}
}
trait TLNoCParams
// Instantiates a private TLNoC. Replaces the TLXbar
// BEGIN: TLNoCParams
case class SimpleTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
nocParams: NoCParams = NoCParams(),
) extends TLNoCParams
class TLNoC(params: SimpleTLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
// END: TLNoCParams
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.nocParams.copy(hasCtrl = false, nocName=name, inlineNoC = inlineNoC),
Seq(protocolParams),
inlineNoC = inlineNoC
)))
noc.io.protocol(0) match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
case class SplitACDxBETLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping,
acdNoCParams: NoCParams = NoCParams(),
beNoCParams: NoCParams = NoCParams(),
beDivision: Int = 2
) extends TLNoCParams
class TLSplitACDxBENoC(params: SplitACDxBETLNoCParams, name: String = "test", inlineNoC: Boolean = false)(implicit p: Parameters) extends TLNoCLike {
override def shouldBeInlined = inlineNoC
lazy val module = new TLNoCModuleImp(this) {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
printNodeMappings()
val acdProtocolParams = TileLinkACDProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val beProtocolParams = TileLinkBEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
val acd_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.acdNoCParams.copy(hasCtrl = false, nocName=s"${name}_acd", inlineNoC = inlineNoC),
Seq(acdProtocolParams),
inlineNoC = inlineNoC
)))
val be_noc = Module(new ProtocolNoC(ProtocolNoCParams(
params.beNoCParams.copy(hasCtrl = false, nocName=s"${name}_be", inlineNoC = inlineNoC),
Seq(beProtocolParams),
widthDivision = params.beDivision,
inlineNoC = inlineNoC
)))
acd_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.a <> r.a
l.c <> r.c
l.d <> r.d
}
}}
be_noc.io.protocol(0) match { case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) =>
l := DontCare
l.b <> r.b
l.e <> r.e
}
(io_out zip protocol.out).foreach { case (l,r) =>
r := DontCare
l.b <> r.b
l.e <> r.e
}
}}
}
}
case class GlobalTLNoCParams(
nodeMappings: DiplomaticNetworkNodeMapping
) extends TLNoCParams
// Maps this interconnect onto a global NoC
class TLGlobalNoC(params: GlobalTLNoCParams, name: String = "test")(implicit p: Parameters) extends TLNoCLike {
lazy val module = new TLNoCModuleImp(this) with CanAttachToGlobalNoC {
val (io_in, edgesIn) = node.in.unzip
val (io_out, edgesOut) = node.out.unzip
val nodeMapping = params.nodeMappings
val nocName = name
val protocolParams = TileLinkABCDEProtocolParams(
edgesIn = edgesIn,
edgesOut = edgesOut,
edgeInNodes = edgeInNodes.flatten,
edgeOutNodes = edgeOutNodes.flatten
)
printNodeMappings()
val io_global = IO(Flipped(protocolParams.genIO()))
io_global match {
case protocol: TileLinkInterconnectInterface => {
(protocol.in zip io_in).foreach { case (l,r) => l <> r }
(io_out zip protocol.out).foreach { case (l,r) => l <> r }
}
}
}
}
| module TLSlaveToNoC( // @[Tilelink.scala:125:7]
input clock, // @[Tilelink.scala:125:7]
input reset, // @[Tilelink.scala:125:7]
input io_tilelink_a_ready, // @[Tilelink.scala:132:14]
output io_tilelink_a_valid, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14]
output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14]
output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14]
output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14]
output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14]
output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14]
output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14]
output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14]
output io_tilelink_d_ready, // @[Tilelink.scala:132:14]
input io_tilelink_d_valid, // @[Tilelink.scala:132:14]
input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14]
input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14]
input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14]
input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14]
input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14]
input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14]
input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14]
output io_flits_a_ready, // @[Tilelink.scala:132:14]
input io_flits_a_valid, // @[Tilelink.scala:132:14]
input io_flits_a_bits_head, // @[Tilelink.scala:132:14]
input io_flits_a_bits_tail, // @[Tilelink.scala:132:14]
input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14]
output io_flits_b_valid, // @[Tilelink.scala:132:14]
output io_flits_c_ready, // @[Tilelink.scala:132:14]
input io_flits_c_valid, // @[Tilelink.scala:132:14]
input io_flits_c_bits_head, // @[Tilelink.scala:132:14]
input io_flits_c_bits_tail, // @[Tilelink.scala:132:14]
input io_flits_d_ready, // @[Tilelink.scala:132:14]
output io_flits_d_valid, // @[Tilelink.scala:132:14]
output io_flits_d_bits_head, // @[Tilelink.scala:132:14]
output io_flits_d_bits_tail, // @[Tilelink.scala:132:14]
output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14]
output [3:0] io_flits_d_bits_egress_id, // @[Tilelink.scala:132:14]
output io_flits_e_ready, // @[Tilelink.scala:132:14]
input io_flits_e_valid, // @[Tilelink.scala:132:14]
input io_flits_e_bits_head, // @[Tilelink.scala:132:14]
input io_flits_e_bits_tail // @[Tilelink.scala:132:14]
);
wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17]
TLAFromNoC a ( // @[Tilelink.scala:143:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_a_ready),
.io_protocol_valid (io_tilelink_a_valid),
.io_protocol_bits_opcode (io_tilelink_a_bits_opcode),
.io_protocol_bits_param (io_tilelink_a_bits_param),
.io_protocol_bits_size (io_tilelink_a_bits_size),
.io_protocol_bits_source (io_tilelink_a_bits_source),
.io_protocol_bits_address (io_tilelink_a_bits_address),
.io_protocol_bits_mask (io_tilelink_a_bits_mask),
.io_protocol_bits_data (io_tilelink_a_bits_data),
.io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt),
.io_flit_ready (io_flits_a_ready),
.io_flit_valid (io_flits_a_valid),
.io_flit_bits_head (io_flits_a_bits_head),
.io_flit_bits_tail (io_flits_a_bits_tail),
.io_flit_bits_payload (io_flits_a_bits_payload)
); // @[Tilelink.scala:143:17]
TLBToNoC b ( // @[Tilelink.scala:144:17]
.clock (clock),
.reset (reset),
.io_flit_valid (io_flits_b_valid)
); // @[Tilelink.scala:144:17]
TLCFromNoC c ( // @[Tilelink.scala:145:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_c_ready),
.io_flit_valid (io_flits_c_valid),
.io_flit_bits_head (io_flits_c_bits_head),
.io_flit_bits_tail (io_flits_c_bits_tail)
); // @[Tilelink.scala:145:17]
TLDToNoC d ( // @[Tilelink.scala:146:17]
.clock (clock),
.reset (reset),
.io_protocol_ready (io_tilelink_d_ready),
.io_protocol_valid (io_tilelink_d_valid),
.io_protocol_bits_opcode (io_tilelink_d_bits_opcode),
.io_protocol_bits_param (io_tilelink_d_bits_param),
.io_protocol_bits_size (io_tilelink_d_bits_size),
.io_protocol_bits_source (io_tilelink_d_bits_source),
.io_protocol_bits_sink (io_tilelink_d_bits_sink),
.io_protocol_bits_denied (io_tilelink_d_bits_denied),
.io_protocol_bits_data (io_tilelink_d_bits_data),
.io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt),
.io_flit_ready (io_flits_d_ready),
.io_flit_valid (io_flits_d_valid),
.io_flit_bits_head (io_flits_d_bits_head),
.io_flit_bits_tail (io_flits_d_bits_tail),
.io_flit_bits_payload (_d_io_flit_bits_payload),
.io_flit_bits_egress_id (io_flits_d_bits_egress_id)
); // @[Tilelink.scala:146:17]
TLEFromNoC e ( // @[Tilelink.scala:147:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_tail (io_flits_e_bits_tail)
); // @[Tilelink.scala:147:17]
assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_177( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_191 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_48( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [4095:0] _GEN = {4084'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [4095:0] _GEN_2 = {4084'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_65( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_40( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [57:0] inflight; // @[Monitor.scala:614:27]
reg [231:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [231:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [57:0] inflight_1; // @[Monitor.scala:726:35]
reg [231:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File tage.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix, MaskLower, WrapInc}
import scala.math.min
class TageResp extends Bundle {
val ctr = UInt(3.W)
val u = UInt(2.W)
}
class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int, val singlePorted: Boolean)
(implicit p: Parameters) extends BoomModule()(p)
with HasBoomFrontendParameters
{
require(histLength <= globalHistoryLength)
val nWrBypassEntries = 2
val io = IO( new Bundle {
val f1_req_valid = Input(Bool())
val f1_req_pc = Input(UInt(vaddrBitsExtended.W))
val f1_req_ghist = Input(UInt(globalHistoryLength.W))
val f2_resp = Output(Vec(bankWidth, Valid(new TageResp)))
val update_mask = Input(Vec(bankWidth, Bool()))
val update_taken = Input(Vec(bankWidth, Bool()))
val update_alloc = Input(Vec(bankWidth, Bool()))
val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))
val update_pc = Input(UInt())
val update_hist = Input(UInt())
val update_u_mask = Input(Vec(bankWidth, Bool()))
val update_u = Input(Vec(bankWidth, UInt(2.W)))
})
def compute_folded_hist(hist: UInt, l: Int) = {
val nChunks = (histLength + l - 1) / l
val hist_chunks = (0 until nChunks) map {i =>
hist(min((i+1)*l, histLength)-1, i*l)
}
hist_chunks.reduce(_^_)
}
def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {
val idx_history = compute_folded_hist(hist, log2Ceil(nRows))
val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)
val tag_history = compute_folded_hist(hist, tagSz)
val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)
(idx, tag)
}
def inc_ctr(ctr: UInt, taken: Bool): UInt = {
Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),
Mux(ctr === 7.U, 7.U, ctr + 1.U))
}
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nRows).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nRows-1).U) { doing_reset := false.B }
class TageEntry extends Bundle {
val valid = Bool() // TODO: Remove this valid bit
val tag = UInt(tagSz.W)
val ctr = UInt(3.W)
}
val tageEntrySz = 1 + tagSz + 3
val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)
val us = SyncReadMem(nRows, Vec(bankWidth*2, Bool()))
val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))
us.suggestName(s"tage_u_${histLength}")
table.suggestName(s"tage_table_${histLength}")
val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz))
val s2_tag = RegNext(s1_tag)
val s2_req_rtage = Wire(Vec(bankWidth, new TageEntry))
val s2_req_rus = Wire(Vec(bankWidth*2, Bool()))
val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))
for (w <- 0 until bankWidth) {
// This bit indicates the TAGE table matched here
io.f2_resp(w).valid := s2_req_rhits(w)
io.f2_resp(w).bits.u := Cat(s2_req_rus(w*2+1), s2_req_rus(w*2))
io.f2_resp(w).bits.ctr := s2_req_rtage(w).ctr
}
val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))
when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }
val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U
val clear_u_hi = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U
val clear_u_lo = clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U
val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)
val clear_u_mask = VecInit((0 until bankWidth*2) map { i => if (i % 2 == 0) clear_u_lo else clear_u_hi }).asUInt
val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)
val update_wdata = Wire(Vec(bankWidth, new TageEntry))
val wen = WireInit(doing_reset || io.update_mask.reduce(_||_))
val rdata = if (singlePorted) table.read(s1_hashed_idx, !wen && io.f1_req_valid) else table.read(s1_hashed_idx, io.f1_req_valid)
when (RegNext(wen) && singlePorted.B) {
s2_req_rtage := 0.U.asTypeOf(Vec(bankWidth, new TageEntry))
} .otherwise {
s2_req_rtage := VecInit(rdata.map(_.asTypeOf(new TageEntry)))
}
when (wen) {
val widx = Mux(doing_reset, reset_idx, update_idx)
val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt)))
val wmask = Mux(doing_reset, ~(0.U(bankWidth.W)), io.update_mask.asUInt)
table.write(widx, wdata, wmask.asBools)
}
val update_u_mask = VecInit((0 until bankWidth*2) map {i => io.update_u_mask(i / 2)})
val update_u_wen = WireInit(doing_reset || doing_clear_u || update_u_mask.reduce(_||_))
val u_rdata = if (singlePorted) {
us.read(s1_hashed_idx, !update_u_wen && io.f1_req_valid)
} else {
us.read(s1_hashed_idx, io.f1_req_valid)
}
s2_req_rus := u_rdata
when (update_u_wen) {
val widx = Mux(doing_reset, reset_idx, Mux(doing_clear_u, clear_u_idx, update_idx))
val wdata = Mux(doing_reset || doing_clear_u, VecInit(0.U((bankWidth*2).W).asBools), VecInit(io.update_u.asUInt.asBools))
val wmask = Mux(doing_reset, ~(0.U((bankWidth*2).W)), Mux(doing_clear_u, clear_u_mask, update_u_mask.asUInt))
us.write(widx, wdata, wmask.asBools)
}
val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_tags(i) === update_tag &&
wrbypass_idxs(i) === update_idx
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
update_wdata(w).ctr := Mux(io.update_alloc(w),
Mux(io.update_taken(w), 4.U,
3.U
),
Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),
inc_ctr(io.update_old_ctr(w), io.update_taken(w))
)
)
update_wdata(w).valid := true.B
update_wdata(w).tag := update_tag
}
when (io.update_mask.reduce(_||_)) {
when (wrbypass_hits.reduce(_||_)) {
wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))
} .otherwise {
wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))
wrbypass_tags(wrbypass_enq_idx) := update_tag
wrbypass_idxs(wrbypass_enq_idx) := update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
case class BoomTageParams(
// nSets, histLen, tagSz
tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),
( 128, 4, 7),
( 256, 8, 8),
( 256, 16, 8),
( 128, 32, 9),
( 128, 64, 9)),
uBitPeriod: Int = 2048,
singlePorted: Boolean = false
)
class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
val tageUBitPeriod = params.uBitPeriod
val tageNTables = params.tableInfo.size
class TageMeta extends Bundle
{
val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
val alt_differs = Vec(bankWidth, Output(Bool()))
val provider_u = Vec(bankWidth, Output(UInt(2.W)))
val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))
val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))
}
val f3_meta = Wire(new TageMeta)
override val metaSz = f3_meta.asUInt.getWidth
require(metaSz <= bpdMaxMetaLength)
def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {
Mux(!alt_differs, u,
Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),
Mux(u === 3.U, 3.U, u + 1.U)))
}
val tt = params.tableInfo map {
case (n, l, s) => {
val t = Module(new TageTable(n, s, l, params.uBitPeriod, params.singlePorted))
t.io.f1_req_valid := RegNext(io.f0_valid)
t.io.f1_req_pc := RegNext(bankAlign(io.f0_pc))
t.io.f1_req_ghist := io.f1_ghist
(t, t.mems)
}
}
val tables = tt.map(_._1)
val mems = tt.map(_._2).flatten
val f2_resps = VecInit(tables.map(_.io.f2_resp))
val f3_resps = RegNext(f2_resps)
val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)
val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &
Fill(bankWidth, s1_update.bits.cfi_mispredicted)
val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))
val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))
val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))
val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))
val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))
s1_update_taken := DontCare
s1_update_old_ctr := DontCare
s1_update_alloc := DontCare
s1_update_u := DontCare
for (w <- 0 until bankWidth) {
var s2_provided = false.B
var s2_provider = 0.U
var s2_alt_provided = false.B
var s2_alt_provider = 0.U
for (i <- 0 until tageNTables) {
val hit = f2_resps(i)(w).valid
s2_alt_provided = s2_alt_provided || (s2_provided && hit)
s2_provided = s2_provided || hit
s2_alt_provider = Mux(hit, s2_provider, s2_alt_provider)
s2_provider = Mux(hit, i.U, s2_provider)
}
val s3_provided = RegNext(s2_provided)
val s3_provider = RegNext(s2_provider)
val s3_alt_provided = RegNext(s2_alt_provided)
val s3_alt_provider = RegNext(s2_alt_provider)
val prov = RegNext(f2_resps(s2_provider)(w).bits)
val alt = RegNext(f2_resps(s2_alt_provider)(w).bits)
io.resp.f3(w).taken := Mux(s3_provided,
Mux(prov.ctr === 3.U || prov.ctr === 4.U,
Mux(s3_alt_provided, alt.ctr(2), io.resp_in(0).f3(w).taken),
prov.ctr(2)),
io.resp_in(0).f3(w).taken
)
f3_meta.provider(w).valid := s3_provided
f3_meta.provider(w).bits := s3_provider
f3_meta.alt_differs(w) := s3_alt_provided && alt.ctr(2) =/= io.resp.f3(w).taken
f3_meta.provider_u(w) := prov.u
f3_meta.provider_ctr(w) := prov.ctr
// Create a mask of tables which did not hit our query, and also contain useless entries
// and also uses a longer history than the provider
val allocatable_slots = (
VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &
~(MaskLower(UIntToOH(f3_meta.provider(w).bits)) & Fill(tageNTables, f3_meta.provider(w).valid))
)
val alloc_lfsr = random.LFSR(tageNTables max 2)
val first_entry = PriorityEncoder(allocatable_slots)
val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)
val alloc_entry = Mux(allocatable_slots(masked_entry),
masked_entry,
first_entry)
f3_meta.allocate(w).valid := allocatable_slots =/= 0.U
f3_meta.allocate(w).bits := alloc_entry
val update_was_taken = (s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
s1_update.bits.cfi_taken)
when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {
when (s1_update_meta.provider(w).valid) {
val provider = s1_update_meta.provider(w).bits
s1_update_mask(provider)(w) := true.B
s1_update_u_mask(provider)(w) := true.B
val new_u = inc_u(s1_update_meta.provider_u(w),
s1_update_meta.alt_differs(w),
s1_update_mispredict_mask(w))
s1_update_u (provider)(w) := new_u
s1_update_taken (provider)(w) := update_was_taken
s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)
s1_update_alloc (provider)(w) := false.B
}
}
}
when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {
val idx = s1_update.bits.cfi_idx.bits
val allocate = s1_update_meta.allocate(idx)
when (allocate.valid) {
s1_update_mask (allocate.bits)(idx) := true.B
s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken
s1_update_alloc(allocate.bits)(idx) := true.B
s1_update_u_mask(allocate.bits)(idx) := true.B
s1_update_u (allocate.bits)(idx) := 0.U
} .otherwise {
val provider = s1_update_meta.provider(idx)
val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)
for (i <- 0 until tageNTables) {
when (decr_mask(i)) {
s1_update_u_mask(i)(idx) := true.B
s1_update_u (i)(idx) := 0.U
}
}
}
}
for (i <- 0 until tageNTables) {
for (w <- 0 until bankWidth) {
tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))
tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))
tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))
tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))
tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))
tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))
}
tables(i).io.update_pc := RegNext(s1_update.bits.pc)
tables(i).io.update_hist := RegNext(s1_update.bits.ghist)
}
//io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))
io.f3_meta := f3_meta.asUInt
}
| module tage_table_64_0( // @[tage.scala:90:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [51:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [51:0] W0_data,
input [3:0] W0_mask
);
tage_table_32_ext tage_table_32_ext ( // @[tage.scala:90:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
); // @[tage.scala:90:27]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_38( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_607; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [127:0] address; // @[Monitor.scala:391:22]
wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_57( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_3( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_33( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [36:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [36:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [3:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [36:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [36:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 4'h5; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 4'h2; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 4'h4; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 4'h7; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 4'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 4'h8; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 4'h3; // @[IngressUnit.scala:30:72]
wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_T_20 = {_route_buffer_io_enq_bits_flow_egress_node_id_T, {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_1} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_2}}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h6 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_5}}; // @[Mux.scala:30:73]
wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_T_20[2], _route_buffer_io_enq_bits_flow_egress_node_T_20[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_6, 1'h0}}; // @[Mux.scala:30:73]
wire _io_router_req_valid_T_1 = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_26 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_32 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_38 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_98 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [975:0] c_opcodes_set = 976'h0; // @[Monitor.scala:740:34]
wire [975:0] c_sizes_set = 976'h0; // @[Monitor.scala:741:34]
wire [243:0] c_set = 244'h0; // @[Monitor.scala:738:34]
wire [243:0] c_set_wo_ready = 244'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_14 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_15 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_6 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_12 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_18 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_24 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_30 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_36 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_42 = io_in_a_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = &_source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 3'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_9 & _source_ok_T_10; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 3'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_16 = source_ok_uncommonBits_2 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_17 = _source_ok_T_15 & _source_ok_T_16; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = _source_ok_T_18 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_22 = source_ok_uncommonBits_3 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_25 = _source_ok_T_24 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_27 = _source_ok_T_25; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_28 = source_ok_uncommonBits_4 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_29 = _source_ok_T_27 & _source_ok_T_28; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_4 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_31 = _source_ok_T_30 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_33 = _source_ok_T_31; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_34 = source_ok_uncommonBits_5 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_35 = _source_ok_T_33 & _source_ok_T_34; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_37 = _source_ok_T_36 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_39 = _source_ok_T_37; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_40 = source_ok_uncommonBits_6 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_41 = _source_ok_T_39 & _source_ok_T_40; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_6 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_43 = _source_ok_T_42 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_46 = source_ok_uncommonBits_7 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_47 = _source_ok_T_45 & _source_ok_T_46; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_7 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_9 = _uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_10 = _uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_11 = _uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_12 = _uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_13 = _uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_14 = _uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_15 = _uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_16 = _uncommonBits_T_16[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_17 = _uncommonBits_T_17[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_18 = _uncommonBits_T_18[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_19 = _uncommonBits_T_19[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_20 = _uncommonBits_T_20[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_21 = _uncommonBits_T_21[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_22 = _uncommonBits_T_22[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_23 = _uncommonBits_T_23[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_24 = _uncommonBits_T_24[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_25 = _uncommonBits_T_25[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_26 = _uncommonBits_T_26[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_27 = _uncommonBits_T_27[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_28 = _uncommonBits_T_28[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_29 = _uncommonBits_T_29[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_30 = _uncommonBits_T_30[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_31 = _uncommonBits_T_31[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_32 = _uncommonBits_T_32[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_33 = _uncommonBits_T_33[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_34 = _uncommonBits_T_34[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_35 = _uncommonBits_T_35[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_36 = _uncommonBits_T_36[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_37 = _uncommonBits_T_37[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_38 = _uncommonBits_T_38[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_39 = _uncommonBits_T_39[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_40 = _uncommonBits_T_40[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_41 = _uncommonBits_T_41[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_42 = _uncommonBits_T_42[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_43 = _uncommonBits_T_43[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_44 = _uncommonBits_T_44[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_45 = _uncommonBits_T_45[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_46 = _uncommonBits_T_46[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_47 = _uncommonBits_T_47[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_48 = _uncommonBits_T_48[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_49 = _uncommonBits_T_49[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_50 = _uncommonBits_T_50[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_51 = _uncommonBits_T_51[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_52 = _uncommonBits_T_52[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_53 = _uncommonBits_T_53[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_54 = _uncommonBits_T_54[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_55 = _uncommonBits_T_55[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_56 = _uncommonBits_T_56[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_57 = _uncommonBits_T_57[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_58 = _uncommonBits_T_58[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_59 = _uncommonBits_T_59[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_60 = _uncommonBits_T_60[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_61 = _uncommonBits_T_61[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_62 = _uncommonBits_T_62[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_63 = _uncommonBits_T_63[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_64 = _uncommonBits_T_64[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_65 = _uncommonBits_T_65[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_66 = _uncommonBits_T_66[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_67 = _uncommonBits_T_67[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_68 = _uncommonBits_T_68[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_69 = _uncommonBits_T_69[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_70 = _uncommonBits_T_70[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_71 = _uncommonBits_T_71[4:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[4:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_54 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_60 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_66 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_72 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_78 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_84 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_90 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_96 = io_in_d_bits_source_0[7:5]; // @[Monitor.scala:36:7]
wire _source_ok_T_55 = &_source_ok_T_54; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = source_ok_uncommonBits_8 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_59 = _source_ok_T_57 & _source_ok_T_58; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 3'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = source_ok_uncommonBits_9 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_65 = _source_ok_T_63 & _source_ok_T_64; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_1 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 3'h5; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_10 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_2 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_73 = _source_ok_T_72 == 3'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = source_ok_uncommonBits_11 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_77 = _source_ok_T_75 & _source_ok_T_76; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_3 = _source_ok_T_77; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_79 = _source_ok_T_78 == 3'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = source_ok_uncommonBits_12 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_83 = _source_ok_T_81 & _source_ok_T_82; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_4 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_85 = _source_ok_T_84 == 3'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = source_ok_uncommonBits_13 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_89 = _source_ok_T_87 & _source_ok_T_88; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_91 = _source_ok_T_90 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_94 = source_ok_uncommonBits_14 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_95 = _source_ok_T_93 & _source_ok_T_94; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_6 = _source_ok_T_95; // @[Parameters.scala:1138:31]
wire [4:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[4:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_97 = _source_ok_T_96 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_99 = _source_ok_T_97; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_100 = source_ok_uncommonBits_15 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_101 = _source_ok_T_99 & _source_ok_T_100; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_7 = _source_ok_T_101; // @[Parameters.scala:1138:31]
wire _source_ok_T_102 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_107 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1162 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1162; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1162; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1235 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1235; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1235; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1235; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg denied; // @[Monitor.scala:543:22]
reg [243:0] inflight; // @[Monitor.scala:614:27]
reg [975:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [975:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [243:0] a_set; // @[Monitor.scala:626:34]
wire [243:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [975:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [975:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [975:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [975:0] _a_opcode_lookup_T_6 = {972'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [975:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [975:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [975:0] _a_size_lookup_T_6 = {972'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [975:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[975:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire _T_1088 = _T_1162 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1088 ? _a_set_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1088 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1088 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1088 ? _a_opcodes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1088 ? _a_sizes_set_T_1[975:0] : 976'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [243:0] d_clr; // @[Monitor.scala:664:34]
wire [243:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [975:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [975:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1134 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1134 & ~d_release_ack ? _d_clr_wo_ready_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire _T_1103 = _T_1235 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1103 ? _d_clr_T[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1103 ? _d_opcodes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1103 ? _d_sizes_clr_T_5[975:0] : 976'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [243:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [243:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [243:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [975:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [975:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [975:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [975:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [975:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [975:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [243:0] inflight_1; // @[Monitor.scala:726:35]
wire [243:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [975:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [975:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [975:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [975:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [975:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [975:0] _c_opcode_lookup_T_6 = {972'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [975:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[975:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [975:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [975:0] _c_size_lookup_T_6 = {972'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [975:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[975:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [243:0] d_clr_1; // @[Monitor.scala:774:34]
wire [243:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [975:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [975:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1206 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1206 & d_release_ack_1 ? _d_clr_wo_ready_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire _T_1188 = _T_1235 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1188 ? _d_clr_T_1[243:0] : 244'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1188 ? _d_opcodes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1188 ? _d_sizes_clr_T_11[975:0] : 976'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [243:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [243:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [975:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [975:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [975:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [975:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
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